1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf 5 */ 6 7 #include <linux/bits.h> 8 #include <linux/clk.h> 9 #include <linux/debugfs.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/i2c.h> 13 #include <linux/iopoll.h> 14 #include <linux/module.h> 15 #include <linux/of_graph.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 20 #include <drm/drm_atomic.h> 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_bridge.h> 23 #include <drm/drm_dp_helper.h> 24 #include <drm/drm_mipi_dsi.h> 25 #include <drm/drm_of.h> 26 #include <drm/drm_panel.h> 27 #include <drm/drm_print.h> 28 #include <drm/drm_probe_helper.h> 29 30 #define SN_DEVICE_REV_REG 0x08 31 #define SN_DPPLL_SRC_REG 0x0A 32 #define DPPLL_CLK_SRC_DSICLK BIT(0) 33 #define REFCLK_FREQ_MASK GENMASK(3, 1) 34 #define REFCLK_FREQ(x) ((x) << 1) 35 #define DPPLL_SRC_DP_PLL_LOCK BIT(7) 36 #define SN_PLL_ENABLE_REG 0x0D 37 #define SN_DSI_LANES_REG 0x10 38 #define CHA_DSI_LANES_MASK GENMASK(4, 3) 39 #define CHA_DSI_LANES(x) ((x) << 3) 40 #define SN_DSIA_CLK_FREQ_REG 0x12 41 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20 42 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24 43 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C 44 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D 45 #define CHA_HSYNC_POLARITY BIT(7) 46 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30 47 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31 48 #define CHA_VSYNC_POLARITY BIT(7) 49 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34 50 #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36 51 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38 52 #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A 53 #define SN_LN_ASSIGN_REG 0x59 54 #define LN_ASSIGN_WIDTH 2 55 #define SN_ENH_FRAME_REG 0x5A 56 #define VSTREAM_ENABLE BIT(3) 57 #define LN_POLRS_OFFSET 4 58 #define LN_POLRS_MASK 0xf0 59 #define SN_DATA_FORMAT_REG 0x5B 60 #define BPP_18_RGB BIT(0) 61 #define SN_HPD_DISABLE_REG 0x5C 62 #define HPD_DISABLE BIT(0) 63 #define SN_GPIO_IO_REG 0x5E 64 #define SN_GPIO_INPUT_SHIFT 4 65 #define SN_GPIO_OUTPUT_SHIFT 0 66 #define SN_GPIO_CTRL_REG 0x5F 67 #define SN_GPIO_MUX_INPUT 0 68 #define SN_GPIO_MUX_OUTPUT 1 69 #define SN_GPIO_MUX_SPECIAL 2 70 #define SN_GPIO_MUX_MASK 0x3 71 #define SN_AUX_WDATA_REG(x) (0x64 + (x)) 72 #define SN_AUX_ADDR_19_16_REG 0x74 73 #define SN_AUX_ADDR_15_8_REG 0x75 74 #define SN_AUX_ADDR_7_0_REG 0x76 75 #define SN_AUX_LENGTH_REG 0x77 76 #define SN_AUX_CMD_REG 0x78 77 #define AUX_CMD_SEND BIT(0) 78 #define AUX_CMD_REQ(x) ((x) << 4) 79 #define SN_AUX_RDATA_REG(x) (0x79 + (x)) 80 #define SN_SSC_CONFIG_REG 0x93 81 #define DP_NUM_LANES_MASK GENMASK(5, 4) 82 #define DP_NUM_LANES(x) ((x) << 4) 83 #define SN_DATARATE_CONFIG_REG 0x94 84 #define DP_DATARATE_MASK GENMASK(7, 5) 85 #define DP_DATARATE(x) ((x) << 5) 86 #define SN_ML_TX_MODE_REG 0x96 87 #define ML_TX_MAIN_LINK_OFF 0 88 #define ML_TX_NORMAL_MODE BIT(0) 89 #define SN_AUX_CMD_STATUS_REG 0xF4 90 #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3) 91 #define AUX_IRQ_STATUS_AUX_SHORT BIT(5) 92 #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6) 93 94 #define MIN_DSI_CLK_FREQ_MHZ 40 95 96 /* fudge factor required to account for 8b/10b encoding */ 97 #define DP_CLK_FUDGE_NUM 10 98 #define DP_CLK_FUDGE_DEN 8 99 100 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */ 101 #define SN_AUX_MAX_PAYLOAD_BYTES 16 102 103 #define SN_REGULATOR_SUPPLY_NUM 4 104 105 #define SN_MAX_DP_LANES 4 106 #define SN_NUM_GPIOS 4 107 #define SN_GPIO_PHYSICAL_OFFSET 1 108 109 #define SN_LINK_TRAINING_TRIES 10 110 111 /** 112 * struct ti_sn_bridge - Platform data for ti-sn65dsi86 driver. 113 * @dev: Pointer to our device. 114 * @regmap: Regmap for accessing i2c. 115 * @aux: Our aux channel. 116 * @bridge: Our bridge. 117 * @connector: Our connector. 118 * @debugfs: Used for managing our debugfs. 119 * @host_node: Remote DSI node. 120 * @dsi: Our MIPI DSI source. 121 * @refclk: Our reference clock. 122 * @panel: Our panel. 123 * @enable_gpio: The GPIO we toggle to enable the bridge. 124 * @supplies: Data for bulk enabling/disabling our regulators. 125 * @dp_lanes: Count of dp_lanes we're using. 126 * @ln_assign: Value to program to the LN_ASSIGN register. 127 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG. 128 * 129 * @gchip: If we expose our GPIOs, this is used. 130 * @gchip_output: A cache of whether we've set GPIOs to output. This 131 * serves double-duty of keeping track of the direction and 132 * also keeping track of whether we've incremented the 133 * pm_runtime reference count for this pin, which we do 134 * whenever a pin is configured as an output. This is a 135 * bitmap so we can do atomic ops on it without an extra 136 * lock so concurrent users of our 4 GPIOs don't stomp on 137 * each other's read-modify-write. 138 */ 139 struct ti_sn_bridge { 140 struct device *dev; 141 struct regmap *regmap; 142 struct drm_dp_aux aux; 143 struct drm_bridge bridge; 144 struct drm_connector connector; 145 struct dentry *debugfs; 146 struct device_node *host_node; 147 struct mipi_dsi_device *dsi; 148 struct clk *refclk; 149 struct drm_panel *panel; 150 struct gpio_desc *enable_gpio; 151 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM]; 152 int dp_lanes; 153 u8 ln_assign; 154 u8 ln_polrs; 155 156 #if defined(CONFIG_OF_GPIO) 157 struct gpio_chip gchip; 158 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS); 159 #endif 160 }; 161 162 static const struct regmap_range ti_sn_bridge_volatile_ranges[] = { 163 { .range_min = 0, .range_max = 0xFF }, 164 }; 165 166 static const struct regmap_access_table ti_sn_bridge_volatile_table = { 167 .yes_ranges = ti_sn_bridge_volatile_ranges, 168 .n_yes_ranges = ARRAY_SIZE(ti_sn_bridge_volatile_ranges), 169 }; 170 171 static const struct regmap_config ti_sn_bridge_regmap_config = { 172 .reg_bits = 8, 173 .val_bits = 8, 174 .volatile_table = &ti_sn_bridge_volatile_table, 175 .cache_type = REGCACHE_NONE, 176 }; 177 178 static void ti_sn_bridge_write_u16(struct ti_sn_bridge *pdata, 179 unsigned int reg, u16 val) 180 { 181 regmap_write(pdata->regmap, reg, val & 0xFF); 182 regmap_write(pdata->regmap, reg + 1, val >> 8); 183 } 184 185 static int __maybe_unused ti_sn_bridge_resume(struct device *dev) 186 { 187 struct ti_sn_bridge *pdata = dev_get_drvdata(dev); 188 int ret; 189 190 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); 191 if (ret) { 192 DRM_ERROR("failed to enable supplies %d\n", ret); 193 return ret; 194 } 195 196 gpiod_set_value(pdata->enable_gpio, 1); 197 198 return ret; 199 } 200 201 static int __maybe_unused ti_sn_bridge_suspend(struct device *dev) 202 { 203 struct ti_sn_bridge *pdata = dev_get_drvdata(dev); 204 int ret; 205 206 gpiod_set_value(pdata->enable_gpio, 0); 207 208 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); 209 if (ret) 210 DRM_ERROR("failed to disable supplies %d\n", ret); 211 212 return ret; 213 } 214 215 static const struct dev_pm_ops ti_sn_bridge_pm_ops = { 216 SET_RUNTIME_PM_OPS(ti_sn_bridge_suspend, ti_sn_bridge_resume, NULL) 217 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 218 pm_runtime_force_resume) 219 }; 220 221 static int status_show(struct seq_file *s, void *data) 222 { 223 struct ti_sn_bridge *pdata = s->private; 224 unsigned int reg, val; 225 226 seq_puts(s, "STATUS REGISTERS:\n"); 227 228 pm_runtime_get_sync(pdata->dev); 229 230 /* IRQ Status Registers, see Table 31 in datasheet */ 231 for (reg = 0xf0; reg <= 0xf8; reg++) { 232 regmap_read(pdata->regmap, reg, &val); 233 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val); 234 } 235 236 pm_runtime_put(pdata->dev); 237 238 return 0; 239 } 240 241 DEFINE_SHOW_ATTRIBUTE(status); 242 243 static void ti_sn_debugfs_init(struct ti_sn_bridge *pdata) 244 { 245 pdata->debugfs = debugfs_create_dir(dev_name(pdata->dev), NULL); 246 247 debugfs_create_file("status", 0600, pdata->debugfs, pdata, 248 &status_fops); 249 } 250 251 static void ti_sn_debugfs_remove(struct ti_sn_bridge *pdata) 252 { 253 debugfs_remove_recursive(pdata->debugfs); 254 pdata->debugfs = NULL; 255 } 256 257 /* Connector funcs */ 258 static struct ti_sn_bridge * 259 connector_to_ti_sn_bridge(struct drm_connector *connector) 260 { 261 return container_of(connector, struct ti_sn_bridge, connector); 262 } 263 264 static int ti_sn_bridge_connector_get_modes(struct drm_connector *connector) 265 { 266 struct ti_sn_bridge *pdata = connector_to_ti_sn_bridge(connector); 267 268 return drm_panel_get_modes(pdata->panel, connector); 269 } 270 271 static enum drm_mode_status 272 ti_sn_bridge_connector_mode_valid(struct drm_connector *connector, 273 struct drm_display_mode *mode) 274 { 275 /* maximum supported resolution is 4K at 60 fps */ 276 if (mode->clock > 594000) 277 return MODE_CLOCK_HIGH; 278 279 return MODE_OK; 280 } 281 282 static struct drm_connector_helper_funcs ti_sn_bridge_connector_helper_funcs = { 283 .get_modes = ti_sn_bridge_connector_get_modes, 284 .mode_valid = ti_sn_bridge_connector_mode_valid, 285 }; 286 287 static enum drm_connector_status 288 ti_sn_bridge_connector_detect(struct drm_connector *connector, bool force) 289 { 290 /** 291 * TODO: Currently if drm_panel is present, then always 292 * return the status as connected. Need to add support to detect 293 * device state for hot pluggable scenarios. 294 */ 295 return connector_status_connected; 296 } 297 298 static const struct drm_connector_funcs ti_sn_bridge_connector_funcs = { 299 .fill_modes = drm_helper_probe_single_connector_modes, 300 .detect = ti_sn_bridge_connector_detect, 301 .destroy = drm_connector_cleanup, 302 .reset = drm_atomic_helper_connector_reset, 303 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 304 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 305 }; 306 307 static struct ti_sn_bridge *bridge_to_ti_sn_bridge(struct drm_bridge *bridge) 308 { 309 return container_of(bridge, struct ti_sn_bridge, bridge); 310 } 311 312 static int ti_sn_bridge_parse_regulators(struct ti_sn_bridge *pdata) 313 { 314 unsigned int i; 315 const char * const ti_sn_bridge_supply_names[] = { 316 "vcca", "vcc", "vccio", "vpll", 317 }; 318 319 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++) 320 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i]; 321 322 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM, 323 pdata->supplies); 324 } 325 326 static int ti_sn_bridge_attach(struct drm_bridge *bridge, 327 enum drm_bridge_attach_flags flags) 328 { 329 int ret, val; 330 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); 331 struct mipi_dsi_host *host; 332 struct mipi_dsi_device *dsi; 333 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge", 334 .channel = 0, 335 .node = NULL, 336 }; 337 338 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) { 339 DRM_ERROR("Fix bridge driver to make connector optional!"); 340 return -EINVAL; 341 } 342 343 ret = drm_connector_init(bridge->dev, &pdata->connector, 344 &ti_sn_bridge_connector_funcs, 345 DRM_MODE_CONNECTOR_eDP); 346 if (ret) { 347 DRM_ERROR("Failed to initialize connector with drm\n"); 348 return ret; 349 } 350 351 drm_connector_helper_add(&pdata->connector, 352 &ti_sn_bridge_connector_helper_funcs); 353 drm_connector_attach_encoder(&pdata->connector, bridge->encoder); 354 355 /* 356 * TODO: ideally finding host resource and dsi dev registration needs 357 * to be done in bridge probe. But some existing DSI host drivers will 358 * wait for any of the drm_bridge/drm_panel to get added to the global 359 * bridge/panel list, before completing their probe. So if we do the 360 * dsi dev registration part in bridge probe, before populating in 361 * the global bridge list, then it will cause deadlock as dsi host probe 362 * will never complete, neither our bridge probe. So keeping it here 363 * will satisfy most of the existing host drivers. Once the host driver 364 * is fixed we can move the below code to bridge probe safely. 365 */ 366 host = of_find_mipi_dsi_host_by_node(pdata->host_node); 367 if (!host) { 368 DRM_ERROR("failed to find dsi host\n"); 369 ret = -ENODEV; 370 goto err_dsi_host; 371 } 372 373 dsi = mipi_dsi_device_register_full(host, &info); 374 if (IS_ERR(dsi)) { 375 DRM_ERROR("failed to create dsi device\n"); 376 ret = PTR_ERR(dsi); 377 goto err_dsi_host; 378 } 379 380 /* TODO: setting to 4 MIPI lanes always for now */ 381 dsi->lanes = 4; 382 dsi->format = MIPI_DSI_FMT_RGB888; 383 dsi->mode_flags = MIPI_DSI_MODE_VIDEO; 384 385 /* check if continuous dsi clock is required or not */ 386 pm_runtime_get_sync(pdata->dev); 387 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val); 388 pm_runtime_put(pdata->dev); 389 if (!(val & DPPLL_CLK_SRC_DSICLK)) 390 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS; 391 392 ret = mipi_dsi_attach(dsi); 393 if (ret < 0) { 394 DRM_ERROR("failed to attach dsi to host\n"); 395 goto err_dsi_attach; 396 } 397 pdata->dsi = dsi; 398 399 return 0; 400 401 err_dsi_attach: 402 mipi_dsi_device_unregister(dsi); 403 err_dsi_host: 404 drm_connector_cleanup(&pdata->connector); 405 return ret; 406 } 407 408 static void ti_sn_bridge_disable(struct drm_bridge *bridge) 409 { 410 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); 411 412 drm_panel_disable(pdata->panel); 413 414 /* disable video stream */ 415 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0); 416 /* semi auto link training mode OFF */ 417 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0); 418 /* disable DP PLL */ 419 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); 420 421 drm_panel_unprepare(pdata->panel); 422 } 423 424 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn_bridge *pdata) 425 { 426 u32 bit_rate_khz, clk_freq_khz; 427 struct drm_display_mode *mode = 428 &pdata->bridge.encoder->crtc->state->adjusted_mode; 429 430 bit_rate_khz = mode->clock * 431 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); 432 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2); 433 434 return clk_freq_khz; 435 } 436 437 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */ 438 static const u32 ti_sn_bridge_refclk_lut[] = { 439 12000000, 440 19200000, 441 26000000, 442 27000000, 443 38400000, 444 }; 445 446 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */ 447 static const u32 ti_sn_bridge_dsiclk_lut[] = { 448 468000000, 449 384000000, 450 416000000, 451 486000000, 452 460800000, 453 }; 454 455 static void ti_sn_bridge_set_refclk_freq(struct ti_sn_bridge *pdata) 456 { 457 int i; 458 u32 refclk_rate; 459 const u32 *refclk_lut; 460 size_t refclk_lut_size; 461 462 if (pdata->refclk) { 463 refclk_rate = clk_get_rate(pdata->refclk); 464 refclk_lut = ti_sn_bridge_refclk_lut; 465 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut); 466 clk_prepare_enable(pdata->refclk); 467 } else { 468 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000; 469 refclk_lut = ti_sn_bridge_dsiclk_lut; 470 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut); 471 } 472 473 /* for i equals to refclk_lut_size means default frequency */ 474 for (i = 0; i < refclk_lut_size; i++) 475 if (refclk_lut[i] == refclk_rate) 476 break; 477 478 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK, 479 REFCLK_FREQ(i)); 480 } 481 482 static void ti_sn_bridge_set_dsi_rate(struct ti_sn_bridge *pdata) 483 { 484 unsigned int bit_rate_mhz, clk_freq_mhz; 485 unsigned int val; 486 struct drm_display_mode *mode = 487 &pdata->bridge.encoder->crtc->state->adjusted_mode; 488 489 /* set DSIA clk frequency */ 490 bit_rate_mhz = (mode->clock / 1000) * 491 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); 492 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2); 493 494 /* for each increment in val, frequency increases by 5MHz */ 495 val = (MIN_DSI_CLK_FREQ_MHZ / 5) + 496 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF); 497 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val); 498 } 499 500 static unsigned int ti_sn_bridge_get_bpp(struct ti_sn_bridge *pdata) 501 { 502 if (pdata->connector.display_info.bpc <= 6) 503 return 18; 504 else 505 return 24; 506 } 507 508 /* 509 * LUT index corresponds to register value and 510 * LUT values corresponds to dp data rate supported 511 * by the bridge in Mbps unit. 512 */ 513 static const unsigned int ti_sn_bridge_dp_rate_lut[] = { 514 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 515 }; 516 517 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn_bridge *pdata) 518 { 519 unsigned int bit_rate_khz, dp_rate_mhz; 520 unsigned int i; 521 struct drm_display_mode *mode = 522 &pdata->bridge.encoder->crtc->state->adjusted_mode; 523 524 /* Calculate minimum bit rate based on our pixel clock. */ 525 bit_rate_khz = mode->clock * ti_sn_bridge_get_bpp(pdata); 526 527 /* Calculate minimum DP data rate, taking 80% as per DP spec */ 528 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM, 529 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN); 530 531 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++) 532 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz) 533 break; 534 535 return i; 536 } 537 538 static void ti_sn_bridge_read_valid_rates(struct ti_sn_bridge *pdata, 539 bool rate_valid[]) 540 { 541 unsigned int rate_per_200khz; 542 unsigned int rate_mhz; 543 u8 dpcd_val; 544 int ret; 545 int i, j; 546 547 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val); 548 if (ret != 1) { 549 DRM_DEV_ERROR(pdata->dev, 550 "Can't read eDP rev (%d), assuming 1.1\n", ret); 551 dpcd_val = DP_EDP_11; 552 } 553 554 if (dpcd_val >= DP_EDP_14) { 555 /* eDP 1.4 devices must provide a custom table */ 556 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 557 558 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES, 559 sink_rates, sizeof(sink_rates)); 560 561 if (ret != sizeof(sink_rates)) { 562 DRM_DEV_ERROR(pdata->dev, 563 "Can't read supported rate table (%d)\n", ret); 564 565 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */ 566 memset(sink_rates, 0, sizeof(sink_rates)); 567 } 568 569 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 570 rate_per_200khz = le16_to_cpu(sink_rates[i]); 571 572 if (!rate_per_200khz) 573 break; 574 575 rate_mhz = rate_per_200khz * 200 / 1000; 576 for (j = 0; 577 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); 578 j++) { 579 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz) 580 rate_valid[j] = true; 581 } 582 } 583 584 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) { 585 if (rate_valid[i]) 586 return; 587 } 588 DRM_DEV_ERROR(pdata->dev, 589 "No matching eDP rates in table; falling back\n"); 590 } 591 592 /* On older versions best we can do is use DP_MAX_LINK_RATE */ 593 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val); 594 if (ret != 1) { 595 DRM_DEV_ERROR(pdata->dev, 596 "Can't read max rate (%d); assuming 5.4 GHz\n", 597 ret); 598 dpcd_val = DP_LINK_BW_5_4; 599 } 600 601 switch (dpcd_val) { 602 default: 603 DRM_DEV_ERROR(pdata->dev, 604 "Unexpected max rate (%#x); assuming 5.4 GHz\n", 605 (int)dpcd_val); 606 fallthrough; 607 case DP_LINK_BW_5_4: 608 rate_valid[7] = 1; 609 fallthrough; 610 case DP_LINK_BW_2_7: 611 rate_valid[4] = 1; 612 fallthrough; 613 case DP_LINK_BW_1_62: 614 rate_valid[1] = 1; 615 break; 616 } 617 } 618 619 static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata) 620 { 621 struct drm_display_mode *mode = 622 &pdata->bridge.encoder->crtc->state->adjusted_mode; 623 u8 hsync_polarity = 0, vsync_polarity = 0; 624 625 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 626 hsync_polarity = CHA_HSYNC_POLARITY; 627 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 628 vsync_polarity = CHA_VSYNC_POLARITY; 629 630 ti_sn_bridge_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG, 631 mode->hdisplay); 632 ti_sn_bridge_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG, 633 mode->vdisplay); 634 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG, 635 (mode->hsync_end - mode->hsync_start) & 0xFF); 636 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG, 637 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) | 638 hsync_polarity); 639 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG, 640 (mode->vsync_end - mode->vsync_start) & 0xFF); 641 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG, 642 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) | 643 vsync_polarity); 644 645 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG, 646 (mode->htotal - mode->hsync_end) & 0xFF); 647 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG, 648 (mode->vtotal - mode->vsync_end) & 0xFF); 649 650 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG, 651 (mode->hsync_start - mode->hdisplay) & 0xFF); 652 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG, 653 (mode->vsync_start - mode->vdisplay) & 0xFF); 654 655 usleep_range(10000, 10500); /* 10ms delay recommended by spec */ 656 } 657 658 static unsigned int ti_sn_get_max_lanes(struct ti_sn_bridge *pdata) 659 { 660 u8 data; 661 int ret; 662 663 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data); 664 if (ret != 1) { 665 DRM_DEV_ERROR(pdata->dev, 666 "Can't read lane count (%d); assuming 4\n", ret); 667 return 4; 668 } 669 670 return data & DP_LANE_COUNT_MASK; 671 } 672 673 static int ti_sn_link_training(struct ti_sn_bridge *pdata, int dp_rate_idx, 674 const char **last_err_str) 675 { 676 unsigned int val; 677 int ret; 678 int i; 679 680 /* set dp clk frequency value */ 681 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG, 682 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx)); 683 684 /* enable DP PLL */ 685 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); 686 687 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val, 688 val & DPPLL_SRC_DP_PLL_LOCK, 1000, 689 50 * 1000); 690 if (ret) { 691 *last_err_str = "DP_PLL_LOCK polling failed"; 692 goto exit; 693 } 694 695 /* 696 * We'll try to link train several times. As part of link training 697 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If 698 * the panel isn't ready quite it might respond NAK here which means 699 * we need to try again. 700 */ 701 for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) { 702 /* Semi auto link training mode */ 703 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A); 704 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val, 705 val == ML_TX_MAIN_LINK_OFF || 706 val == ML_TX_NORMAL_MODE, 1000, 707 500 * 1000); 708 if (ret) { 709 *last_err_str = "Training complete polling failed"; 710 } else if (val == ML_TX_MAIN_LINK_OFF) { 711 *last_err_str = "Link training failed, link is off"; 712 ret = -EIO; 713 continue; 714 } 715 716 break; 717 } 718 719 /* If we saw quite a few retries, add a note about it */ 720 if (!ret && i > SN_LINK_TRAINING_TRIES / 2) 721 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i); 722 723 exit: 724 /* Disable the PLL if we failed */ 725 if (ret) 726 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); 727 728 return ret; 729 } 730 731 static void ti_sn_bridge_enable(struct drm_bridge *bridge) 732 { 733 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); 734 bool rate_valid[ARRAY_SIZE(ti_sn_bridge_dp_rate_lut)] = { }; 735 const char *last_err_str = "No supported DP rate"; 736 int dp_rate_idx; 737 unsigned int val; 738 int ret = -EINVAL; 739 int max_dp_lanes; 740 741 max_dp_lanes = ti_sn_get_max_lanes(pdata); 742 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes); 743 744 /* DSI_A lane config */ 745 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes); 746 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG, 747 CHA_DSI_LANES_MASK, val); 748 749 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign); 750 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK, 751 pdata->ln_polrs << LN_POLRS_OFFSET); 752 753 /* set dsi clk frequency value */ 754 ti_sn_bridge_set_dsi_rate(pdata); 755 756 /** 757 * The SN65DSI86 only supports ASSR Display Authentication method and 758 * this method is enabled by default. An eDP panel must support this 759 * authentication method. We need to enable this method in the eDP panel 760 * at DisplayPort address 0x0010A prior to link training. 761 */ 762 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET, 763 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); 764 765 /* Set the DP output format (18 bpp or 24 bpp) */ 766 val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0; 767 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val); 768 769 /* DP lane config */ 770 val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); 771 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 772 val); 773 774 ti_sn_bridge_read_valid_rates(pdata, rate_valid); 775 776 /* Train until we run out of rates */ 777 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata); 778 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); 779 dp_rate_idx++) { 780 if (!rate_valid[dp_rate_idx]) 781 continue; 782 783 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str); 784 if (!ret) 785 break; 786 } 787 if (ret) { 788 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret); 789 return; 790 } 791 792 /* config video parameters */ 793 ti_sn_bridge_set_video_timings(pdata); 794 795 /* enable video stream */ 796 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 797 VSTREAM_ENABLE); 798 799 drm_panel_enable(pdata->panel); 800 } 801 802 static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge) 803 { 804 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); 805 806 pm_runtime_get_sync(pdata->dev); 807 808 /* configure bridge ref_clk */ 809 ti_sn_bridge_set_refclk_freq(pdata); 810 811 /* 812 * HPD on this bridge chip is a bit useless. This is an eDP bridge 813 * so the HPD is an internal signal that's only there to signal that 814 * the panel is done powering up. ...but the bridge chip debounces 815 * this signal by between 100 ms and 400 ms (depending on process, 816 * voltage, and temperate--I measured it at about 200 ms). One 817 * particular panel asserted HPD 84 ms after it was powered on meaning 818 * that we saw HPD 284 ms after power on. ...but the same panel said 819 * that instead of looking at HPD you could just hardcode a delay of 820 * 200 ms. We'll assume that the panel driver will have the hardcoded 821 * delay in its prepare and always disable HPD. 822 * 823 * If HPD somehow makes sense on some future panel we'll have to 824 * change this to be conditional on someone specifying that HPD should 825 * be used. 826 */ 827 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE, 828 HPD_DISABLE); 829 830 drm_panel_prepare(pdata->panel); 831 } 832 833 static void ti_sn_bridge_post_disable(struct drm_bridge *bridge) 834 { 835 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); 836 837 clk_disable_unprepare(pdata->refclk); 838 839 pm_runtime_put_sync(pdata->dev); 840 } 841 842 static const struct drm_bridge_funcs ti_sn_bridge_funcs = { 843 .attach = ti_sn_bridge_attach, 844 .pre_enable = ti_sn_bridge_pre_enable, 845 .enable = ti_sn_bridge_enable, 846 .disable = ti_sn_bridge_disable, 847 .post_disable = ti_sn_bridge_post_disable, 848 }; 849 850 static struct ti_sn_bridge *aux_to_ti_sn_bridge(struct drm_dp_aux *aux) 851 { 852 return container_of(aux, struct ti_sn_bridge, aux); 853 } 854 855 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux, 856 struct drm_dp_aux_msg *msg) 857 { 858 struct ti_sn_bridge *pdata = aux_to_ti_sn_bridge(aux); 859 u32 request = msg->request & ~DP_AUX_I2C_MOT; 860 u32 request_val = AUX_CMD_REQ(msg->request); 861 u8 *buf = (u8 *)msg->buffer; 862 unsigned int val; 863 int ret, i; 864 865 if (msg->size > SN_AUX_MAX_PAYLOAD_BYTES) 866 return -EINVAL; 867 868 switch (request) { 869 case DP_AUX_NATIVE_WRITE: 870 case DP_AUX_I2C_WRITE: 871 case DP_AUX_NATIVE_READ: 872 case DP_AUX_I2C_READ: 873 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val); 874 break; 875 default: 876 return -EINVAL; 877 } 878 879 regmap_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, 880 (msg->address >> 16) & 0xF); 881 regmap_write(pdata->regmap, SN_AUX_ADDR_15_8_REG, 882 (msg->address >> 8) & 0xFF); 883 regmap_write(pdata->regmap, SN_AUX_ADDR_7_0_REG, msg->address & 0xFF); 884 885 regmap_write(pdata->regmap, SN_AUX_LENGTH_REG, msg->size); 886 887 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) { 888 for (i = 0; i < msg->size; i++) 889 regmap_write(pdata->regmap, SN_AUX_WDATA_REG(i), 890 buf[i]); 891 } 892 893 /* Clear old status bits before start so we don't get confused */ 894 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG, 895 AUX_IRQ_STATUS_NAT_I2C_FAIL | 896 AUX_IRQ_STATUS_AUX_RPLY_TOUT | 897 AUX_IRQ_STATUS_AUX_SHORT); 898 899 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND); 900 901 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val, 902 !(val & AUX_CMD_SEND), 200, 903 50 * 1000); 904 if (ret) 905 return ret; 906 907 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val); 908 if (ret) 909 return ret; 910 else if ((val & AUX_IRQ_STATUS_NAT_I2C_FAIL) 911 || (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) 912 || (val & AUX_IRQ_STATUS_AUX_SHORT)) 913 return -ENXIO; 914 915 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) 916 return msg->size; 917 918 for (i = 0; i < msg->size; i++) { 919 unsigned int val; 920 ret = regmap_read(pdata->regmap, SN_AUX_RDATA_REG(i), 921 &val); 922 if (ret) 923 return ret; 924 925 WARN_ON(val & ~0xFF); 926 buf[i] = (u8)(val & 0xFF); 927 } 928 929 return msg->size; 930 } 931 932 static int ti_sn_bridge_parse_dsi_host(struct ti_sn_bridge *pdata) 933 { 934 struct device_node *np = pdata->dev->of_node; 935 936 pdata->host_node = of_graph_get_remote_node(np, 0, 0); 937 938 if (!pdata->host_node) { 939 DRM_ERROR("remote dsi host node not found\n"); 940 return -ENODEV; 941 } 942 943 return 0; 944 } 945 946 #if defined(CONFIG_OF_GPIO) 947 948 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip, 949 const struct of_phandle_args *gpiospec, 950 u32 *flags) 951 { 952 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells)) 953 return -EINVAL; 954 955 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1) 956 return -EINVAL; 957 958 if (flags) 959 *flags = gpiospec->args[1]; 960 961 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET; 962 } 963 964 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip, 965 unsigned int offset) 966 { 967 struct ti_sn_bridge *pdata = gpiochip_get_data(chip); 968 969 /* 970 * We already have to keep track of the direction because we use 971 * that to figure out whether we've powered the device. We can 972 * just return that rather than (maybe) powering up the device 973 * to ask its direction. 974 */ 975 return test_bit(offset, pdata->gchip_output) ? 976 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 977 } 978 979 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset) 980 { 981 struct ti_sn_bridge *pdata = gpiochip_get_data(chip); 982 unsigned int val; 983 int ret; 984 985 /* 986 * When the pin is an input we don't forcibly keep the bridge 987 * powered--we just power it on to read the pin. NOTE: part of 988 * the reason this works is that the bridge defaults (when 989 * powered back on) to all 4 GPIOs being configured as GPIO input. 990 * Also note that if something else is keeping the chip powered the 991 * pm_runtime functions are lightweight increments of a refcount. 992 */ 993 pm_runtime_get_sync(pdata->dev); 994 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val); 995 pm_runtime_put(pdata->dev); 996 997 if (ret) 998 return ret; 999 1000 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset)); 1001 } 1002 1003 static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset, 1004 int val) 1005 { 1006 struct ti_sn_bridge *pdata = gpiochip_get_data(chip); 1007 int ret; 1008 1009 if (!test_bit(offset, pdata->gchip_output)) { 1010 dev_err(pdata->dev, "Ignoring GPIO set while input\n"); 1011 return; 1012 } 1013 1014 val &= 1; 1015 ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG, 1016 BIT(SN_GPIO_OUTPUT_SHIFT + offset), 1017 val << (SN_GPIO_OUTPUT_SHIFT + offset)); 1018 if (ret) 1019 dev_warn(pdata->dev, 1020 "Failed to set bridge GPIO %u: %d\n", offset, ret); 1021 } 1022 1023 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip, 1024 unsigned int offset) 1025 { 1026 struct ti_sn_bridge *pdata = gpiochip_get_data(chip); 1027 int shift = offset * 2; 1028 int ret; 1029 1030 if (!test_and_clear_bit(offset, pdata->gchip_output)) 1031 return 0; 1032 1033 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1034 SN_GPIO_MUX_MASK << shift, 1035 SN_GPIO_MUX_INPUT << shift); 1036 if (ret) { 1037 set_bit(offset, pdata->gchip_output); 1038 return ret; 1039 } 1040 1041 /* 1042 * NOTE: if nobody else is powering the device this may fully power 1043 * it off and when it comes back it will have lost all state, but 1044 * that's OK because the default is input and we're now an input. 1045 */ 1046 pm_runtime_put(pdata->dev); 1047 1048 return 0; 1049 } 1050 1051 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip, 1052 unsigned int offset, int val) 1053 { 1054 struct ti_sn_bridge *pdata = gpiochip_get_data(chip); 1055 int shift = offset * 2; 1056 int ret; 1057 1058 if (test_and_set_bit(offset, pdata->gchip_output)) 1059 return 0; 1060 1061 pm_runtime_get_sync(pdata->dev); 1062 1063 /* Set value first to avoid glitching */ 1064 ti_sn_bridge_gpio_set(chip, offset, val); 1065 1066 /* Set direction */ 1067 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1068 SN_GPIO_MUX_MASK << shift, 1069 SN_GPIO_MUX_OUTPUT << shift); 1070 if (ret) { 1071 clear_bit(offset, pdata->gchip_output); 1072 pm_runtime_put(pdata->dev); 1073 } 1074 1075 return ret; 1076 } 1077 1078 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset) 1079 { 1080 /* We won't keep pm_runtime if we're input, so switch there on free */ 1081 ti_sn_bridge_gpio_direction_input(chip, offset); 1082 } 1083 1084 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = { 1085 "GPIO1", "GPIO2", "GPIO3", "GPIO4" 1086 }; 1087 1088 static int ti_sn_setup_gpio_controller(struct ti_sn_bridge *pdata) 1089 { 1090 int ret; 1091 1092 /* Only init if someone is going to use us as a GPIO controller */ 1093 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller")) 1094 return 0; 1095 1096 pdata->gchip.label = dev_name(pdata->dev); 1097 pdata->gchip.parent = pdata->dev; 1098 pdata->gchip.owner = THIS_MODULE; 1099 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate; 1100 pdata->gchip.of_gpio_n_cells = 2; 1101 pdata->gchip.free = ti_sn_bridge_gpio_free; 1102 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction; 1103 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input; 1104 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output; 1105 pdata->gchip.get = ti_sn_bridge_gpio_get; 1106 pdata->gchip.set = ti_sn_bridge_gpio_set; 1107 pdata->gchip.can_sleep = true; 1108 pdata->gchip.names = ti_sn_bridge_gpio_names; 1109 pdata->gchip.ngpio = SN_NUM_GPIOS; 1110 pdata->gchip.base = -1; 1111 ret = devm_gpiochip_add_data(pdata->dev, &pdata->gchip, pdata); 1112 if (ret) 1113 dev_err(pdata->dev, "can't add gpio chip\n"); 1114 1115 return ret; 1116 } 1117 1118 #else 1119 1120 static inline int ti_sn_setup_gpio_controller(struct ti_sn_bridge *pdata) 1121 { 1122 return 0; 1123 } 1124 1125 #endif 1126 1127 static void ti_sn_bridge_parse_lanes(struct ti_sn_bridge *pdata, 1128 struct device_node *np) 1129 { 1130 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 }; 1131 u32 lane_polarities[SN_MAX_DP_LANES] = { }; 1132 struct device_node *endpoint; 1133 u8 ln_assign = 0; 1134 u8 ln_polrs = 0; 1135 int dp_lanes; 1136 int i; 1137 1138 /* 1139 * Read config from the device tree about lane remapping and lane 1140 * polarities. These are optional and we assume identity map and 1141 * normal polarity if nothing is specified. It's OK to specify just 1142 * data-lanes but not lane-polarities but not vice versa. 1143 * 1144 * Error checking is light (we just make sure we don't crash or 1145 * buffer overrun) and we assume dts is well formed and specifying 1146 * mappings that the hardware supports. 1147 */ 1148 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1149 dp_lanes = of_property_count_u32_elems(endpoint, "data-lanes"); 1150 if (dp_lanes > 0 && dp_lanes <= SN_MAX_DP_LANES) { 1151 of_property_read_u32_array(endpoint, "data-lanes", 1152 lane_assignments, dp_lanes); 1153 of_property_read_u32_array(endpoint, "lane-polarities", 1154 lane_polarities, dp_lanes); 1155 } else { 1156 dp_lanes = SN_MAX_DP_LANES; 1157 } 1158 of_node_put(endpoint); 1159 1160 /* 1161 * Convert into register format. Loop over all lanes even if 1162 * data-lanes had fewer elements so that we nicely initialize 1163 * the LN_ASSIGN register. 1164 */ 1165 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) { 1166 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i]; 1167 ln_polrs = ln_polrs << 1 | lane_polarities[i]; 1168 } 1169 1170 /* Stash in our struct for when we power on */ 1171 pdata->dp_lanes = dp_lanes; 1172 pdata->ln_assign = ln_assign; 1173 pdata->ln_polrs = ln_polrs; 1174 } 1175 1176 static int ti_sn_bridge_probe(struct i2c_client *client, 1177 const struct i2c_device_id *id) 1178 { 1179 struct ti_sn_bridge *pdata; 1180 int ret; 1181 1182 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1183 DRM_ERROR("device doesn't support I2C\n"); 1184 return -ENODEV; 1185 } 1186 1187 pdata = devm_kzalloc(&client->dev, sizeof(struct ti_sn_bridge), 1188 GFP_KERNEL); 1189 if (!pdata) 1190 return -ENOMEM; 1191 1192 pdata->regmap = devm_regmap_init_i2c(client, 1193 &ti_sn_bridge_regmap_config); 1194 if (IS_ERR(pdata->regmap)) { 1195 DRM_ERROR("regmap i2c init failed\n"); 1196 return PTR_ERR(pdata->regmap); 1197 } 1198 1199 pdata->dev = &client->dev; 1200 1201 ret = drm_of_find_panel_or_bridge(pdata->dev->of_node, 1, 0, 1202 &pdata->panel, NULL); 1203 if (ret) { 1204 DRM_ERROR("could not find any panel node\n"); 1205 return ret; 1206 } 1207 1208 dev_set_drvdata(&client->dev, pdata); 1209 1210 pdata->enable_gpio = devm_gpiod_get(pdata->dev, "enable", 1211 GPIOD_OUT_LOW); 1212 if (IS_ERR(pdata->enable_gpio)) { 1213 DRM_ERROR("failed to get enable gpio from DT\n"); 1214 ret = PTR_ERR(pdata->enable_gpio); 1215 return ret; 1216 } 1217 1218 ti_sn_bridge_parse_lanes(pdata, client->dev.of_node); 1219 1220 ret = ti_sn_bridge_parse_regulators(pdata); 1221 if (ret) { 1222 DRM_ERROR("failed to parse regulators\n"); 1223 return ret; 1224 } 1225 1226 pdata->refclk = devm_clk_get(pdata->dev, "refclk"); 1227 if (IS_ERR(pdata->refclk)) { 1228 ret = PTR_ERR(pdata->refclk); 1229 if (ret == -EPROBE_DEFER) 1230 return ret; 1231 DRM_DEBUG_KMS("refclk not found\n"); 1232 pdata->refclk = NULL; 1233 } 1234 1235 ret = ti_sn_bridge_parse_dsi_host(pdata); 1236 if (ret) 1237 return ret; 1238 1239 pm_runtime_enable(pdata->dev); 1240 1241 ret = ti_sn_setup_gpio_controller(pdata); 1242 if (ret) { 1243 pm_runtime_disable(pdata->dev); 1244 return ret; 1245 } 1246 1247 i2c_set_clientdata(client, pdata); 1248 1249 pdata->aux.name = "ti-sn65dsi86-aux"; 1250 pdata->aux.dev = pdata->dev; 1251 pdata->aux.transfer = ti_sn_aux_transfer; 1252 drm_dp_aux_register(&pdata->aux); 1253 1254 pdata->bridge.funcs = &ti_sn_bridge_funcs; 1255 pdata->bridge.of_node = client->dev.of_node; 1256 1257 drm_bridge_add(&pdata->bridge); 1258 1259 ti_sn_debugfs_init(pdata); 1260 1261 return 0; 1262 } 1263 1264 static int ti_sn_bridge_remove(struct i2c_client *client) 1265 { 1266 struct ti_sn_bridge *pdata = i2c_get_clientdata(client); 1267 1268 if (!pdata) 1269 return -EINVAL; 1270 1271 ti_sn_debugfs_remove(pdata); 1272 1273 of_node_put(pdata->host_node); 1274 1275 pm_runtime_disable(pdata->dev); 1276 1277 if (pdata->dsi) { 1278 mipi_dsi_detach(pdata->dsi); 1279 mipi_dsi_device_unregister(pdata->dsi); 1280 } 1281 1282 drm_bridge_remove(&pdata->bridge); 1283 1284 return 0; 1285 } 1286 1287 static struct i2c_device_id ti_sn_bridge_id[] = { 1288 { "ti,sn65dsi86", 0}, 1289 {}, 1290 }; 1291 MODULE_DEVICE_TABLE(i2c, ti_sn_bridge_id); 1292 1293 static const struct of_device_id ti_sn_bridge_match_table[] = { 1294 {.compatible = "ti,sn65dsi86"}, 1295 {}, 1296 }; 1297 MODULE_DEVICE_TABLE(of, ti_sn_bridge_match_table); 1298 1299 static struct i2c_driver ti_sn_bridge_driver = { 1300 .driver = { 1301 .name = "ti_sn65dsi86", 1302 .of_match_table = ti_sn_bridge_match_table, 1303 .pm = &ti_sn_bridge_pm_ops, 1304 }, 1305 .probe = ti_sn_bridge_probe, 1306 .remove = ti_sn_bridge_remove, 1307 .id_table = ti_sn_bridge_id, 1308 }; 1309 module_i2c_driver(ti_sn_bridge_driver); 1310 1311 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>"); 1312 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver"); 1313 MODULE_LICENSE("GPL v2"); 1314