1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * TI SN65DSI83,84,85 driver 4 * 5 * Currently supported: 6 * - SN65DSI83 7 * = 1x Single-link DSI ~ 1x Single-link LVDS 8 * - Supported 9 * - Single-link LVDS mode tested 10 * - SN65DSI84 11 * = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS 12 * - Supported 13 * - Dual-link LVDS mode tested 14 * - 2x Single-link LVDS mode unsupported 15 * (should be easy to add by someone who has the HW) 16 * - SN65DSI85 17 * = 2x Single-link or 1x Dual-link DSI ~ 2x Single-link or 1x Dual-link LVDS 18 * - Unsupported 19 * (should be easy to add by someone who has the HW) 20 * 21 * Copyright (C) 2021 Marek Vasut <marex@denx.de> 22 * 23 * Based on previous work of: 24 * Valentin Raevsky <valentin@compulab.co.il> 25 * Philippe Schenker <philippe.schenker@toradex.com> 26 */ 27 28 #include <linux/bits.h> 29 #include <linux/clk.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/i2c.h> 32 #include <linux/module.h> 33 #include <linux/of_device.h> 34 #include <linux/of_graph.h> 35 #include <linux/regmap.h> 36 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_bridge.h> 39 #include <drm/drm_mipi_dsi.h> 40 #include <drm/drm_of.h> 41 #include <drm/drm_panel.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_probe_helper.h> 44 45 /* ID registers */ 46 #define REG_ID(n) (0x00 + (n)) 47 /* Reset and clock registers */ 48 #define REG_RC_RESET 0x09 49 #define REG_RC_RESET_SOFT_RESET BIT(0) 50 #define REG_RC_LVDS_PLL 0x0a 51 #define REG_RC_LVDS_PLL_PLL_EN_STAT BIT(7) 52 #define REG_RC_LVDS_PLL_LVDS_CLK_RANGE(n) (((n) & 0x7) << 1) 53 #define REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY BIT(0) 54 #define REG_RC_DSI_CLK 0x0b 55 #define REG_RC_DSI_CLK_DSI_CLK_DIVIDER(n) (((n) & 0x1f) << 3) 56 #define REG_RC_DSI_CLK_REFCLK_MULTIPLIER(n) ((n) & 0x3) 57 #define REG_RC_PLL_EN 0x0d 58 #define REG_RC_PLL_EN_PLL_EN BIT(0) 59 /* DSI registers */ 60 #define REG_DSI_LANE 0x10 61 #define REG_DSI_LANE_LEFT_RIGHT_PIXELS BIT(7) /* DSI85-only */ 62 #define REG_DSI_LANE_DSI_CHANNEL_MODE_DUAL 0 /* DSI85-only */ 63 #define REG_DSI_LANE_DSI_CHANNEL_MODE_2SINGLE BIT(6) /* DSI85-only */ 64 #define REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE BIT(5) 65 #define REG_DSI_LANE_CHA_DSI_LANES(n) (((n) & 0x3) << 3) 66 #define REG_DSI_LANE_CHB_DSI_LANES(n) (((n) & 0x3) << 1) 67 #define REG_DSI_LANE_SOT_ERR_TOL_DIS BIT(0) 68 #define REG_DSI_EQ 0x11 69 #define REG_DSI_EQ_CHA_DSI_DATA_EQ(n) (((n) & 0x3) << 6) 70 #define REG_DSI_EQ_CHA_DSI_CLK_EQ(n) (((n) & 0x3) << 2) 71 #define REG_DSI_CLK 0x12 72 #define REG_DSI_CLK_CHA_DSI_CLK_RANGE(n) ((n) & 0xff) 73 /* LVDS registers */ 74 #define REG_LVDS_FMT 0x18 75 #define REG_LVDS_FMT_DE_NEG_POLARITY BIT(7) 76 #define REG_LVDS_FMT_HS_NEG_POLARITY BIT(6) 77 #define REG_LVDS_FMT_VS_NEG_POLARITY BIT(5) 78 #define REG_LVDS_FMT_LVDS_LINK_CFG BIT(4) /* 0:AB 1:A-only */ 79 #define REG_LVDS_FMT_CHA_24BPP_MODE BIT(3) 80 #define REG_LVDS_FMT_CHB_24BPP_MODE BIT(2) 81 #define REG_LVDS_FMT_CHA_24BPP_FORMAT1 BIT(1) 82 #define REG_LVDS_FMT_CHB_24BPP_FORMAT1 BIT(0) 83 #define REG_LVDS_VCOM 0x19 84 #define REG_LVDS_VCOM_CHA_LVDS_VOCM BIT(6) 85 #define REG_LVDS_VCOM_CHB_LVDS_VOCM BIT(4) 86 #define REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(n) (((n) & 0x3) << 2) 87 #define REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(n) ((n) & 0x3) 88 #define REG_LVDS_LANE 0x1a 89 #define REG_LVDS_LANE_EVEN_ODD_SWAP BIT(6) 90 #define REG_LVDS_LANE_CHA_REVERSE_LVDS BIT(5) 91 #define REG_LVDS_LANE_CHB_REVERSE_LVDS BIT(4) 92 #define REG_LVDS_LANE_CHA_LVDS_TERM BIT(1) 93 #define REG_LVDS_LANE_CHB_LVDS_TERM BIT(0) 94 #define REG_LVDS_CM 0x1b 95 #define REG_LVDS_CM_CHA_LVDS_CM_ADJUST(n) (((n) & 0x3) << 4) 96 #define REG_LVDS_CM_CHB_LVDS_CM_ADJUST(n) ((n) & 0x3) 97 /* Video registers */ 98 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW 0x20 99 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH 0x21 100 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW 0x24 101 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH 0x25 102 #define REG_VID_CHA_SYNC_DELAY_LOW 0x28 103 #define REG_VID_CHA_SYNC_DELAY_HIGH 0x29 104 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW 0x2c 105 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH 0x2d 106 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW 0x30 107 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH 0x31 108 #define REG_VID_CHA_HORIZONTAL_BACK_PORCH 0x34 109 #define REG_VID_CHA_VERTICAL_BACK_PORCH 0x36 110 #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH 0x38 111 #define REG_VID_CHA_VERTICAL_FRONT_PORCH 0x3a 112 #define REG_VID_CHA_TEST_PATTERN 0x3c 113 /* IRQ registers */ 114 #define REG_IRQ_GLOBAL 0xe0 115 #define REG_IRQ_GLOBAL_IRQ_EN BIT(0) 116 #define REG_IRQ_EN 0xe1 117 #define REG_IRQ_EN_CHA_SYNCH_ERR_EN BIT(7) 118 #define REG_IRQ_EN_CHA_CRC_ERR_EN BIT(6) 119 #define REG_IRQ_EN_CHA_UNC_ECC_ERR_EN BIT(5) 120 #define REG_IRQ_EN_CHA_COR_ECC_ERR_EN BIT(4) 121 #define REG_IRQ_EN_CHA_LLP_ERR_EN BIT(3) 122 #define REG_IRQ_EN_CHA_SOT_BIT_ERR_EN BIT(2) 123 #define REG_IRQ_EN_CHA_PLL_UNLOCK_EN BIT(0) 124 #define REG_IRQ_STAT 0xe5 125 #define REG_IRQ_STAT_CHA_SYNCH_ERR BIT(7) 126 #define REG_IRQ_STAT_CHA_CRC_ERR BIT(6) 127 #define REG_IRQ_STAT_CHA_UNC_ECC_ERR BIT(5) 128 #define REG_IRQ_STAT_CHA_COR_ECC_ERR BIT(4) 129 #define REG_IRQ_STAT_CHA_LLP_ERR BIT(3) 130 #define REG_IRQ_STAT_CHA_SOT_BIT_ERR BIT(2) 131 #define REG_IRQ_STAT_CHA_PLL_UNLOCK BIT(0) 132 133 enum sn65dsi83_model { 134 MODEL_SN65DSI83, 135 MODEL_SN65DSI84, 136 }; 137 138 struct sn65dsi83 { 139 struct drm_bridge bridge; 140 struct device *dev; 141 struct regmap *regmap; 142 struct device_node *host_node; 143 struct mipi_dsi_device *dsi; 144 struct drm_bridge *panel_bridge; 145 struct gpio_desc *enable_gpio; 146 int dsi_lanes; 147 bool lvds_dual_link; 148 bool lvds_dual_link_even_odd_swap; 149 }; 150 151 static const struct regmap_range sn65dsi83_readable_ranges[] = { 152 regmap_reg_range(REG_ID(0), REG_ID(8)), 153 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_DSI_CLK), 154 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN), 155 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK), 156 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM), 157 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 158 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH), 159 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 160 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH), 161 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW, 162 REG_VID_CHA_SYNC_DELAY_HIGH), 163 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 164 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH), 165 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 166 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH), 167 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH, 168 REG_VID_CHA_HORIZONTAL_BACK_PORCH), 169 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH, 170 REG_VID_CHA_VERTICAL_BACK_PORCH), 171 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 172 REG_VID_CHA_HORIZONTAL_FRONT_PORCH), 173 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH, 174 REG_VID_CHA_VERTICAL_FRONT_PORCH), 175 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN), 176 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN), 177 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 178 }; 179 180 static const struct regmap_access_table sn65dsi83_readable_table = { 181 .yes_ranges = sn65dsi83_readable_ranges, 182 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_readable_ranges), 183 }; 184 185 static const struct regmap_range sn65dsi83_writeable_ranges[] = { 186 regmap_reg_range(REG_RC_RESET, REG_RC_DSI_CLK), 187 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN), 188 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK), 189 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM), 190 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 191 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH), 192 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 193 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH), 194 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW, 195 REG_VID_CHA_SYNC_DELAY_HIGH), 196 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 197 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH), 198 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 199 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH), 200 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH, 201 REG_VID_CHA_HORIZONTAL_BACK_PORCH), 202 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH, 203 REG_VID_CHA_VERTICAL_BACK_PORCH), 204 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 205 REG_VID_CHA_HORIZONTAL_FRONT_PORCH), 206 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH, 207 REG_VID_CHA_VERTICAL_FRONT_PORCH), 208 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN), 209 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN), 210 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 211 }; 212 213 static const struct regmap_access_table sn65dsi83_writeable_table = { 214 .yes_ranges = sn65dsi83_writeable_ranges, 215 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_writeable_ranges), 216 }; 217 218 static const struct regmap_range sn65dsi83_volatile_ranges[] = { 219 regmap_reg_range(REG_RC_RESET, REG_RC_RESET), 220 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_LVDS_PLL), 221 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 222 }; 223 224 static const struct regmap_access_table sn65dsi83_volatile_table = { 225 .yes_ranges = sn65dsi83_volatile_ranges, 226 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_volatile_ranges), 227 }; 228 229 static const struct regmap_config sn65dsi83_regmap_config = { 230 .reg_bits = 8, 231 .val_bits = 8, 232 .rd_table = &sn65dsi83_readable_table, 233 .wr_table = &sn65dsi83_writeable_table, 234 .volatile_table = &sn65dsi83_volatile_table, 235 .cache_type = REGCACHE_RBTREE, 236 .max_register = REG_IRQ_STAT, 237 }; 238 239 static struct sn65dsi83 *bridge_to_sn65dsi83(struct drm_bridge *bridge) 240 { 241 return container_of(bridge, struct sn65dsi83, bridge); 242 } 243 244 static int sn65dsi83_attach(struct drm_bridge *bridge, 245 enum drm_bridge_attach_flags flags) 246 { 247 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 248 struct device *dev = ctx->dev; 249 struct mipi_dsi_device *dsi; 250 struct mipi_dsi_host *host; 251 int ret = 0; 252 253 const struct mipi_dsi_device_info info = { 254 .type = "sn65dsi83", 255 .channel = 0, 256 .node = NULL, 257 }; 258 259 host = of_find_mipi_dsi_host_by_node(ctx->host_node); 260 if (!host) { 261 dev_err(dev, "failed to find dsi host\n"); 262 return -EPROBE_DEFER; 263 } 264 265 dsi = mipi_dsi_device_register_full(host, &info); 266 if (IS_ERR(dsi)) { 267 return dev_err_probe(dev, PTR_ERR(dsi), 268 "failed to create dsi device\n"); 269 } 270 271 ctx->dsi = dsi; 272 273 dsi->lanes = ctx->dsi_lanes; 274 dsi->format = MIPI_DSI_FMT_RGB888; 275 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST; 276 277 ret = mipi_dsi_attach(dsi); 278 if (ret < 0) { 279 dev_err(dev, "failed to attach dsi to host\n"); 280 goto err_dsi_attach; 281 } 282 283 return drm_bridge_attach(bridge->encoder, ctx->panel_bridge, 284 &ctx->bridge, flags); 285 286 err_dsi_attach: 287 mipi_dsi_device_unregister(dsi); 288 return ret; 289 } 290 291 static void sn65dsi83_detach(struct drm_bridge *bridge) 292 { 293 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 294 295 if (!ctx->dsi) 296 return; 297 298 mipi_dsi_detach(ctx->dsi); 299 mipi_dsi_device_unregister(ctx->dsi); 300 drm_bridge_remove(&ctx->bridge); 301 ctx->dsi = NULL; 302 } 303 304 static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, 305 struct drm_bridge_state *old_bridge_state) 306 { 307 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 308 309 /* 310 * Reset the chip, pull EN line low for t_reset=10ms, 311 * then high for t_en=1ms. 312 */ 313 regcache_mark_dirty(ctx->regmap); 314 gpiod_set_value(ctx->enable_gpio, 0); 315 usleep_range(10000, 11000); 316 gpiod_set_value(ctx->enable_gpio, 1); 317 usleep_range(1000, 1100); 318 } 319 320 static u8 sn65dsi83_get_lvds_range(struct sn65dsi83 *ctx, 321 const struct drm_display_mode *mode) 322 { 323 /* 324 * The encoding of the LVDS_CLK_RANGE is as follows: 325 * 000 - 25 MHz <= LVDS_CLK < 37.5 MHz 326 * 001 - 37.5 MHz <= LVDS_CLK < 62.5 MHz 327 * 010 - 62.5 MHz <= LVDS_CLK < 87.5 MHz 328 * 011 - 87.5 MHz <= LVDS_CLK < 112.5 MHz 329 * 100 - 112.5 MHz <= LVDS_CLK < 137.5 MHz 330 * 101 - 137.5 MHz <= LVDS_CLK <= 154 MHz 331 * which is a range of 12.5MHz..162.5MHz in 50MHz steps, except that 332 * the ends of the ranges are clamped to the supported range. Since 333 * sn65dsi83_mode_valid() already filters the valid modes and limits 334 * the clock to 25..154 MHz, the range calculation can be simplified 335 * as follows: 336 */ 337 int mode_clock = mode->clock; 338 339 if (ctx->lvds_dual_link) 340 mode_clock /= 2; 341 342 return (mode_clock - 12500) / 25000; 343 } 344 345 static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx, 346 const struct drm_display_mode *mode) 347 { 348 /* 349 * The encoding of the CHA_DSI_CLK_RANGE is as follows: 350 * 0x00 through 0x07 - Reserved 351 * 0x08 - 40 <= DSI_CLK < 45 MHz 352 * 0x09 - 45 <= DSI_CLK < 50 MHz 353 * ... 354 * 0x63 - 495 <= DSI_CLK < 500 MHz 355 * 0x64 - 500 MHz 356 * 0x65 through 0xFF - Reserved 357 * which is DSI clock in 5 MHz steps, clamped to 40..500 MHz. 358 * The DSI clock are calculated as: 359 * DSI_CLK = mode clock * bpp / dsi_data_lanes / 2 360 * the 2 is there because the bus is DDR. 361 */ 362 return DIV_ROUND_UP(clamp((unsigned int)mode->clock * 363 mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) / 364 ctx->dsi_lanes / 2, 40000U, 500000U), 5000U); 365 } 366 367 static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx) 368 { 369 /* The divider is (DSI_CLK / LVDS_CLK) - 1, which really is: */ 370 unsigned int dsi_div = mipi_dsi_pixel_format_to_bpp(ctx->dsi->format); 371 372 dsi_div /= ctx->dsi_lanes; 373 374 if (!ctx->lvds_dual_link) 375 dsi_div /= 2; 376 377 return dsi_div - 1; 378 } 379 380 static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, 381 struct drm_bridge_state *old_bridge_state) 382 { 383 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 384 struct drm_atomic_state *state = old_bridge_state->base.state; 385 const struct drm_bridge_state *bridge_state; 386 const struct drm_crtc_state *crtc_state; 387 const struct drm_display_mode *mode; 388 struct drm_connector *connector; 389 struct drm_crtc *crtc; 390 bool lvds_format_24bpp; 391 bool lvds_format_jeida; 392 unsigned int pval; 393 __le16 le16val; 394 u16 val; 395 int ret; 396 397 /* Get the LVDS format from the bridge state. */ 398 bridge_state = drm_atomic_get_new_bridge_state(state, bridge); 399 400 switch (bridge_state->output_bus_cfg.format) { 401 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 402 lvds_format_24bpp = false; 403 lvds_format_jeida = true; 404 break; 405 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 406 lvds_format_24bpp = true; 407 lvds_format_jeida = true; 408 break; 409 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 410 lvds_format_24bpp = true; 411 lvds_format_jeida = false; 412 break; 413 default: 414 /* 415 * Some bridges still don't set the correct 416 * LVDS bus pixel format, use SPWG24 default 417 * format until those are fixed. 418 */ 419 lvds_format_24bpp = true; 420 lvds_format_jeida = false; 421 dev_warn(ctx->dev, 422 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n", 423 bridge_state->output_bus_cfg.format); 424 break; 425 } 426 427 /* 428 * Retrieve the CRTC adjusted mode. This requires a little dance to go 429 * from the bridge to the encoder, to the connector and to the CRTC. 430 */ 431 connector = drm_atomic_get_new_connector_for_encoder(state, 432 bridge->encoder); 433 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 434 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 435 mode = &crtc_state->adjusted_mode; 436 437 /* Clear reset, disable PLL */ 438 regmap_write(ctx->regmap, REG_RC_RESET, 0x00); 439 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); 440 441 /* Reference clock derived from DSI link clock. */ 442 regmap_write(ctx->regmap, REG_RC_LVDS_PLL, 443 REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx, mode)) | 444 REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY); 445 regmap_write(ctx->regmap, REG_DSI_CLK, 446 REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx, mode))); 447 regmap_write(ctx->regmap, REG_RC_DSI_CLK, 448 REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx))); 449 450 /* Set number of DSI lanes and LVDS link config. */ 451 regmap_write(ctx->regmap, REG_DSI_LANE, 452 REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE | 453 REG_DSI_LANE_CHA_DSI_LANES(~(ctx->dsi_lanes - 1)) | 454 /* CHB is DSI85-only, set to default on DSI83/DSI84 */ 455 REG_DSI_LANE_CHB_DSI_LANES(3)); 456 /* No equalization. */ 457 regmap_write(ctx->regmap, REG_DSI_EQ, 0x00); 458 459 /* Set up sync signal polarity. */ 460 val = (mode->flags & DRM_MODE_FLAG_NHSYNC ? 461 REG_LVDS_FMT_HS_NEG_POLARITY : 0) | 462 (mode->flags & DRM_MODE_FLAG_NVSYNC ? 463 REG_LVDS_FMT_VS_NEG_POLARITY : 0); 464 465 /* Set up bits-per-pixel, 18bpp or 24bpp. */ 466 if (lvds_format_24bpp) { 467 val |= REG_LVDS_FMT_CHA_24BPP_MODE; 468 if (ctx->lvds_dual_link) 469 val |= REG_LVDS_FMT_CHB_24BPP_MODE; 470 } 471 472 /* Set up LVDS format, JEIDA/Format 1 or SPWG/Format 2 */ 473 if (lvds_format_jeida) { 474 val |= REG_LVDS_FMT_CHA_24BPP_FORMAT1; 475 if (ctx->lvds_dual_link) 476 val |= REG_LVDS_FMT_CHB_24BPP_FORMAT1; 477 } 478 479 /* Set up LVDS output config (DSI84,DSI85) */ 480 if (!ctx->lvds_dual_link) 481 val |= REG_LVDS_FMT_LVDS_LINK_CFG; 482 483 regmap_write(ctx->regmap, REG_LVDS_FMT, val); 484 regmap_write(ctx->regmap, REG_LVDS_VCOM, 0x05); 485 regmap_write(ctx->regmap, REG_LVDS_LANE, 486 (ctx->lvds_dual_link_even_odd_swap ? 487 REG_LVDS_LANE_EVEN_ODD_SWAP : 0) | 488 REG_LVDS_LANE_CHA_LVDS_TERM | 489 REG_LVDS_LANE_CHB_LVDS_TERM); 490 regmap_write(ctx->regmap, REG_LVDS_CM, 0x00); 491 492 le16val = cpu_to_le16(mode->hdisplay); 493 regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 494 &le16val, 2); 495 le16val = cpu_to_le16(mode->vdisplay); 496 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 497 &le16val, 2); 498 /* 32 + 1 pixel clock to ensure proper operation */ 499 le16val = cpu_to_le16(32 + 1); 500 regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &le16val, 2); 501 le16val = cpu_to_le16(mode->hsync_end - mode->hsync_start); 502 regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 503 &le16val, 2); 504 le16val = cpu_to_le16(mode->vsync_end - mode->vsync_start); 505 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 506 &le16val, 2); 507 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH, 508 mode->htotal - mode->hsync_end); 509 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH, 510 mode->vtotal - mode->vsync_end); 511 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 512 mode->hsync_start - mode->hdisplay); 513 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH, 514 mode->vsync_start - mode->vdisplay); 515 regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00); 516 517 /* Enable PLL */ 518 regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN); 519 usleep_range(3000, 4000); 520 ret = regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval, 521 pval & REG_RC_LVDS_PLL_PLL_EN_STAT, 522 1000, 100000); 523 if (ret) { 524 dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret); 525 /* On failure, disable PLL again and exit. */ 526 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); 527 return; 528 } 529 530 /* Trigger reset after CSR register update. */ 531 regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET); 532 533 /* Clear all errors that got asserted during initialization. */ 534 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); 535 regmap_write(ctx->regmap, REG_IRQ_STAT, pval); 536 } 537 538 static void sn65dsi83_atomic_disable(struct drm_bridge *bridge, 539 struct drm_bridge_state *old_bridge_state) 540 { 541 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 542 543 /* Clear reset, disable PLL */ 544 regmap_write(ctx->regmap, REG_RC_RESET, 0x00); 545 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); 546 } 547 548 static void sn65dsi83_atomic_post_disable(struct drm_bridge *bridge, 549 struct drm_bridge_state *old_bridge_state) 550 { 551 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 552 553 /* Put the chip in reset, pull EN line low. */ 554 gpiod_set_value(ctx->enable_gpio, 0); 555 } 556 557 static enum drm_mode_status 558 sn65dsi83_mode_valid(struct drm_bridge *bridge, 559 const struct drm_display_info *info, 560 const struct drm_display_mode *mode) 561 { 562 /* LVDS output clock range 25..154 MHz */ 563 if (mode->clock < 25000) 564 return MODE_CLOCK_LOW; 565 if (mode->clock > 154000) 566 return MODE_CLOCK_HIGH; 567 568 return MODE_OK; 569 } 570 571 #define MAX_INPUT_SEL_FORMATS 1 572 573 static u32 * 574 sn65dsi83_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 575 struct drm_bridge_state *bridge_state, 576 struct drm_crtc_state *crtc_state, 577 struct drm_connector_state *conn_state, 578 u32 output_fmt, 579 unsigned int *num_input_fmts) 580 { 581 u32 *input_fmts; 582 583 *num_input_fmts = 0; 584 585 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 586 GFP_KERNEL); 587 if (!input_fmts) 588 return NULL; 589 590 /* This is the DSI-end bus format */ 591 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 592 *num_input_fmts = 1; 593 594 return input_fmts; 595 } 596 597 static const struct drm_bridge_funcs sn65dsi83_funcs = { 598 .attach = sn65dsi83_attach, 599 .detach = sn65dsi83_detach, 600 .atomic_pre_enable = sn65dsi83_atomic_pre_enable, 601 .atomic_enable = sn65dsi83_atomic_enable, 602 .atomic_disable = sn65dsi83_atomic_disable, 603 .atomic_post_disable = sn65dsi83_atomic_post_disable, 604 .mode_valid = sn65dsi83_mode_valid, 605 606 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 607 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 608 .atomic_reset = drm_atomic_helper_bridge_reset, 609 .atomic_get_input_bus_fmts = sn65dsi83_atomic_get_input_bus_fmts, 610 }; 611 612 static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model) 613 { 614 struct drm_bridge *panel_bridge; 615 struct device *dev = ctx->dev; 616 struct device_node *endpoint; 617 struct drm_panel *panel; 618 int ret; 619 620 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0); 621 ctx->dsi_lanes = of_property_count_u32_elems(endpoint, "data-lanes"); 622 ctx->host_node = of_graph_get_remote_port_parent(endpoint); 623 of_node_put(endpoint); 624 625 if (ctx->dsi_lanes < 0 || ctx->dsi_lanes > 4) 626 return -EINVAL; 627 if (!ctx->host_node) 628 return -ENODEV; 629 630 ctx->lvds_dual_link = false; 631 ctx->lvds_dual_link_even_odd_swap = false; 632 if (model != MODEL_SN65DSI83) { 633 struct device_node *port2, *port3; 634 int dual_link; 635 636 port2 = of_graph_get_port_by_id(dev->of_node, 2); 637 port3 = of_graph_get_port_by_id(dev->of_node, 3); 638 dual_link = drm_of_lvds_get_dual_link_pixel_order(port2, port3); 639 of_node_put(port2); 640 of_node_put(port3); 641 642 if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) { 643 ctx->lvds_dual_link = true; 644 /* Odd pixels to LVDS Channel A, even pixels to B */ 645 ctx->lvds_dual_link_even_odd_swap = false; 646 } else if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) { 647 ctx->lvds_dual_link = true; 648 /* Even pixels to LVDS Channel A, odd pixels to B */ 649 ctx->lvds_dual_link_even_odd_swap = true; 650 } 651 } 652 653 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, &panel_bridge); 654 if (ret < 0) 655 return ret; 656 if (panel) { 657 panel_bridge = devm_drm_panel_bridge_add(dev, panel); 658 if (IS_ERR(panel_bridge)) 659 return PTR_ERR(panel_bridge); 660 } 661 662 ctx->panel_bridge = panel_bridge; 663 664 return 0; 665 } 666 667 static int sn65dsi83_probe(struct i2c_client *client, 668 const struct i2c_device_id *id) 669 { 670 struct device *dev = &client->dev; 671 enum sn65dsi83_model model; 672 struct sn65dsi83 *ctx; 673 int ret; 674 675 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 676 if (!ctx) 677 return -ENOMEM; 678 679 ctx->dev = dev; 680 681 if (dev->of_node) { 682 model = (enum sn65dsi83_model)(uintptr_t) 683 of_device_get_match_data(dev); 684 } else { 685 model = id->driver_data; 686 } 687 688 ctx->enable_gpio = devm_gpiod_get(ctx->dev, "enable", GPIOD_OUT_LOW); 689 if (IS_ERR(ctx->enable_gpio)) 690 return PTR_ERR(ctx->enable_gpio); 691 692 ret = sn65dsi83_parse_dt(ctx, model); 693 if (ret) 694 return ret; 695 696 ctx->regmap = devm_regmap_init_i2c(client, &sn65dsi83_regmap_config); 697 if (IS_ERR(ctx->regmap)) 698 return PTR_ERR(ctx->regmap); 699 700 dev_set_drvdata(dev, ctx); 701 i2c_set_clientdata(client, ctx); 702 703 ctx->bridge.funcs = &sn65dsi83_funcs; 704 ctx->bridge.of_node = dev->of_node; 705 drm_bridge_add(&ctx->bridge); 706 707 return 0; 708 } 709 710 static int sn65dsi83_remove(struct i2c_client *client) 711 { 712 struct sn65dsi83 *ctx = i2c_get_clientdata(client); 713 714 of_node_put(ctx->host_node); 715 716 return 0; 717 } 718 719 static struct i2c_device_id sn65dsi83_id[] = { 720 { "ti,sn65dsi83", MODEL_SN65DSI83 }, 721 { "ti,sn65dsi84", MODEL_SN65DSI84 }, 722 {}, 723 }; 724 MODULE_DEVICE_TABLE(i2c, sn65dsi83_id); 725 726 static const struct of_device_id sn65dsi83_match_table[] = { 727 { .compatible = "ti,sn65dsi83", .data = (void *)MODEL_SN65DSI83 }, 728 { .compatible = "ti,sn65dsi84", .data = (void *)MODEL_SN65DSI84 }, 729 {}, 730 }; 731 MODULE_DEVICE_TABLE(of, sn65dsi83_match_table); 732 733 static struct i2c_driver sn65dsi83_driver = { 734 .probe = sn65dsi83_probe, 735 .remove = sn65dsi83_remove, 736 .id_table = sn65dsi83_id, 737 .driver = { 738 .name = "sn65dsi83", 739 .of_match_table = sn65dsi83_match_table, 740 }, 741 }; 742 module_i2c_driver(sn65dsi83_driver); 743 744 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 745 MODULE_DESCRIPTION("TI SN65DSI83 DSI to LVDS bridge driver"); 746 MODULE_LICENSE("GPL v2"); 747