1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * TI SN65DSI83,84,85 driver 4 * 5 * Currently supported: 6 * - SN65DSI83 7 * = 1x Single-link DSI ~ 1x Single-link LVDS 8 * - Supported 9 * - Single-link LVDS mode tested 10 * - SN65DSI84 11 * = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS 12 * - Supported 13 * - Dual-link LVDS mode tested 14 * - 2x Single-link LVDS mode unsupported 15 * (should be easy to add by someone who has the HW) 16 * - SN65DSI85 17 * = 2x Single-link or 1x Dual-link DSI ~ 2x Single-link or 1x Dual-link LVDS 18 * - Unsupported 19 * (should be easy to add by someone who has the HW) 20 * 21 * Copyright (C) 2021 Marek Vasut <marex@denx.de> 22 * 23 * Based on previous work of: 24 * Valentin Raevsky <valentin@compulab.co.il> 25 * Philippe Schenker <philippe.schenker@toradex.com> 26 */ 27 28 #include <linux/bits.h> 29 #include <linux/clk.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/i2c.h> 32 #include <linux/module.h> 33 #include <linux/of_device.h> 34 #include <linux/of_graph.h> 35 #include <linux/regmap.h> 36 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_bridge.h> 39 #include <drm/drm_mipi_dsi.h> 40 #include <drm/drm_of.h> 41 #include <drm/drm_panel.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_probe_helper.h> 44 45 /* ID registers */ 46 #define REG_ID(n) (0x00 + (n)) 47 /* Reset and clock registers */ 48 #define REG_RC_RESET 0x09 49 #define REG_RC_RESET_SOFT_RESET BIT(0) 50 #define REG_RC_LVDS_PLL 0x0a 51 #define REG_RC_LVDS_PLL_PLL_EN_STAT BIT(7) 52 #define REG_RC_LVDS_PLL_LVDS_CLK_RANGE(n) (((n) & 0x7) << 1) 53 #define REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY BIT(0) 54 #define REG_RC_DSI_CLK 0x0b 55 #define REG_RC_DSI_CLK_DSI_CLK_DIVIDER(n) (((n) & 0x1f) << 3) 56 #define REG_RC_DSI_CLK_REFCLK_MULTIPLIER(n) ((n) & 0x3) 57 #define REG_RC_PLL_EN 0x0d 58 #define REG_RC_PLL_EN_PLL_EN BIT(0) 59 /* DSI registers */ 60 #define REG_DSI_LANE 0x10 61 #define REG_DSI_LANE_LEFT_RIGHT_PIXELS BIT(7) /* DSI85-only */ 62 #define REG_DSI_LANE_DSI_CHANNEL_MODE_DUAL 0 /* DSI85-only */ 63 #define REG_DSI_LANE_DSI_CHANNEL_MODE_2SINGLE BIT(6) /* DSI85-only */ 64 #define REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE BIT(5) 65 #define REG_DSI_LANE_CHA_DSI_LANES(n) (((n) & 0x3) << 3) 66 #define REG_DSI_LANE_CHB_DSI_LANES(n) (((n) & 0x3) << 1) 67 #define REG_DSI_LANE_SOT_ERR_TOL_DIS BIT(0) 68 #define REG_DSI_EQ 0x11 69 #define REG_DSI_EQ_CHA_DSI_DATA_EQ(n) (((n) & 0x3) << 6) 70 #define REG_DSI_EQ_CHA_DSI_CLK_EQ(n) (((n) & 0x3) << 2) 71 #define REG_DSI_CLK 0x12 72 #define REG_DSI_CLK_CHA_DSI_CLK_RANGE(n) ((n) & 0xff) 73 /* LVDS registers */ 74 #define REG_LVDS_FMT 0x18 75 #define REG_LVDS_FMT_DE_NEG_POLARITY BIT(7) 76 #define REG_LVDS_FMT_HS_NEG_POLARITY BIT(6) 77 #define REG_LVDS_FMT_VS_NEG_POLARITY BIT(5) 78 #define REG_LVDS_FMT_LVDS_LINK_CFG BIT(4) /* 0:AB 1:A-only */ 79 #define REG_LVDS_FMT_CHA_24BPP_MODE BIT(3) 80 #define REG_LVDS_FMT_CHB_24BPP_MODE BIT(2) 81 #define REG_LVDS_FMT_CHA_24BPP_FORMAT1 BIT(1) 82 #define REG_LVDS_FMT_CHB_24BPP_FORMAT1 BIT(0) 83 #define REG_LVDS_VCOM 0x19 84 #define REG_LVDS_VCOM_CHA_LVDS_VOCM BIT(6) 85 #define REG_LVDS_VCOM_CHB_LVDS_VOCM BIT(4) 86 #define REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(n) (((n) & 0x3) << 2) 87 #define REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(n) ((n) & 0x3) 88 #define REG_LVDS_LANE 0x1a 89 #define REG_LVDS_LANE_EVEN_ODD_SWAP BIT(6) 90 #define REG_LVDS_LANE_CHA_REVERSE_LVDS BIT(5) 91 #define REG_LVDS_LANE_CHB_REVERSE_LVDS BIT(4) 92 #define REG_LVDS_LANE_CHA_LVDS_TERM BIT(1) 93 #define REG_LVDS_LANE_CHB_LVDS_TERM BIT(0) 94 #define REG_LVDS_CM 0x1b 95 #define REG_LVDS_CM_CHA_LVDS_CM_ADJUST(n) (((n) & 0x3) << 4) 96 #define REG_LVDS_CM_CHB_LVDS_CM_ADJUST(n) ((n) & 0x3) 97 /* Video registers */ 98 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW 0x20 99 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH 0x21 100 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW 0x24 101 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH 0x25 102 #define REG_VID_CHA_SYNC_DELAY_LOW 0x28 103 #define REG_VID_CHA_SYNC_DELAY_HIGH 0x29 104 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW 0x2c 105 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH 0x2d 106 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW 0x30 107 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH 0x31 108 #define REG_VID_CHA_HORIZONTAL_BACK_PORCH 0x34 109 #define REG_VID_CHA_VERTICAL_BACK_PORCH 0x36 110 #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH 0x38 111 #define REG_VID_CHA_VERTICAL_FRONT_PORCH 0x3a 112 #define REG_VID_CHA_TEST_PATTERN 0x3c 113 /* IRQ registers */ 114 #define REG_IRQ_GLOBAL 0xe0 115 #define REG_IRQ_GLOBAL_IRQ_EN BIT(0) 116 #define REG_IRQ_EN 0xe1 117 #define REG_IRQ_EN_CHA_SYNCH_ERR_EN BIT(7) 118 #define REG_IRQ_EN_CHA_CRC_ERR_EN BIT(6) 119 #define REG_IRQ_EN_CHA_UNC_ECC_ERR_EN BIT(5) 120 #define REG_IRQ_EN_CHA_COR_ECC_ERR_EN BIT(4) 121 #define REG_IRQ_EN_CHA_LLP_ERR_EN BIT(3) 122 #define REG_IRQ_EN_CHA_SOT_BIT_ERR_EN BIT(2) 123 #define REG_IRQ_EN_CHA_PLL_UNLOCK_EN BIT(0) 124 #define REG_IRQ_STAT 0xe5 125 #define REG_IRQ_STAT_CHA_SYNCH_ERR BIT(7) 126 #define REG_IRQ_STAT_CHA_CRC_ERR BIT(6) 127 #define REG_IRQ_STAT_CHA_UNC_ECC_ERR BIT(5) 128 #define REG_IRQ_STAT_CHA_COR_ECC_ERR BIT(4) 129 #define REG_IRQ_STAT_CHA_LLP_ERR BIT(3) 130 #define REG_IRQ_STAT_CHA_SOT_BIT_ERR BIT(2) 131 #define REG_IRQ_STAT_CHA_PLL_UNLOCK BIT(0) 132 133 enum sn65dsi83_model { 134 MODEL_SN65DSI83, 135 MODEL_SN65DSI84, 136 }; 137 138 struct sn65dsi83 { 139 struct drm_bridge bridge; 140 struct device *dev; 141 struct regmap *regmap; 142 struct device_node *host_node; 143 struct mipi_dsi_device *dsi; 144 struct drm_bridge *panel_bridge; 145 struct gpio_desc *enable_gpio; 146 int dsi_lanes; 147 bool lvds_dual_link; 148 bool lvds_dual_link_even_odd_swap; 149 }; 150 151 static const struct regmap_range sn65dsi83_readable_ranges[] = { 152 regmap_reg_range(REG_ID(0), REG_ID(8)), 153 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_DSI_CLK), 154 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN), 155 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK), 156 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM), 157 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 158 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH), 159 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 160 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH), 161 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW, 162 REG_VID_CHA_SYNC_DELAY_HIGH), 163 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 164 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH), 165 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 166 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH), 167 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH, 168 REG_VID_CHA_HORIZONTAL_BACK_PORCH), 169 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH, 170 REG_VID_CHA_VERTICAL_BACK_PORCH), 171 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 172 REG_VID_CHA_HORIZONTAL_FRONT_PORCH), 173 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH, 174 REG_VID_CHA_VERTICAL_FRONT_PORCH), 175 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN), 176 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN), 177 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 178 }; 179 180 static const struct regmap_access_table sn65dsi83_readable_table = { 181 .yes_ranges = sn65dsi83_readable_ranges, 182 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_readable_ranges), 183 }; 184 185 static const struct regmap_range sn65dsi83_writeable_ranges[] = { 186 regmap_reg_range(REG_RC_RESET, REG_RC_DSI_CLK), 187 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN), 188 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK), 189 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM), 190 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 191 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH), 192 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 193 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH), 194 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW, 195 REG_VID_CHA_SYNC_DELAY_HIGH), 196 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 197 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH), 198 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 199 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH), 200 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH, 201 REG_VID_CHA_HORIZONTAL_BACK_PORCH), 202 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH, 203 REG_VID_CHA_VERTICAL_BACK_PORCH), 204 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 205 REG_VID_CHA_HORIZONTAL_FRONT_PORCH), 206 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH, 207 REG_VID_CHA_VERTICAL_FRONT_PORCH), 208 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN), 209 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN), 210 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 211 }; 212 213 static const struct regmap_access_table sn65dsi83_writeable_table = { 214 .yes_ranges = sn65dsi83_writeable_ranges, 215 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_writeable_ranges), 216 }; 217 218 static const struct regmap_range sn65dsi83_volatile_ranges[] = { 219 regmap_reg_range(REG_RC_RESET, REG_RC_RESET), 220 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_LVDS_PLL), 221 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 222 }; 223 224 static const struct regmap_access_table sn65dsi83_volatile_table = { 225 .yes_ranges = sn65dsi83_volatile_ranges, 226 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_volatile_ranges), 227 }; 228 229 static const struct regmap_config sn65dsi83_regmap_config = { 230 .reg_bits = 8, 231 .val_bits = 8, 232 .rd_table = &sn65dsi83_readable_table, 233 .wr_table = &sn65dsi83_writeable_table, 234 .volatile_table = &sn65dsi83_volatile_table, 235 .cache_type = REGCACHE_RBTREE, 236 .max_register = REG_IRQ_STAT, 237 }; 238 239 static struct sn65dsi83 *bridge_to_sn65dsi83(struct drm_bridge *bridge) 240 { 241 return container_of(bridge, struct sn65dsi83, bridge); 242 } 243 244 static int sn65dsi83_attach(struct drm_bridge *bridge, 245 enum drm_bridge_attach_flags flags) 246 { 247 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 248 249 return drm_bridge_attach(bridge->encoder, ctx->panel_bridge, 250 &ctx->bridge, flags); 251 } 252 253 static void sn65dsi83_detach(struct drm_bridge *bridge) 254 { 255 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 256 257 if (!ctx->dsi) 258 return; 259 260 ctx->dsi = NULL; 261 } 262 263 static u8 sn65dsi83_get_lvds_range(struct sn65dsi83 *ctx, 264 const struct drm_display_mode *mode) 265 { 266 /* 267 * The encoding of the LVDS_CLK_RANGE is as follows: 268 * 000 - 25 MHz <= LVDS_CLK < 37.5 MHz 269 * 001 - 37.5 MHz <= LVDS_CLK < 62.5 MHz 270 * 010 - 62.5 MHz <= LVDS_CLK < 87.5 MHz 271 * 011 - 87.5 MHz <= LVDS_CLK < 112.5 MHz 272 * 100 - 112.5 MHz <= LVDS_CLK < 137.5 MHz 273 * 101 - 137.5 MHz <= LVDS_CLK <= 154 MHz 274 * which is a range of 12.5MHz..162.5MHz in 50MHz steps, except that 275 * the ends of the ranges are clamped to the supported range. Since 276 * sn65dsi83_mode_valid() already filters the valid modes and limits 277 * the clock to 25..154 MHz, the range calculation can be simplified 278 * as follows: 279 */ 280 int mode_clock = mode->clock; 281 282 if (ctx->lvds_dual_link) 283 mode_clock /= 2; 284 285 return (mode_clock - 12500) / 25000; 286 } 287 288 static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx, 289 const struct drm_display_mode *mode) 290 { 291 /* 292 * The encoding of the CHA_DSI_CLK_RANGE is as follows: 293 * 0x00 through 0x07 - Reserved 294 * 0x08 - 40 <= DSI_CLK < 45 MHz 295 * 0x09 - 45 <= DSI_CLK < 50 MHz 296 * ... 297 * 0x63 - 495 <= DSI_CLK < 500 MHz 298 * 0x64 - 500 MHz 299 * 0x65 through 0xFF - Reserved 300 * which is DSI clock in 5 MHz steps, clamped to 40..500 MHz. 301 * The DSI clock are calculated as: 302 * DSI_CLK = mode clock * bpp / dsi_data_lanes / 2 303 * the 2 is there because the bus is DDR. 304 */ 305 return DIV_ROUND_UP(clamp((unsigned int)mode->clock * 306 mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) / 307 ctx->dsi_lanes / 2, 40000U, 500000U), 5000U); 308 } 309 310 static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx) 311 { 312 /* The divider is (DSI_CLK / LVDS_CLK) - 1, which really is: */ 313 unsigned int dsi_div = mipi_dsi_pixel_format_to_bpp(ctx->dsi->format); 314 315 dsi_div /= ctx->dsi_lanes; 316 317 if (!ctx->lvds_dual_link) 318 dsi_div /= 2; 319 320 return dsi_div - 1; 321 } 322 323 static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, 324 struct drm_bridge_state *old_bridge_state) 325 { 326 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 327 struct drm_atomic_state *state = old_bridge_state->base.state; 328 const struct drm_bridge_state *bridge_state; 329 const struct drm_crtc_state *crtc_state; 330 const struct drm_display_mode *mode; 331 struct drm_connector *connector; 332 struct drm_crtc *crtc; 333 bool lvds_format_24bpp; 334 bool lvds_format_jeida; 335 unsigned int pval; 336 __le16 le16val; 337 u16 val; 338 int ret; 339 340 /* Deassert reset */ 341 gpiod_set_value(ctx->enable_gpio, 1); 342 usleep_range(1000, 1100); 343 344 /* Get the LVDS format from the bridge state. */ 345 bridge_state = drm_atomic_get_new_bridge_state(state, bridge); 346 347 switch (bridge_state->output_bus_cfg.format) { 348 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 349 lvds_format_24bpp = false; 350 lvds_format_jeida = true; 351 break; 352 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 353 lvds_format_24bpp = true; 354 lvds_format_jeida = true; 355 break; 356 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 357 lvds_format_24bpp = true; 358 lvds_format_jeida = false; 359 break; 360 default: 361 /* 362 * Some bridges still don't set the correct 363 * LVDS bus pixel format, use SPWG24 default 364 * format until those are fixed. 365 */ 366 lvds_format_24bpp = true; 367 lvds_format_jeida = false; 368 dev_warn(ctx->dev, 369 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n", 370 bridge_state->output_bus_cfg.format); 371 break; 372 } 373 374 /* 375 * Retrieve the CRTC adjusted mode. This requires a little dance to go 376 * from the bridge to the encoder, to the connector and to the CRTC. 377 */ 378 connector = drm_atomic_get_new_connector_for_encoder(state, 379 bridge->encoder); 380 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 381 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 382 mode = &crtc_state->adjusted_mode; 383 384 /* Clear reset, disable PLL */ 385 regmap_write(ctx->regmap, REG_RC_RESET, 0x00); 386 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); 387 388 /* Reference clock derived from DSI link clock. */ 389 regmap_write(ctx->regmap, REG_RC_LVDS_PLL, 390 REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx, mode)) | 391 REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY); 392 regmap_write(ctx->regmap, REG_DSI_CLK, 393 REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx, mode))); 394 regmap_write(ctx->regmap, REG_RC_DSI_CLK, 395 REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx))); 396 397 /* Set number of DSI lanes and LVDS link config. */ 398 regmap_write(ctx->regmap, REG_DSI_LANE, 399 REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE | 400 REG_DSI_LANE_CHA_DSI_LANES(~(ctx->dsi_lanes - 1)) | 401 /* CHB is DSI85-only, set to default on DSI83/DSI84 */ 402 REG_DSI_LANE_CHB_DSI_LANES(3)); 403 /* No equalization. */ 404 regmap_write(ctx->regmap, REG_DSI_EQ, 0x00); 405 406 /* Set up sync signal polarity. */ 407 val = (mode->flags & DRM_MODE_FLAG_NHSYNC ? 408 REG_LVDS_FMT_HS_NEG_POLARITY : 0) | 409 (mode->flags & DRM_MODE_FLAG_NVSYNC ? 410 REG_LVDS_FMT_VS_NEG_POLARITY : 0); 411 412 /* Set up bits-per-pixel, 18bpp or 24bpp. */ 413 if (lvds_format_24bpp) { 414 val |= REG_LVDS_FMT_CHA_24BPP_MODE; 415 if (ctx->lvds_dual_link) 416 val |= REG_LVDS_FMT_CHB_24BPP_MODE; 417 } 418 419 /* Set up LVDS format, JEIDA/Format 1 or SPWG/Format 2 */ 420 if (lvds_format_jeida) { 421 val |= REG_LVDS_FMT_CHA_24BPP_FORMAT1; 422 if (ctx->lvds_dual_link) 423 val |= REG_LVDS_FMT_CHB_24BPP_FORMAT1; 424 } 425 426 /* Set up LVDS output config (DSI84,DSI85) */ 427 if (!ctx->lvds_dual_link) 428 val |= REG_LVDS_FMT_LVDS_LINK_CFG; 429 430 regmap_write(ctx->regmap, REG_LVDS_FMT, val); 431 regmap_write(ctx->regmap, REG_LVDS_VCOM, 0x05); 432 regmap_write(ctx->regmap, REG_LVDS_LANE, 433 (ctx->lvds_dual_link_even_odd_swap ? 434 REG_LVDS_LANE_EVEN_ODD_SWAP : 0) | 435 REG_LVDS_LANE_CHA_LVDS_TERM | 436 REG_LVDS_LANE_CHB_LVDS_TERM); 437 regmap_write(ctx->regmap, REG_LVDS_CM, 0x00); 438 439 le16val = cpu_to_le16(mode->hdisplay); 440 regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 441 &le16val, 2); 442 le16val = cpu_to_le16(mode->vdisplay); 443 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 444 &le16val, 2); 445 /* 32 + 1 pixel clock to ensure proper operation */ 446 le16val = cpu_to_le16(32 + 1); 447 regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &le16val, 2); 448 le16val = cpu_to_le16(mode->hsync_end - mode->hsync_start); 449 regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 450 &le16val, 2); 451 le16val = cpu_to_le16(mode->vsync_end - mode->vsync_start); 452 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 453 &le16val, 2); 454 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH, 455 mode->htotal - mode->hsync_end); 456 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH, 457 mode->vtotal - mode->vsync_end); 458 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 459 mode->hsync_start - mode->hdisplay); 460 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH, 461 mode->vsync_start - mode->vdisplay); 462 regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00); 463 464 /* Enable PLL */ 465 regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN); 466 usleep_range(3000, 4000); 467 ret = regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval, 468 pval & REG_RC_LVDS_PLL_PLL_EN_STAT, 469 1000, 100000); 470 if (ret) { 471 dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret); 472 /* On failure, disable PLL again and exit. */ 473 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); 474 return; 475 } 476 477 /* Trigger reset after CSR register update. */ 478 regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET); 479 480 /* Clear all errors that got asserted during initialization. */ 481 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); 482 regmap_write(ctx->regmap, REG_IRQ_STAT, pval); 483 } 484 485 static void sn65dsi83_atomic_disable(struct drm_bridge *bridge, 486 struct drm_bridge_state *old_bridge_state) 487 { 488 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 489 490 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */ 491 gpiod_set_value(ctx->enable_gpio, 0); 492 usleep_range(10000, 11000); 493 494 regcache_mark_dirty(ctx->regmap); 495 } 496 497 static enum drm_mode_status 498 sn65dsi83_mode_valid(struct drm_bridge *bridge, 499 const struct drm_display_info *info, 500 const struct drm_display_mode *mode) 501 { 502 /* LVDS output clock range 25..154 MHz */ 503 if (mode->clock < 25000) 504 return MODE_CLOCK_LOW; 505 if (mode->clock > 154000) 506 return MODE_CLOCK_HIGH; 507 508 return MODE_OK; 509 } 510 511 #define MAX_INPUT_SEL_FORMATS 1 512 513 static u32 * 514 sn65dsi83_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 515 struct drm_bridge_state *bridge_state, 516 struct drm_crtc_state *crtc_state, 517 struct drm_connector_state *conn_state, 518 u32 output_fmt, 519 unsigned int *num_input_fmts) 520 { 521 u32 *input_fmts; 522 523 *num_input_fmts = 0; 524 525 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 526 GFP_KERNEL); 527 if (!input_fmts) 528 return NULL; 529 530 /* This is the DSI-end bus format */ 531 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 532 *num_input_fmts = 1; 533 534 return input_fmts; 535 } 536 537 static const struct drm_bridge_funcs sn65dsi83_funcs = { 538 .attach = sn65dsi83_attach, 539 .detach = sn65dsi83_detach, 540 .atomic_enable = sn65dsi83_atomic_enable, 541 .atomic_disable = sn65dsi83_atomic_disable, 542 .mode_valid = sn65dsi83_mode_valid, 543 544 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 545 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 546 .atomic_reset = drm_atomic_helper_bridge_reset, 547 .atomic_get_input_bus_fmts = sn65dsi83_atomic_get_input_bus_fmts, 548 }; 549 550 static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model) 551 { 552 struct drm_bridge *panel_bridge; 553 struct device *dev = ctx->dev; 554 struct device_node *endpoint; 555 struct drm_panel *panel; 556 int ret; 557 558 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0); 559 ctx->dsi_lanes = of_property_count_u32_elems(endpoint, "data-lanes"); 560 ctx->host_node = of_graph_get_remote_port_parent(endpoint); 561 of_node_put(endpoint); 562 563 if (ctx->dsi_lanes < 0 || ctx->dsi_lanes > 4) 564 return -EINVAL; 565 if (!ctx->host_node) 566 return -ENODEV; 567 568 ctx->lvds_dual_link = false; 569 ctx->lvds_dual_link_even_odd_swap = false; 570 if (model != MODEL_SN65DSI83) { 571 struct device_node *port2, *port3; 572 int dual_link; 573 574 port2 = of_graph_get_port_by_id(dev->of_node, 2); 575 port3 = of_graph_get_port_by_id(dev->of_node, 3); 576 dual_link = drm_of_lvds_get_dual_link_pixel_order(port2, port3); 577 of_node_put(port2); 578 of_node_put(port3); 579 580 if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) { 581 ctx->lvds_dual_link = true; 582 /* Odd pixels to LVDS Channel A, even pixels to B */ 583 ctx->lvds_dual_link_even_odd_swap = false; 584 } else if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) { 585 ctx->lvds_dual_link = true; 586 /* Even pixels to LVDS Channel A, odd pixels to B */ 587 ctx->lvds_dual_link_even_odd_swap = true; 588 } 589 } 590 591 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, &panel_bridge); 592 if (ret < 0) 593 return ret; 594 if (panel) { 595 panel_bridge = devm_drm_panel_bridge_add(dev, panel); 596 if (IS_ERR(panel_bridge)) 597 return PTR_ERR(panel_bridge); 598 } 599 600 ctx->panel_bridge = panel_bridge; 601 602 return 0; 603 } 604 605 static int sn65dsi83_host_attach(struct sn65dsi83 *ctx) 606 { 607 struct device *dev = ctx->dev; 608 struct mipi_dsi_device *dsi; 609 struct mipi_dsi_host *host; 610 const struct mipi_dsi_device_info info = { 611 .type = "sn65dsi83", 612 .channel = 0, 613 .node = NULL, 614 }; 615 int ret; 616 617 host = of_find_mipi_dsi_host_by_node(ctx->host_node); 618 if (!host) { 619 dev_err(dev, "failed to find dsi host\n"); 620 return -EPROBE_DEFER; 621 } 622 623 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 624 if (IS_ERR(dsi)) 625 return dev_err_probe(dev, PTR_ERR(dsi), 626 "failed to create dsi device\n"); 627 628 ctx->dsi = dsi; 629 630 dsi->lanes = ctx->dsi_lanes; 631 dsi->format = MIPI_DSI_FMT_RGB888; 632 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST; 633 634 ret = devm_mipi_dsi_attach(dev, dsi); 635 if (ret < 0) { 636 dev_err(dev, "failed to attach dsi to host: %d\n", ret); 637 return ret; 638 } 639 640 return 0; 641 } 642 643 static int sn65dsi83_probe(struct i2c_client *client, 644 const struct i2c_device_id *id) 645 { 646 struct device *dev = &client->dev; 647 enum sn65dsi83_model model; 648 struct sn65dsi83 *ctx; 649 int ret; 650 651 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 652 if (!ctx) 653 return -ENOMEM; 654 655 ctx->dev = dev; 656 657 if (dev->of_node) { 658 model = (enum sn65dsi83_model)(uintptr_t) 659 of_device_get_match_data(dev); 660 } else { 661 model = id->driver_data; 662 } 663 664 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */ 665 ctx->enable_gpio = devm_gpiod_get(ctx->dev, "enable", GPIOD_OUT_LOW); 666 if (IS_ERR(ctx->enable_gpio)) 667 return PTR_ERR(ctx->enable_gpio); 668 669 usleep_range(10000, 11000); 670 671 ret = sn65dsi83_parse_dt(ctx, model); 672 if (ret) 673 return ret; 674 675 ctx->regmap = devm_regmap_init_i2c(client, &sn65dsi83_regmap_config); 676 if (IS_ERR(ctx->regmap)) 677 return PTR_ERR(ctx->regmap); 678 679 dev_set_drvdata(dev, ctx); 680 i2c_set_clientdata(client, ctx); 681 682 ctx->bridge.funcs = &sn65dsi83_funcs; 683 ctx->bridge.of_node = dev->of_node; 684 drm_bridge_add(&ctx->bridge); 685 686 ret = sn65dsi83_host_attach(ctx); 687 if (ret) 688 goto err_remove_bridge; 689 690 return 0; 691 692 err_remove_bridge: 693 drm_bridge_remove(&ctx->bridge); 694 return ret; 695 } 696 697 static int sn65dsi83_remove(struct i2c_client *client) 698 { 699 struct sn65dsi83 *ctx = i2c_get_clientdata(client); 700 701 drm_bridge_remove(&ctx->bridge); 702 of_node_put(ctx->host_node); 703 704 return 0; 705 } 706 707 static struct i2c_device_id sn65dsi83_id[] = { 708 { "ti,sn65dsi83", MODEL_SN65DSI83 }, 709 { "ti,sn65dsi84", MODEL_SN65DSI84 }, 710 {}, 711 }; 712 MODULE_DEVICE_TABLE(i2c, sn65dsi83_id); 713 714 static const struct of_device_id sn65dsi83_match_table[] = { 715 { .compatible = "ti,sn65dsi83", .data = (void *)MODEL_SN65DSI83 }, 716 { .compatible = "ti,sn65dsi84", .data = (void *)MODEL_SN65DSI84 }, 717 {}, 718 }; 719 MODULE_DEVICE_TABLE(of, sn65dsi83_match_table); 720 721 static struct i2c_driver sn65dsi83_driver = { 722 .probe = sn65dsi83_probe, 723 .remove = sn65dsi83_remove, 724 .id_table = sn65dsi83_id, 725 .driver = { 726 .name = "sn65dsi83", 727 .of_match_table = sn65dsi83_match_table, 728 }, 729 }; 730 module_i2c_driver(sn65dsi83_driver); 731 732 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 733 MODULE_DESCRIPTION("TI SN65DSI83 DSI to LVDS bridge driver"); 734 MODULE_LICENSE("GPL v2"); 735