1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * TI SN65DSI83,84,85 driver 4 * 5 * Currently supported: 6 * - SN65DSI83 7 * = 1x Single-link DSI ~ 1x Single-link LVDS 8 * - Supported 9 * - Single-link LVDS mode tested 10 * - SN65DSI84 11 * = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS 12 * - Supported 13 * - Dual-link LVDS mode tested 14 * - 2x Single-link LVDS mode unsupported 15 * (should be easy to add by someone who has the HW) 16 * - SN65DSI85 17 * = 2x Single-link or 1x Dual-link DSI ~ 2x Single-link or 1x Dual-link LVDS 18 * - Unsupported 19 * (should be easy to add by someone who has the HW) 20 * 21 * Copyright (C) 2021 Marek Vasut <marex@denx.de> 22 * 23 * Based on previous work of: 24 * Valentin Raevsky <valentin@compulab.co.il> 25 * Philippe Schenker <philippe.schenker@toradex.com> 26 */ 27 28 #include <linux/bits.h> 29 #include <linux/clk.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/i2c.h> 32 #include <linux/module.h> 33 #include <linux/of_device.h> 34 #include <linux/of_graph.h> 35 #include <linux/regmap.h> 36 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_bridge.h> 39 #include <drm/drm_mipi_dsi.h> 40 #include <drm/drm_of.h> 41 #include <drm/drm_panel.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_probe_helper.h> 44 45 /* ID registers */ 46 #define REG_ID(n) (0x00 + (n)) 47 /* Reset and clock registers */ 48 #define REG_RC_RESET 0x09 49 #define REG_RC_RESET_SOFT_RESET BIT(0) 50 #define REG_RC_LVDS_PLL 0x0a 51 #define REG_RC_LVDS_PLL_PLL_EN_STAT BIT(7) 52 #define REG_RC_LVDS_PLL_LVDS_CLK_RANGE(n) (((n) & 0x7) << 1) 53 #define REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY BIT(0) 54 #define REG_RC_DSI_CLK 0x0b 55 #define REG_RC_DSI_CLK_DSI_CLK_DIVIDER(n) (((n) & 0x1f) << 3) 56 #define REG_RC_DSI_CLK_REFCLK_MULTIPLIER(n) ((n) & 0x3) 57 #define REG_RC_PLL_EN 0x0d 58 #define REG_RC_PLL_EN_PLL_EN BIT(0) 59 /* DSI registers */ 60 #define REG_DSI_LANE 0x10 61 #define REG_DSI_LANE_LEFT_RIGHT_PIXELS BIT(7) /* DSI85-only */ 62 #define REG_DSI_LANE_DSI_CHANNEL_MODE_DUAL 0 /* DSI85-only */ 63 #define REG_DSI_LANE_DSI_CHANNEL_MODE_2SINGLE BIT(6) /* DSI85-only */ 64 #define REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE BIT(5) 65 #define REG_DSI_LANE_CHA_DSI_LANES(n) (((n) & 0x3) << 3) 66 #define REG_DSI_LANE_CHB_DSI_LANES(n) (((n) & 0x3) << 1) 67 #define REG_DSI_LANE_SOT_ERR_TOL_DIS BIT(0) 68 #define REG_DSI_EQ 0x11 69 #define REG_DSI_EQ_CHA_DSI_DATA_EQ(n) (((n) & 0x3) << 6) 70 #define REG_DSI_EQ_CHA_DSI_CLK_EQ(n) (((n) & 0x3) << 2) 71 #define REG_DSI_CLK 0x12 72 #define REG_DSI_CLK_CHA_DSI_CLK_RANGE(n) ((n) & 0xff) 73 /* LVDS registers */ 74 #define REG_LVDS_FMT 0x18 75 #define REG_LVDS_FMT_DE_NEG_POLARITY BIT(7) 76 #define REG_LVDS_FMT_HS_NEG_POLARITY BIT(6) 77 #define REG_LVDS_FMT_VS_NEG_POLARITY BIT(5) 78 #define REG_LVDS_FMT_LVDS_LINK_CFG BIT(4) /* 0:AB 1:A-only */ 79 #define REG_LVDS_FMT_CHA_24BPP_MODE BIT(3) 80 #define REG_LVDS_FMT_CHB_24BPP_MODE BIT(2) 81 #define REG_LVDS_FMT_CHA_24BPP_FORMAT1 BIT(1) 82 #define REG_LVDS_FMT_CHB_24BPP_FORMAT1 BIT(0) 83 #define REG_LVDS_VCOM 0x19 84 #define REG_LVDS_VCOM_CHA_LVDS_VOCM BIT(6) 85 #define REG_LVDS_VCOM_CHB_LVDS_VOCM BIT(4) 86 #define REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(n) (((n) & 0x3) << 2) 87 #define REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(n) ((n) & 0x3) 88 #define REG_LVDS_LANE 0x1a 89 #define REG_LVDS_LANE_EVEN_ODD_SWAP BIT(6) 90 #define REG_LVDS_LANE_CHA_REVERSE_LVDS BIT(5) 91 #define REG_LVDS_LANE_CHB_REVERSE_LVDS BIT(4) 92 #define REG_LVDS_LANE_CHA_LVDS_TERM BIT(1) 93 #define REG_LVDS_LANE_CHB_LVDS_TERM BIT(0) 94 #define REG_LVDS_CM 0x1b 95 #define REG_LVDS_CM_CHA_LVDS_CM_ADJUST(n) (((n) & 0x3) << 4) 96 #define REG_LVDS_CM_CHB_LVDS_CM_ADJUST(n) ((n) & 0x3) 97 /* Video registers */ 98 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW 0x20 99 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH 0x21 100 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW 0x24 101 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH 0x25 102 #define REG_VID_CHA_SYNC_DELAY_LOW 0x28 103 #define REG_VID_CHA_SYNC_DELAY_HIGH 0x29 104 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW 0x2c 105 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH 0x2d 106 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW 0x30 107 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH 0x31 108 #define REG_VID_CHA_HORIZONTAL_BACK_PORCH 0x34 109 #define REG_VID_CHA_VERTICAL_BACK_PORCH 0x36 110 #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH 0x38 111 #define REG_VID_CHA_VERTICAL_FRONT_PORCH 0x3a 112 #define REG_VID_CHA_TEST_PATTERN 0x3c 113 /* IRQ registers */ 114 #define REG_IRQ_GLOBAL 0xe0 115 #define REG_IRQ_GLOBAL_IRQ_EN BIT(0) 116 #define REG_IRQ_EN 0xe1 117 #define REG_IRQ_EN_CHA_SYNCH_ERR_EN BIT(7) 118 #define REG_IRQ_EN_CHA_CRC_ERR_EN BIT(6) 119 #define REG_IRQ_EN_CHA_UNC_ECC_ERR_EN BIT(5) 120 #define REG_IRQ_EN_CHA_COR_ECC_ERR_EN BIT(4) 121 #define REG_IRQ_EN_CHA_LLP_ERR_EN BIT(3) 122 #define REG_IRQ_EN_CHA_SOT_BIT_ERR_EN BIT(2) 123 #define REG_IRQ_EN_CHA_PLL_UNLOCK_EN BIT(0) 124 #define REG_IRQ_STAT 0xe5 125 #define REG_IRQ_STAT_CHA_SYNCH_ERR BIT(7) 126 #define REG_IRQ_STAT_CHA_CRC_ERR BIT(6) 127 #define REG_IRQ_STAT_CHA_UNC_ECC_ERR BIT(5) 128 #define REG_IRQ_STAT_CHA_COR_ECC_ERR BIT(4) 129 #define REG_IRQ_STAT_CHA_LLP_ERR BIT(3) 130 #define REG_IRQ_STAT_CHA_SOT_BIT_ERR BIT(2) 131 #define REG_IRQ_STAT_CHA_PLL_UNLOCK BIT(0) 132 133 enum sn65dsi83_model { 134 MODEL_SN65DSI83, 135 MODEL_SN65DSI84, 136 }; 137 138 struct sn65dsi83 { 139 struct drm_bridge bridge; 140 struct drm_display_mode mode; 141 struct device *dev; 142 struct regmap *regmap; 143 struct device_node *host_node; 144 struct mipi_dsi_device *dsi; 145 struct drm_bridge *panel_bridge; 146 struct gpio_desc *enable_gpio; 147 int dsi_lanes; 148 bool lvds_dual_link; 149 bool lvds_dual_link_even_odd_swap; 150 bool lvds_format_24bpp; 151 bool lvds_format_jeida; 152 }; 153 154 static const struct regmap_range sn65dsi83_readable_ranges[] = { 155 regmap_reg_range(REG_ID(0), REG_ID(8)), 156 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_DSI_CLK), 157 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN), 158 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK), 159 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM), 160 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 161 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH), 162 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 163 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH), 164 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW, 165 REG_VID_CHA_SYNC_DELAY_HIGH), 166 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 167 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH), 168 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 169 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH), 170 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH, 171 REG_VID_CHA_HORIZONTAL_BACK_PORCH), 172 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH, 173 REG_VID_CHA_VERTICAL_BACK_PORCH), 174 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 175 REG_VID_CHA_HORIZONTAL_FRONT_PORCH), 176 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH, 177 REG_VID_CHA_VERTICAL_FRONT_PORCH), 178 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN), 179 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN), 180 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 181 }; 182 183 static const struct regmap_access_table sn65dsi83_readable_table = { 184 .yes_ranges = sn65dsi83_readable_ranges, 185 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_readable_ranges), 186 }; 187 188 static const struct regmap_range sn65dsi83_writeable_ranges[] = { 189 regmap_reg_range(REG_RC_RESET, REG_RC_DSI_CLK), 190 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN), 191 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK), 192 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM), 193 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 194 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH), 195 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 196 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH), 197 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW, 198 REG_VID_CHA_SYNC_DELAY_HIGH), 199 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 200 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH), 201 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 202 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH), 203 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH, 204 REG_VID_CHA_HORIZONTAL_BACK_PORCH), 205 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH, 206 REG_VID_CHA_VERTICAL_BACK_PORCH), 207 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 208 REG_VID_CHA_HORIZONTAL_FRONT_PORCH), 209 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH, 210 REG_VID_CHA_VERTICAL_FRONT_PORCH), 211 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN), 212 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN), 213 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 214 }; 215 216 static const struct regmap_access_table sn65dsi83_writeable_table = { 217 .yes_ranges = sn65dsi83_writeable_ranges, 218 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_writeable_ranges), 219 }; 220 221 static const struct regmap_range sn65dsi83_volatile_ranges[] = { 222 regmap_reg_range(REG_RC_RESET, REG_RC_RESET), 223 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_LVDS_PLL), 224 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 225 }; 226 227 static const struct regmap_access_table sn65dsi83_volatile_table = { 228 .yes_ranges = sn65dsi83_volatile_ranges, 229 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_volatile_ranges), 230 }; 231 232 static const struct regmap_config sn65dsi83_regmap_config = { 233 .reg_bits = 8, 234 .val_bits = 8, 235 .rd_table = &sn65dsi83_readable_table, 236 .wr_table = &sn65dsi83_writeable_table, 237 .volatile_table = &sn65dsi83_volatile_table, 238 .cache_type = REGCACHE_RBTREE, 239 .max_register = REG_IRQ_STAT, 240 }; 241 242 static struct sn65dsi83 *bridge_to_sn65dsi83(struct drm_bridge *bridge) 243 { 244 return container_of(bridge, struct sn65dsi83, bridge); 245 } 246 247 static int sn65dsi83_attach(struct drm_bridge *bridge, 248 enum drm_bridge_attach_flags flags) 249 { 250 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 251 struct device *dev = ctx->dev; 252 struct mipi_dsi_device *dsi; 253 struct mipi_dsi_host *host; 254 int ret = 0; 255 256 const struct mipi_dsi_device_info info = { 257 .type = "sn65dsi83", 258 .channel = 0, 259 .node = NULL, 260 }; 261 262 host = of_find_mipi_dsi_host_by_node(ctx->host_node); 263 if (!host) { 264 dev_err(dev, "failed to find dsi host\n"); 265 return -EPROBE_DEFER; 266 } 267 268 dsi = mipi_dsi_device_register_full(host, &info); 269 if (IS_ERR(dsi)) { 270 return dev_err_probe(dev, PTR_ERR(dsi), 271 "failed to create dsi device\n"); 272 } 273 274 ctx->dsi = dsi; 275 276 dsi->lanes = ctx->dsi_lanes; 277 dsi->format = MIPI_DSI_FMT_RGB888; 278 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST; 279 280 ret = mipi_dsi_attach(dsi); 281 if (ret < 0) { 282 dev_err(dev, "failed to attach dsi to host\n"); 283 goto err_dsi_attach; 284 } 285 286 return drm_bridge_attach(bridge->encoder, ctx->panel_bridge, 287 &ctx->bridge, flags); 288 289 err_dsi_attach: 290 mipi_dsi_device_unregister(dsi); 291 return ret; 292 } 293 294 static void sn65dsi83_pre_enable(struct drm_bridge *bridge) 295 { 296 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 297 298 /* 299 * Reset the chip, pull EN line low for t_reset=10ms, 300 * then high for t_en=1ms. 301 */ 302 regcache_mark_dirty(ctx->regmap); 303 gpiod_set_value(ctx->enable_gpio, 0); 304 usleep_range(10000, 11000); 305 gpiod_set_value(ctx->enable_gpio, 1); 306 usleep_range(1000, 1100); 307 } 308 309 static u8 sn65dsi83_get_lvds_range(struct sn65dsi83 *ctx) 310 { 311 /* 312 * The encoding of the LVDS_CLK_RANGE is as follows: 313 * 000 - 25 MHz <= LVDS_CLK < 37.5 MHz 314 * 001 - 37.5 MHz <= LVDS_CLK < 62.5 MHz 315 * 010 - 62.5 MHz <= LVDS_CLK < 87.5 MHz 316 * 011 - 87.5 MHz <= LVDS_CLK < 112.5 MHz 317 * 100 - 112.5 MHz <= LVDS_CLK < 137.5 MHz 318 * 101 - 137.5 MHz <= LVDS_CLK <= 154 MHz 319 * which is a range of 12.5MHz..162.5MHz in 50MHz steps, except that 320 * the ends of the ranges are clamped to the supported range. Since 321 * sn65dsi83_mode_valid() already filters the valid modes and limits 322 * the clock to 25..154 MHz, the range calculation can be simplified 323 * as follows: 324 */ 325 int mode_clock = ctx->mode.clock; 326 327 if (ctx->lvds_dual_link) 328 mode_clock /= 2; 329 330 return (mode_clock - 12500) / 25000; 331 } 332 333 static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx) 334 { 335 /* 336 * The encoding of the CHA_DSI_CLK_RANGE is as follows: 337 * 0x00 through 0x07 - Reserved 338 * 0x08 - 40 <= DSI_CLK < 45 MHz 339 * 0x09 - 45 <= DSI_CLK < 50 MHz 340 * ... 341 * 0x63 - 495 <= DSI_CLK < 500 MHz 342 * 0x64 - 500 MHz 343 * 0x65 through 0xFF - Reserved 344 * which is DSI clock in 5 MHz steps, clamped to 40..500 MHz. 345 * The DSI clock are calculated as: 346 * DSI_CLK = mode clock * bpp / dsi_data_lanes / 2 347 * the 2 is there because the bus is DDR. 348 */ 349 return DIV_ROUND_UP(clamp((unsigned int)ctx->mode.clock * 350 mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) / 351 ctx->dsi_lanes / 2, 40000U, 500000U), 5000U); 352 } 353 354 static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx) 355 { 356 /* The divider is (DSI_CLK / LVDS_CLK) - 1, which really is: */ 357 unsigned int dsi_div = mipi_dsi_pixel_format_to_bpp(ctx->dsi->format); 358 359 dsi_div /= ctx->dsi_lanes; 360 361 if (!ctx->lvds_dual_link) 362 dsi_div /= 2; 363 364 return dsi_div - 1; 365 } 366 367 static void sn65dsi83_enable(struct drm_bridge *bridge) 368 { 369 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 370 unsigned int pval; 371 u16 val; 372 int ret; 373 374 /* Clear reset, disable PLL */ 375 regmap_write(ctx->regmap, REG_RC_RESET, 0x00); 376 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); 377 378 /* Reference clock derived from DSI link clock. */ 379 regmap_write(ctx->regmap, REG_RC_LVDS_PLL, 380 REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx)) | 381 REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY); 382 regmap_write(ctx->regmap, REG_DSI_CLK, 383 REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx))); 384 regmap_write(ctx->regmap, REG_RC_DSI_CLK, 385 REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx))); 386 387 /* Set number of DSI lanes and LVDS link config. */ 388 regmap_write(ctx->regmap, REG_DSI_LANE, 389 REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE | 390 REG_DSI_LANE_CHA_DSI_LANES(~(ctx->dsi_lanes - 1)) | 391 /* CHB is DSI85-only, set to default on DSI83/DSI84 */ 392 REG_DSI_LANE_CHB_DSI_LANES(3)); 393 /* No equalization. */ 394 regmap_write(ctx->regmap, REG_DSI_EQ, 0x00); 395 396 /* Set up sync signal polarity. */ 397 val = (ctx->mode.flags & DRM_MODE_FLAG_NHSYNC ? 398 REG_LVDS_FMT_HS_NEG_POLARITY : 0) | 399 (ctx->mode.flags & DRM_MODE_FLAG_NVSYNC ? 400 REG_LVDS_FMT_VS_NEG_POLARITY : 0); 401 402 /* Set up bits-per-pixel, 18bpp or 24bpp. */ 403 if (ctx->lvds_format_24bpp) { 404 val |= REG_LVDS_FMT_CHA_24BPP_MODE; 405 if (ctx->lvds_dual_link) 406 val |= REG_LVDS_FMT_CHB_24BPP_MODE; 407 } 408 409 /* Set up LVDS format, JEIDA/Format 1 or SPWG/Format 2 */ 410 if (ctx->lvds_format_jeida) { 411 val |= REG_LVDS_FMT_CHA_24BPP_FORMAT1; 412 if (ctx->lvds_dual_link) 413 val |= REG_LVDS_FMT_CHB_24BPP_FORMAT1; 414 } 415 416 /* Set up LVDS output config (DSI84,DSI85) */ 417 if (!ctx->lvds_dual_link) 418 val |= REG_LVDS_FMT_LVDS_LINK_CFG; 419 420 regmap_write(ctx->regmap, REG_LVDS_FMT, val); 421 regmap_write(ctx->regmap, REG_LVDS_VCOM, 0x05); 422 regmap_write(ctx->regmap, REG_LVDS_LANE, 423 (ctx->lvds_dual_link_even_odd_swap ? 424 REG_LVDS_LANE_EVEN_ODD_SWAP : 0) | 425 REG_LVDS_LANE_CHA_LVDS_TERM | 426 REG_LVDS_LANE_CHB_LVDS_TERM); 427 regmap_write(ctx->regmap, REG_LVDS_CM, 0x00); 428 429 val = cpu_to_le16(ctx->mode.hdisplay); 430 regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 431 &val, 2); 432 val = cpu_to_le16(ctx->mode.vdisplay); 433 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 434 &val, 2); 435 /* 32 + 1 pixel clock to ensure proper operation */ 436 val = cpu_to_le16(32 + 1); 437 regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &val, 2); 438 val = cpu_to_le16(ctx->mode.hsync_end - ctx->mode.hsync_start); 439 regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 440 &val, 2); 441 val = cpu_to_le16(ctx->mode.vsync_end - ctx->mode.vsync_start); 442 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 443 &val, 2); 444 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH, 445 ctx->mode.htotal - ctx->mode.hsync_end); 446 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH, 447 ctx->mode.vtotal - ctx->mode.vsync_end); 448 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 449 ctx->mode.hsync_start - ctx->mode.hdisplay); 450 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH, 451 ctx->mode.vsync_start - ctx->mode.vdisplay); 452 regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00); 453 454 /* Enable PLL */ 455 regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN); 456 usleep_range(3000, 4000); 457 ret = regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval, 458 pval & REG_RC_LVDS_PLL_PLL_EN_STAT, 459 1000, 100000); 460 if (ret) { 461 dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret); 462 /* On failure, disable PLL again and exit. */ 463 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); 464 return; 465 } 466 467 /* Trigger reset after CSR register update. */ 468 regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET); 469 470 /* Clear all errors that got asserted during initialization. */ 471 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); 472 regmap_write(ctx->regmap, REG_IRQ_STAT, pval); 473 } 474 475 static void sn65dsi83_disable(struct drm_bridge *bridge) 476 { 477 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 478 479 /* Clear reset, disable PLL */ 480 regmap_write(ctx->regmap, REG_RC_RESET, 0x00); 481 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); 482 } 483 484 static void sn65dsi83_post_disable(struct drm_bridge *bridge) 485 { 486 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 487 488 /* Put the chip in reset, pull EN line low. */ 489 gpiod_set_value(ctx->enable_gpio, 0); 490 } 491 492 static enum drm_mode_status 493 sn65dsi83_mode_valid(struct drm_bridge *bridge, 494 const struct drm_display_info *info, 495 const struct drm_display_mode *mode) 496 { 497 /* LVDS output clock range 25..154 MHz */ 498 if (mode->clock < 25000) 499 return MODE_CLOCK_LOW; 500 if (mode->clock > 154000) 501 return MODE_CLOCK_HIGH; 502 503 return MODE_OK; 504 } 505 506 static void sn65dsi83_mode_set(struct drm_bridge *bridge, 507 const struct drm_display_mode *mode, 508 const struct drm_display_mode *adj) 509 { 510 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 511 512 ctx->mode = *adj; 513 } 514 515 static bool sn65dsi83_mode_fixup(struct drm_bridge *bridge, 516 const struct drm_display_mode *mode, 517 struct drm_display_mode *adj) 518 { 519 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 520 u32 input_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 521 struct drm_encoder *encoder = bridge->encoder; 522 struct drm_device *ddev = encoder->dev; 523 struct drm_connector *connector; 524 525 /* The DSI format is always RGB888_1X24 */ 526 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { 527 switch (connector->display_info.bus_formats[0]) { 528 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 529 ctx->lvds_format_24bpp = false; 530 ctx->lvds_format_jeida = true; 531 break; 532 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 533 ctx->lvds_format_24bpp = true; 534 ctx->lvds_format_jeida = true; 535 break; 536 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 537 ctx->lvds_format_24bpp = true; 538 ctx->lvds_format_jeida = false; 539 break; 540 default: 541 /* 542 * Some bridges still don't set the correct 543 * LVDS bus pixel format, use SPWG24 default 544 * format until those are fixed. 545 */ 546 ctx->lvds_format_24bpp = true; 547 ctx->lvds_format_jeida = false; 548 dev_warn(ctx->dev, 549 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n", 550 connector->display_info.bus_formats[0]); 551 break; 552 } 553 554 drm_display_info_set_bus_formats(&connector->display_info, 555 &input_bus_format, 1); 556 } 557 558 return true; 559 } 560 561 static const struct drm_bridge_funcs sn65dsi83_funcs = { 562 .attach = sn65dsi83_attach, 563 .pre_enable = sn65dsi83_pre_enable, 564 .enable = sn65dsi83_enable, 565 .disable = sn65dsi83_disable, 566 .post_disable = sn65dsi83_post_disable, 567 .mode_valid = sn65dsi83_mode_valid, 568 .mode_set = sn65dsi83_mode_set, 569 .mode_fixup = sn65dsi83_mode_fixup, 570 }; 571 572 static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model) 573 { 574 struct drm_bridge *panel_bridge; 575 struct device *dev = ctx->dev; 576 struct device_node *endpoint; 577 struct drm_panel *panel; 578 int ret; 579 580 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0); 581 ctx->dsi_lanes = of_property_count_u32_elems(endpoint, "data-lanes"); 582 ctx->host_node = of_graph_get_remote_port_parent(endpoint); 583 of_node_put(endpoint); 584 585 if (ctx->dsi_lanes < 0 || ctx->dsi_lanes > 4) 586 return -EINVAL; 587 if (!ctx->host_node) 588 return -ENODEV; 589 590 ctx->lvds_dual_link = false; 591 ctx->lvds_dual_link_even_odd_swap = false; 592 if (model != MODEL_SN65DSI83) { 593 struct device_node *port2, *port3; 594 int dual_link; 595 596 port2 = of_graph_get_port_by_id(dev->of_node, 2); 597 port3 = of_graph_get_port_by_id(dev->of_node, 3); 598 dual_link = drm_of_lvds_get_dual_link_pixel_order(port2, port3); 599 of_node_put(port2); 600 of_node_put(port3); 601 602 if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) { 603 ctx->lvds_dual_link = true; 604 /* Odd pixels to LVDS Channel A, even pixels to B */ 605 ctx->lvds_dual_link_even_odd_swap = false; 606 } else if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) { 607 ctx->lvds_dual_link = true; 608 /* Even pixels to LVDS Channel A, odd pixels to B */ 609 ctx->lvds_dual_link_even_odd_swap = true; 610 } 611 } 612 613 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, &panel_bridge); 614 if (ret < 0) 615 return ret; 616 if (panel) { 617 panel_bridge = devm_drm_panel_bridge_add(dev, panel); 618 if (IS_ERR(panel_bridge)) 619 return PTR_ERR(panel_bridge); 620 } 621 622 ctx->panel_bridge = panel_bridge; 623 624 return 0; 625 } 626 627 static int sn65dsi83_probe(struct i2c_client *client, 628 const struct i2c_device_id *id) 629 { 630 struct device *dev = &client->dev; 631 enum sn65dsi83_model model; 632 struct sn65dsi83 *ctx; 633 int ret; 634 635 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 636 if (!ctx) 637 return -ENOMEM; 638 639 ctx->dev = dev; 640 641 if (dev->of_node) { 642 model = (enum sn65dsi83_model)(uintptr_t) 643 of_device_get_match_data(dev); 644 } else { 645 model = id->driver_data; 646 } 647 648 ctx->enable_gpio = devm_gpiod_get(ctx->dev, "enable", GPIOD_OUT_LOW); 649 if (IS_ERR(ctx->enable_gpio)) 650 return PTR_ERR(ctx->enable_gpio); 651 652 ret = sn65dsi83_parse_dt(ctx, model); 653 if (ret) 654 return ret; 655 656 ctx->regmap = devm_regmap_init_i2c(client, &sn65dsi83_regmap_config); 657 if (IS_ERR(ctx->regmap)) 658 return PTR_ERR(ctx->regmap); 659 660 dev_set_drvdata(dev, ctx); 661 i2c_set_clientdata(client, ctx); 662 663 ctx->bridge.funcs = &sn65dsi83_funcs; 664 ctx->bridge.of_node = dev->of_node; 665 drm_bridge_add(&ctx->bridge); 666 667 return 0; 668 } 669 670 static int sn65dsi83_remove(struct i2c_client *client) 671 { 672 struct sn65dsi83 *ctx = i2c_get_clientdata(client); 673 674 mipi_dsi_detach(ctx->dsi); 675 mipi_dsi_device_unregister(ctx->dsi); 676 drm_bridge_remove(&ctx->bridge); 677 of_node_put(ctx->host_node); 678 679 return 0; 680 } 681 682 static struct i2c_device_id sn65dsi83_id[] = { 683 { "ti,sn65dsi83", MODEL_SN65DSI83 }, 684 { "ti,sn65dsi84", MODEL_SN65DSI84 }, 685 {}, 686 }; 687 MODULE_DEVICE_TABLE(i2c, sn65dsi83_id); 688 689 static const struct of_device_id sn65dsi83_match_table[] = { 690 { .compatible = "ti,sn65dsi83", .data = (void *)MODEL_SN65DSI83 }, 691 { .compatible = "ti,sn65dsi84", .data = (void *)MODEL_SN65DSI84 }, 692 {}, 693 }; 694 MODULE_DEVICE_TABLE(of, sn65dsi83_match_table); 695 696 static struct i2c_driver sn65dsi83_driver = { 697 .probe = sn65dsi83_probe, 698 .remove = sn65dsi83_remove, 699 .id_table = sn65dsi83_id, 700 .driver = { 701 .name = "sn65dsi83", 702 .of_match_table = sn65dsi83_match_table, 703 }, 704 }; 705 module_i2c_driver(sn65dsi83_driver); 706 707 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 708 MODULE_DESCRIPTION("TI SN65DSI83 DSI to LVDS bridge driver"); 709 MODULE_LICENSE("GPL v2"); 710