1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * TI SN65DSI83,84,85 driver 4 * 5 * Currently supported: 6 * - SN65DSI83 7 * = 1x Single-link DSI ~ 1x Single-link LVDS 8 * - Supported 9 * - Single-link LVDS mode tested 10 * - SN65DSI84 11 * = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS 12 * - Supported 13 * - Dual-link LVDS mode tested 14 * - 2x Single-link LVDS mode unsupported 15 * (should be easy to add by someone who has the HW) 16 * - SN65DSI85 17 * = 2x Single-link or 1x Dual-link DSI ~ 2x Single-link or 1x Dual-link LVDS 18 * - Unsupported 19 * (should be easy to add by someone who has the HW) 20 * 21 * Copyright (C) 2021 Marek Vasut <marex@denx.de> 22 * 23 * Based on previous work of: 24 * Valentin Raevsky <valentin@compulab.co.il> 25 * Philippe Schenker <philippe.schenker@toradex.com> 26 */ 27 28 #include <linux/bits.h> 29 #include <linux/clk.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/i2c.h> 32 #include <linux/module.h> 33 #include <linux/of_device.h> 34 #include <linux/of_graph.h> 35 #include <linux/regmap.h> 36 #include <linux/regulator/consumer.h> 37 38 #include <drm/drm_atomic_helper.h> 39 #include <drm/drm_bridge.h> 40 #include <drm/drm_mipi_dsi.h> 41 #include <drm/drm_of.h> 42 #include <drm/drm_panel.h> 43 #include <drm/drm_print.h> 44 #include <drm/drm_probe_helper.h> 45 46 /* ID registers */ 47 #define REG_ID(n) (0x00 + (n)) 48 /* Reset and clock registers */ 49 #define REG_RC_RESET 0x09 50 #define REG_RC_RESET_SOFT_RESET BIT(0) 51 #define REG_RC_LVDS_PLL 0x0a 52 #define REG_RC_LVDS_PLL_PLL_EN_STAT BIT(7) 53 #define REG_RC_LVDS_PLL_LVDS_CLK_RANGE(n) (((n) & 0x7) << 1) 54 #define REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY BIT(0) 55 #define REG_RC_DSI_CLK 0x0b 56 #define REG_RC_DSI_CLK_DSI_CLK_DIVIDER(n) (((n) & 0x1f) << 3) 57 #define REG_RC_DSI_CLK_REFCLK_MULTIPLIER(n) ((n) & 0x3) 58 #define REG_RC_PLL_EN 0x0d 59 #define REG_RC_PLL_EN_PLL_EN BIT(0) 60 /* DSI registers */ 61 #define REG_DSI_LANE 0x10 62 #define REG_DSI_LANE_LEFT_RIGHT_PIXELS BIT(7) /* DSI85-only */ 63 #define REG_DSI_LANE_DSI_CHANNEL_MODE_DUAL 0 /* DSI85-only */ 64 #define REG_DSI_LANE_DSI_CHANNEL_MODE_2SINGLE BIT(6) /* DSI85-only */ 65 #define REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE BIT(5) 66 #define REG_DSI_LANE_CHA_DSI_LANES(n) (((n) & 0x3) << 3) 67 #define REG_DSI_LANE_CHB_DSI_LANES(n) (((n) & 0x3) << 1) 68 #define REG_DSI_LANE_SOT_ERR_TOL_DIS BIT(0) 69 #define REG_DSI_EQ 0x11 70 #define REG_DSI_EQ_CHA_DSI_DATA_EQ(n) (((n) & 0x3) << 6) 71 #define REG_DSI_EQ_CHA_DSI_CLK_EQ(n) (((n) & 0x3) << 2) 72 #define REG_DSI_CLK 0x12 73 #define REG_DSI_CLK_CHA_DSI_CLK_RANGE(n) ((n) & 0xff) 74 /* LVDS registers */ 75 #define REG_LVDS_FMT 0x18 76 #define REG_LVDS_FMT_DE_NEG_POLARITY BIT(7) 77 #define REG_LVDS_FMT_HS_NEG_POLARITY BIT(6) 78 #define REG_LVDS_FMT_VS_NEG_POLARITY BIT(5) 79 #define REG_LVDS_FMT_LVDS_LINK_CFG BIT(4) /* 0:AB 1:A-only */ 80 #define REG_LVDS_FMT_CHA_24BPP_MODE BIT(3) 81 #define REG_LVDS_FMT_CHB_24BPP_MODE BIT(2) 82 #define REG_LVDS_FMT_CHA_24BPP_FORMAT1 BIT(1) 83 #define REG_LVDS_FMT_CHB_24BPP_FORMAT1 BIT(0) 84 #define REG_LVDS_VCOM 0x19 85 #define REG_LVDS_VCOM_CHA_LVDS_VOCM BIT(6) 86 #define REG_LVDS_VCOM_CHB_LVDS_VOCM BIT(4) 87 #define REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(n) (((n) & 0x3) << 2) 88 #define REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(n) ((n) & 0x3) 89 #define REG_LVDS_LANE 0x1a 90 #define REG_LVDS_LANE_EVEN_ODD_SWAP BIT(6) 91 #define REG_LVDS_LANE_CHA_REVERSE_LVDS BIT(5) 92 #define REG_LVDS_LANE_CHB_REVERSE_LVDS BIT(4) 93 #define REG_LVDS_LANE_CHA_LVDS_TERM BIT(1) 94 #define REG_LVDS_LANE_CHB_LVDS_TERM BIT(0) 95 #define REG_LVDS_CM 0x1b 96 #define REG_LVDS_CM_CHA_LVDS_CM_ADJUST(n) (((n) & 0x3) << 4) 97 #define REG_LVDS_CM_CHB_LVDS_CM_ADJUST(n) ((n) & 0x3) 98 /* Video registers */ 99 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW 0x20 100 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH 0x21 101 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW 0x24 102 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH 0x25 103 #define REG_VID_CHA_SYNC_DELAY_LOW 0x28 104 #define REG_VID_CHA_SYNC_DELAY_HIGH 0x29 105 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW 0x2c 106 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH 0x2d 107 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW 0x30 108 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH 0x31 109 #define REG_VID_CHA_HORIZONTAL_BACK_PORCH 0x34 110 #define REG_VID_CHA_VERTICAL_BACK_PORCH 0x36 111 #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH 0x38 112 #define REG_VID_CHA_VERTICAL_FRONT_PORCH 0x3a 113 #define REG_VID_CHA_TEST_PATTERN 0x3c 114 /* IRQ registers */ 115 #define REG_IRQ_GLOBAL 0xe0 116 #define REG_IRQ_GLOBAL_IRQ_EN BIT(0) 117 #define REG_IRQ_EN 0xe1 118 #define REG_IRQ_EN_CHA_SYNCH_ERR_EN BIT(7) 119 #define REG_IRQ_EN_CHA_CRC_ERR_EN BIT(6) 120 #define REG_IRQ_EN_CHA_UNC_ECC_ERR_EN BIT(5) 121 #define REG_IRQ_EN_CHA_COR_ECC_ERR_EN BIT(4) 122 #define REG_IRQ_EN_CHA_LLP_ERR_EN BIT(3) 123 #define REG_IRQ_EN_CHA_SOT_BIT_ERR_EN BIT(2) 124 #define REG_IRQ_EN_CHA_PLL_UNLOCK_EN BIT(0) 125 #define REG_IRQ_STAT 0xe5 126 #define REG_IRQ_STAT_CHA_SYNCH_ERR BIT(7) 127 #define REG_IRQ_STAT_CHA_CRC_ERR BIT(6) 128 #define REG_IRQ_STAT_CHA_UNC_ECC_ERR BIT(5) 129 #define REG_IRQ_STAT_CHA_COR_ECC_ERR BIT(4) 130 #define REG_IRQ_STAT_CHA_LLP_ERR BIT(3) 131 #define REG_IRQ_STAT_CHA_SOT_BIT_ERR BIT(2) 132 #define REG_IRQ_STAT_CHA_PLL_UNLOCK BIT(0) 133 134 enum sn65dsi83_model { 135 MODEL_SN65DSI83, 136 MODEL_SN65DSI84, 137 }; 138 139 struct sn65dsi83 { 140 struct drm_bridge bridge; 141 struct device *dev; 142 struct regmap *regmap; 143 struct device_node *host_node; 144 struct mipi_dsi_device *dsi; 145 struct drm_bridge *panel_bridge; 146 struct gpio_desc *enable_gpio; 147 struct regulator *vcc; 148 int dsi_lanes; 149 bool lvds_dual_link; 150 bool lvds_dual_link_even_odd_swap; 151 }; 152 153 static const struct regmap_range sn65dsi83_readable_ranges[] = { 154 regmap_reg_range(REG_ID(0), REG_ID(8)), 155 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_DSI_CLK), 156 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN), 157 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK), 158 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM), 159 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 160 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH), 161 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 162 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH), 163 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW, 164 REG_VID_CHA_SYNC_DELAY_HIGH), 165 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 166 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH), 167 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 168 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH), 169 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH, 170 REG_VID_CHA_HORIZONTAL_BACK_PORCH), 171 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH, 172 REG_VID_CHA_VERTICAL_BACK_PORCH), 173 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 174 REG_VID_CHA_HORIZONTAL_FRONT_PORCH), 175 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH, 176 REG_VID_CHA_VERTICAL_FRONT_PORCH), 177 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN), 178 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN), 179 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 180 }; 181 182 static const struct regmap_access_table sn65dsi83_readable_table = { 183 .yes_ranges = sn65dsi83_readable_ranges, 184 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_readable_ranges), 185 }; 186 187 static const struct regmap_range sn65dsi83_writeable_ranges[] = { 188 regmap_reg_range(REG_RC_RESET, REG_RC_DSI_CLK), 189 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN), 190 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK), 191 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM), 192 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 193 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH), 194 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 195 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH), 196 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW, 197 REG_VID_CHA_SYNC_DELAY_HIGH), 198 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 199 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH), 200 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 201 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH), 202 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH, 203 REG_VID_CHA_HORIZONTAL_BACK_PORCH), 204 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH, 205 REG_VID_CHA_VERTICAL_BACK_PORCH), 206 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 207 REG_VID_CHA_HORIZONTAL_FRONT_PORCH), 208 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH, 209 REG_VID_CHA_VERTICAL_FRONT_PORCH), 210 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN), 211 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN), 212 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 213 }; 214 215 static const struct regmap_access_table sn65dsi83_writeable_table = { 216 .yes_ranges = sn65dsi83_writeable_ranges, 217 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_writeable_ranges), 218 }; 219 220 static const struct regmap_range sn65dsi83_volatile_ranges[] = { 221 regmap_reg_range(REG_RC_RESET, REG_RC_RESET), 222 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_LVDS_PLL), 223 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 224 }; 225 226 static const struct regmap_access_table sn65dsi83_volatile_table = { 227 .yes_ranges = sn65dsi83_volatile_ranges, 228 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_volatile_ranges), 229 }; 230 231 static const struct regmap_config sn65dsi83_regmap_config = { 232 .reg_bits = 8, 233 .val_bits = 8, 234 .rd_table = &sn65dsi83_readable_table, 235 .wr_table = &sn65dsi83_writeable_table, 236 .volatile_table = &sn65dsi83_volatile_table, 237 .cache_type = REGCACHE_RBTREE, 238 .max_register = REG_IRQ_STAT, 239 }; 240 241 static struct sn65dsi83 *bridge_to_sn65dsi83(struct drm_bridge *bridge) 242 { 243 return container_of(bridge, struct sn65dsi83, bridge); 244 } 245 246 static int sn65dsi83_attach(struct drm_bridge *bridge, 247 enum drm_bridge_attach_flags flags) 248 { 249 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 250 251 return drm_bridge_attach(bridge->encoder, ctx->panel_bridge, 252 &ctx->bridge, flags); 253 } 254 255 static void sn65dsi83_detach(struct drm_bridge *bridge) 256 { 257 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 258 259 if (!ctx->dsi) 260 return; 261 262 ctx->dsi = NULL; 263 } 264 265 static u8 sn65dsi83_get_lvds_range(struct sn65dsi83 *ctx, 266 const struct drm_display_mode *mode) 267 { 268 /* 269 * The encoding of the LVDS_CLK_RANGE is as follows: 270 * 000 - 25 MHz <= LVDS_CLK < 37.5 MHz 271 * 001 - 37.5 MHz <= LVDS_CLK < 62.5 MHz 272 * 010 - 62.5 MHz <= LVDS_CLK < 87.5 MHz 273 * 011 - 87.5 MHz <= LVDS_CLK < 112.5 MHz 274 * 100 - 112.5 MHz <= LVDS_CLK < 137.5 MHz 275 * 101 - 137.5 MHz <= LVDS_CLK <= 154 MHz 276 * which is a range of 12.5MHz..162.5MHz in 50MHz steps, except that 277 * the ends of the ranges are clamped to the supported range. Since 278 * sn65dsi83_mode_valid() already filters the valid modes and limits 279 * the clock to 25..154 MHz, the range calculation can be simplified 280 * as follows: 281 */ 282 int mode_clock = mode->clock; 283 284 if (ctx->lvds_dual_link) 285 mode_clock /= 2; 286 287 return (mode_clock - 12500) / 25000; 288 } 289 290 static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx, 291 const struct drm_display_mode *mode) 292 { 293 /* 294 * The encoding of the CHA_DSI_CLK_RANGE is as follows: 295 * 0x00 through 0x07 - Reserved 296 * 0x08 - 40 <= DSI_CLK < 45 MHz 297 * 0x09 - 45 <= DSI_CLK < 50 MHz 298 * ... 299 * 0x63 - 495 <= DSI_CLK < 500 MHz 300 * 0x64 - 500 MHz 301 * 0x65 through 0xFF - Reserved 302 * which is DSI clock in 5 MHz steps, clamped to 40..500 MHz. 303 * The DSI clock are calculated as: 304 * DSI_CLK = mode clock * bpp / dsi_data_lanes / 2 305 * the 2 is there because the bus is DDR. 306 */ 307 return DIV_ROUND_UP(clamp((unsigned int)mode->clock * 308 mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) / 309 ctx->dsi_lanes / 2, 40000U, 500000U), 5000U); 310 } 311 312 static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx) 313 { 314 /* The divider is (DSI_CLK / LVDS_CLK) - 1, which really is: */ 315 unsigned int dsi_div = mipi_dsi_pixel_format_to_bpp(ctx->dsi->format); 316 317 dsi_div /= ctx->dsi_lanes; 318 319 if (!ctx->lvds_dual_link) 320 dsi_div /= 2; 321 322 return dsi_div - 1; 323 } 324 325 static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, 326 struct drm_bridge_state *old_bridge_state) 327 { 328 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 329 struct drm_atomic_state *state = old_bridge_state->base.state; 330 const struct drm_bridge_state *bridge_state; 331 const struct drm_crtc_state *crtc_state; 332 const struct drm_display_mode *mode; 333 struct drm_connector *connector; 334 struct drm_crtc *crtc; 335 bool lvds_format_24bpp; 336 bool lvds_format_jeida; 337 unsigned int pval; 338 __le16 le16val; 339 u16 val; 340 int ret; 341 342 ret = regulator_enable(ctx->vcc); 343 if (ret) { 344 dev_err(ctx->dev, "Failed to enable vcc: %d\n", ret); 345 return; 346 } 347 348 /* Deassert reset */ 349 gpiod_set_value(ctx->enable_gpio, 1); 350 usleep_range(1000, 1100); 351 352 /* Get the LVDS format from the bridge state. */ 353 bridge_state = drm_atomic_get_new_bridge_state(state, bridge); 354 355 switch (bridge_state->output_bus_cfg.format) { 356 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 357 lvds_format_24bpp = false; 358 lvds_format_jeida = true; 359 break; 360 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 361 lvds_format_24bpp = true; 362 lvds_format_jeida = true; 363 break; 364 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 365 lvds_format_24bpp = true; 366 lvds_format_jeida = false; 367 break; 368 default: 369 /* 370 * Some bridges still don't set the correct 371 * LVDS bus pixel format, use SPWG24 default 372 * format until those are fixed. 373 */ 374 lvds_format_24bpp = true; 375 lvds_format_jeida = false; 376 dev_warn(ctx->dev, 377 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n", 378 bridge_state->output_bus_cfg.format); 379 break; 380 } 381 382 /* 383 * Retrieve the CRTC adjusted mode. This requires a little dance to go 384 * from the bridge to the encoder, to the connector and to the CRTC. 385 */ 386 connector = drm_atomic_get_new_connector_for_encoder(state, 387 bridge->encoder); 388 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 389 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 390 mode = &crtc_state->adjusted_mode; 391 392 /* Clear reset, disable PLL */ 393 regmap_write(ctx->regmap, REG_RC_RESET, 0x00); 394 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); 395 396 /* Reference clock derived from DSI link clock. */ 397 regmap_write(ctx->regmap, REG_RC_LVDS_PLL, 398 REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx, mode)) | 399 REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY); 400 regmap_write(ctx->regmap, REG_DSI_CLK, 401 REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx, mode))); 402 regmap_write(ctx->regmap, REG_RC_DSI_CLK, 403 REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx))); 404 405 /* Set number of DSI lanes and LVDS link config. */ 406 regmap_write(ctx->regmap, REG_DSI_LANE, 407 REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE | 408 REG_DSI_LANE_CHA_DSI_LANES(~(ctx->dsi_lanes - 1)) | 409 /* CHB is DSI85-only, set to default on DSI83/DSI84 */ 410 REG_DSI_LANE_CHB_DSI_LANES(3)); 411 /* No equalization. */ 412 regmap_write(ctx->regmap, REG_DSI_EQ, 0x00); 413 414 /* Set up sync signal polarity. */ 415 val = (mode->flags & DRM_MODE_FLAG_NHSYNC ? 416 REG_LVDS_FMT_HS_NEG_POLARITY : 0) | 417 (mode->flags & DRM_MODE_FLAG_NVSYNC ? 418 REG_LVDS_FMT_VS_NEG_POLARITY : 0); 419 420 /* Set up bits-per-pixel, 18bpp or 24bpp. */ 421 if (lvds_format_24bpp) { 422 val |= REG_LVDS_FMT_CHA_24BPP_MODE; 423 if (ctx->lvds_dual_link) 424 val |= REG_LVDS_FMT_CHB_24BPP_MODE; 425 } 426 427 /* Set up LVDS format, JEIDA/Format 1 or SPWG/Format 2 */ 428 if (lvds_format_jeida) { 429 val |= REG_LVDS_FMT_CHA_24BPP_FORMAT1; 430 if (ctx->lvds_dual_link) 431 val |= REG_LVDS_FMT_CHB_24BPP_FORMAT1; 432 } 433 434 /* Set up LVDS output config (DSI84,DSI85) */ 435 if (!ctx->lvds_dual_link) 436 val |= REG_LVDS_FMT_LVDS_LINK_CFG; 437 438 regmap_write(ctx->regmap, REG_LVDS_FMT, val); 439 regmap_write(ctx->regmap, REG_LVDS_VCOM, 0x05); 440 regmap_write(ctx->regmap, REG_LVDS_LANE, 441 (ctx->lvds_dual_link_even_odd_swap ? 442 REG_LVDS_LANE_EVEN_ODD_SWAP : 0) | 443 REG_LVDS_LANE_CHA_LVDS_TERM | 444 REG_LVDS_LANE_CHB_LVDS_TERM); 445 regmap_write(ctx->regmap, REG_LVDS_CM, 0x00); 446 447 le16val = cpu_to_le16(mode->hdisplay); 448 regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 449 &le16val, 2); 450 le16val = cpu_to_le16(mode->vdisplay); 451 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 452 &le16val, 2); 453 /* 32 + 1 pixel clock to ensure proper operation */ 454 le16val = cpu_to_le16(32 + 1); 455 regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &le16val, 2); 456 le16val = cpu_to_le16(mode->hsync_end - mode->hsync_start); 457 regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 458 &le16val, 2); 459 le16val = cpu_to_le16(mode->vsync_end - mode->vsync_start); 460 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 461 &le16val, 2); 462 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH, 463 mode->htotal - mode->hsync_end); 464 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH, 465 mode->vtotal - mode->vsync_end); 466 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 467 mode->hsync_start - mode->hdisplay); 468 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH, 469 mode->vsync_start - mode->vdisplay); 470 regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00); 471 472 /* Enable PLL */ 473 regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN); 474 usleep_range(3000, 4000); 475 ret = regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval, 476 pval & REG_RC_LVDS_PLL_PLL_EN_STAT, 477 1000, 100000); 478 if (ret) { 479 dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret); 480 /* On failure, disable PLL again and exit. */ 481 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); 482 return; 483 } 484 485 /* Trigger reset after CSR register update. */ 486 regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET); 487 488 /* Clear all errors that got asserted during initialization. */ 489 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); 490 regmap_write(ctx->regmap, REG_IRQ_STAT, pval); 491 492 usleep_range(10000, 12000); 493 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); 494 if (pval) 495 dev_err(ctx->dev, "Unexpected link status 0x%02x\n", pval); 496 } 497 498 static void sn65dsi83_atomic_disable(struct drm_bridge *bridge, 499 struct drm_bridge_state *old_bridge_state) 500 { 501 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 502 int ret; 503 504 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */ 505 gpiod_set_value(ctx->enable_gpio, 0); 506 usleep_range(10000, 11000); 507 508 ret = regulator_disable(ctx->vcc); 509 if (ret) 510 dev_err(ctx->dev, "Failed to disable vcc: %d\n", ret); 511 512 regcache_mark_dirty(ctx->regmap); 513 } 514 515 static enum drm_mode_status 516 sn65dsi83_mode_valid(struct drm_bridge *bridge, 517 const struct drm_display_info *info, 518 const struct drm_display_mode *mode) 519 { 520 /* LVDS output clock range 25..154 MHz */ 521 if (mode->clock < 25000) 522 return MODE_CLOCK_LOW; 523 if (mode->clock > 154000) 524 return MODE_CLOCK_HIGH; 525 526 return MODE_OK; 527 } 528 529 #define MAX_INPUT_SEL_FORMATS 1 530 531 static u32 * 532 sn65dsi83_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 533 struct drm_bridge_state *bridge_state, 534 struct drm_crtc_state *crtc_state, 535 struct drm_connector_state *conn_state, 536 u32 output_fmt, 537 unsigned int *num_input_fmts) 538 { 539 u32 *input_fmts; 540 541 *num_input_fmts = 0; 542 543 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 544 GFP_KERNEL); 545 if (!input_fmts) 546 return NULL; 547 548 /* This is the DSI-end bus format */ 549 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 550 *num_input_fmts = 1; 551 552 return input_fmts; 553 } 554 555 static const struct drm_bridge_funcs sn65dsi83_funcs = { 556 .attach = sn65dsi83_attach, 557 .detach = sn65dsi83_detach, 558 .atomic_enable = sn65dsi83_atomic_enable, 559 .atomic_disable = sn65dsi83_atomic_disable, 560 .mode_valid = sn65dsi83_mode_valid, 561 562 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 563 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 564 .atomic_reset = drm_atomic_helper_bridge_reset, 565 .atomic_get_input_bus_fmts = sn65dsi83_atomic_get_input_bus_fmts, 566 }; 567 568 static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model) 569 { 570 struct drm_bridge *panel_bridge; 571 struct device *dev = ctx->dev; 572 struct device_node *endpoint; 573 int ret; 574 575 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0); 576 ctx->dsi_lanes = of_property_count_u32_elems(endpoint, "data-lanes"); 577 ctx->host_node = of_graph_get_remote_port_parent(endpoint); 578 of_node_put(endpoint); 579 580 if (ctx->dsi_lanes < 0 || ctx->dsi_lanes > 4) { 581 ret = -EINVAL; 582 goto err_put_node; 583 } 584 if (!ctx->host_node) { 585 ret = -ENODEV; 586 goto err_put_node; 587 } 588 589 ctx->lvds_dual_link = false; 590 ctx->lvds_dual_link_even_odd_swap = false; 591 if (model != MODEL_SN65DSI83) { 592 struct device_node *port2, *port3; 593 int dual_link; 594 595 port2 = of_graph_get_port_by_id(dev->of_node, 2); 596 port3 = of_graph_get_port_by_id(dev->of_node, 3); 597 dual_link = drm_of_lvds_get_dual_link_pixel_order(port2, port3); 598 of_node_put(port2); 599 of_node_put(port3); 600 601 if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) { 602 ctx->lvds_dual_link = true; 603 /* Odd pixels to LVDS Channel A, even pixels to B */ 604 ctx->lvds_dual_link_even_odd_swap = false; 605 } else if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) { 606 ctx->lvds_dual_link = true; 607 /* Even pixels to LVDS Channel A, odd pixels to B */ 608 ctx->lvds_dual_link_even_odd_swap = true; 609 } 610 } 611 612 panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0); 613 if (IS_ERR(panel_bridge)) { 614 ret = PTR_ERR(panel_bridge); 615 goto err_put_node; 616 } 617 618 ctx->panel_bridge = panel_bridge; 619 620 ctx->vcc = devm_regulator_get(dev, "vcc"); 621 if (IS_ERR(ctx->vcc)) 622 return dev_err_probe(dev, PTR_ERR(ctx->vcc), 623 "Failed to get supply 'vcc'\n"); 624 625 return 0; 626 627 err_put_node: 628 of_node_put(ctx->host_node); 629 return ret; 630 } 631 632 static int sn65dsi83_host_attach(struct sn65dsi83 *ctx) 633 { 634 struct device *dev = ctx->dev; 635 struct mipi_dsi_device *dsi; 636 struct mipi_dsi_host *host; 637 const struct mipi_dsi_device_info info = { 638 .type = "sn65dsi83", 639 .channel = 0, 640 .node = NULL, 641 }; 642 int ret; 643 644 host = of_find_mipi_dsi_host_by_node(ctx->host_node); 645 if (!host) { 646 dev_err(dev, "failed to find dsi host\n"); 647 return -EPROBE_DEFER; 648 } 649 650 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 651 if (IS_ERR(dsi)) 652 return dev_err_probe(dev, PTR_ERR(dsi), 653 "failed to create dsi device\n"); 654 655 ctx->dsi = dsi; 656 657 dsi->lanes = ctx->dsi_lanes; 658 dsi->format = MIPI_DSI_FMT_RGB888; 659 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST; 660 661 ret = devm_mipi_dsi_attach(dev, dsi); 662 if (ret < 0) { 663 dev_err(dev, "failed to attach dsi to host: %d\n", ret); 664 return ret; 665 } 666 667 return 0; 668 } 669 670 static int sn65dsi83_probe(struct i2c_client *client, 671 const struct i2c_device_id *id) 672 { 673 struct device *dev = &client->dev; 674 enum sn65dsi83_model model; 675 struct sn65dsi83 *ctx; 676 int ret; 677 678 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 679 if (!ctx) 680 return -ENOMEM; 681 682 ctx->dev = dev; 683 684 if (dev->of_node) { 685 model = (enum sn65dsi83_model)(uintptr_t) 686 of_device_get_match_data(dev); 687 } else { 688 model = id->driver_data; 689 } 690 691 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */ 692 ctx->enable_gpio = devm_gpiod_get_optional(ctx->dev, "enable", 693 GPIOD_OUT_LOW); 694 if (IS_ERR(ctx->enable_gpio)) 695 return PTR_ERR(ctx->enable_gpio); 696 697 usleep_range(10000, 11000); 698 699 ret = sn65dsi83_parse_dt(ctx, model); 700 if (ret) 701 return ret; 702 703 ctx->regmap = devm_regmap_init_i2c(client, &sn65dsi83_regmap_config); 704 if (IS_ERR(ctx->regmap)) { 705 ret = PTR_ERR(ctx->regmap); 706 goto err_put_node; 707 } 708 709 dev_set_drvdata(dev, ctx); 710 i2c_set_clientdata(client, ctx); 711 712 ctx->bridge.funcs = &sn65dsi83_funcs; 713 ctx->bridge.of_node = dev->of_node; 714 drm_bridge_add(&ctx->bridge); 715 716 ret = sn65dsi83_host_attach(ctx); 717 if (ret) 718 goto err_remove_bridge; 719 720 return 0; 721 722 err_remove_bridge: 723 drm_bridge_remove(&ctx->bridge); 724 err_put_node: 725 of_node_put(ctx->host_node); 726 return ret; 727 } 728 729 static int sn65dsi83_remove(struct i2c_client *client) 730 { 731 struct sn65dsi83 *ctx = i2c_get_clientdata(client); 732 733 drm_bridge_remove(&ctx->bridge); 734 of_node_put(ctx->host_node); 735 736 return 0; 737 } 738 739 static struct i2c_device_id sn65dsi83_id[] = { 740 { "ti,sn65dsi83", MODEL_SN65DSI83 }, 741 { "ti,sn65dsi84", MODEL_SN65DSI84 }, 742 {}, 743 }; 744 MODULE_DEVICE_TABLE(i2c, sn65dsi83_id); 745 746 static const struct of_device_id sn65dsi83_match_table[] = { 747 { .compatible = "ti,sn65dsi83", .data = (void *)MODEL_SN65DSI83 }, 748 { .compatible = "ti,sn65dsi84", .data = (void *)MODEL_SN65DSI84 }, 749 {}, 750 }; 751 MODULE_DEVICE_TABLE(of, sn65dsi83_match_table); 752 753 static struct i2c_driver sn65dsi83_driver = { 754 .probe = sn65dsi83_probe, 755 .remove = sn65dsi83_remove, 756 .id_table = sn65dsi83_id, 757 .driver = { 758 .name = "sn65dsi83", 759 .of_match_table = sn65dsi83_match_table, 760 }, 761 }; 762 module_i2c_driver(sn65dsi83_driver); 763 764 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 765 MODULE_DESCRIPTION("TI SN65DSI83 DSI to LVDS bridge driver"); 766 MODULE_LICENSE("GPL v2"); 767