1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * TC358775 DSI to LVDS bridge driver 4 * 5 * Copyright (C) 2020 SMART Wireless Computing 6 * Author: Vinay Simha BN <simhavcs@gmail.com> 7 * 8 */ 9 /* #define DEBUG */ 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/i2c.h> 15 #include <linux/kernel.h> 16 #include <linux/media-bus-format.h> 17 #include <linux/module.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/slab.h> 20 21 #include <asm/unaligned.h> 22 23 #include <drm/display/drm_dp_helper.h> 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_bridge.h> 26 #include <drm/drm_crtc_helper.h> 27 #include <drm/drm_mipi_dsi.h> 28 #include <drm/drm_of.h> 29 #include <drm/drm_panel.h> 30 #include <drm/drm_probe_helper.h> 31 32 #define FLD_VAL(val, start, end) FIELD_PREP(GENMASK(start, end), val) 33 34 /* Registers */ 35 36 /* DSI D-PHY Layer Registers */ 37 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */ 38 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */ 39 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */ 40 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */ 41 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */ 42 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */ 43 #define COM_DPHYCONTRX 0x0038 /* DPHY Rx Common Control */ 44 #define CLW_CNTRL 0x0040 /* Clock Lane Control */ 45 #define D0W_CNTRL 0x0044 /* Data Lane 0 Control */ 46 #define D1W_CNTRL 0x0048 /* Data Lane 1 Control */ 47 #define D2W_CNTRL 0x004C /* Data Lane 2 Control */ 48 #define D3W_CNTRL 0x0050 /* Data Lane 3 Control */ 49 #define DFTMODE_CNTRL 0x0054 /* DFT Mode Control */ 50 51 /* DSI PPI Layer Registers */ 52 #define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */ 53 #define PPI_START_FUNCTION 1 54 55 #define PPI_BUSYPPI 0x0108 56 #define PPI_LINEINITCNT 0x0110 /* Line Initialization Wait Counter */ 57 #define PPI_LPTXTIMECNT 0x0114 58 #define PPI_LANEENABLE 0x0134 /* Enables each lane at the PPI layer. */ 59 #define PPI_TX_RX_TA 0x013C /* DSI Bus Turn Around timing parameters */ 60 61 /* Analog timer function enable */ 62 #define PPI_CLS_ATMR 0x0140 /* Delay for Clock Lane in LPRX */ 63 #define PPI_D0S_ATMR 0x0144 /* Delay for Data Lane 0 in LPRX */ 64 #define PPI_D1S_ATMR 0x0148 /* Delay for Data Lane 1 in LPRX */ 65 #define PPI_D2S_ATMR 0x014C /* Delay for Data Lane 2 in LPRX */ 66 #define PPI_D3S_ATMR 0x0150 /* Delay for Data Lane 3 in LPRX */ 67 68 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* For lane 0 */ 69 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* For lane 1 */ 70 #define PPI_D2S_CLRSIPOCOUNT 0x016C /* For lane 2 */ 71 #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* For lane 3 */ 72 73 #define CLS_PRE 0x0180 /* Digital Counter inside of PHY IO */ 74 #define D0S_PRE 0x0184 /* Digital Counter inside of PHY IO */ 75 #define D1S_PRE 0x0188 /* Digital Counter inside of PHY IO */ 76 #define D2S_PRE 0x018C /* Digital Counter inside of PHY IO */ 77 #define D3S_PRE 0x0190 /* Digital Counter inside of PHY IO */ 78 #define CLS_PREP 0x01A0 /* Digital Counter inside of PHY IO */ 79 #define D0S_PREP 0x01A4 /* Digital Counter inside of PHY IO */ 80 #define D1S_PREP 0x01A8 /* Digital Counter inside of PHY IO */ 81 #define D2S_PREP 0x01AC /* Digital Counter inside of PHY IO */ 82 #define D3S_PREP 0x01B0 /* Digital Counter inside of PHY IO */ 83 #define CLS_ZERO 0x01C0 /* Digital Counter inside of PHY IO */ 84 #define D0S_ZERO 0x01C4 /* Digital Counter inside of PHY IO */ 85 #define D1S_ZERO 0x01C8 /* Digital Counter inside of PHY IO */ 86 #define D2S_ZERO 0x01CC /* Digital Counter inside of PHY IO */ 87 #define D3S_ZERO 0x01D0 /* Digital Counter inside of PHY IO */ 88 89 #define PPI_CLRFLG 0x01E0 /* PRE Counters has reached set values */ 90 #define PPI_CLRSIPO 0x01E4 /* Clear SIPO values, Slave mode use only. */ 91 #define HSTIMEOUT 0x01F0 /* HS Rx Time Out Counter */ 92 #define HSTIMEOUTENABLE 0x01F4 /* Enable HS Rx Time Out Counter */ 93 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX function */ 94 #define DSI_RX_START 1 95 96 #define DSI_BUSYDSI 0x0208 97 #define DSI_LANEENABLE 0x0210 /* Enables each lane at the Protocol layer. */ 98 #define DSI_LANESTATUS0 0x0214 /* Displays lane is in HS RX mode. */ 99 #define DSI_LANESTATUS1 0x0218 /* Displays lane is in ULPS or STOP state */ 100 101 #define DSI_INTSTATUS 0x0220 /* Interrupt Status */ 102 #define DSI_INTMASK 0x0224 /* Interrupt Mask */ 103 #define DSI_INTCLR 0x0228 /* Interrupt Clear */ 104 #define DSI_LPTXTO 0x0230 /* Low Power Tx Time Out Counter */ 105 106 #define DSIERRCNT 0x0300 /* DSI Error Count */ 107 #define APLCTRL 0x0400 /* Application Layer Control */ 108 #define RDPKTLN 0x0404 /* Command Read Packet Length */ 109 110 #define VPCTRL 0x0450 /* Video Path Control */ 111 #define HTIM1 0x0454 /* Horizontal Timing Control 1 */ 112 #define HTIM2 0x0458 /* Horizontal Timing Control 2 */ 113 #define VTIM1 0x045C /* Vertical Timing Control 1 */ 114 #define VTIM2 0x0460 /* Vertical Timing Control 2 */ 115 #define VFUEN 0x0464 /* Video Frame Timing Update Enable */ 116 #define VFUEN_EN BIT(0) /* Upload Enable */ 117 118 /* Mux Input Select for LVDS LINK Input */ 119 #define LV_MX0003 0x0480 /* Bit 0 to 3 */ 120 #define LV_MX0407 0x0484 /* Bit 4 to 7 */ 121 #define LV_MX0811 0x0488 /* Bit 8 to 11 */ 122 #define LV_MX1215 0x048C /* Bit 12 to 15 */ 123 #define LV_MX1619 0x0490 /* Bit 16 to 19 */ 124 #define LV_MX2023 0x0494 /* Bit 20 to 23 */ 125 #define LV_MX2427 0x0498 /* Bit 24 to 27 */ 126 #define LV_MX(b0, b1, b2, b3) (FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \ 127 FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24)) 128 129 /* Input bit numbers used in mux registers */ 130 enum { 131 LVI_R0, 132 LVI_R1, 133 LVI_R2, 134 LVI_R3, 135 LVI_R4, 136 LVI_R5, 137 LVI_R6, 138 LVI_R7, 139 LVI_G0, 140 LVI_G1, 141 LVI_G2, 142 LVI_G3, 143 LVI_G4, 144 LVI_G5, 145 LVI_G6, 146 LVI_G7, 147 LVI_B0, 148 LVI_B1, 149 LVI_B2, 150 LVI_B3, 151 LVI_B4, 152 LVI_B5, 153 LVI_B6, 154 LVI_B7, 155 LVI_HS, 156 LVI_VS, 157 LVI_DE, 158 LVI_L0 159 }; 160 161 #define LVCFG 0x049C /* LVDS Configuration */ 162 #define LVPHY0 0x04A0 /* LVDS PHY 0 */ 163 #define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */ 164 #define LV_PHY0_IS(v) FLD_VAL(v, 15, 14) 165 #define LV_PHY0_ND(v) FLD_VAL(v, 4, 0) /* Frequency range select */ 166 #define LV_PHY0_PRBS_ON(v) FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */ 167 168 #define LVPHY1 0x04A4 /* LVDS PHY 1 */ 169 #define SYSSTAT 0x0500 /* System Status */ 170 #define SYSRST 0x0504 /* System Reset */ 171 172 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */ 173 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */ 174 #define SYS_RST_LCD BIT(2) /* Reset LCD controller */ 175 #define SYS_RST_BM BIT(3) /* Reset Bus Management controller */ 176 #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */ 177 #define SYS_RST_REG BIT(5) /* Reset Register module */ 178 179 /* GPIO Registers */ 180 #define GPIOC 0x0520 /* GPIO Control */ 181 #define GPIOO 0x0524 /* GPIO Output */ 182 #define GPIOI 0x0528 /* GPIO Input */ 183 184 /* I2C Registers */ 185 #define I2CTIMCTRL 0x0540 /* I2C IF Timing and Enable Control */ 186 #define I2CMADDR 0x0544 /* I2C Master Addressing */ 187 #define WDATAQ 0x0548 /* Write Data Queue */ 188 #define RDATAQ 0x054C /* Read Data Queue */ 189 190 /* Chip ID and Revision ID Register */ 191 #define IDREG 0x0580 192 193 #define LPX_PERIOD 4 194 #define TTA_GET 0x40000 195 #define TTA_SURE 6 196 #define SINGLE_LINK 1 197 #define DUAL_LINK 2 198 199 #define TC358775XBG_ID 0x00007500 200 201 /* Debug Registers */ 202 #define DEBUG00 0x05A0 /* Debug */ 203 #define DEBUG01 0x05A4 /* LVDS Data */ 204 205 #define DSI_CLEN_BIT BIT(0) 206 #define DIVIDE_BY_3 3 /* PCLK=DCLK/3 */ 207 #define DIVIDE_BY_6 6 /* PCLK=DCLK/6 */ 208 #define LVCFG_LVEN_BIT BIT(0) 209 210 #define L0EN BIT(1) 211 212 #define TC358775_VPCTRL_VSDELAY__MASK 0x3FF00000 213 #define TC358775_VPCTRL_VSDELAY__SHIFT 20 214 static inline u32 TC358775_VPCTRL_VSDELAY(uint32_t val) 215 { 216 return ((val) << TC358775_VPCTRL_VSDELAY__SHIFT) & 217 TC358775_VPCTRL_VSDELAY__MASK; 218 } 219 220 #define TC358775_VPCTRL_OPXLFMT__MASK 0x00000100 221 #define TC358775_VPCTRL_OPXLFMT__SHIFT 8 222 static inline u32 TC358775_VPCTRL_OPXLFMT(uint32_t val) 223 { 224 return ((val) << TC358775_VPCTRL_OPXLFMT__SHIFT) & 225 TC358775_VPCTRL_OPXLFMT__MASK; 226 } 227 228 #define TC358775_VPCTRL_MSF__MASK 0x00000001 229 #define TC358775_VPCTRL_MSF__SHIFT 0 230 static inline u32 TC358775_VPCTRL_MSF(uint32_t val) 231 { 232 return ((val) << TC358775_VPCTRL_MSF__SHIFT) & 233 TC358775_VPCTRL_MSF__MASK; 234 } 235 236 #define TC358775_LVCFG_PCLKDIV__MASK 0x000000f0 237 #define TC358775_LVCFG_PCLKDIV__SHIFT 4 238 static inline u32 TC358775_LVCFG_PCLKDIV(uint32_t val) 239 { 240 return ((val) << TC358775_LVCFG_PCLKDIV__SHIFT) & 241 TC358775_LVCFG_PCLKDIV__MASK; 242 } 243 244 #define TC358775_LVCFG_LVDLINK__MASK 0x00000002 245 #define TC358775_LVCFG_LVDLINK__SHIFT 1 246 static inline u32 TC358775_LVCFG_LVDLINK(uint32_t val) 247 { 248 return ((val) << TC358775_LVCFG_LVDLINK__SHIFT) & 249 TC358775_LVCFG_LVDLINK__MASK; 250 } 251 252 enum tc358775_ports { 253 TC358775_DSI_IN, 254 TC358775_LVDS_OUT0, 255 TC358775_LVDS_OUT1, 256 }; 257 258 struct tc_data { 259 struct i2c_client *i2c; 260 struct device *dev; 261 262 struct drm_bridge bridge; 263 struct drm_bridge *panel_bridge; 264 265 struct device_node *host_node; 266 struct mipi_dsi_device *dsi; 267 u8 num_dsi_lanes; 268 269 struct regulator *vdd; 270 struct regulator *vddio; 271 struct gpio_desc *reset_gpio; 272 struct gpio_desc *stby_gpio; 273 u8 lvds_link; /* single-link or dual-link */ 274 u8 bpc; 275 }; 276 277 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b) 278 { 279 return container_of(b, struct tc_data, bridge); 280 } 281 282 static void tc_bridge_pre_enable(struct drm_bridge *bridge) 283 { 284 struct tc_data *tc = bridge_to_tc(bridge); 285 struct device *dev = &tc->dsi->dev; 286 int ret; 287 288 ret = regulator_enable(tc->vddio); 289 if (ret < 0) 290 dev_err(dev, "regulator vddio enable failed, %d\n", ret); 291 usleep_range(10000, 11000); 292 293 ret = regulator_enable(tc->vdd); 294 if (ret < 0) 295 dev_err(dev, "regulator vdd enable failed, %d\n", ret); 296 usleep_range(10000, 11000); 297 298 gpiod_set_value(tc->stby_gpio, 0); 299 usleep_range(10000, 11000); 300 301 gpiod_set_value(tc->reset_gpio, 0); 302 usleep_range(10, 20); 303 } 304 305 static void tc_bridge_post_disable(struct drm_bridge *bridge) 306 { 307 struct tc_data *tc = bridge_to_tc(bridge); 308 struct device *dev = &tc->dsi->dev; 309 int ret; 310 311 gpiod_set_value(tc->reset_gpio, 1); 312 usleep_range(10, 20); 313 314 gpiod_set_value(tc->stby_gpio, 1); 315 usleep_range(10000, 11000); 316 317 ret = regulator_disable(tc->vdd); 318 if (ret < 0) 319 dev_err(dev, "regulator vdd disable failed, %d\n", ret); 320 usleep_range(10000, 11000); 321 322 ret = regulator_disable(tc->vddio); 323 if (ret < 0) 324 dev_err(dev, "regulator vddio disable failed, %d\n", ret); 325 usleep_range(10000, 11000); 326 } 327 328 static void d2l_read(struct i2c_client *i2c, u16 addr, u32 *val) 329 { 330 int ret; 331 u8 buf_addr[2]; 332 333 put_unaligned_be16(addr, buf_addr); 334 ret = i2c_master_send(i2c, buf_addr, sizeof(buf_addr)); 335 if (ret < 0) 336 goto fail; 337 338 ret = i2c_master_recv(i2c, (u8 *)val, sizeof(*val)); 339 if (ret < 0) 340 goto fail; 341 342 pr_debug("d2l: I2C : addr:%04x value:%08x\n", addr, *val); 343 return; 344 345 fail: 346 dev_err(&i2c->dev, "Error %d reading from subaddress 0x%x\n", 347 ret, addr); 348 } 349 350 static void d2l_write(struct i2c_client *i2c, u16 addr, u32 val) 351 { 352 u8 data[6]; 353 int ret; 354 355 put_unaligned_be16(addr, data); 356 put_unaligned_le32(val, data + 2); 357 358 ret = i2c_master_send(i2c, data, ARRAY_SIZE(data)); 359 if (ret < 0) 360 dev_err(&i2c->dev, "Error %d writing to subaddress 0x%x\n", 361 ret, addr); 362 } 363 364 /* helper function to access bus_formats */ 365 static struct drm_connector *get_connector(struct drm_encoder *encoder) 366 { 367 struct drm_device *dev = encoder->dev; 368 struct drm_connector *connector; 369 370 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 371 if (connector->encoder == encoder) 372 return connector; 373 374 return NULL; 375 } 376 377 static void tc_bridge_enable(struct drm_bridge *bridge) 378 { 379 struct tc_data *tc = bridge_to_tc(bridge); 380 u32 hback_porch, hsync_len, hfront_porch, hactive, htime1, htime2; 381 u32 vback_porch, vsync_len, vfront_porch, vactive, vtime1, vtime2; 382 u32 val = 0; 383 u16 dsiclk, clkdiv, byteclk, t1, t2, t3, vsdelay; 384 struct drm_display_mode *mode; 385 struct drm_connector *connector = get_connector(bridge->encoder); 386 387 mode = &bridge->encoder->crtc->state->adjusted_mode; 388 389 hback_porch = mode->htotal - mode->hsync_end; 390 hsync_len = mode->hsync_end - mode->hsync_start; 391 vback_porch = mode->vtotal - mode->vsync_end; 392 vsync_len = mode->vsync_end - mode->vsync_start; 393 394 htime1 = (hback_porch << 16) + hsync_len; 395 vtime1 = (vback_porch << 16) + vsync_len; 396 397 hfront_porch = mode->hsync_start - mode->hdisplay; 398 hactive = mode->hdisplay; 399 vfront_porch = mode->vsync_start - mode->vdisplay; 400 vactive = mode->vdisplay; 401 402 htime2 = (hfront_porch << 16) + hactive; 403 vtime2 = (vfront_porch << 16) + vactive; 404 405 d2l_read(tc->i2c, IDREG, &val); 406 407 dev_info(tc->dev, "DSI2LVDS Chip ID.%02x Revision ID. %02x **\n", 408 (val >> 8) & 0xFF, val & 0xFF); 409 410 d2l_write(tc->i2c, SYSRST, SYS_RST_REG | SYS_RST_DSIRX | SYS_RST_BM | 411 SYS_RST_LCD | SYS_RST_I2CM | SYS_RST_I2CS); 412 usleep_range(30000, 40000); 413 414 d2l_write(tc->i2c, PPI_TX_RX_TA, TTA_GET | TTA_SURE); 415 d2l_write(tc->i2c, PPI_LPTXTIMECNT, LPX_PERIOD); 416 d2l_write(tc->i2c, PPI_D0S_CLRSIPOCOUNT, 3); 417 d2l_write(tc->i2c, PPI_D1S_CLRSIPOCOUNT, 3); 418 d2l_write(tc->i2c, PPI_D2S_CLRSIPOCOUNT, 3); 419 d2l_write(tc->i2c, PPI_D3S_CLRSIPOCOUNT, 3); 420 421 val = ((L0EN << tc->num_dsi_lanes) - L0EN) | DSI_CLEN_BIT; 422 d2l_write(tc->i2c, PPI_LANEENABLE, val); 423 d2l_write(tc->i2c, DSI_LANEENABLE, val); 424 425 d2l_write(tc->i2c, PPI_STARTPPI, PPI_START_FUNCTION); 426 d2l_write(tc->i2c, DSI_STARTDSI, DSI_RX_START); 427 428 if (tc->bpc == 8) 429 val = TC358775_VPCTRL_OPXLFMT(1); 430 else /* bpc = 6; */ 431 val = TC358775_VPCTRL_MSF(1); 432 433 dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000; 434 clkdiv = dsiclk / (tc->lvds_link == DUAL_LINK ? DIVIDE_BY_6 : DIVIDE_BY_3); 435 byteclk = dsiclk / 4; 436 t1 = hactive * (tc->bpc * 3 / 8) / tc->num_dsi_lanes; 437 t2 = ((100000 / clkdiv)) * (hactive + hback_porch + hsync_len + hfront_porch) / 1000; 438 t3 = ((t2 * byteclk) / 100) - (hactive * (tc->bpc * 3 / 8) / 439 tc->num_dsi_lanes); 440 441 vsdelay = (clkdiv * (t1 + t3) / byteclk) - hback_porch - hsync_len - hactive; 442 443 val |= TC358775_VPCTRL_VSDELAY(vsdelay); 444 d2l_write(tc->i2c, VPCTRL, val); 445 446 d2l_write(tc->i2c, HTIM1, htime1); 447 d2l_write(tc->i2c, VTIM1, vtime1); 448 d2l_write(tc->i2c, HTIM2, htime2); 449 d2l_write(tc->i2c, VTIM2, vtime2); 450 451 d2l_write(tc->i2c, VFUEN, VFUEN_EN); 452 d2l_write(tc->i2c, SYSRST, SYS_RST_LCD); 453 d2l_write(tc->i2c, LVPHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_ND(6)); 454 455 dev_dbg(tc->dev, "bus_formats %04x bpc %d\n", 456 connector->display_info.bus_formats[0], 457 tc->bpc); 458 /* 459 * Default hardware register settings of tc358775 configured 460 * with MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA jeida-24 format 461 */ 462 if (connector->display_info.bus_formats[0] == 463 MEDIA_BUS_FMT_RGB888_1X7X4_SPWG) { 464 /* VESA-24 */ 465 d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3)); 466 d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0)); 467 d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7)); 468 d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0)); 469 d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2)); 470 d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0)); 471 d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6)); 472 } else { /* MEDIA_BUS_FMT_RGB666_1X7X3_SPWG - JEIDA-18 */ 473 d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3)); 474 d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_L0, LVI_R5, LVI_G0)); 475 d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_L0, LVI_L0)); 476 d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0)); 477 d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_L0, LVI_L0, LVI_B1, LVI_B2)); 478 d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0)); 479 d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_L0)); 480 } 481 482 d2l_write(tc->i2c, VFUEN, VFUEN_EN); 483 484 val = LVCFG_LVEN_BIT; 485 if (tc->lvds_link == DUAL_LINK) { 486 val |= TC358775_LVCFG_LVDLINK(1); 487 val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_6); 488 } else { 489 val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_3); 490 } 491 d2l_write(tc->i2c, LVCFG, val); 492 } 493 494 static enum drm_mode_status 495 tc_mode_valid(struct drm_bridge *bridge, 496 const struct drm_display_info *info, 497 const struct drm_display_mode *mode) 498 { 499 struct tc_data *tc = bridge_to_tc(bridge); 500 501 /* 502 * Maximum pixel clock speed 135MHz for single-link 503 * 270MHz for dual-link 504 */ 505 if ((mode->clock > 135000 && tc->lvds_link == SINGLE_LINK) || 506 (mode->clock > 270000 && tc->lvds_link == DUAL_LINK)) 507 return MODE_CLOCK_HIGH; 508 509 switch (info->bus_formats[0]) { 510 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 511 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 512 /* RGB888 */ 513 tc->bpc = 8; 514 break; 515 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 516 /* RGB666 */ 517 tc->bpc = 6; 518 break; 519 default: 520 dev_warn(tc->dev, 521 "unsupported LVDS bus format 0x%04x\n", 522 info->bus_formats[0]); 523 return MODE_NOMODE; 524 } 525 526 return MODE_OK; 527 } 528 529 static int tc358775_parse_dt(struct device_node *np, struct tc_data *tc) 530 { 531 struct device_node *endpoint; 532 struct device_node *parent; 533 struct device_node *remote; 534 int dsi_lanes = -1; 535 536 /* 537 * To get the data-lanes of dsi, we need to access the dsi0_out of port1 538 * of dsi0 endpoint from bridge port0 of d2l_in 539 */ 540 endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node, 541 TC358775_DSI_IN, -1); 542 if (endpoint) { 543 /* dsi0_out node */ 544 parent = of_graph_get_remote_port_parent(endpoint); 545 of_node_put(endpoint); 546 if (parent) { 547 /* dsi0 port 1 */ 548 dsi_lanes = drm_of_get_data_lanes_count_ep(parent, 1, -1, 1, 4); 549 of_node_put(parent); 550 } 551 } 552 553 if (dsi_lanes < 0) 554 return dsi_lanes; 555 556 tc->num_dsi_lanes = dsi_lanes; 557 558 tc->host_node = of_graph_get_remote_node(np, 0, 0); 559 if (!tc->host_node) 560 return -ENODEV; 561 562 of_node_put(tc->host_node); 563 564 tc->lvds_link = SINGLE_LINK; 565 endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node, 566 TC358775_LVDS_OUT1, -1); 567 if (endpoint) { 568 remote = of_graph_get_remote_port_parent(endpoint); 569 of_node_put(endpoint); 570 571 if (remote) { 572 if (of_device_is_available(remote)) 573 tc->lvds_link = DUAL_LINK; 574 of_node_put(remote); 575 } 576 } 577 578 dev_dbg(tc->dev, "no.of dsi lanes: %d\n", tc->num_dsi_lanes); 579 dev_dbg(tc->dev, "operating in %d-link mode\n", tc->lvds_link); 580 581 return 0; 582 } 583 584 static int tc_bridge_attach(struct drm_bridge *bridge, 585 enum drm_bridge_attach_flags flags) 586 { 587 struct tc_data *tc = bridge_to_tc(bridge); 588 589 /* Attach the panel-bridge to the dsi bridge */ 590 return drm_bridge_attach(bridge->encoder, tc->panel_bridge, 591 &tc->bridge, flags); 592 } 593 594 static const struct drm_bridge_funcs tc_bridge_funcs = { 595 .attach = tc_bridge_attach, 596 .pre_enable = tc_bridge_pre_enable, 597 .enable = tc_bridge_enable, 598 .mode_valid = tc_mode_valid, 599 .post_disable = tc_bridge_post_disable, 600 }; 601 602 static int tc_attach_host(struct tc_data *tc) 603 { 604 struct device *dev = &tc->i2c->dev; 605 struct mipi_dsi_host *host; 606 struct mipi_dsi_device *dsi; 607 int ret; 608 const struct mipi_dsi_device_info info = { .type = "tc358775", 609 .channel = 0, 610 .node = NULL, 611 }; 612 613 host = of_find_mipi_dsi_host_by_node(tc->host_node); 614 if (!host) { 615 dev_err(dev, "failed to find dsi host\n"); 616 return -EPROBE_DEFER; 617 } 618 619 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 620 if (IS_ERR(dsi)) { 621 dev_err(dev, "failed to create dsi device\n"); 622 return PTR_ERR(dsi); 623 } 624 625 tc->dsi = dsi; 626 627 dsi->lanes = tc->num_dsi_lanes; 628 dsi->format = MIPI_DSI_FMT_RGB888; 629 dsi->mode_flags = MIPI_DSI_MODE_VIDEO; 630 631 ret = devm_mipi_dsi_attach(dev, dsi); 632 if (ret < 0) { 633 dev_err(dev, "failed to attach dsi to host\n"); 634 return ret; 635 } 636 637 return 0; 638 } 639 640 static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id) 641 { 642 struct device *dev = &client->dev; 643 struct tc_data *tc; 644 int ret; 645 646 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL); 647 if (!tc) 648 return -ENOMEM; 649 650 tc->dev = dev; 651 tc->i2c = client; 652 653 tc->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 654 TC358775_LVDS_OUT0, 0); 655 if (IS_ERR(tc->panel_bridge)) 656 return PTR_ERR(tc->panel_bridge); 657 658 ret = tc358775_parse_dt(dev->of_node, tc); 659 if (ret) 660 return ret; 661 662 tc->vddio = devm_regulator_get(dev, "vddio-supply"); 663 if (IS_ERR(tc->vddio)) { 664 ret = PTR_ERR(tc->vddio); 665 dev_err(dev, "vddio-supply not found\n"); 666 return ret; 667 } 668 669 tc->vdd = devm_regulator_get(dev, "vdd-supply"); 670 if (IS_ERR(tc->vdd)) { 671 ret = PTR_ERR(tc->vdd); 672 dev_err(dev, "vdd-supply not found\n"); 673 return ret; 674 } 675 676 tc->stby_gpio = devm_gpiod_get(dev, "stby", GPIOD_OUT_HIGH); 677 if (IS_ERR(tc->stby_gpio)) { 678 ret = PTR_ERR(tc->stby_gpio); 679 dev_err(dev, "cannot get stby-gpio %d\n", ret); 680 return ret; 681 } 682 683 tc->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); 684 if (IS_ERR(tc->reset_gpio)) { 685 ret = PTR_ERR(tc->reset_gpio); 686 dev_err(dev, "cannot get reset-gpios %d\n", ret); 687 return ret; 688 } 689 690 tc->bridge.funcs = &tc_bridge_funcs; 691 tc->bridge.of_node = dev->of_node; 692 drm_bridge_add(&tc->bridge); 693 694 i2c_set_clientdata(client, tc); 695 696 ret = tc_attach_host(tc); 697 if (ret) 698 goto err_bridge_remove; 699 700 return 0; 701 702 err_bridge_remove: 703 drm_bridge_remove(&tc->bridge); 704 return ret; 705 } 706 707 static int tc_remove(struct i2c_client *client) 708 { 709 struct tc_data *tc = i2c_get_clientdata(client); 710 711 drm_bridge_remove(&tc->bridge); 712 713 return 0; 714 } 715 716 static const struct i2c_device_id tc358775_i2c_ids[] = { 717 { "tc358775", 0 }, 718 { } 719 }; 720 MODULE_DEVICE_TABLE(i2c, tc358775_i2c_ids); 721 722 static const struct of_device_id tc358775_of_ids[] = { 723 { .compatible = "toshiba,tc358775", }, 724 { } 725 }; 726 MODULE_DEVICE_TABLE(of, tc358775_of_ids); 727 728 static struct i2c_driver tc358775_driver = { 729 .driver = { 730 .name = "tc358775", 731 .of_match_table = tc358775_of_ids, 732 }, 733 .id_table = tc358775_i2c_ids, 734 .probe = tc_probe, 735 .remove = tc_remove, 736 }; 737 module_i2c_driver(tc358775_driver); 738 739 MODULE_AUTHOR("Vinay Simha BN <simhavcs@gmail.com>"); 740 MODULE_DESCRIPTION("TC358775 DSI/LVDS bridge driver"); 741 MODULE_LICENSE("GPL v2"); 742