1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/i2c.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/slab.h> 16 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_drv.h> 19 #include <drm/drm_mipi_dsi.h> 20 #include <drm/drm_of.h> 21 #include <drm/drm_panel.h> 22 #include <video/mipi_display.h> 23 #include <video/videomode.h> 24 25 /* Global (16-bit addressable) */ 26 #define TC358768_CHIPID 0x0000 27 #define TC358768_SYSCTL 0x0002 28 #define TC358768_CONFCTL 0x0004 29 #define TC358768_VSDLY 0x0006 30 #define TC358768_DATAFMT 0x0008 31 #define TC358768_GPIOEN 0x000E 32 #define TC358768_GPIODIR 0x0010 33 #define TC358768_GPIOIN 0x0012 34 #define TC358768_GPIOOUT 0x0014 35 #define TC358768_PLLCTL0 0x0016 36 #define TC358768_PLLCTL1 0x0018 37 #define TC358768_CMDBYTE 0x0022 38 #define TC358768_PP_MISC 0x0032 39 #define TC358768_DSITX_DT 0x0050 40 #define TC358768_FIFOSTATUS 0x00F8 41 42 /* Debug (16-bit addressable) */ 43 #define TC358768_VBUFCTRL 0x00E0 44 #define TC358768_DBG_WIDTH 0x00E2 45 #define TC358768_DBG_VBLANK 0x00E4 46 #define TC358768_DBG_DATA 0x00E8 47 48 /* TX PHY (32-bit addressable) */ 49 #define TC358768_CLW_DPHYCONTTX 0x0100 50 #define TC358768_D0W_DPHYCONTTX 0x0104 51 #define TC358768_D1W_DPHYCONTTX 0x0108 52 #define TC358768_D2W_DPHYCONTTX 0x010C 53 #define TC358768_D3W_DPHYCONTTX 0x0110 54 #define TC358768_CLW_CNTRL 0x0140 55 #define TC358768_D0W_CNTRL 0x0144 56 #define TC358768_D1W_CNTRL 0x0148 57 #define TC358768_D2W_CNTRL 0x014C 58 #define TC358768_D3W_CNTRL 0x0150 59 60 /* TX PPI (32-bit addressable) */ 61 #define TC358768_STARTCNTRL 0x0204 62 #define TC358768_DSITXSTATUS 0x0208 63 #define TC358768_LINEINITCNT 0x0210 64 #define TC358768_LPTXTIMECNT 0x0214 65 #define TC358768_TCLK_HEADERCNT 0x0218 66 #define TC358768_TCLK_TRAILCNT 0x021C 67 #define TC358768_THS_HEADERCNT 0x0220 68 #define TC358768_TWAKEUP 0x0224 69 #define TC358768_TCLK_POSTCNT 0x0228 70 #define TC358768_THS_TRAILCNT 0x022C 71 #define TC358768_HSTXVREGCNT 0x0230 72 #define TC358768_HSTXVREGEN 0x0234 73 #define TC358768_TXOPTIONCNTRL 0x0238 74 #define TC358768_BTACNTRL1 0x023C 75 76 /* TX CTRL (32-bit addressable) */ 77 #define TC358768_DSI_CONTROL 0x040C 78 #define TC358768_DSI_STATUS 0x0410 79 #define TC358768_DSI_INT 0x0414 80 #define TC358768_DSI_INT_ENA 0x0418 81 #define TC358768_DSICMD_RDFIFO 0x0430 82 #define TC358768_DSI_ACKERR 0x0434 83 #define TC358768_DSI_ACKERR_INTENA 0x0438 84 #define TC358768_DSI_ACKERR_HALT 0x043c 85 #define TC358768_DSI_RXERR 0x0440 86 #define TC358768_DSI_RXERR_INTENA 0x0444 87 #define TC358768_DSI_RXERR_HALT 0x0448 88 #define TC358768_DSI_ERR 0x044C 89 #define TC358768_DSI_ERR_INTENA 0x0450 90 #define TC358768_DSI_ERR_HALT 0x0454 91 #define TC358768_DSI_CONFW 0x0500 92 #define TC358768_DSI_LPCMD 0x0500 93 #define TC358768_DSI_RESET 0x0504 94 #define TC358768_DSI_INT_CLR 0x050C 95 #define TC358768_DSI_START 0x0518 96 97 /* DSITX CTRL (16-bit addressable) */ 98 #define TC358768_DSICMD_TX 0x0600 99 #define TC358768_DSICMD_TYPE 0x0602 100 #define TC358768_DSICMD_WC 0x0604 101 #define TC358768_DSICMD_WD0 0x0610 102 #define TC358768_DSICMD_WD1 0x0612 103 #define TC358768_DSICMD_WD2 0x0614 104 #define TC358768_DSICMD_WD3 0x0616 105 #define TC358768_DSI_EVENT 0x0620 106 #define TC358768_DSI_VSW 0x0622 107 #define TC358768_DSI_VBPR 0x0624 108 #define TC358768_DSI_VACT 0x0626 109 #define TC358768_DSI_HSW 0x0628 110 #define TC358768_DSI_HBPR 0x062A 111 #define TC358768_DSI_HACT 0x062C 112 113 /* TC358768_DSI_CONTROL (0x040C) register */ 114 #define TC358768_DSI_CONTROL_DIS_MODE BIT(15) 115 #define TC358768_DSI_CONTROL_TXMD BIT(7) 116 #define TC358768_DSI_CONTROL_HSCKMD BIT(5) 117 #define TC358768_DSI_CONTROL_EOTDIS BIT(0) 118 119 /* TC358768_DSI_CONFW (0x0500) register */ 120 #define TC358768_DSI_CONFW_MODE_SET (5 << 29) 121 #define TC358768_DSI_CONFW_MODE_CLR (6 << 29) 122 #define TC358768_DSI_CONFW_ADDR_DSI_CONTROL (0x3 << 24) 123 124 static const char * const tc358768_supplies[] = { 125 "vddc", "vddmipi", "vddio" 126 }; 127 128 struct tc358768_dsi_output { 129 struct mipi_dsi_device *dev; 130 struct drm_panel *panel; 131 struct drm_bridge *bridge; 132 }; 133 134 struct tc358768_priv { 135 struct device *dev; 136 struct regmap *regmap; 137 struct gpio_desc *reset_gpio; 138 struct regulator_bulk_data supplies[ARRAY_SIZE(tc358768_supplies)]; 139 struct clk *refclk; 140 int enabled; 141 int error; 142 143 struct mipi_dsi_host dsi_host; 144 struct drm_bridge bridge; 145 struct tc358768_dsi_output output; 146 147 u32 pd_lines; /* number of Parallel Port Input Data Lines */ 148 u32 dsi_lanes; /* number of DSI Lanes */ 149 150 /* Parameters for PLL programming */ 151 u32 fbd; /* PLL feedback divider */ 152 u32 prd; /* PLL input divider */ 153 u32 frs; /* PLL Freqency range for HSCK (post divider) */ 154 155 u32 dsiclk; /* pll_clk / 2 */ 156 }; 157 158 static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_host 159 *host) 160 { 161 return container_of(host, struct tc358768_priv, dsi_host); 162 } 163 164 static inline struct tc358768_priv *bridge_to_tc358768(struct drm_bridge 165 *bridge) 166 { 167 return container_of(bridge, struct tc358768_priv, bridge); 168 } 169 170 static int tc358768_clear_error(struct tc358768_priv *priv) 171 { 172 int ret = priv->error; 173 174 priv->error = 0; 175 return ret; 176 } 177 178 static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val) 179 { 180 /* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ 181 int tmpval = val; 182 size_t count = 2; 183 184 if (priv->error) 185 return; 186 187 /* 16-bit register? */ 188 if (reg < 0x100 || reg >= 0x600) 189 count = 1; 190 191 priv->error = regmap_bulk_write(priv->regmap, reg, &tmpval, count); 192 } 193 194 static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val) 195 { 196 size_t count = 2; 197 198 if (priv->error) 199 return; 200 201 /* 16-bit register? */ 202 if (reg < 0x100 || reg >= 0x600) { 203 *val = 0; 204 count = 1; 205 } 206 207 priv->error = regmap_bulk_read(priv->regmap, reg, val, count); 208 } 209 210 static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask, 211 u32 val) 212 { 213 u32 tmp, orig; 214 215 tc358768_read(priv, reg, &orig); 216 tmp = orig & ~mask; 217 tmp |= val & mask; 218 if (tmp != orig) 219 tc358768_write(priv, reg, tmp); 220 } 221 222 static int tc358768_sw_reset(struct tc358768_priv *priv) 223 { 224 /* Assert Reset */ 225 tc358768_write(priv, TC358768_SYSCTL, 1); 226 /* Release Reset, Exit Sleep */ 227 tc358768_write(priv, TC358768_SYSCTL, 0); 228 229 return tc358768_clear_error(priv); 230 } 231 232 static void tc358768_hw_enable(struct tc358768_priv *priv) 233 { 234 int ret; 235 236 if (priv->enabled) 237 return; 238 239 ret = clk_prepare_enable(priv->refclk); 240 if (ret < 0) 241 dev_err(priv->dev, "error enabling refclk (%d)\n", ret); 242 243 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); 244 if (ret < 0) 245 dev_err(priv->dev, "error enabling regulators (%d)\n", ret); 246 247 if (priv->reset_gpio) 248 usleep_range(200, 300); 249 250 /* 251 * The RESX is active low (GPIO_ACTIVE_LOW). 252 * DEASSERT (value = 0) the reset_gpio to enable the chip 253 */ 254 gpiod_set_value_cansleep(priv->reset_gpio, 0); 255 256 /* wait for encoder clocks to stabilize */ 257 usleep_range(1000, 2000); 258 259 priv->enabled = true; 260 } 261 262 static void tc358768_hw_disable(struct tc358768_priv *priv) 263 { 264 int ret; 265 266 if (!priv->enabled) 267 return; 268 269 /* 270 * The RESX is active low (GPIO_ACTIVE_LOW). 271 * ASSERT (value = 1) the reset_gpio to disable the chip 272 */ 273 gpiod_set_value_cansleep(priv->reset_gpio, 1); 274 275 ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies), 276 priv->supplies); 277 if (ret < 0) 278 dev_err(priv->dev, "error disabling regulators (%d)\n", ret); 279 280 clk_disable_unprepare(priv->refclk); 281 282 priv->enabled = false; 283 } 284 285 static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk) 286 { 287 return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->pd_lines); 288 } 289 290 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk) 291 { 292 return (u32)div_u64((u64)pclk * priv->pd_lines, priv->dsi_lanes); 293 } 294 295 static int tc358768_calc_pll(struct tc358768_priv *priv, 296 const struct drm_display_mode *mode, 297 bool verify_only) 298 { 299 static const u32 frs_limits[] = { 300 1000000000, 301 500000000, 302 250000000, 303 125000000, 304 62500000 305 }; 306 unsigned long refclk; 307 u32 prd, target_pll, i, max_pll, min_pll; 308 u32 frs, best_diff, best_pll, best_prd, best_fbd; 309 310 target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000); 311 312 /* pll_clk = RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] */ 313 314 for (i = 0; i < ARRAY_SIZE(frs_limits); i++) 315 if (target_pll >= frs_limits[i]) 316 break; 317 318 if (i == ARRAY_SIZE(frs_limits) || i == 0) 319 return -EINVAL; 320 321 frs = i - 1; 322 max_pll = frs_limits[i - 1]; 323 min_pll = frs_limits[i]; 324 325 refclk = clk_get_rate(priv->refclk); 326 327 best_diff = UINT_MAX; 328 best_pll = 0; 329 best_prd = 0; 330 best_fbd = 0; 331 332 for (prd = 0; prd < 16; ++prd) { 333 u32 divisor = (prd + 1) * (1 << frs); 334 u32 fbd; 335 336 for (fbd = 0; fbd < 512; ++fbd) { 337 u32 pll, diff; 338 339 pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor); 340 341 if (pll >= max_pll || pll < min_pll) 342 continue; 343 344 diff = max(pll, target_pll) - min(pll, target_pll); 345 346 if (diff < best_diff) { 347 best_diff = diff; 348 best_pll = pll; 349 best_prd = prd; 350 best_fbd = fbd; 351 352 if (best_diff == 0) 353 goto found; 354 } 355 } 356 } 357 358 if (best_diff == UINT_MAX) { 359 dev_err(priv->dev, "could not find suitable PLL setup\n"); 360 return -EINVAL; 361 } 362 363 found: 364 if (verify_only) 365 return 0; 366 367 priv->fbd = best_fbd; 368 priv->prd = best_prd; 369 priv->frs = frs; 370 priv->dsiclk = best_pll / 2; 371 372 return 0; 373 } 374 375 static int tc358768_dsi_host_attach(struct mipi_dsi_host *host, 376 struct mipi_dsi_device *dev) 377 { 378 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 379 struct drm_bridge *bridge; 380 struct drm_panel *panel; 381 struct device_node *ep; 382 int ret; 383 384 if (dev->lanes > 4) { 385 dev_err(priv->dev, "unsupported number of data lanes(%u)\n", 386 dev->lanes); 387 return -EINVAL; 388 } 389 390 /* 391 * tc358768 supports both Video and Pulse mode, but the driver only 392 * implements Video (event) mode currently 393 */ 394 if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) { 395 dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n"); 396 return -ENOTSUPP; 397 } 398 399 /* 400 * tc358768 supports RGB888, RGB666, RGB666_PACKED and RGB565, but only 401 * RGB888 is verified. 402 */ 403 if (dev->format != MIPI_DSI_FMT_RGB888) { 404 dev_warn(priv->dev, "Only MIPI_DSI_FMT_RGB888 tested!\n"); 405 return -ENOTSUPP; 406 } 407 408 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel, 409 &bridge); 410 if (ret) 411 return ret; 412 413 if (panel) { 414 bridge = drm_panel_bridge_add_typed(panel, 415 DRM_MODE_CONNECTOR_DSI); 416 if (IS_ERR(bridge)) 417 return PTR_ERR(bridge); 418 } 419 420 priv->output.dev = dev; 421 priv->output.bridge = bridge; 422 priv->output.panel = panel; 423 424 priv->dsi_lanes = dev->lanes; 425 426 /* get input ep (port0/endpoint0) */ 427 ret = -EINVAL; 428 ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0); 429 if (ep) { 430 ret = of_property_read_u32(ep, "data-lines", &priv->pd_lines); 431 432 of_node_put(ep); 433 } 434 435 if (ret) 436 priv->pd_lines = mipi_dsi_pixel_format_to_bpp(dev->format); 437 438 drm_bridge_add(&priv->bridge); 439 440 return 0; 441 } 442 443 static int tc358768_dsi_host_detach(struct mipi_dsi_host *host, 444 struct mipi_dsi_device *dev) 445 { 446 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 447 448 drm_bridge_remove(&priv->bridge); 449 if (priv->output.panel) 450 drm_panel_bridge_remove(priv->output.bridge); 451 452 return 0; 453 } 454 455 static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host, 456 const struct mipi_dsi_msg *msg) 457 { 458 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 459 struct mipi_dsi_packet packet; 460 int ret; 461 462 if (!priv->enabled) { 463 dev_err(priv->dev, "Bridge is not enabled\n"); 464 return -ENODEV; 465 } 466 467 if (msg->rx_len) { 468 dev_warn(priv->dev, "MIPI rx is not supported\n"); 469 return -ENOTSUPP; 470 } 471 472 if (msg->tx_len > 8) { 473 dev_warn(priv->dev, "Maximum 8 byte MIPI tx is supported\n"); 474 return -ENOTSUPP; 475 } 476 477 ret = mipi_dsi_create_packet(&packet, msg); 478 if (ret) 479 return ret; 480 481 if (mipi_dsi_packet_format_is_short(msg->type)) { 482 tc358768_write(priv, TC358768_DSICMD_TYPE, 483 (0x10 << 8) | (packet.header[0] & 0x3f)); 484 tc358768_write(priv, TC358768_DSICMD_WC, 0); 485 tc358768_write(priv, TC358768_DSICMD_WD0, 486 (packet.header[2] << 8) | packet.header[1]); 487 } else { 488 int i; 489 490 tc358768_write(priv, TC358768_DSICMD_TYPE, 491 (0x40 << 8) | (packet.header[0] & 0x3f)); 492 tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length); 493 for (i = 0; i < packet.payload_length; i += 2) { 494 u16 val = packet.payload[i]; 495 496 if (i + 1 < packet.payload_length) 497 val |= packet.payload[i + 1] << 8; 498 499 tc358768_write(priv, TC358768_DSICMD_WD0 + i, val); 500 } 501 } 502 503 /* start transfer */ 504 tc358768_write(priv, TC358768_DSICMD_TX, 1); 505 506 ret = tc358768_clear_error(priv); 507 if (ret) 508 dev_warn(priv->dev, "Software disable failed: %d\n", ret); 509 else 510 ret = packet.size; 511 512 return ret; 513 } 514 515 static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = { 516 .attach = tc358768_dsi_host_attach, 517 .detach = tc358768_dsi_host_detach, 518 .transfer = tc358768_dsi_host_transfer, 519 }; 520 521 static int tc358768_bridge_attach(struct drm_bridge *bridge, 522 enum drm_bridge_attach_flags flags) 523 { 524 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 525 526 if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) { 527 dev_err(priv->dev, "needs atomic updates support\n"); 528 return -ENOTSUPP; 529 } 530 531 return drm_bridge_attach(bridge->encoder, priv->output.bridge, bridge, 532 flags); 533 } 534 535 static enum drm_mode_status 536 tc358768_bridge_mode_valid(struct drm_bridge *bridge, 537 const struct drm_display_info *info, 538 const struct drm_display_mode *mode) 539 { 540 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 541 542 if (tc358768_calc_pll(priv, mode, true)) 543 return MODE_CLOCK_RANGE; 544 545 return MODE_OK; 546 } 547 548 static void tc358768_bridge_disable(struct drm_bridge *bridge) 549 { 550 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 551 int ret; 552 553 /* set FrmStop */ 554 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(15), BIT(15)); 555 556 /* wait at least for one frame */ 557 msleep(50); 558 559 /* clear PP_en */ 560 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), 0); 561 562 /* set RstPtr */ 563 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), BIT(14)); 564 565 ret = tc358768_clear_error(priv); 566 if (ret) 567 dev_warn(priv->dev, "Software disable failed: %d\n", ret); 568 } 569 570 static void tc358768_bridge_post_disable(struct drm_bridge *bridge) 571 { 572 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 573 574 tc358768_hw_disable(priv); 575 } 576 577 static int tc358768_setup_pll(struct tc358768_priv *priv, 578 const struct drm_display_mode *mode) 579 { 580 u32 fbd, prd, frs; 581 int ret; 582 583 ret = tc358768_calc_pll(priv, mode, false); 584 if (ret) { 585 dev_err(priv->dev, "PLL calculation failed: %d\n", ret); 586 return ret; 587 } 588 589 fbd = priv->fbd; 590 prd = priv->prd; 591 frs = priv->frs; 592 593 dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n", 594 clk_get_rate(priv->refclk), fbd, prd, frs); 595 dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, DSIByteClk %u\n", 596 priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4); 597 dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n", 598 tc358768_pll_to_pclk(priv, priv->dsiclk * 2), 599 mode->clock * 1000); 600 601 /* PRD[15:12] FBD[8:0] */ 602 tc358768_write(priv, TC358768_PLLCTL0, (prd << 12) | fbd); 603 604 /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */ 605 tc358768_write(priv, TC358768_PLLCTL1, 606 (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0)); 607 608 /* wait for lock */ 609 usleep_range(1000, 2000); 610 611 /* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */ 612 tc358768_write(priv, TC358768_PLLCTL1, 613 (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0)); 614 615 return tc358768_clear_error(priv); 616 } 617 618 #define TC358768_PRECISION 1000 619 static u32 tc358768_ns_to_cnt(u32 ns, u32 period_nsk) 620 { 621 return (ns * TC358768_PRECISION + period_nsk) / period_nsk; 622 } 623 624 static u32 tc358768_to_ns(u32 nsk) 625 { 626 return (nsk / TC358768_PRECISION); 627 } 628 629 static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) 630 { 631 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 632 struct mipi_dsi_device *dsi_dev = priv->output.dev; 633 unsigned long mode_flags = dsi_dev->mode_flags; 634 u32 val, val2, lptxcnt, hact, data_type; 635 const struct drm_display_mode *mode; 636 u32 dsibclk_nsk, dsiclk_nsk, ui_nsk, phy_delay_nsk; 637 u32 dsiclk, dsibclk, video_start; 638 const u32 internal_delay = 40; 639 int ret, i; 640 641 if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 642 dev_warn_once(priv->dev, "Non-continuous mode unimplemented, falling back to continuous\n"); 643 mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS; 644 } 645 646 tc358768_hw_enable(priv); 647 648 ret = tc358768_sw_reset(priv); 649 if (ret) { 650 dev_err(priv->dev, "Software reset failed: %d\n", ret); 651 tc358768_hw_disable(priv); 652 return; 653 } 654 655 mode = &bridge->encoder->crtc->state->adjusted_mode; 656 ret = tc358768_setup_pll(priv, mode); 657 if (ret) { 658 dev_err(priv->dev, "PLL setup failed: %d\n", ret); 659 tc358768_hw_disable(priv); 660 return; 661 } 662 663 dsiclk = priv->dsiclk; 664 dsibclk = dsiclk / 4; 665 666 /* Data Format Control Register */ 667 val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */ 668 switch (dsi_dev->format) { 669 case MIPI_DSI_FMT_RGB888: 670 val |= (0x3 << 4); 671 hact = mode->hdisplay * 3; 672 video_start = (mode->htotal - mode->hsync_start) * 3; 673 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; 674 break; 675 case MIPI_DSI_FMT_RGB666: 676 val |= (0x4 << 4); 677 hact = mode->hdisplay * 3; 678 video_start = (mode->htotal - mode->hsync_start) * 3; 679 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; 680 break; 681 682 case MIPI_DSI_FMT_RGB666_PACKED: 683 val |= (0x4 << 4) | BIT(3); 684 hact = mode->hdisplay * 18 / 8; 685 video_start = (mode->htotal - mode->hsync_start) * 18 / 8; 686 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; 687 break; 688 689 case MIPI_DSI_FMT_RGB565: 690 val |= (0x5 << 4); 691 hact = mode->hdisplay * 2; 692 video_start = (mode->htotal - mode->hsync_start) * 2; 693 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; 694 break; 695 default: 696 dev_err(priv->dev, "Invalid data format (%u)\n", 697 dsi_dev->format); 698 tc358768_hw_disable(priv); 699 return; 700 } 701 702 /* VSDly[9:0] */ 703 video_start = max(video_start, internal_delay + 1) - internal_delay; 704 tc358768_write(priv, TC358768_VSDLY, video_start); 705 706 tc358768_write(priv, TC358768_DATAFMT, val); 707 tc358768_write(priv, TC358768_DSITX_DT, data_type); 708 709 /* Enable D-PHY (HiZ->LP11) */ 710 tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000); 711 /* Enable lanes */ 712 for (i = 0; i < dsi_dev->lanes; i++) 713 tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000); 714 715 /* DSI Timings */ 716 dsibclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION, 717 dsibclk); 718 dsiclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk); 719 ui_nsk = dsiclk_nsk / 2; 720 phy_delay_nsk = dsibclk_nsk + 2 * dsiclk_nsk; 721 dev_dbg(priv->dev, "dsiclk_nsk: %u\n", dsiclk_nsk); 722 dev_dbg(priv->dev, "ui_nsk: %u\n", ui_nsk); 723 dev_dbg(priv->dev, "dsibclk_nsk: %u\n", dsibclk_nsk); 724 dev_dbg(priv->dev, "phy_delay_nsk: %u\n", phy_delay_nsk); 725 726 /* LP11 > 100us for D-PHY Rx Init */ 727 val = tc358768_ns_to_cnt(100 * 1000, dsibclk_nsk) - 1; 728 dev_dbg(priv->dev, "LINEINITCNT: 0x%x\n", val); 729 tc358768_write(priv, TC358768_LINEINITCNT, val); 730 731 /* LPTimeCnt > 50ns */ 732 val = tc358768_ns_to_cnt(50, dsibclk_nsk) - 1; 733 lptxcnt = val; 734 dev_dbg(priv->dev, "LPTXTIMECNT: 0x%x\n", val); 735 tc358768_write(priv, TC358768_LPTXTIMECNT, val); 736 737 /* 38ns < TCLK_PREPARE < 95ns */ 738 val = tc358768_ns_to_cnt(65, dsibclk_nsk) - 1; 739 /* TCLK_PREPARE > 300ns */ 740 val2 = tc358768_ns_to_cnt(300 + tc358768_to_ns(3 * ui_nsk), 741 dsibclk_nsk); 742 val |= (val2 - tc358768_to_ns(phy_delay_nsk - dsibclk_nsk)) << 8; 743 dev_dbg(priv->dev, "TCLK_HEADERCNT: 0x%x\n", val); 744 tc358768_write(priv, TC358768_TCLK_HEADERCNT, val); 745 746 /* TCLK_TRAIL > 60ns + 3*UI */ 747 val = 60 + tc358768_to_ns(3 * ui_nsk); 748 val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 5; 749 dev_dbg(priv->dev, "TCLK_TRAILCNT: 0x%x\n", val); 750 tc358768_write(priv, TC358768_TCLK_TRAILCNT, val); 751 752 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */ 753 val = 50 + tc358768_to_ns(4 * ui_nsk); 754 val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1; 755 /* THS_ZERO > 145ns + 10*UI */ 756 val2 = tc358768_ns_to_cnt(145 - tc358768_to_ns(ui_nsk), dsibclk_nsk); 757 val |= (val2 - tc358768_to_ns(phy_delay_nsk)) << 8; 758 dev_dbg(priv->dev, "THS_HEADERCNT: 0x%x\n", val); 759 tc358768_write(priv, TC358768_THS_HEADERCNT, val); 760 761 /* TWAKEUP > 1ms in lptxcnt steps */ 762 val = tc358768_ns_to_cnt(1020000, dsibclk_nsk); 763 val = val / (lptxcnt + 1) - 1; 764 dev_dbg(priv->dev, "TWAKEUP: 0x%x\n", val); 765 tc358768_write(priv, TC358768_TWAKEUP, val); 766 767 /* TCLK_POSTCNT > 60ns + 52*UI */ 768 val = tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk), 769 dsibclk_nsk) - 3; 770 dev_dbg(priv->dev, "TCLK_POSTCNT: 0x%x\n", val); 771 tc358768_write(priv, TC358768_TCLK_POSTCNT, val); 772 773 /* 60ns + 4*UI < THS_PREPARE < 105ns + 12*UI */ 774 val = tc358768_ns_to_cnt(60 + tc358768_to_ns(15 * ui_nsk), 775 dsibclk_nsk) - 5; 776 dev_dbg(priv->dev, "THS_TRAILCNT: 0x%x\n", val); 777 tc358768_write(priv, TC358768_THS_TRAILCNT, val); 778 779 val = BIT(0); 780 for (i = 0; i < dsi_dev->lanes; i++) 781 val |= BIT(i + 1); 782 tc358768_write(priv, TC358768_HSTXVREGEN, val); 783 784 if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 785 tc358768_write(priv, TC358768_TXOPTIONCNTRL, 0x1); 786 787 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ 788 val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4); 789 val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1; 790 val2 = tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk), 791 dsibclk_nsk) - 2; 792 val = val << 16 | val2; 793 dev_dbg(priv->dev, "BTACNTRL1: 0x%x\n", val); 794 tc358768_write(priv, TC358768_BTACNTRL1, val); 795 796 /* START[0] */ 797 tc358768_write(priv, TC358768_STARTCNTRL, 1); 798 799 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 800 /* Set pulse mode */ 801 tc358768_write(priv, TC358768_DSI_EVENT, 0); 802 803 /* vact */ 804 tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay); 805 806 /* vsw */ 807 tc358768_write(priv, TC358768_DSI_VSW, 808 mode->vsync_end - mode->vsync_start); 809 /* vbp */ 810 tc358768_write(priv, TC358768_DSI_VBPR, 811 mode->vtotal - mode->vsync_end); 812 813 /* hsw * byteclk * ndl / pclk */ 814 val = (u32)div_u64((mode->hsync_end - mode->hsync_start) * 815 ((u64)priv->dsiclk / 4) * priv->dsi_lanes, 816 mode->clock * 1000); 817 tc358768_write(priv, TC358768_DSI_HSW, val); 818 819 /* hbp * byteclk * ndl / pclk */ 820 val = (u32)div_u64((mode->htotal - mode->hsync_end) * 821 ((u64)priv->dsiclk / 4) * priv->dsi_lanes, 822 mode->clock * 1000); 823 tc358768_write(priv, TC358768_DSI_HBPR, val); 824 } else { 825 /* Set event mode */ 826 tc358768_write(priv, TC358768_DSI_EVENT, 1); 827 828 /* vact */ 829 tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay); 830 831 /* vsw (+ vbp) */ 832 tc358768_write(priv, TC358768_DSI_VSW, 833 mode->vtotal - mode->vsync_start); 834 /* vbp (not used in event mode) */ 835 tc358768_write(priv, TC358768_DSI_VBPR, 0); 836 837 /* (hsw + hbp) * byteclk * ndl / pclk */ 838 val = (u32)div_u64((mode->htotal - mode->hsync_start) * 839 ((u64)priv->dsiclk / 4) * priv->dsi_lanes, 840 mode->clock * 1000); 841 tc358768_write(priv, TC358768_DSI_HSW, val); 842 843 /* hbp (not used in event mode) */ 844 tc358768_write(priv, TC358768_DSI_HBPR, 0); 845 } 846 847 /* hact (bytes) */ 848 tc358768_write(priv, TC358768_DSI_HACT, hact); 849 850 /* VSYNC polarity */ 851 if (!(mode->flags & DRM_MODE_FLAG_NVSYNC)) 852 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), BIT(5)); 853 /* HSYNC polarity */ 854 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 855 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), BIT(0)); 856 857 /* Start DSI Tx */ 858 tc358768_write(priv, TC358768_DSI_START, 0x1); 859 860 /* Configure DSI_Control register */ 861 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; 862 val |= TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD | 863 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS; 864 tc358768_write(priv, TC358768_DSI_CONFW, val); 865 866 val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; 867 val |= (dsi_dev->lanes - 1) << 1; 868 869 if (!(dsi_dev->mode_flags & MIPI_DSI_MODE_LPM)) 870 val |= TC358768_DSI_CONTROL_TXMD; 871 872 if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 873 val |= TC358768_DSI_CONTROL_HSCKMD; 874 875 if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 876 val |= TC358768_DSI_CONTROL_EOTDIS; 877 878 tc358768_write(priv, TC358768_DSI_CONFW, val); 879 880 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; 881 val |= TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */ 882 tc358768_write(priv, TC358768_DSI_CONFW, val); 883 884 ret = tc358768_clear_error(priv); 885 if (ret) { 886 dev_err(priv->dev, "Bridge pre_enable failed: %d\n", ret); 887 tc358768_bridge_disable(bridge); 888 tc358768_bridge_post_disable(bridge); 889 } 890 } 891 892 static void tc358768_bridge_enable(struct drm_bridge *bridge) 893 { 894 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 895 int ret; 896 897 if (!priv->enabled) { 898 dev_err(priv->dev, "Bridge is not enabled\n"); 899 return; 900 } 901 902 /* clear FrmStop and RstPtr */ 903 tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0); 904 905 /* set PP_en */ 906 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), BIT(6)); 907 908 ret = tc358768_clear_error(priv); 909 if (ret) { 910 dev_err(priv->dev, "Bridge enable failed: %d\n", ret); 911 tc358768_bridge_disable(bridge); 912 tc358768_bridge_post_disable(bridge); 913 } 914 } 915 916 static const struct drm_bridge_funcs tc358768_bridge_funcs = { 917 .attach = tc358768_bridge_attach, 918 .mode_valid = tc358768_bridge_mode_valid, 919 .pre_enable = tc358768_bridge_pre_enable, 920 .enable = tc358768_bridge_enable, 921 .disable = tc358768_bridge_disable, 922 .post_disable = tc358768_bridge_post_disable, 923 }; 924 925 static const struct drm_bridge_timings default_tc358768_timings = { 926 .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 927 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE 928 | DRM_BUS_FLAG_DE_HIGH, 929 }; 930 931 static bool tc358768_is_reserved_reg(unsigned int reg) 932 { 933 switch (reg) { 934 case 0x114 ... 0x13f: 935 case 0x200: 936 case 0x20c: 937 case 0x400 ... 0x408: 938 case 0x41c ... 0x42f: 939 return true; 940 default: 941 return false; 942 } 943 } 944 945 static bool tc358768_writeable_reg(struct device *dev, unsigned int reg) 946 { 947 if (tc358768_is_reserved_reg(reg)) 948 return false; 949 950 switch (reg) { 951 case TC358768_CHIPID: 952 case TC358768_FIFOSTATUS: 953 case TC358768_DSITXSTATUS ... (TC358768_DSITXSTATUS + 2): 954 case TC358768_DSI_CONTROL ... (TC358768_DSI_INT_ENA + 2): 955 case TC358768_DSICMD_RDFIFO ... (TC358768_DSI_ERR_HALT + 2): 956 return false; 957 default: 958 return true; 959 } 960 } 961 962 static bool tc358768_readable_reg(struct device *dev, unsigned int reg) 963 { 964 if (tc358768_is_reserved_reg(reg)) 965 return false; 966 967 switch (reg) { 968 case TC358768_STARTCNTRL: 969 case TC358768_DSI_CONFW ... (TC358768_DSI_CONFW + 2): 970 case TC358768_DSI_INT_CLR ... (TC358768_DSI_INT_CLR + 2): 971 case TC358768_DSI_START ... (TC358768_DSI_START + 2): 972 case TC358768_DBG_DATA: 973 return false; 974 default: 975 return true; 976 } 977 } 978 979 static const struct regmap_config tc358768_regmap_config = { 980 .name = "tc358768", 981 .reg_bits = 16, 982 .val_bits = 16, 983 .max_register = TC358768_DSI_HACT, 984 .cache_type = REGCACHE_NONE, 985 .writeable_reg = tc358768_writeable_reg, 986 .readable_reg = tc358768_readable_reg, 987 .reg_format_endian = REGMAP_ENDIAN_BIG, 988 .val_format_endian = REGMAP_ENDIAN_BIG, 989 }; 990 991 static const struct i2c_device_id tc358768_i2c_ids[] = { 992 { "tc358768", 0 }, 993 { "tc358778", 0 }, 994 { } 995 }; 996 MODULE_DEVICE_TABLE(i2c, tc358768_i2c_ids); 997 998 static const struct of_device_id tc358768_of_ids[] = { 999 { .compatible = "toshiba,tc358768", }, 1000 { .compatible = "toshiba,tc358778", }, 1001 { } 1002 }; 1003 MODULE_DEVICE_TABLE(of, tc358768_of_ids); 1004 1005 static int tc358768_get_regulators(struct tc358768_priv *priv) 1006 { 1007 int i, ret; 1008 1009 for (i = 0; i < ARRAY_SIZE(priv->supplies); ++i) 1010 priv->supplies[i].supply = tc358768_supplies[i]; 1011 1012 ret = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(priv->supplies), 1013 priv->supplies); 1014 if (ret < 0) 1015 dev_err(priv->dev, "failed to get regulators: %d\n", ret); 1016 1017 return ret; 1018 } 1019 1020 static int tc358768_i2c_probe(struct i2c_client *client) 1021 { 1022 struct tc358768_priv *priv; 1023 struct device *dev = &client->dev; 1024 struct device_node *np = dev->of_node; 1025 int ret; 1026 1027 if (!np) 1028 return -ENODEV; 1029 1030 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1031 if (!priv) 1032 return -ENOMEM; 1033 1034 dev_set_drvdata(dev, priv); 1035 priv->dev = dev; 1036 1037 ret = tc358768_get_regulators(priv); 1038 if (ret) 1039 return ret; 1040 1041 priv->refclk = devm_clk_get(dev, "refclk"); 1042 if (IS_ERR(priv->refclk)) 1043 return PTR_ERR(priv->refclk); 1044 1045 /* 1046 * RESX is low active, to disable tc358768 initially (keep in reset) 1047 * the gpio line must be LOW. This is the ASSERTED state of 1048 * GPIO_ACTIVE_LOW (GPIOD_OUT_HIGH == ASSERTED). 1049 */ 1050 priv->reset_gpio = devm_gpiod_get_optional(dev, "reset", 1051 GPIOD_OUT_HIGH); 1052 if (IS_ERR(priv->reset_gpio)) 1053 return PTR_ERR(priv->reset_gpio); 1054 1055 priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config); 1056 if (IS_ERR(priv->regmap)) { 1057 dev_err(dev, "Failed to init regmap\n"); 1058 return PTR_ERR(priv->regmap); 1059 } 1060 1061 priv->dsi_host.dev = dev; 1062 priv->dsi_host.ops = &tc358768_dsi_host_ops; 1063 1064 priv->bridge.funcs = &tc358768_bridge_funcs; 1065 priv->bridge.timings = &default_tc358768_timings; 1066 priv->bridge.of_node = np; 1067 1068 i2c_set_clientdata(client, priv); 1069 1070 return mipi_dsi_host_register(&priv->dsi_host); 1071 } 1072 1073 static void tc358768_i2c_remove(struct i2c_client *client) 1074 { 1075 struct tc358768_priv *priv = i2c_get_clientdata(client); 1076 1077 mipi_dsi_host_unregister(&priv->dsi_host); 1078 } 1079 1080 static struct i2c_driver tc358768_driver = { 1081 .driver = { 1082 .name = "tc358768", 1083 .of_match_table = tc358768_of_ids, 1084 }, 1085 .id_table = tc358768_i2c_ids, 1086 .probe_new = tc358768_i2c_probe, 1087 .remove = tc358768_i2c_remove, 1088 }; 1089 module_i2c_driver(tc358768_driver); 1090 1091 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>"); 1092 MODULE_DESCRIPTION("TC358768AXBG/TC358778XBG DSI bridge"); 1093 MODULE_LICENSE("GPL v2"); 1094