xref: /openbmc/linux/drivers/gpu/drm/bridge/tc358768.c (revision f0168042)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  *  Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
4  *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
5  */
6 
7 #include <linux/clk.h>
8 #include <linux/device.h>
9 #include <linux/gpio/consumer.h>
10 #include <linux/i2c.h>
11 #include <linux/kernel.h>
12 #include <linux/media-bus-format.h>
13 #include <linux/minmax.h>
14 #include <linux/module.h>
15 #include <linux/regmap.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/slab.h>
18 
19 #include <drm/drm_atomic_helper.h>
20 #include <drm/drm_drv.h>
21 #include <drm/drm_mipi_dsi.h>
22 #include <drm/drm_of.h>
23 #include <drm/drm_panel.h>
24 #include <video/mipi_display.h>
25 #include <video/videomode.h>
26 
27 /* Global (16-bit addressable) */
28 #define TC358768_CHIPID			0x0000
29 #define TC358768_SYSCTL			0x0002
30 #define TC358768_CONFCTL		0x0004
31 #define TC358768_VSDLY			0x0006
32 #define TC358768_DATAFMT		0x0008
33 #define TC358768_GPIOEN			0x000E
34 #define TC358768_GPIODIR		0x0010
35 #define TC358768_GPIOIN			0x0012
36 #define TC358768_GPIOOUT		0x0014
37 #define TC358768_PLLCTL0		0x0016
38 #define TC358768_PLLCTL1		0x0018
39 #define TC358768_CMDBYTE		0x0022
40 #define TC358768_PP_MISC		0x0032
41 #define TC358768_DSITX_DT		0x0050
42 #define TC358768_FIFOSTATUS		0x00F8
43 
44 /* Debug (16-bit addressable) */
45 #define TC358768_VBUFCTRL		0x00E0
46 #define TC358768_DBG_WIDTH		0x00E2
47 #define TC358768_DBG_VBLANK		0x00E4
48 #define TC358768_DBG_DATA		0x00E8
49 
50 /* TX PHY (32-bit addressable) */
51 #define TC358768_CLW_DPHYCONTTX		0x0100
52 #define TC358768_D0W_DPHYCONTTX		0x0104
53 #define TC358768_D1W_DPHYCONTTX		0x0108
54 #define TC358768_D2W_DPHYCONTTX		0x010C
55 #define TC358768_D3W_DPHYCONTTX		0x0110
56 #define TC358768_CLW_CNTRL		0x0140
57 #define TC358768_D0W_CNTRL		0x0144
58 #define TC358768_D1W_CNTRL		0x0148
59 #define TC358768_D2W_CNTRL		0x014C
60 #define TC358768_D3W_CNTRL		0x0150
61 
62 /* TX PPI (32-bit addressable) */
63 #define TC358768_STARTCNTRL		0x0204
64 #define TC358768_DSITXSTATUS		0x0208
65 #define TC358768_LINEINITCNT		0x0210
66 #define TC358768_LPTXTIMECNT		0x0214
67 #define TC358768_TCLK_HEADERCNT		0x0218
68 #define TC358768_TCLK_TRAILCNT		0x021C
69 #define TC358768_THS_HEADERCNT		0x0220
70 #define TC358768_TWAKEUP		0x0224
71 #define TC358768_TCLK_POSTCNT		0x0228
72 #define TC358768_THS_TRAILCNT		0x022C
73 #define TC358768_HSTXVREGCNT		0x0230
74 #define TC358768_HSTXVREGEN		0x0234
75 #define TC358768_TXOPTIONCNTRL		0x0238
76 #define TC358768_BTACNTRL1		0x023C
77 
78 /* TX CTRL (32-bit addressable) */
79 #define TC358768_DSI_CONTROL		0x040C
80 #define TC358768_DSI_STATUS		0x0410
81 #define TC358768_DSI_INT		0x0414
82 #define TC358768_DSI_INT_ENA		0x0418
83 #define TC358768_DSICMD_RDFIFO		0x0430
84 #define TC358768_DSI_ACKERR		0x0434
85 #define TC358768_DSI_ACKERR_INTENA	0x0438
86 #define TC358768_DSI_ACKERR_HALT	0x043c
87 #define TC358768_DSI_RXERR		0x0440
88 #define TC358768_DSI_RXERR_INTENA	0x0444
89 #define TC358768_DSI_RXERR_HALT		0x0448
90 #define TC358768_DSI_ERR		0x044C
91 #define TC358768_DSI_ERR_INTENA		0x0450
92 #define TC358768_DSI_ERR_HALT		0x0454
93 #define TC358768_DSI_CONFW		0x0500
94 #define TC358768_DSI_LPCMD		0x0500
95 #define TC358768_DSI_RESET		0x0504
96 #define TC358768_DSI_INT_CLR		0x050C
97 #define TC358768_DSI_START		0x0518
98 
99 /* DSITX CTRL (16-bit addressable) */
100 #define TC358768_DSICMD_TX		0x0600
101 #define TC358768_DSICMD_TYPE		0x0602
102 #define TC358768_DSICMD_WC		0x0604
103 #define TC358768_DSICMD_WD0		0x0610
104 #define TC358768_DSICMD_WD1		0x0612
105 #define TC358768_DSICMD_WD2		0x0614
106 #define TC358768_DSICMD_WD3		0x0616
107 #define TC358768_DSI_EVENT		0x0620
108 #define TC358768_DSI_VSW		0x0622
109 #define TC358768_DSI_VBPR		0x0624
110 #define TC358768_DSI_VACT		0x0626
111 #define TC358768_DSI_HSW		0x0628
112 #define TC358768_DSI_HBPR		0x062A
113 #define TC358768_DSI_HACT		0x062C
114 
115 /* TC358768_DSI_CONTROL (0x040C) register */
116 #define TC358768_DSI_CONTROL_DIS_MODE	BIT(15)
117 #define TC358768_DSI_CONTROL_TXMD	BIT(7)
118 #define TC358768_DSI_CONTROL_HSCKMD	BIT(5)
119 #define TC358768_DSI_CONTROL_EOTDIS	BIT(0)
120 
121 /* TC358768_DSI_CONFW (0x0500) register */
122 #define TC358768_DSI_CONFW_MODE_SET	(5 << 29)
123 #define TC358768_DSI_CONFW_MODE_CLR	(6 << 29)
124 #define TC358768_DSI_CONFW_ADDR_DSI_CONTROL	(0x3 << 24)
125 
126 static const char * const tc358768_supplies[] = {
127 	"vddc", "vddmipi", "vddio"
128 };
129 
130 struct tc358768_dsi_output {
131 	struct mipi_dsi_device *dev;
132 	struct drm_panel *panel;
133 	struct drm_bridge *bridge;
134 };
135 
136 struct tc358768_priv {
137 	struct device *dev;
138 	struct regmap *regmap;
139 	struct gpio_desc *reset_gpio;
140 	struct regulator_bulk_data supplies[ARRAY_SIZE(tc358768_supplies)];
141 	struct clk *refclk;
142 	int enabled;
143 	int error;
144 
145 	struct mipi_dsi_host dsi_host;
146 	struct drm_bridge bridge;
147 	struct tc358768_dsi_output output;
148 
149 	u32 pd_lines; /* number of Parallel Port Input Data Lines */
150 	u32 dsi_lanes; /* number of DSI Lanes */
151 	u32 dsi_bpp; /* number of Bits Per Pixel over DSI */
152 
153 	/* Parameters for PLL programming */
154 	u32 fbd;	/* PLL feedback divider */
155 	u32 prd;	/* PLL input divider */
156 	u32 frs;	/* PLL Freqency range for HSCK (post divider) */
157 
158 	u32 dsiclk;	/* pll_clk / 2 */
159 };
160 
161 static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_host
162 							 *host)
163 {
164 	return container_of(host, struct tc358768_priv, dsi_host);
165 }
166 
167 static inline struct tc358768_priv *bridge_to_tc358768(struct drm_bridge
168 						       *bridge)
169 {
170 	return container_of(bridge, struct tc358768_priv, bridge);
171 }
172 
173 static int tc358768_clear_error(struct tc358768_priv *priv)
174 {
175 	int ret = priv->error;
176 
177 	priv->error = 0;
178 	return ret;
179 }
180 
181 static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val)
182 {
183 	/* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
184 	int tmpval = val;
185 	size_t count = 2;
186 
187 	if (priv->error)
188 		return;
189 
190 	/* 16-bit register? */
191 	if (reg < 0x100 || reg >= 0x600)
192 		count = 1;
193 
194 	priv->error = regmap_bulk_write(priv->regmap, reg, &tmpval, count);
195 }
196 
197 static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val)
198 {
199 	size_t count = 2;
200 
201 	if (priv->error)
202 		return;
203 
204 	/* 16-bit register? */
205 	if (reg < 0x100 || reg >= 0x600) {
206 		*val = 0;
207 		count = 1;
208 	}
209 
210 	priv->error = regmap_bulk_read(priv->regmap, reg, val, count);
211 }
212 
213 static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask,
214 				 u32 val)
215 {
216 	u32 tmp, orig;
217 
218 	tc358768_read(priv, reg, &orig);
219 	tmp = orig & ~mask;
220 	tmp |= val & mask;
221 	if (tmp != orig)
222 		tc358768_write(priv, reg, tmp);
223 }
224 
225 static int tc358768_sw_reset(struct tc358768_priv *priv)
226 {
227 	/* Assert Reset */
228 	tc358768_write(priv, TC358768_SYSCTL, 1);
229 	/* Release Reset, Exit Sleep */
230 	tc358768_write(priv, TC358768_SYSCTL, 0);
231 
232 	return tc358768_clear_error(priv);
233 }
234 
235 static void tc358768_hw_enable(struct tc358768_priv *priv)
236 {
237 	int ret;
238 
239 	if (priv->enabled)
240 		return;
241 
242 	ret = clk_prepare_enable(priv->refclk);
243 	if (ret < 0)
244 		dev_err(priv->dev, "error enabling refclk (%d)\n", ret);
245 
246 	ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
247 	if (ret < 0)
248 		dev_err(priv->dev, "error enabling regulators (%d)\n", ret);
249 
250 	if (priv->reset_gpio)
251 		usleep_range(200, 300);
252 
253 	/*
254 	 * The RESX is active low (GPIO_ACTIVE_LOW).
255 	 * DEASSERT (value = 0) the reset_gpio to enable the chip
256 	 */
257 	gpiod_set_value_cansleep(priv->reset_gpio, 0);
258 
259 	/* wait for encoder clocks to stabilize */
260 	usleep_range(1000, 2000);
261 
262 	priv->enabled = true;
263 }
264 
265 static void tc358768_hw_disable(struct tc358768_priv *priv)
266 {
267 	int ret;
268 
269 	if (!priv->enabled)
270 		return;
271 
272 	/*
273 	 * The RESX is active low (GPIO_ACTIVE_LOW).
274 	 * ASSERT (value = 1) the reset_gpio to disable the chip
275 	 */
276 	gpiod_set_value_cansleep(priv->reset_gpio, 1);
277 
278 	ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
279 				     priv->supplies);
280 	if (ret < 0)
281 		dev_err(priv->dev, "error disabling regulators (%d)\n", ret);
282 
283 	clk_disable_unprepare(priv->refclk);
284 
285 	priv->enabled = false;
286 }
287 
288 static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk)
289 {
290 	return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->dsi_bpp);
291 }
292 
293 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk)
294 {
295 	return (u32)div_u64((u64)pclk * priv->dsi_bpp, priv->dsi_lanes);
296 }
297 
298 static int tc358768_calc_pll(struct tc358768_priv *priv,
299 			     const struct drm_display_mode *mode,
300 			     bool verify_only)
301 {
302 	static const u32 frs_limits[] = {
303 		1000000000,
304 		500000000,
305 		250000000,
306 		125000000,
307 		62500000
308 	};
309 	unsigned long refclk;
310 	u32 prd, target_pll, i, max_pll, min_pll;
311 	u32 frs, best_diff, best_pll, best_prd, best_fbd;
312 
313 	target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000);
314 
315 	/* pll_clk = RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] */
316 
317 	for (i = 0; i < ARRAY_SIZE(frs_limits); i++)
318 		if (target_pll >= frs_limits[i])
319 			break;
320 
321 	if (i == ARRAY_SIZE(frs_limits) || i == 0)
322 		return -EINVAL;
323 
324 	frs = i - 1;
325 	max_pll = frs_limits[i - 1];
326 	min_pll = frs_limits[i];
327 
328 	refclk = clk_get_rate(priv->refclk);
329 
330 	best_diff = UINT_MAX;
331 	best_pll = 0;
332 	best_prd = 0;
333 	best_fbd = 0;
334 
335 	for (prd = 0; prd < 16; ++prd) {
336 		u32 divisor = (prd + 1) * (1 << frs);
337 		u32 fbd;
338 
339 		for (fbd = 0; fbd < 512; ++fbd) {
340 			u32 pll, diff, pll_in;
341 
342 			pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor);
343 
344 			if (pll >= max_pll || pll < min_pll)
345 				continue;
346 
347 			pll_in = (u32)div_u64((u64)refclk, prd + 1);
348 			if (pll_in < 4000000)
349 				continue;
350 
351 			diff = max(pll, target_pll) - min(pll, target_pll);
352 
353 			if (diff < best_diff) {
354 				best_diff = diff;
355 				best_pll = pll;
356 				best_prd = prd;
357 				best_fbd = fbd;
358 
359 				if (best_diff == 0)
360 					goto found;
361 			}
362 		}
363 	}
364 
365 	if (best_diff == UINT_MAX) {
366 		dev_err(priv->dev, "could not find suitable PLL setup\n");
367 		return -EINVAL;
368 	}
369 
370 found:
371 	if (verify_only)
372 		return 0;
373 
374 	priv->fbd = best_fbd;
375 	priv->prd = best_prd;
376 	priv->frs = frs;
377 	priv->dsiclk = best_pll / 2;
378 
379 	return 0;
380 }
381 
382 static int tc358768_dsi_host_attach(struct mipi_dsi_host *host,
383 				    struct mipi_dsi_device *dev)
384 {
385 	struct tc358768_priv *priv = dsi_host_to_tc358768(host);
386 	struct drm_bridge *bridge;
387 	struct drm_panel *panel;
388 	struct device_node *ep;
389 	int ret;
390 
391 	if (dev->lanes > 4) {
392 		dev_err(priv->dev, "unsupported number of data lanes(%u)\n",
393 			dev->lanes);
394 		return -EINVAL;
395 	}
396 
397 	/*
398 	 * tc358768 supports both Video and Pulse mode, but the driver only
399 	 * implements Video (event) mode currently
400 	 */
401 	if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) {
402 		dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n");
403 		return -ENOTSUPP;
404 	}
405 
406 	/*
407 	 * tc358768 supports RGB888, RGB666, RGB666_PACKED and RGB565, but only
408 	 * RGB888 is verified.
409 	 */
410 	if (dev->format != MIPI_DSI_FMT_RGB888) {
411 		dev_warn(priv->dev, "Only MIPI_DSI_FMT_RGB888 tested!\n");
412 		return -ENOTSUPP;
413 	}
414 
415 	ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel,
416 					  &bridge);
417 	if (ret)
418 		return ret;
419 
420 	if (panel) {
421 		bridge = drm_panel_bridge_add_typed(panel,
422 						    DRM_MODE_CONNECTOR_DSI);
423 		if (IS_ERR(bridge))
424 			return PTR_ERR(bridge);
425 	}
426 
427 	priv->output.dev = dev;
428 	priv->output.bridge = bridge;
429 	priv->output.panel = panel;
430 
431 	priv->dsi_lanes = dev->lanes;
432 	priv->dsi_bpp = mipi_dsi_pixel_format_to_bpp(dev->format);
433 
434 	/* get input ep (port0/endpoint0) */
435 	ret = -EINVAL;
436 	ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0);
437 	if (ep) {
438 		ret = of_property_read_u32(ep, "data-lines", &priv->pd_lines);
439 
440 		of_node_put(ep);
441 	}
442 
443 	if (ret)
444 		priv->pd_lines = priv->dsi_bpp;
445 
446 	drm_bridge_add(&priv->bridge);
447 
448 	return 0;
449 }
450 
451 static int tc358768_dsi_host_detach(struct mipi_dsi_host *host,
452 				    struct mipi_dsi_device *dev)
453 {
454 	struct tc358768_priv *priv = dsi_host_to_tc358768(host);
455 
456 	drm_bridge_remove(&priv->bridge);
457 	if (priv->output.panel)
458 		drm_panel_bridge_remove(priv->output.bridge);
459 
460 	return 0;
461 }
462 
463 static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host,
464 					  const struct mipi_dsi_msg *msg)
465 {
466 	struct tc358768_priv *priv = dsi_host_to_tc358768(host);
467 	struct mipi_dsi_packet packet;
468 	int ret;
469 
470 	if (!priv->enabled) {
471 		dev_err(priv->dev, "Bridge is not enabled\n");
472 		return -ENODEV;
473 	}
474 
475 	if (msg->rx_len) {
476 		dev_warn(priv->dev, "MIPI rx is not supported\n");
477 		return -ENOTSUPP;
478 	}
479 
480 	if (msg->tx_len > 8) {
481 		dev_warn(priv->dev, "Maximum 8 byte MIPI tx is supported\n");
482 		return -ENOTSUPP;
483 	}
484 
485 	ret = mipi_dsi_create_packet(&packet, msg);
486 	if (ret)
487 		return ret;
488 
489 	if (mipi_dsi_packet_format_is_short(msg->type)) {
490 		tc358768_write(priv, TC358768_DSICMD_TYPE,
491 			       (0x10 << 8) | (packet.header[0] & 0x3f));
492 		tc358768_write(priv, TC358768_DSICMD_WC, 0);
493 		tc358768_write(priv, TC358768_DSICMD_WD0,
494 			       (packet.header[2] << 8) | packet.header[1]);
495 	} else {
496 		int i;
497 
498 		tc358768_write(priv, TC358768_DSICMD_TYPE,
499 			       (0x40 << 8) | (packet.header[0] & 0x3f));
500 		tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length);
501 		for (i = 0; i < packet.payload_length; i += 2) {
502 			u16 val = packet.payload[i];
503 
504 			if (i + 1 < packet.payload_length)
505 				val |= packet.payload[i + 1] << 8;
506 
507 			tc358768_write(priv, TC358768_DSICMD_WD0 + i, val);
508 		}
509 	}
510 
511 	/* start transfer */
512 	tc358768_write(priv, TC358768_DSICMD_TX, 1);
513 
514 	ret = tc358768_clear_error(priv);
515 	if (ret)
516 		dev_warn(priv->dev, "Software disable failed: %d\n", ret);
517 	else
518 		ret = packet.size;
519 
520 	return ret;
521 }
522 
523 static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = {
524 	.attach = tc358768_dsi_host_attach,
525 	.detach = tc358768_dsi_host_detach,
526 	.transfer = tc358768_dsi_host_transfer,
527 };
528 
529 static int tc358768_bridge_attach(struct drm_bridge *bridge,
530 				  enum drm_bridge_attach_flags flags)
531 {
532 	struct tc358768_priv *priv = bridge_to_tc358768(bridge);
533 
534 	if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) {
535 		dev_err(priv->dev, "needs atomic updates support\n");
536 		return -ENOTSUPP;
537 	}
538 
539 	return drm_bridge_attach(bridge->encoder, priv->output.bridge, bridge,
540 				 flags);
541 }
542 
543 static enum drm_mode_status
544 tc358768_bridge_mode_valid(struct drm_bridge *bridge,
545 			   const struct drm_display_info *info,
546 			   const struct drm_display_mode *mode)
547 {
548 	struct tc358768_priv *priv = bridge_to_tc358768(bridge);
549 
550 	if (tc358768_calc_pll(priv, mode, true))
551 		return MODE_CLOCK_RANGE;
552 
553 	return MODE_OK;
554 }
555 
556 static void tc358768_bridge_disable(struct drm_bridge *bridge)
557 {
558 	struct tc358768_priv *priv = bridge_to_tc358768(bridge);
559 	int ret;
560 
561 	/* set FrmStop */
562 	tc358768_update_bits(priv, TC358768_PP_MISC, BIT(15), BIT(15));
563 
564 	/* wait at least for one frame */
565 	msleep(50);
566 
567 	/* clear PP_en */
568 	tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), 0);
569 
570 	/* set RstPtr */
571 	tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), BIT(14));
572 
573 	ret = tc358768_clear_error(priv);
574 	if (ret)
575 		dev_warn(priv->dev, "Software disable failed: %d\n", ret);
576 }
577 
578 static void tc358768_bridge_post_disable(struct drm_bridge *bridge)
579 {
580 	struct tc358768_priv *priv = bridge_to_tc358768(bridge);
581 
582 	tc358768_hw_disable(priv);
583 }
584 
585 static int tc358768_setup_pll(struct tc358768_priv *priv,
586 			      const struct drm_display_mode *mode)
587 {
588 	u32 fbd, prd, frs;
589 	int ret;
590 
591 	ret = tc358768_calc_pll(priv, mode, false);
592 	if (ret) {
593 		dev_err(priv->dev, "PLL calculation failed: %d\n", ret);
594 		return ret;
595 	}
596 
597 	fbd = priv->fbd;
598 	prd = priv->prd;
599 	frs = priv->frs;
600 
601 	dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n",
602 		clk_get_rate(priv->refclk), fbd, prd, frs);
603 	dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, DSIByteClk %u\n",
604 		priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4);
605 	dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n",
606 		tc358768_pll_to_pclk(priv, priv->dsiclk * 2),
607 		mode->clock * 1000);
608 
609 	/* PRD[15:12] FBD[8:0] */
610 	tc358768_write(priv, TC358768_PLLCTL0, (prd << 12) | fbd);
611 
612 	/* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */
613 	tc358768_write(priv, TC358768_PLLCTL1,
614 		       (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0));
615 
616 	/* wait for lock */
617 	usleep_range(1000, 2000);
618 
619 	/* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */
620 	tc358768_write(priv, TC358768_PLLCTL1,
621 		       (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0));
622 
623 	return tc358768_clear_error(priv);
624 }
625 
626 #define TC358768_PRECISION	1000
627 static u32 tc358768_ns_to_cnt(u32 ns, u32 period_nsk)
628 {
629 	return (ns * TC358768_PRECISION + period_nsk) / period_nsk;
630 }
631 
632 static u32 tc358768_to_ns(u32 nsk)
633 {
634 	return (nsk / TC358768_PRECISION);
635 }
636 
637 static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
638 {
639 	struct tc358768_priv *priv = bridge_to_tc358768(bridge);
640 	struct mipi_dsi_device *dsi_dev = priv->output.dev;
641 	unsigned long mode_flags = dsi_dev->mode_flags;
642 	u32 val, val2, lptxcnt, hact, data_type;
643 	s32 raw_val;
644 	const struct drm_display_mode *mode;
645 	u32 dsibclk_nsk, dsiclk_nsk, ui_nsk;
646 	u32 dsiclk, dsibclk, video_start;
647 	const u32 internal_delay = 40;
648 	int ret, i;
649 
650 	if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
651 		dev_warn_once(priv->dev, "Non-continuous mode unimplemented, falling back to continuous\n");
652 		mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS;
653 	}
654 
655 	tc358768_hw_enable(priv);
656 
657 	ret = tc358768_sw_reset(priv);
658 	if (ret) {
659 		dev_err(priv->dev, "Software reset failed: %d\n", ret);
660 		tc358768_hw_disable(priv);
661 		return;
662 	}
663 
664 	mode = &bridge->encoder->crtc->state->adjusted_mode;
665 	ret = tc358768_setup_pll(priv, mode);
666 	if (ret) {
667 		dev_err(priv->dev, "PLL setup failed: %d\n", ret);
668 		tc358768_hw_disable(priv);
669 		return;
670 	}
671 
672 	dsiclk = priv->dsiclk;
673 	dsibclk = dsiclk / 4;
674 
675 	/* Data Format Control Register */
676 	val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */
677 	switch (dsi_dev->format) {
678 	case MIPI_DSI_FMT_RGB888:
679 		val |= (0x3 << 4);
680 		hact = mode->hdisplay * 3;
681 		video_start = (mode->htotal - mode->hsync_start) * 3;
682 		data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
683 		break;
684 	case MIPI_DSI_FMT_RGB666:
685 		val |= (0x4 << 4);
686 		hact = mode->hdisplay * 3;
687 		video_start = (mode->htotal - mode->hsync_start) * 3;
688 		data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
689 		break;
690 
691 	case MIPI_DSI_FMT_RGB666_PACKED:
692 		val |= (0x4 << 4) | BIT(3);
693 		hact = mode->hdisplay * 18 / 8;
694 		video_start = (mode->htotal - mode->hsync_start) * 18 / 8;
695 		data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
696 		break;
697 
698 	case MIPI_DSI_FMT_RGB565:
699 		val |= (0x5 << 4);
700 		hact = mode->hdisplay * 2;
701 		video_start = (mode->htotal - mode->hsync_start) * 2;
702 		data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
703 		break;
704 	default:
705 		dev_err(priv->dev, "Invalid data format (%u)\n",
706 			dsi_dev->format);
707 		tc358768_hw_disable(priv);
708 		return;
709 	}
710 
711 	/* VSDly[9:0] */
712 	video_start = max(video_start, internal_delay + 1) - internal_delay;
713 	tc358768_write(priv, TC358768_VSDLY, video_start);
714 
715 	tc358768_write(priv, TC358768_DATAFMT, val);
716 	tc358768_write(priv, TC358768_DSITX_DT, data_type);
717 
718 	/* Enable D-PHY (HiZ->LP11) */
719 	tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000);
720 	/* Enable lanes */
721 	for (i = 0; i < dsi_dev->lanes; i++)
722 		tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000);
723 
724 	/* DSI Timings */
725 	dsibclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION,
726 				  dsibclk);
727 	dsiclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk);
728 	ui_nsk = dsiclk_nsk / 2;
729 	dev_dbg(priv->dev, "dsiclk_nsk: %u\n", dsiclk_nsk);
730 	dev_dbg(priv->dev, "ui_nsk: %u\n", ui_nsk);
731 	dev_dbg(priv->dev, "dsibclk_nsk: %u\n", dsibclk_nsk);
732 
733 	/* LP11 > 100us for D-PHY Rx Init */
734 	val = tc358768_ns_to_cnt(100 * 1000, dsibclk_nsk) - 1;
735 	dev_dbg(priv->dev, "LINEINITCNT: 0x%x\n", val);
736 	tc358768_write(priv, TC358768_LINEINITCNT, val);
737 
738 	/* LPTimeCnt > 50ns */
739 	val = tc358768_ns_to_cnt(50, dsibclk_nsk) - 1;
740 	lptxcnt = val;
741 	dev_dbg(priv->dev, "LPTXTIMECNT: 0x%x\n", val);
742 	tc358768_write(priv, TC358768_LPTXTIMECNT, val);
743 
744 	/* 38ns < TCLK_PREPARE < 95ns */
745 	val = tc358768_ns_to_cnt(65, dsibclk_nsk) - 1;
746 	/* TCLK_PREPARE + TCLK_ZERO > 300ns */
747 	val2 = tc358768_ns_to_cnt(300 - tc358768_to_ns(2 * ui_nsk),
748 				  dsibclk_nsk) - 2;
749 	val |= val2 << 8;
750 	dev_dbg(priv->dev, "TCLK_HEADERCNT: 0x%x\n", val);
751 	tc358768_write(priv, TC358768_TCLK_HEADERCNT, val);
752 
753 	/* TCLK_TRAIL > 60ns AND TEOT <= 105 ns + 12*UI */
754 	raw_val = tc358768_ns_to_cnt(60 + tc358768_to_ns(2 * ui_nsk), dsibclk_nsk) - 5;
755 	val = clamp(raw_val, 0, 127);
756 	dev_dbg(priv->dev, "TCLK_TRAILCNT: 0x%x\n", val);
757 	tc358768_write(priv, TC358768_TCLK_TRAILCNT, val);
758 
759 	/* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */
760 	val = 50 + tc358768_to_ns(4 * ui_nsk);
761 	val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1;
762 	/* THS_PREPARE + THS_ZERO > 145ns + 10*UI */
763 	raw_val = tc358768_ns_to_cnt(145 - tc358768_to_ns(3 * ui_nsk), dsibclk_nsk) - 10;
764 	val2 = clamp(raw_val, 0, 127);
765 	val |= val2 << 8;
766 	dev_dbg(priv->dev, "THS_HEADERCNT: 0x%x\n", val);
767 	tc358768_write(priv, TC358768_THS_HEADERCNT, val);
768 
769 	/* TWAKEUP > 1ms in lptxcnt steps */
770 	val = tc358768_ns_to_cnt(1020000, dsibclk_nsk);
771 	val = val / (lptxcnt + 1) - 1;
772 	dev_dbg(priv->dev, "TWAKEUP: 0x%x\n", val);
773 	tc358768_write(priv, TC358768_TWAKEUP, val);
774 
775 	/* TCLK_POSTCNT > 60ns + 52*UI */
776 	val = tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk),
777 				 dsibclk_nsk) - 3;
778 	dev_dbg(priv->dev, "TCLK_POSTCNT: 0x%x\n", val);
779 	tc358768_write(priv, TC358768_TCLK_POSTCNT, val);
780 
781 	/* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */
782 	raw_val = tc358768_ns_to_cnt(60 + tc358768_to_ns(18 * ui_nsk),
783 				     dsibclk_nsk) - 4;
784 	val = clamp(raw_val, 0, 15);
785 	dev_dbg(priv->dev, "THS_TRAILCNT: 0x%x\n", val);
786 	tc358768_write(priv, TC358768_THS_TRAILCNT, val);
787 
788 	val = BIT(0);
789 	for (i = 0; i < dsi_dev->lanes; i++)
790 		val |= BIT(i + 1);
791 	tc358768_write(priv, TC358768_HSTXVREGEN, val);
792 
793 	if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
794 		tc358768_write(priv, TC358768_TXOPTIONCNTRL, 0x1);
795 
796 	/* TXTAGOCNT[26:16] RXTASURECNT[10:0] */
797 	val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4);
798 	val = tc358768_ns_to_cnt(val, dsibclk_nsk) / 4 - 1;
799 	val2 = tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk),
800 				  dsibclk_nsk) - 2;
801 	val = val << 16 | val2;
802 	dev_dbg(priv->dev, "BTACNTRL1: 0x%x\n", val);
803 	tc358768_write(priv, TC358768_BTACNTRL1, val);
804 
805 	/* START[0] */
806 	tc358768_write(priv, TC358768_STARTCNTRL, 1);
807 
808 	if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
809 		/* Set pulse mode */
810 		tc358768_write(priv, TC358768_DSI_EVENT, 0);
811 
812 		/* vact */
813 		tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay);
814 
815 		/* vsw */
816 		tc358768_write(priv, TC358768_DSI_VSW,
817 			       mode->vsync_end - mode->vsync_start);
818 		/* vbp */
819 		tc358768_write(priv, TC358768_DSI_VBPR,
820 			       mode->vtotal - mode->vsync_end);
821 
822 		/* hsw * byteclk * ndl / pclk */
823 		val = (u32)div_u64((mode->hsync_end - mode->hsync_start) *
824 				   ((u64)priv->dsiclk / 4) * priv->dsi_lanes,
825 				   mode->clock * 1000);
826 		tc358768_write(priv, TC358768_DSI_HSW, val);
827 
828 		/* hbp * byteclk * ndl / pclk */
829 		val = (u32)div_u64((mode->htotal - mode->hsync_end) *
830 				   ((u64)priv->dsiclk / 4) * priv->dsi_lanes,
831 				   mode->clock * 1000);
832 		tc358768_write(priv, TC358768_DSI_HBPR, val);
833 	} else {
834 		/* Set event mode */
835 		tc358768_write(priv, TC358768_DSI_EVENT, 1);
836 
837 		/* vact */
838 		tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay);
839 
840 		/* vsw (+ vbp) */
841 		tc358768_write(priv, TC358768_DSI_VSW,
842 			       mode->vtotal - mode->vsync_start);
843 		/* vbp (not used in event mode) */
844 		tc358768_write(priv, TC358768_DSI_VBPR, 0);
845 
846 		/* (hsw + hbp) * byteclk * ndl / pclk */
847 		val = (u32)div_u64((mode->htotal - mode->hsync_start) *
848 				   ((u64)priv->dsiclk / 4) * priv->dsi_lanes,
849 				   mode->clock * 1000);
850 		tc358768_write(priv, TC358768_DSI_HSW, val);
851 
852 		/* hbp (not used in event mode) */
853 		tc358768_write(priv, TC358768_DSI_HBPR, 0);
854 	}
855 
856 	/* hact (bytes) */
857 	tc358768_write(priv, TC358768_DSI_HACT, hact);
858 
859 	/* VSYNC polarity */
860 	if (!(mode->flags & DRM_MODE_FLAG_NVSYNC))
861 		tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), BIT(5));
862 	/* HSYNC polarity */
863 	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
864 		tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), BIT(0));
865 
866 	/* Start DSI Tx */
867 	tc358768_write(priv, TC358768_DSI_START, 0x1);
868 
869 	/* Configure DSI_Control register */
870 	val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
871 	val |= TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD |
872 	       0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS;
873 	tc358768_write(priv, TC358768_DSI_CONFW, val);
874 
875 	val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
876 	val |= (dsi_dev->lanes - 1) << 1;
877 
878 	val |= TC358768_DSI_CONTROL_TXMD;
879 
880 	if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
881 		val |= TC358768_DSI_CONTROL_HSCKMD;
882 
883 	if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
884 		val |= TC358768_DSI_CONTROL_EOTDIS;
885 
886 	tc358768_write(priv, TC358768_DSI_CONFW, val);
887 
888 	val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
889 	val |= TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */
890 	tc358768_write(priv, TC358768_DSI_CONFW, val);
891 
892 	ret = tc358768_clear_error(priv);
893 	if (ret) {
894 		dev_err(priv->dev, "Bridge pre_enable failed: %d\n", ret);
895 		tc358768_bridge_disable(bridge);
896 		tc358768_bridge_post_disable(bridge);
897 	}
898 }
899 
900 static void tc358768_bridge_enable(struct drm_bridge *bridge)
901 {
902 	struct tc358768_priv *priv = bridge_to_tc358768(bridge);
903 	int ret;
904 
905 	if (!priv->enabled) {
906 		dev_err(priv->dev, "Bridge is not enabled\n");
907 		return;
908 	}
909 
910 	/* clear FrmStop and RstPtr */
911 	tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0);
912 
913 	/* set PP_en */
914 	tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), BIT(6));
915 
916 	ret = tc358768_clear_error(priv);
917 	if (ret) {
918 		dev_err(priv->dev, "Bridge enable failed: %d\n", ret);
919 		tc358768_bridge_disable(bridge);
920 		tc358768_bridge_post_disable(bridge);
921 	}
922 }
923 
924 #define MAX_INPUT_SEL_FORMATS	1
925 
926 static u32 *
927 tc358768_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
928 				   struct drm_bridge_state *bridge_state,
929 				   struct drm_crtc_state *crtc_state,
930 				   struct drm_connector_state *conn_state,
931 				   u32 output_fmt,
932 				   unsigned int *num_input_fmts)
933 {
934 	struct tc358768_priv *priv = bridge_to_tc358768(bridge);
935 	u32 *input_fmts;
936 
937 	*num_input_fmts = 0;
938 
939 	input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
940 			     GFP_KERNEL);
941 	if (!input_fmts)
942 		return NULL;
943 
944 	switch (priv->pd_lines) {
945 	case 16:
946 		input_fmts[0] = MEDIA_BUS_FMT_RGB565_1X16;
947 		break;
948 	case 18:
949 		input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X18;
950 		break;
951 	default:
952 	case 24:
953 		input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
954 		break;
955 	}
956 
957 	*num_input_fmts = MAX_INPUT_SEL_FORMATS;
958 
959 	return input_fmts;
960 }
961 
962 static const struct drm_bridge_funcs tc358768_bridge_funcs = {
963 	.attach = tc358768_bridge_attach,
964 	.mode_valid = tc358768_bridge_mode_valid,
965 	.pre_enable = tc358768_bridge_pre_enable,
966 	.enable = tc358768_bridge_enable,
967 	.disable = tc358768_bridge_disable,
968 	.post_disable = tc358768_bridge_post_disable,
969 
970 	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
971 	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
972 	.atomic_reset = drm_atomic_helper_bridge_reset,
973 	.atomic_get_input_bus_fmts = tc358768_atomic_get_input_bus_fmts,
974 };
975 
976 static const struct drm_bridge_timings default_tc358768_timings = {
977 	.input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
978 		 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
979 		 | DRM_BUS_FLAG_DE_HIGH,
980 };
981 
982 static bool tc358768_is_reserved_reg(unsigned int reg)
983 {
984 	switch (reg) {
985 	case 0x114 ... 0x13f:
986 	case 0x200:
987 	case 0x20c:
988 	case 0x400 ... 0x408:
989 	case 0x41c ... 0x42f:
990 		return true;
991 	default:
992 		return false;
993 	}
994 }
995 
996 static bool tc358768_writeable_reg(struct device *dev, unsigned int reg)
997 {
998 	if (tc358768_is_reserved_reg(reg))
999 		return false;
1000 
1001 	switch (reg) {
1002 	case TC358768_CHIPID:
1003 	case TC358768_FIFOSTATUS:
1004 	case TC358768_DSITXSTATUS ... (TC358768_DSITXSTATUS + 2):
1005 	case TC358768_DSI_CONTROL ... (TC358768_DSI_INT_ENA + 2):
1006 	case TC358768_DSICMD_RDFIFO ... (TC358768_DSI_ERR_HALT + 2):
1007 		return false;
1008 	default:
1009 		return true;
1010 	}
1011 }
1012 
1013 static bool tc358768_readable_reg(struct device *dev, unsigned int reg)
1014 {
1015 	if (tc358768_is_reserved_reg(reg))
1016 		return false;
1017 
1018 	switch (reg) {
1019 	case TC358768_STARTCNTRL:
1020 	case TC358768_DSI_CONFW ... (TC358768_DSI_CONFW + 2):
1021 	case TC358768_DSI_INT_CLR ... (TC358768_DSI_INT_CLR + 2):
1022 	case TC358768_DSI_START ... (TC358768_DSI_START + 2):
1023 	case TC358768_DBG_DATA:
1024 		return false;
1025 	default:
1026 		return true;
1027 	}
1028 }
1029 
1030 static const struct regmap_config tc358768_regmap_config = {
1031 	.name = "tc358768",
1032 	.reg_bits = 16,
1033 	.val_bits = 16,
1034 	.max_register = TC358768_DSI_HACT,
1035 	.cache_type = REGCACHE_NONE,
1036 	.writeable_reg = tc358768_writeable_reg,
1037 	.readable_reg = tc358768_readable_reg,
1038 	.reg_format_endian = REGMAP_ENDIAN_BIG,
1039 	.val_format_endian = REGMAP_ENDIAN_BIG,
1040 };
1041 
1042 static const struct i2c_device_id tc358768_i2c_ids[] = {
1043 	{ "tc358768", 0 },
1044 	{ "tc358778", 0 },
1045 	{ }
1046 };
1047 MODULE_DEVICE_TABLE(i2c, tc358768_i2c_ids);
1048 
1049 static const struct of_device_id tc358768_of_ids[] = {
1050 	{ .compatible = "toshiba,tc358768", },
1051 	{ .compatible = "toshiba,tc358778", },
1052 	{ }
1053 };
1054 MODULE_DEVICE_TABLE(of, tc358768_of_ids);
1055 
1056 static int tc358768_get_regulators(struct tc358768_priv *priv)
1057 {
1058 	int i, ret;
1059 
1060 	for (i = 0; i < ARRAY_SIZE(priv->supplies); ++i)
1061 		priv->supplies[i].supply = tc358768_supplies[i];
1062 
1063 	ret = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(priv->supplies),
1064 				      priv->supplies);
1065 	if (ret < 0)
1066 		dev_err(priv->dev, "failed to get regulators: %d\n", ret);
1067 
1068 	return ret;
1069 }
1070 
1071 static int tc358768_i2c_probe(struct i2c_client *client)
1072 {
1073 	struct tc358768_priv *priv;
1074 	struct device *dev = &client->dev;
1075 	struct device_node *np = dev->of_node;
1076 	int ret;
1077 
1078 	if (!np)
1079 		return -ENODEV;
1080 
1081 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1082 	if (!priv)
1083 		return -ENOMEM;
1084 
1085 	dev_set_drvdata(dev, priv);
1086 	priv->dev = dev;
1087 
1088 	ret = tc358768_get_regulators(priv);
1089 	if (ret)
1090 		return ret;
1091 
1092 	priv->refclk = devm_clk_get(dev, "refclk");
1093 	if (IS_ERR(priv->refclk))
1094 		return PTR_ERR(priv->refclk);
1095 
1096 	/*
1097 	 * RESX is low active, to disable tc358768 initially (keep in reset)
1098 	 * the gpio line must be LOW. This is the ASSERTED state of
1099 	 * GPIO_ACTIVE_LOW (GPIOD_OUT_HIGH == ASSERTED).
1100 	 */
1101 	priv->reset_gpio  = devm_gpiod_get_optional(dev, "reset",
1102 						    GPIOD_OUT_HIGH);
1103 	if (IS_ERR(priv->reset_gpio))
1104 		return PTR_ERR(priv->reset_gpio);
1105 
1106 	priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config);
1107 	if (IS_ERR(priv->regmap)) {
1108 		dev_err(dev, "Failed to init regmap\n");
1109 		return PTR_ERR(priv->regmap);
1110 	}
1111 
1112 	priv->dsi_host.dev = dev;
1113 	priv->dsi_host.ops = &tc358768_dsi_host_ops;
1114 
1115 	priv->bridge.funcs = &tc358768_bridge_funcs;
1116 	priv->bridge.timings = &default_tc358768_timings;
1117 	priv->bridge.of_node = np;
1118 
1119 	i2c_set_clientdata(client, priv);
1120 
1121 	return mipi_dsi_host_register(&priv->dsi_host);
1122 }
1123 
1124 static void tc358768_i2c_remove(struct i2c_client *client)
1125 {
1126 	struct tc358768_priv *priv = i2c_get_clientdata(client);
1127 
1128 	mipi_dsi_host_unregister(&priv->dsi_host);
1129 }
1130 
1131 static struct i2c_driver tc358768_driver = {
1132 	.driver = {
1133 		.name = "tc358768",
1134 		.of_match_table = tc358768_of_ids,
1135 	},
1136 	.id_table = tc358768_i2c_ids,
1137 	.probe = tc358768_i2c_probe,
1138 	.remove	= tc358768_i2c_remove,
1139 };
1140 module_i2c_driver(tc358768_driver);
1141 
1142 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
1143 MODULE_DESCRIPTION("TC358768AXBG/TC358778XBG DSI bridge");
1144 MODULE_LICENSE("GPL v2");
1145