1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/i2c.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/slab.h> 16 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_crtc_helper.h> 19 #include <drm/drm_drv.h> 20 #include <drm/drm_mipi_dsi.h> 21 #include <drm/drm_of.h> 22 #include <drm/drm_panel.h> 23 #include <video/mipi_display.h> 24 #include <video/videomode.h> 25 26 /* Global (16-bit addressable) */ 27 #define TC358768_CHIPID 0x0000 28 #define TC358768_SYSCTL 0x0002 29 #define TC358768_CONFCTL 0x0004 30 #define TC358768_VSDLY 0x0006 31 #define TC358768_DATAFMT 0x0008 32 #define TC358768_GPIOEN 0x000E 33 #define TC358768_GPIODIR 0x0010 34 #define TC358768_GPIOIN 0x0012 35 #define TC358768_GPIOOUT 0x0014 36 #define TC358768_PLLCTL0 0x0016 37 #define TC358768_PLLCTL1 0x0018 38 #define TC358768_CMDBYTE 0x0022 39 #define TC358768_PP_MISC 0x0032 40 #define TC358768_DSITX_DT 0x0050 41 #define TC358768_FIFOSTATUS 0x00F8 42 43 /* Debug (16-bit addressable) */ 44 #define TC358768_VBUFCTRL 0x00E0 45 #define TC358768_DBG_WIDTH 0x00E2 46 #define TC358768_DBG_VBLANK 0x00E4 47 #define TC358768_DBG_DATA 0x00E8 48 49 /* TX PHY (32-bit addressable) */ 50 #define TC358768_CLW_DPHYCONTTX 0x0100 51 #define TC358768_D0W_DPHYCONTTX 0x0104 52 #define TC358768_D1W_DPHYCONTTX 0x0108 53 #define TC358768_D2W_DPHYCONTTX 0x010C 54 #define TC358768_D3W_DPHYCONTTX 0x0110 55 #define TC358768_CLW_CNTRL 0x0140 56 #define TC358768_D0W_CNTRL 0x0144 57 #define TC358768_D1W_CNTRL 0x0148 58 #define TC358768_D2W_CNTRL 0x014C 59 #define TC358768_D3W_CNTRL 0x0150 60 61 /* TX PPI (32-bit addressable) */ 62 #define TC358768_STARTCNTRL 0x0204 63 #define TC358768_DSITXSTATUS 0x0208 64 #define TC358768_LINEINITCNT 0x0210 65 #define TC358768_LPTXTIMECNT 0x0214 66 #define TC358768_TCLK_HEADERCNT 0x0218 67 #define TC358768_TCLK_TRAILCNT 0x021C 68 #define TC358768_THS_HEADERCNT 0x0220 69 #define TC358768_TWAKEUP 0x0224 70 #define TC358768_TCLK_POSTCNT 0x0228 71 #define TC358768_THS_TRAILCNT 0x022C 72 #define TC358768_HSTXVREGCNT 0x0230 73 #define TC358768_HSTXVREGEN 0x0234 74 #define TC358768_TXOPTIONCNTRL 0x0238 75 #define TC358768_BTACNTRL1 0x023C 76 77 /* TX CTRL (32-bit addressable) */ 78 #define TC358768_DSI_CONTROL 0x040C 79 #define TC358768_DSI_STATUS 0x0410 80 #define TC358768_DSI_INT 0x0414 81 #define TC358768_DSI_INT_ENA 0x0418 82 #define TC358768_DSICMD_RDFIFO 0x0430 83 #define TC358768_DSI_ACKERR 0x0434 84 #define TC358768_DSI_ACKERR_INTENA 0x0438 85 #define TC358768_DSI_ACKERR_HALT 0x043c 86 #define TC358768_DSI_RXERR 0x0440 87 #define TC358768_DSI_RXERR_INTENA 0x0444 88 #define TC358768_DSI_RXERR_HALT 0x0448 89 #define TC358768_DSI_ERR 0x044C 90 #define TC358768_DSI_ERR_INTENA 0x0450 91 #define TC358768_DSI_ERR_HALT 0x0454 92 #define TC358768_DSI_CONFW 0x0500 93 #define TC358768_DSI_LPCMD 0x0500 94 #define TC358768_DSI_RESET 0x0504 95 #define TC358768_DSI_INT_CLR 0x050C 96 #define TC358768_DSI_START 0x0518 97 98 /* DSITX CTRL (16-bit addressable) */ 99 #define TC358768_DSICMD_TX 0x0600 100 #define TC358768_DSICMD_TYPE 0x0602 101 #define TC358768_DSICMD_WC 0x0604 102 #define TC358768_DSICMD_WD0 0x0610 103 #define TC358768_DSICMD_WD1 0x0612 104 #define TC358768_DSICMD_WD2 0x0614 105 #define TC358768_DSICMD_WD3 0x0616 106 #define TC358768_DSI_EVENT 0x0620 107 #define TC358768_DSI_VSW 0x0622 108 #define TC358768_DSI_VBPR 0x0624 109 #define TC358768_DSI_VACT 0x0626 110 #define TC358768_DSI_HSW 0x0628 111 #define TC358768_DSI_HBPR 0x062A 112 #define TC358768_DSI_HACT 0x062C 113 114 /* TC358768_DSI_CONTROL (0x040C) register */ 115 #define TC358768_DSI_CONTROL_DIS_MODE BIT(15) 116 #define TC358768_DSI_CONTROL_TXMD BIT(7) 117 #define TC358768_DSI_CONTROL_HSCKMD BIT(5) 118 #define TC358768_DSI_CONTROL_EOTDIS BIT(0) 119 120 /* TC358768_DSI_CONFW (0x0500) register */ 121 #define TC358768_DSI_CONFW_MODE_SET (5 << 29) 122 #define TC358768_DSI_CONFW_MODE_CLR (6 << 29) 123 #define TC358768_DSI_CONFW_ADDR_DSI_CONTROL (0x3 << 24) 124 125 static const char * const tc358768_supplies[] = { 126 "vddc", "vddmipi", "vddio" 127 }; 128 129 struct tc358768_dsi_output { 130 struct mipi_dsi_device *dev; 131 struct drm_panel *panel; 132 struct drm_bridge *bridge; 133 }; 134 135 struct tc358768_priv { 136 struct device *dev; 137 struct regmap *regmap; 138 struct gpio_desc *reset_gpio; 139 struct regulator_bulk_data supplies[ARRAY_SIZE(tc358768_supplies)]; 140 struct clk *refclk; 141 int enabled; 142 int error; 143 144 struct mipi_dsi_host dsi_host; 145 struct drm_bridge bridge; 146 struct tc358768_dsi_output output; 147 148 u32 pd_lines; /* number of Parallel Port Input Data Lines */ 149 u32 dsi_lanes; /* number of DSI Lanes */ 150 151 /* Parameters for PLL programming */ 152 u32 fbd; /* PLL feedback divider */ 153 u32 prd; /* PLL input divider */ 154 u32 frs; /* PLL Freqency range for HSCK (post divider) */ 155 156 u32 dsiclk; /* pll_clk / 2 */ 157 }; 158 159 static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_host 160 *host) 161 { 162 return container_of(host, struct tc358768_priv, dsi_host); 163 } 164 165 static inline struct tc358768_priv *bridge_to_tc358768(struct drm_bridge 166 *bridge) 167 { 168 return container_of(bridge, struct tc358768_priv, bridge); 169 } 170 171 static int tc358768_clear_error(struct tc358768_priv *priv) 172 { 173 int ret = priv->error; 174 175 priv->error = 0; 176 return ret; 177 } 178 179 static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val) 180 { 181 size_t count = 2; 182 183 if (priv->error) 184 return; 185 186 /* 16-bit register? */ 187 if (reg < 0x100 || reg >= 0x600) 188 count = 1; 189 190 priv->error = regmap_bulk_write(priv->regmap, reg, &val, count); 191 } 192 193 static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val) 194 { 195 size_t count = 2; 196 197 if (priv->error) 198 return; 199 200 /* 16-bit register? */ 201 if (reg < 0x100 || reg >= 0x600) { 202 *val = 0; 203 count = 1; 204 } 205 206 priv->error = regmap_bulk_read(priv->regmap, reg, val, count); 207 } 208 209 static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask, 210 u32 val) 211 { 212 u32 tmp, orig; 213 214 tc358768_read(priv, reg, &orig); 215 tmp = orig & ~mask; 216 tmp |= val & mask; 217 if (tmp != orig) 218 tc358768_write(priv, reg, tmp); 219 } 220 221 static int tc358768_sw_reset(struct tc358768_priv *priv) 222 { 223 /* Assert Reset */ 224 tc358768_write(priv, TC358768_SYSCTL, 1); 225 /* Release Reset, Exit Sleep */ 226 tc358768_write(priv, TC358768_SYSCTL, 0); 227 228 return tc358768_clear_error(priv); 229 } 230 231 static void tc358768_hw_enable(struct tc358768_priv *priv) 232 { 233 int ret; 234 235 if (priv->enabled) 236 return; 237 238 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); 239 if (ret < 0) 240 dev_err(priv->dev, "error enabling regulators (%d)\n", ret); 241 242 if (priv->reset_gpio) 243 usleep_range(200, 300); 244 245 /* 246 * The RESX is active low (GPIO_ACTIVE_LOW). 247 * DEASSERT (value = 0) the reset_gpio to enable the chip 248 */ 249 gpiod_set_value_cansleep(priv->reset_gpio, 0); 250 251 /* wait for encoder clocks to stabilize */ 252 usleep_range(1000, 2000); 253 254 priv->enabled = true; 255 } 256 257 static void tc358768_hw_disable(struct tc358768_priv *priv) 258 { 259 int ret; 260 261 if (!priv->enabled) 262 return; 263 264 /* 265 * The RESX is active low (GPIO_ACTIVE_LOW). 266 * ASSERT (value = 1) the reset_gpio to disable the chip 267 */ 268 gpiod_set_value_cansleep(priv->reset_gpio, 1); 269 270 ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies), 271 priv->supplies); 272 if (ret < 0) 273 dev_err(priv->dev, "error disabling regulators (%d)\n", ret); 274 275 priv->enabled = false; 276 } 277 278 static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk) 279 { 280 return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->pd_lines); 281 } 282 283 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk) 284 { 285 return (u32)div_u64((u64)pclk * priv->pd_lines, priv->dsi_lanes); 286 } 287 288 static int tc358768_calc_pll(struct tc358768_priv *priv, 289 const struct drm_display_mode *mode, 290 bool verify_only) 291 { 292 const u32 frs_limits[] = { 293 1000000000, 294 500000000, 295 250000000, 296 125000000, 297 62500000 298 }; 299 unsigned long refclk; 300 u32 prd, target_pll, i, max_pll, min_pll; 301 u32 frs, best_diff, best_pll, best_prd, best_fbd; 302 303 target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000); 304 305 /* pll_clk = RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] */ 306 307 for (i = 0; i < ARRAY_SIZE(frs_limits); i++) 308 if (target_pll >= frs_limits[i]) 309 break; 310 311 if (i == ARRAY_SIZE(frs_limits) || i == 0) 312 return -EINVAL; 313 314 frs = i - 1; 315 max_pll = frs_limits[i - 1]; 316 min_pll = frs_limits[i]; 317 318 refclk = clk_get_rate(priv->refclk); 319 320 best_diff = UINT_MAX; 321 best_pll = 0; 322 best_prd = 0; 323 best_fbd = 0; 324 325 for (prd = 0; prd < 16; ++prd) { 326 u32 divisor = (prd + 1) * (1 << frs); 327 u32 fbd; 328 329 for (fbd = 0; fbd < 512; ++fbd) { 330 u32 pll, diff; 331 332 pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor); 333 334 if (pll >= max_pll || pll < min_pll) 335 continue; 336 337 diff = max(pll, target_pll) - min(pll, target_pll); 338 339 if (diff < best_diff) { 340 best_diff = diff; 341 best_pll = pll; 342 best_prd = prd; 343 best_fbd = fbd; 344 345 if (best_diff == 0) 346 goto found; 347 } 348 } 349 } 350 351 if (best_diff == UINT_MAX) { 352 dev_err(priv->dev, "could not find suitable PLL setup\n"); 353 return -EINVAL; 354 } 355 356 found: 357 if (verify_only) 358 return 0; 359 360 priv->fbd = best_fbd; 361 priv->prd = best_prd; 362 priv->frs = frs; 363 priv->dsiclk = best_pll / 2; 364 365 return 0; 366 } 367 368 static int tc358768_dsi_host_attach(struct mipi_dsi_host *host, 369 struct mipi_dsi_device *dev) 370 { 371 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 372 struct drm_bridge *bridge; 373 struct drm_panel *panel; 374 struct device_node *ep; 375 int ret; 376 377 if (dev->lanes > 4) { 378 dev_err(priv->dev, "unsupported number of data lanes(%u)\n", 379 dev->lanes); 380 return -EINVAL; 381 } 382 383 /* 384 * tc358768 supports both Video and Pulse mode, but the driver only 385 * implements Video (event) mode currently 386 */ 387 if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) { 388 dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n"); 389 return -ENOTSUPP; 390 } 391 392 /* 393 * tc358768 supports RGB888, RGB666, RGB666_PACKED and RGB565, but only 394 * RGB888 is verified. 395 */ 396 if (dev->format != MIPI_DSI_FMT_RGB888) { 397 dev_warn(priv->dev, "Only MIPI_DSI_FMT_RGB888 tested!\n"); 398 return -ENOTSUPP; 399 } 400 401 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel, 402 &bridge); 403 if (ret) 404 return ret; 405 406 if (panel) { 407 bridge = drm_panel_bridge_add_typed(panel, 408 DRM_MODE_CONNECTOR_DSI); 409 if (IS_ERR(bridge)) 410 return PTR_ERR(bridge); 411 } 412 413 priv->output.dev = dev; 414 priv->output.bridge = bridge; 415 priv->output.panel = panel; 416 417 priv->dsi_lanes = dev->lanes; 418 419 /* get input ep (port0/endpoint0) */ 420 ret = -EINVAL; 421 ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0); 422 if (ep) { 423 ret = of_property_read_u32(ep, "data-lines", &priv->pd_lines); 424 425 of_node_put(ep); 426 } 427 428 if (ret) 429 priv->pd_lines = mipi_dsi_pixel_format_to_bpp(dev->format); 430 431 drm_bridge_add(&priv->bridge); 432 433 return 0; 434 } 435 436 static int tc358768_dsi_host_detach(struct mipi_dsi_host *host, 437 struct mipi_dsi_device *dev) 438 { 439 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 440 441 drm_bridge_remove(&priv->bridge); 442 if (priv->output.panel) 443 drm_panel_bridge_remove(priv->output.bridge); 444 445 return 0; 446 } 447 448 static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host, 449 const struct mipi_dsi_msg *msg) 450 { 451 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 452 struct mipi_dsi_packet packet; 453 int ret; 454 455 if (!priv->enabled) { 456 dev_err(priv->dev, "Bridge is not enabled\n"); 457 return -ENODEV; 458 } 459 460 if (msg->rx_len) { 461 dev_warn(priv->dev, "MIPI rx is not supported\n"); 462 return -ENOTSUPP; 463 } 464 465 if (msg->tx_len > 8) { 466 dev_warn(priv->dev, "Maximum 8 byte MIPI tx is supported\n"); 467 return -ENOTSUPP; 468 } 469 470 ret = mipi_dsi_create_packet(&packet, msg); 471 if (ret) 472 return ret; 473 474 if (mipi_dsi_packet_format_is_short(msg->type)) { 475 tc358768_write(priv, TC358768_DSICMD_TYPE, 476 (0x10 << 8) | (packet.header[0] & 0x3f)); 477 tc358768_write(priv, TC358768_DSICMD_WC, 0); 478 tc358768_write(priv, TC358768_DSICMD_WD0, 479 (packet.header[2] << 8) | packet.header[1]); 480 } else { 481 int i; 482 483 tc358768_write(priv, TC358768_DSICMD_TYPE, 484 (0x40 << 8) | (packet.header[0] & 0x3f)); 485 tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length); 486 for (i = 0; i < packet.payload_length; i += 2) { 487 u16 val = packet.payload[i]; 488 489 if (i + 1 < packet.payload_length) 490 val |= packet.payload[i + 1] << 8; 491 492 tc358768_write(priv, TC358768_DSICMD_WD0 + i, val); 493 } 494 } 495 496 /* start transfer */ 497 tc358768_write(priv, TC358768_DSICMD_TX, 1); 498 499 ret = tc358768_clear_error(priv); 500 if (ret) 501 dev_warn(priv->dev, "Software disable failed: %d\n", ret); 502 else 503 ret = packet.size; 504 505 return ret; 506 } 507 508 static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = { 509 .attach = tc358768_dsi_host_attach, 510 .detach = tc358768_dsi_host_detach, 511 .transfer = tc358768_dsi_host_transfer, 512 }; 513 514 static int tc358768_bridge_attach(struct drm_bridge *bridge, 515 enum drm_bridge_attach_flags flags) 516 { 517 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 518 519 if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) { 520 dev_err(priv->dev, "needs atomic updates support\n"); 521 return -ENOTSUPP; 522 } 523 524 return drm_bridge_attach(bridge->encoder, priv->output.bridge, bridge, 525 flags); 526 } 527 528 static enum drm_mode_status 529 tc358768_bridge_mode_valid(struct drm_bridge *bridge, 530 const struct drm_display_mode *mode) 531 { 532 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 533 534 if (tc358768_calc_pll(priv, mode, true)) 535 return MODE_CLOCK_RANGE; 536 537 return MODE_OK; 538 } 539 540 static void tc358768_bridge_disable(struct drm_bridge *bridge) 541 { 542 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 543 int ret; 544 545 /* set FrmStop */ 546 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(15), BIT(15)); 547 548 /* wait at least for one frame */ 549 msleep(50); 550 551 /* clear PP_en */ 552 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), 0); 553 554 /* set RstPtr */ 555 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), BIT(14)); 556 557 ret = tc358768_clear_error(priv); 558 if (ret) 559 dev_warn(priv->dev, "Software disable failed: %d\n", ret); 560 } 561 562 static void tc358768_bridge_post_disable(struct drm_bridge *bridge) 563 { 564 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 565 566 tc358768_hw_disable(priv); 567 } 568 569 static int tc358768_setup_pll(struct tc358768_priv *priv, 570 const struct drm_display_mode *mode) 571 { 572 u32 fbd, prd, frs; 573 int ret; 574 575 ret = tc358768_calc_pll(priv, mode, false); 576 if (ret) { 577 dev_err(priv->dev, "PLL calculation failed: %d\n", ret); 578 return ret; 579 } 580 581 fbd = priv->fbd; 582 prd = priv->prd; 583 frs = priv->frs; 584 585 dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n", 586 clk_get_rate(priv->refclk), fbd, prd, frs); 587 dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, DSIByteClk %u\n", 588 priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4); 589 dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n", 590 tc358768_pll_to_pclk(priv, priv->dsiclk * 2), 591 mode->clock * 1000); 592 593 /* PRD[15:12] FBD[8:0] */ 594 tc358768_write(priv, TC358768_PLLCTL0, (prd << 12) | fbd); 595 596 /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */ 597 tc358768_write(priv, TC358768_PLLCTL1, 598 (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0)); 599 600 /* wait for lock */ 601 usleep_range(1000, 2000); 602 603 /* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */ 604 tc358768_write(priv, TC358768_PLLCTL1, 605 (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0)); 606 607 return tc358768_clear_error(priv); 608 } 609 610 #define TC358768_PRECISION 1000 611 static u32 tc358768_ns_to_cnt(u32 ns, u32 period_nsk) 612 { 613 return (ns * TC358768_PRECISION + period_nsk) / period_nsk; 614 } 615 616 static u32 tc358768_to_ns(u32 nsk) 617 { 618 return (nsk / TC358768_PRECISION); 619 } 620 621 static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) 622 { 623 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 624 struct mipi_dsi_device *dsi_dev = priv->output.dev; 625 u32 val, val2, lptxcnt, hact, data_type; 626 const struct drm_display_mode *mode; 627 u32 dsibclk_nsk, dsiclk_nsk, ui_nsk, phy_delay_nsk; 628 u32 dsiclk, dsibclk; 629 int ret, i; 630 631 tc358768_hw_enable(priv); 632 633 ret = tc358768_sw_reset(priv); 634 if (ret) { 635 dev_err(priv->dev, "Software reset failed: %d\n", ret); 636 tc358768_hw_disable(priv); 637 return; 638 } 639 640 mode = &bridge->encoder->crtc->state->adjusted_mode; 641 ret = tc358768_setup_pll(priv, mode); 642 if (ret) { 643 dev_err(priv->dev, "PLL setup failed: %d\n", ret); 644 tc358768_hw_disable(priv); 645 return; 646 } 647 648 dsiclk = priv->dsiclk; 649 dsibclk = dsiclk / 4; 650 651 /* Data Format Control Register */ 652 val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */ 653 switch (dsi_dev->format) { 654 case MIPI_DSI_FMT_RGB888: 655 val |= (0x3 << 4); 656 hact = mode->hdisplay * 3; 657 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; 658 break; 659 case MIPI_DSI_FMT_RGB666: 660 val |= (0x4 << 4); 661 hact = mode->hdisplay * 3; 662 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; 663 break; 664 665 case MIPI_DSI_FMT_RGB666_PACKED: 666 val |= (0x4 << 4) | BIT(3); 667 hact = mode->hdisplay * 18 / 8; 668 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; 669 break; 670 671 case MIPI_DSI_FMT_RGB565: 672 val |= (0x5 << 4); 673 hact = mode->hdisplay * 2; 674 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; 675 break; 676 default: 677 dev_err(priv->dev, "Invalid data format (%u)\n", 678 dsi_dev->format); 679 tc358768_hw_disable(priv); 680 return; 681 } 682 683 /* VSDly[9:0] */ 684 tc358768_write(priv, TC358768_VSDLY, 1); 685 686 tc358768_write(priv, TC358768_DATAFMT, val); 687 tc358768_write(priv, TC358768_DSITX_DT, data_type); 688 689 /* Enable D-PHY (HiZ->LP11) */ 690 tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000); 691 /* Enable lanes */ 692 for (i = 0; i < dsi_dev->lanes; i++) 693 tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000); 694 695 /* DSI Timings */ 696 dsibclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION, 697 dsibclk); 698 dsiclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk); 699 ui_nsk = dsiclk_nsk / 2; 700 phy_delay_nsk = dsibclk_nsk + 2 * dsiclk_nsk; 701 dev_dbg(priv->dev, "dsiclk_nsk: %u\n", dsiclk_nsk); 702 dev_dbg(priv->dev, "ui_nsk: %u\n", ui_nsk); 703 dev_dbg(priv->dev, "dsibclk_nsk: %u\n", dsibclk_nsk); 704 dev_dbg(priv->dev, "phy_delay_nsk: %u\n", phy_delay_nsk); 705 706 /* LP11 > 100us for D-PHY Rx Init */ 707 val = tc358768_ns_to_cnt(100 * 1000, dsibclk_nsk) - 1; 708 dev_dbg(priv->dev, "LINEINITCNT: 0x%x\n", val); 709 tc358768_write(priv, TC358768_LINEINITCNT, val); 710 711 /* LPTimeCnt > 50ns */ 712 val = tc358768_ns_to_cnt(50, dsibclk_nsk) - 1; 713 lptxcnt = val; 714 dev_dbg(priv->dev, "LPTXTIMECNT: 0x%x\n", val); 715 tc358768_write(priv, TC358768_LPTXTIMECNT, val); 716 717 /* 38ns < TCLK_PREPARE < 95ns */ 718 val = tc358768_ns_to_cnt(65, dsibclk_nsk) - 1; 719 /* TCLK_PREPARE > 300ns */ 720 val2 = tc358768_ns_to_cnt(300 + tc358768_to_ns(3 * ui_nsk), 721 dsibclk_nsk); 722 val |= (val2 - tc358768_to_ns(phy_delay_nsk - dsibclk_nsk)) << 8; 723 dev_dbg(priv->dev, "TCLK_HEADERCNT: 0x%x\n", val); 724 tc358768_write(priv, TC358768_TCLK_HEADERCNT, val); 725 726 /* TCLK_TRAIL > 60ns + 3*UI */ 727 val = 60 + tc358768_to_ns(3 * ui_nsk); 728 val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 5; 729 dev_dbg(priv->dev, "TCLK_TRAILCNT: 0x%x\n", val); 730 tc358768_write(priv, TC358768_TCLK_TRAILCNT, val); 731 732 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */ 733 val = 50 + tc358768_to_ns(4 * ui_nsk); 734 val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1; 735 /* THS_ZERO > 145ns + 10*UI */ 736 val2 = tc358768_ns_to_cnt(145 - tc358768_to_ns(ui_nsk), dsibclk_nsk); 737 val |= (val2 - tc358768_to_ns(phy_delay_nsk)) << 8; 738 dev_dbg(priv->dev, "THS_HEADERCNT: 0x%x\n", val); 739 tc358768_write(priv, TC358768_THS_HEADERCNT, val); 740 741 /* TWAKEUP > 1ms in lptxcnt steps */ 742 val = tc358768_ns_to_cnt(1020000, dsibclk_nsk); 743 val = val / (lptxcnt + 1) - 1; 744 dev_dbg(priv->dev, "TWAKEUP: 0x%x\n", val); 745 tc358768_write(priv, TC358768_TWAKEUP, val); 746 747 /* TCLK_POSTCNT > 60ns + 52*UI */ 748 val = tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk), 749 dsibclk_nsk) - 3; 750 dev_dbg(priv->dev, "TCLK_POSTCNT: 0x%x\n", val); 751 tc358768_write(priv, TC358768_TCLK_POSTCNT, val); 752 753 /* 60ns + 4*UI < THS_PREPARE < 105ns + 12*UI */ 754 val = tc358768_ns_to_cnt(60 + tc358768_to_ns(15 * ui_nsk), 755 dsibclk_nsk) - 5; 756 dev_dbg(priv->dev, "THS_TRAILCNT: 0x%x\n", val); 757 tc358768_write(priv, TC358768_THS_TRAILCNT, val); 758 759 val = BIT(0); 760 for (i = 0; i < dsi_dev->lanes; i++) 761 val |= BIT(i + 1); 762 tc358768_write(priv, TC358768_HSTXVREGEN, val); 763 764 if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 765 tc358768_write(priv, TC358768_TXOPTIONCNTRL, 0x1); 766 767 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ 768 val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4); 769 val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1; 770 val2 = tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk), 771 dsibclk_nsk) - 2; 772 val |= val2 << 16; 773 dev_dbg(priv->dev, "BTACNTRL1: 0x%x\n", val); 774 tc358768_write(priv, TC358768_BTACNTRL1, val); 775 776 /* START[0] */ 777 tc358768_write(priv, TC358768_STARTCNTRL, 1); 778 779 /* Set event mode */ 780 tc358768_write(priv, TC358768_DSI_EVENT, 1); 781 782 /* vsw (+ vbp) */ 783 tc358768_write(priv, TC358768_DSI_VSW, 784 mode->vtotal - mode->vsync_start); 785 /* vbp (not used in event mode) */ 786 tc358768_write(priv, TC358768_DSI_VBPR, 0); 787 /* vact */ 788 tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay); 789 790 /* (hsw + hbp) * byteclk * ndl / pclk */ 791 val = (u32)div_u64((mode->htotal - mode->hsync_start) * 792 ((u64)priv->dsiclk / 4) * priv->dsi_lanes, 793 mode->clock * 1000); 794 tc358768_write(priv, TC358768_DSI_HSW, val); 795 /* hbp (not used in event mode) */ 796 tc358768_write(priv, TC358768_DSI_HBPR, 0); 797 /* hact (bytes) */ 798 tc358768_write(priv, TC358768_DSI_HACT, hact); 799 800 /* VSYNC polarity */ 801 if (!(mode->flags & DRM_MODE_FLAG_NVSYNC)) 802 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), BIT(5)); 803 /* HSYNC polarity */ 804 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 805 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), BIT(0)); 806 807 /* Start DSI Tx */ 808 tc358768_write(priv, TC358768_DSI_START, 0x1); 809 810 /* Configure DSI_Control register */ 811 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; 812 val |= TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD | 813 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS; 814 tc358768_write(priv, TC358768_DSI_CONFW, val); 815 816 val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; 817 val |= (dsi_dev->lanes - 1) << 1; 818 819 if (!(dsi_dev->mode_flags & MIPI_DSI_MODE_LPM)) 820 val |= TC358768_DSI_CONTROL_TXMD; 821 822 if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 823 val |= TC358768_DSI_CONTROL_HSCKMD; 824 825 if (dsi_dev->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 826 val |= TC358768_DSI_CONTROL_EOTDIS; 827 828 tc358768_write(priv, TC358768_DSI_CONFW, val); 829 830 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; 831 val |= TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */ 832 tc358768_write(priv, TC358768_DSI_CONFW, val); 833 834 ret = tc358768_clear_error(priv); 835 if (ret) { 836 dev_err(priv->dev, "Bridge pre_enable failed: %d\n", ret); 837 tc358768_bridge_disable(bridge); 838 tc358768_bridge_post_disable(bridge); 839 } 840 } 841 842 static void tc358768_bridge_enable(struct drm_bridge *bridge) 843 { 844 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 845 int ret; 846 847 if (!priv->enabled) { 848 dev_err(priv->dev, "Bridge is not enabled\n"); 849 return; 850 } 851 852 /* clear FrmStop and RstPtr */ 853 tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0); 854 855 /* set PP_en */ 856 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), BIT(6)); 857 858 ret = tc358768_clear_error(priv); 859 if (ret) { 860 dev_err(priv->dev, "Bridge enable failed: %d\n", ret); 861 tc358768_bridge_disable(bridge); 862 tc358768_bridge_post_disable(bridge); 863 } 864 } 865 866 static const struct drm_bridge_funcs tc358768_bridge_funcs = { 867 .attach = tc358768_bridge_attach, 868 .mode_valid = tc358768_bridge_mode_valid, 869 .pre_enable = tc358768_bridge_pre_enable, 870 .enable = tc358768_bridge_enable, 871 .disable = tc358768_bridge_disable, 872 .post_disable = tc358768_bridge_post_disable, 873 }; 874 875 static const struct drm_bridge_timings default_tc358768_timings = { 876 .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 877 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE 878 | DRM_BUS_FLAG_DE_HIGH, 879 }; 880 881 static bool tc358768_is_reserved_reg(unsigned int reg) 882 { 883 switch (reg) { 884 case 0x114 ... 0x13f: 885 case 0x200: 886 case 0x20c: 887 case 0x400 ... 0x408: 888 case 0x41c ... 0x42f: 889 return true; 890 default: 891 return false; 892 } 893 } 894 895 static bool tc358768_writeable_reg(struct device *dev, unsigned int reg) 896 { 897 if (tc358768_is_reserved_reg(reg)) 898 return false; 899 900 switch (reg) { 901 case TC358768_CHIPID: 902 case TC358768_FIFOSTATUS: 903 case TC358768_DSITXSTATUS ... (TC358768_DSITXSTATUS + 2): 904 case TC358768_DSI_CONTROL ... (TC358768_DSI_INT_ENA + 2): 905 case TC358768_DSICMD_RDFIFO ... (TC358768_DSI_ERR_HALT + 2): 906 return false; 907 default: 908 return true; 909 } 910 } 911 912 static bool tc358768_readable_reg(struct device *dev, unsigned int reg) 913 { 914 if (tc358768_is_reserved_reg(reg)) 915 return false; 916 917 switch (reg) { 918 case TC358768_STARTCNTRL: 919 case TC358768_DSI_CONFW ... (TC358768_DSI_CONFW + 2): 920 case TC358768_DSI_INT_CLR ... (TC358768_DSI_INT_CLR + 2): 921 case TC358768_DSI_START ... (TC358768_DSI_START + 2): 922 case TC358768_DBG_DATA: 923 return false; 924 default: 925 return true; 926 } 927 } 928 929 static const struct regmap_config tc358768_regmap_config = { 930 .name = "tc358768", 931 .reg_bits = 16, 932 .val_bits = 16, 933 .max_register = TC358768_DSI_HACT, 934 .cache_type = REGCACHE_NONE, 935 .writeable_reg = tc358768_writeable_reg, 936 .readable_reg = tc358768_readable_reg, 937 .reg_format_endian = REGMAP_ENDIAN_BIG, 938 .val_format_endian = REGMAP_ENDIAN_BIG, 939 }; 940 941 static const struct i2c_device_id tc358768_i2c_ids[] = { 942 { "tc358768", 0 }, 943 { "tc358778", 0 }, 944 { } 945 }; 946 MODULE_DEVICE_TABLE(i2c, tc358768_i2c_ids); 947 948 static const struct of_device_id tc358768_of_ids[] = { 949 { .compatible = "toshiba,tc358768", }, 950 { .compatible = "toshiba,tc358778", }, 951 { } 952 }; 953 MODULE_DEVICE_TABLE(of, tc358768_of_ids); 954 955 static int tc358768_get_regulators(struct tc358768_priv *priv) 956 { 957 int i, ret; 958 959 for (i = 0; i < ARRAY_SIZE(priv->supplies); ++i) 960 priv->supplies[i].supply = tc358768_supplies[i]; 961 962 ret = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(priv->supplies), 963 priv->supplies); 964 if (ret < 0) 965 dev_err(priv->dev, "failed to get regulators: %d\n", ret); 966 967 return ret; 968 } 969 970 static int tc358768_i2c_probe(struct i2c_client *client, 971 const struct i2c_device_id *id) 972 { 973 struct tc358768_priv *priv; 974 struct device *dev = &client->dev; 975 struct device_node *np = dev->of_node; 976 int ret; 977 978 if (!np) 979 return -ENODEV; 980 981 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 982 if (!priv) 983 return -ENOMEM; 984 985 dev_set_drvdata(dev, priv); 986 priv->dev = dev; 987 988 ret = tc358768_get_regulators(priv); 989 if (ret) 990 return ret; 991 992 priv->refclk = devm_clk_get(dev, "refclk"); 993 if (IS_ERR(priv->refclk)) 994 return PTR_ERR(priv->refclk); 995 996 /* 997 * RESX is low active, to disable tc358768 initially (keep in reset) 998 * the gpio line must be LOW. This is the ASSERTED state of 999 * GPIO_ACTIVE_LOW (GPIOD_OUT_HIGH == ASSERTED). 1000 */ 1001 priv->reset_gpio = devm_gpiod_get_optional(dev, "reset", 1002 GPIOD_OUT_HIGH); 1003 if (IS_ERR(priv->reset_gpio)) 1004 return PTR_ERR(priv->reset_gpio); 1005 1006 priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config); 1007 if (IS_ERR(priv->regmap)) { 1008 dev_err(dev, "Failed to init regmap\n"); 1009 return PTR_ERR(priv->regmap); 1010 } 1011 1012 priv->dsi_host.dev = dev; 1013 priv->dsi_host.ops = &tc358768_dsi_host_ops; 1014 1015 priv->bridge.funcs = &tc358768_bridge_funcs; 1016 priv->bridge.timings = &default_tc358768_timings; 1017 priv->bridge.of_node = np; 1018 1019 i2c_set_clientdata(client, priv); 1020 1021 return mipi_dsi_host_register(&priv->dsi_host); 1022 } 1023 1024 static int tc358768_i2c_remove(struct i2c_client *client) 1025 { 1026 struct tc358768_priv *priv = i2c_get_clientdata(client); 1027 1028 mipi_dsi_host_unregister(&priv->dsi_host); 1029 1030 return 0; 1031 } 1032 1033 static struct i2c_driver tc358768_driver = { 1034 .driver = { 1035 .name = "tc358768", 1036 .of_match_table = tc358768_of_ids, 1037 }, 1038 .id_table = tc358768_i2c_ids, 1039 .probe = tc358768_i2c_probe, 1040 .remove = tc358768_i2c_remove, 1041 }; 1042 module_i2c_driver(tc358768_driver); 1043 1044 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>"); 1045 MODULE_DESCRIPTION("TC358768AXBG/TC358778XBG DSI bridge"); 1046 MODULE_LICENSE("GPL v2"); 1047