1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/device.h>
9 #include <linux/gpio/consumer.h>
10 #include <linux/i2c.h>
11 #include <linux/kernel.h>
12 #include <linux/math64.h>
13 #include <linux/media-bus-format.h>
14 #include <linux/minmax.h>
15 #include <linux/module.h>
16 #include <linux/regmap.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/slab.h>
19 #include <linux/units.h>
20
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_drv.h>
23 #include <drm/drm_mipi_dsi.h>
24 #include <drm/drm_of.h>
25 #include <drm/drm_panel.h>
26 #include <video/mipi_display.h>
27 #include <video/videomode.h>
28
29 /* Global (16-bit addressable) */
30 #define TC358768_CHIPID 0x0000
31 #define TC358768_SYSCTL 0x0002
32 #define TC358768_CONFCTL 0x0004
33 #define TC358768_VSDLY 0x0006
34 #define TC358768_DATAFMT 0x0008
35 #define TC358768_GPIOEN 0x000E
36 #define TC358768_GPIODIR 0x0010
37 #define TC358768_GPIOIN 0x0012
38 #define TC358768_GPIOOUT 0x0014
39 #define TC358768_PLLCTL0 0x0016
40 #define TC358768_PLLCTL1 0x0018
41 #define TC358768_CMDBYTE 0x0022
42 #define TC358768_PP_MISC 0x0032
43 #define TC358768_DSITX_DT 0x0050
44 #define TC358768_FIFOSTATUS 0x00F8
45
46 /* Debug (16-bit addressable) */
47 #define TC358768_VBUFCTRL 0x00E0
48 #define TC358768_DBG_WIDTH 0x00E2
49 #define TC358768_DBG_VBLANK 0x00E4
50 #define TC358768_DBG_DATA 0x00E8
51
52 /* TX PHY (32-bit addressable) */
53 #define TC358768_CLW_DPHYCONTTX 0x0100
54 #define TC358768_D0W_DPHYCONTTX 0x0104
55 #define TC358768_D1W_DPHYCONTTX 0x0108
56 #define TC358768_D2W_DPHYCONTTX 0x010C
57 #define TC358768_D3W_DPHYCONTTX 0x0110
58 #define TC358768_CLW_CNTRL 0x0140
59 #define TC358768_D0W_CNTRL 0x0144
60 #define TC358768_D1W_CNTRL 0x0148
61 #define TC358768_D2W_CNTRL 0x014C
62 #define TC358768_D3W_CNTRL 0x0150
63
64 /* TX PPI (32-bit addressable) */
65 #define TC358768_STARTCNTRL 0x0204
66 #define TC358768_DSITXSTATUS 0x0208
67 #define TC358768_LINEINITCNT 0x0210
68 #define TC358768_LPTXTIMECNT 0x0214
69 #define TC358768_TCLK_HEADERCNT 0x0218
70 #define TC358768_TCLK_TRAILCNT 0x021C
71 #define TC358768_THS_HEADERCNT 0x0220
72 #define TC358768_TWAKEUP 0x0224
73 #define TC358768_TCLK_POSTCNT 0x0228
74 #define TC358768_THS_TRAILCNT 0x022C
75 #define TC358768_HSTXVREGCNT 0x0230
76 #define TC358768_HSTXVREGEN 0x0234
77 #define TC358768_TXOPTIONCNTRL 0x0238
78 #define TC358768_BTACNTRL1 0x023C
79
80 /* TX CTRL (32-bit addressable) */
81 #define TC358768_DSI_CONTROL 0x040C
82 #define TC358768_DSI_STATUS 0x0410
83 #define TC358768_DSI_INT 0x0414
84 #define TC358768_DSI_INT_ENA 0x0418
85 #define TC358768_DSICMD_RDFIFO 0x0430
86 #define TC358768_DSI_ACKERR 0x0434
87 #define TC358768_DSI_ACKERR_INTENA 0x0438
88 #define TC358768_DSI_ACKERR_HALT 0x043c
89 #define TC358768_DSI_RXERR 0x0440
90 #define TC358768_DSI_RXERR_INTENA 0x0444
91 #define TC358768_DSI_RXERR_HALT 0x0448
92 #define TC358768_DSI_ERR 0x044C
93 #define TC358768_DSI_ERR_INTENA 0x0450
94 #define TC358768_DSI_ERR_HALT 0x0454
95 #define TC358768_DSI_CONFW 0x0500
96 #define TC358768_DSI_LPCMD 0x0500
97 #define TC358768_DSI_RESET 0x0504
98 #define TC358768_DSI_INT_CLR 0x050C
99 #define TC358768_DSI_START 0x0518
100
101 /* DSITX CTRL (16-bit addressable) */
102 #define TC358768_DSICMD_TX 0x0600
103 #define TC358768_DSICMD_TYPE 0x0602
104 #define TC358768_DSICMD_WC 0x0604
105 #define TC358768_DSICMD_WD0 0x0610
106 #define TC358768_DSICMD_WD1 0x0612
107 #define TC358768_DSICMD_WD2 0x0614
108 #define TC358768_DSICMD_WD3 0x0616
109 #define TC358768_DSI_EVENT 0x0620
110 #define TC358768_DSI_VSW 0x0622
111 #define TC358768_DSI_VBPR 0x0624
112 #define TC358768_DSI_VACT 0x0626
113 #define TC358768_DSI_HSW 0x0628
114 #define TC358768_DSI_HBPR 0x062A
115 #define TC358768_DSI_HACT 0x062C
116
117 /* TC358768_DSI_CONTROL (0x040C) register */
118 #define TC358768_DSI_CONTROL_DIS_MODE BIT(15)
119 #define TC358768_DSI_CONTROL_TXMD BIT(7)
120 #define TC358768_DSI_CONTROL_HSCKMD BIT(5)
121 #define TC358768_DSI_CONTROL_EOTDIS BIT(0)
122
123 /* TC358768_DSI_CONFW (0x0500) register */
124 #define TC358768_DSI_CONFW_MODE_SET (5 << 29)
125 #define TC358768_DSI_CONFW_MODE_CLR (6 << 29)
126 #define TC358768_DSI_CONFW_ADDR_DSI_CONTROL (0x3 << 24)
127
128 /* TC358768_DSICMD_TX (0x0600) register */
129 #define TC358768_DSI_CMDTX_DC_START BIT(0)
130
131 static const char * const tc358768_supplies[] = {
132 "vddc", "vddmipi", "vddio"
133 };
134
135 struct tc358768_dsi_output {
136 struct mipi_dsi_device *dev;
137 struct drm_panel *panel;
138 struct drm_bridge *bridge;
139 };
140
141 struct tc358768_priv {
142 struct device *dev;
143 struct regmap *regmap;
144 struct gpio_desc *reset_gpio;
145 struct regulator_bulk_data supplies[ARRAY_SIZE(tc358768_supplies)];
146 struct clk *refclk;
147 int enabled;
148 int error;
149
150 struct mipi_dsi_host dsi_host;
151 struct drm_bridge bridge;
152 struct tc358768_dsi_output output;
153
154 u32 pd_lines; /* number of Parallel Port Input Data Lines */
155 u32 dsi_lanes; /* number of DSI Lanes */
156 u32 dsi_bpp; /* number of Bits Per Pixel over DSI */
157
158 /* Parameters for PLL programming */
159 u32 fbd; /* PLL feedback divider */
160 u32 prd; /* PLL input divider */
161 u32 frs; /* PLL Freqency range for HSCK (post divider) */
162
163 u32 dsiclk; /* pll_clk / 2 */
164 u32 pclk; /* incoming pclk rate */
165 };
166
dsi_host_to_tc358768(struct mipi_dsi_host * host)167 static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_host
168 *host)
169 {
170 return container_of(host, struct tc358768_priv, dsi_host);
171 }
172
bridge_to_tc358768(struct drm_bridge * bridge)173 static inline struct tc358768_priv *bridge_to_tc358768(struct drm_bridge
174 *bridge)
175 {
176 return container_of(bridge, struct tc358768_priv, bridge);
177 }
178
tc358768_clear_error(struct tc358768_priv * priv)179 static int tc358768_clear_error(struct tc358768_priv *priv)
180 {
181 int ret = priv->error;
182
183 priv->error = 0;
184 return ret;
185 }
186
tc358768_write(struct tc358768_priv * priv,u32 reg,u32 val)187 static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val)
188 {
189 /* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
190 int tmpval = val;
191 size_t count = 2;
192
193 if (priv->error)
194 return;
195
196 /* 16-bit register? */
197 if (reg < 0x100 || reg >= 0x600)
198 count = 1;
199
200 priv->error = regmap_bulk_write(priv->regmap, reg, &tmpval, count);
201 }
202
tc358768_read(struct tc358768_priv * priv,u32 reg,u32 * val)203 static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val)
204 {
205 size_t count = 2;
206
207 if (priv->error)
208 return;
209
210 /* 16-bit register? */
211 if (reg < 0x100 || reg >= 0x600) {
212 *val = 0;
213 count = 1;
214 }
215
216 priv->error = regmap_bulk_read(priv->regmap, reg, val, count);
217 }
218
tc358768_update_bits(struct tc358768_priv * priv,u32 reg,u32 mask,u32 val)219 static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask,
220 u32 val)
221 {
222 u32 tmp, orig;
223
224 tc358768_read(priv, reg, &orig);
225
226 if (priv->error)
227 return;
228
229 tmp = orig & ~mask;
230 tmp |= val & mask;
231 if (tmp != orig)
232 tc358768_write(priv, reg, tmp);
233 }
234
tc358768_dsicmd_tx(struct tc358768_priv * priv)235 static void tc358768_dsicmd_tx(struct tc358768_priv *priv)
236 {
237 u32 val;
238
239 /* start transfer */
240 tc358768_write(priv, TC358768_DSICMD_TX, TC358768_DSI_CMDTX_DC_START);
241 if (priv->error)
242 return;
243
244 /* wait transfer completion */
245 priv->error = regmap_read_poll_timeout(priv->regmap, TC358768_DSICMD_TX, val,
246 (val & TC358768_DSI_CMDTX_DC_START) == 0,
247 100, 100000);
248 }
249
tc358768_sw_reset(struct tc358768_priv * priv)250 static int tc358768_sw_reset(struct tc358768_priv *priv)
251 {
252 /* Assert Reset */
253 tc358768_write(priv, TC358768_SYSCTL, 1);
254 /* Release Reset, Exit Sleep */
255 tc358768_write(priv, TC358768_SYSCTL, 0);
256
257 return tc358768_clear_error(priv);
258 }
259
tc358768_hw_enable(struct tc358768_priv * priv)260 static void tc358768_hw_enable(struct tc358768_priv *priv)
261 {
262 int ret;
263
264 if (priv->enabled)
265 return;
266
267 ret = clk_prepare_enable(priv->refclk);
268 if (ret < 0)
269 dev_err(priv->dev, "error enabling refclk (%d)\n", ret);
270
271 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
272 if (ret < 0)
273 dev_err(priv->dev, "error enabling regulators (%d)\n", ret);
274
275 if (priv->reset_gpio)
276 usleep_range(200, 300);
277
278 /*
279 * The RESX is active low (GPIO_ACTIVE_LOW).
280 * DEASSERT (value = 0) the reset_gpio to enable the chip
281 */
282 gpiod_set_value_cansleep(priv->reset_gpio, 0);
283
284 /* wait for encoder clocks to stabilize */
285 usleep_range(1000, 2000);
286
287 priv->enabled = true;
288 }
289
tc358768_hw_disable(struct tc358768_priv * priv)290 static void tc358768_hw_disable(struct tc358768_priv *priv)
291 {
292 int ret;
293
294 if (!priv->enabled)
295 return;
296
297 /*
298 * The RESX is active low (GPIO_ACTIVE_LOW).
299 * ASSERT (value = 1) the reset_gpio to disable the chip
300 */
301 gpiod_set_value_cansleep(priv->reset_gpio, 1);
302
303 ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
304 priv->supplies);
305 if (ret < 0)
306 dev_err(priv->dev, "error disabling regulators (%d)\n", ret);
307
308 clk_disable_unprepare(priv->refclk);
309
310 priv->enabled = false;
311 }
312
tc358768_pll_to_pclk(struct tc358768_priv * priv,u32 pll_clk)313 static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk)
314 {
315 return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->dsi_bpp);
316 }
317
tc358768_pclk_to_pll(struct tc358768_priv * priv,u32 pclk)318 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk)
319 {
320 return (u32)div_u64((u64)pclk * priv->dsi_bpp, priv->dsi_lanes);
321 }
322
tc358768_calc_pll(struct tc358768_priv * priv,const struct drm_display_mode * mode,bool verify_only)323 static int tc358768_calc_pll(struct tc358768_priv *priv,
324 const struct drm_display_mode *mode,
325 bool verify_only)
326 {
327 static const u32 frs_limits[] = {
328 1000000000,
329 500000000,
330 250000000,
331 125000000,
332 62500000
333 };
334 unsigned long refclk;
335 u32 prd, target_pll, i, max_pll, min_pll;
336 u32 frs, best_diff, best_pll, best_prd, best_fbd;
337
338 target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000);
339
340 /* pll_clk = RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] */
341
342 for (i = 0; i < ARRAY_SIZE(frs_limits); i++)
343 if (target_pll >= frs_limits[i])
344 break;
345
346 if (i == ARRAY_SIZE(frs_limits) || i == 0)
347 return -EINVAL;
348
349 frs = i - 1;
350 max_pll = frs_limits[i - 1];
351 min_pll = frs_limits[i];
352
353 refclk = clk_get_rate(priv->refclk);
354
355 best_diff = UINT_MAX;
356 best_pll = 0;
357 best_prd = 0;
358 best_fbd = 0;
359
360 for (prd = 0; prd < 16; ++prd) {
361 u32 divisor = (prd + 1) * (1 << frs);
362 u32 fbd;
363
364 for (fbd = 0; fbd < 512; ++fbd) {
365 u32 pll, diff, pll_in;
366
367 pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor);
368
369 if (pll >= max_pll || pll < min_pll)
370 continue;
371
372 pll_in = (u32)div_u64((u64)refclk, prd + 1);
373 if (pll_in < 4000000)
374 continue;
375
376 diff = max(pll, target_pll) - min(pll, target_pll);
377
378 if (diff < best_diff) {
379 best_diff = diff;
380 best_pll = pll;
381 best_prd = prd;
382 best_fbd = fbd;
383
384 if (best_diff == 0)
385 goto found;
386 }
387 }
388 }
389
390 if (best_diff == UINT_MAX) {
391 dev_err(priv->dev, "could not find suitable PLL setup\n");
392 return -EINVAL;
393 }
394
395 found:
396 if (verify_only)
397 return 0;
398
399 priv->fbd = best_fbd;
400 priv->prd = best_prd;
401 priv->frs = frs;
402 priv->dsiclk = best_pll / 2;
403 priv->pclk = mode->clock * 1000;
404
405 return 0;
406 }
407
tc358768_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * dev)408 static int tc358768_dsi_host_attach(struct mipi_dsi_host *host,
409 struct mipi_dsi_device *dev)
410 {
411 struct tc358768_priv *priv = dsi_host_to_tc358768(host);
412 struct drm_bridge *bridge;
413 struct drm_panel *panel;
414 struct device_node *ep;
415 int ret;
416
417 if (dev->lanes > 4) {
418 dev_err(priv->dev, "unsupported number of data lanes(%u)\n",
419 dev->lanes);
420 return -EINVAL;
421 }
422
423 /*
424 * tc358768 supports both Video and Pulse mode, but the driver only
425 * implements Video (event) mode currently
426 */
427 if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) {
428 dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n");
429 return -ENOTSUPP;
430 }
431
432 /*
433 * tc358768 supports RGB888, RGB666, RGB666_PACKED and RGB565, but only
434 * RGB888 is verified.
435 */
436 if (dev->format != MIPI_DSI_FMT_RGB888) {
437 dev_warn(priv->dev, "Only MIPI_DSI_FMT_RGB888 tested!\n");
438 return -ENOTSUPP;
439 }
440
441 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel,
442 &bridge);
443 if (ret)
444 return ret;
445
446 if (panel) {
447 bridge = drm_panel_bridge_add_typed(panel,
448 DRM_MODE_CONNECTOR_DSI);
449 if (IS_ERR(bridge))
450 return PTR_ERR(bridge);
451 }
452
453 priv->output.dev = dev;
454 priv->output.bridge = bridge;
455 priv->output.panel = panel;
456
457 priv->dsi_lanes = dev->lanes;
458 priv->dsi_bpp = mipi_dsi_pixel_format_to_bpp(dev->format);
459
460 /* get input ep (port0/endpoint0) */
461 ret = -EINVAL;
462 ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0);
463 if (ep) {
464 ret = of_property_read_u32(ep, "data-lines", &priv->pd_lines);
465
466 of_node_put(ep);
467 }
468
469 if (ret)
470 priv->pd_lines = priv->dsi_bpp;
471
472 drm_bridge_add(&priv->bridge);
473
474 return 0;
475 }
476
tc358768_dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * dev)477 static int tc358768_dsi_host_detach(struct mipi_dsi_host *host,
478 struct mipi_dsi_device *dev)
479 {
480 struct tc358768_priv *priv = dsi_host_to_tc358768(host);
481
482 drm_bridge_remove(&priv->bridge);
483 if (priv->output.panel)
484 drm_panel_bridge_remove(priv->output.bridge);
485
486 return 0;
487 }
488
tc358768_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)489 static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host,
490 const struct mipi_dsi_msg *msg)
491 {
492 struct tc358768_priv *priv = dsi_host_to_tc358768(host);
493 struct mipi_dsi_packet packet;
494 int ret;
495
496 if (!priv->enabled) {
497 dev_err(priv->dev, "Bridge is not enabled\n");
498 return -ENODEV;
499 }
500
501 if (msg->rx_len) {
502 dev_warn(priv->dev, "MIPI rx is not supported\n");
503 return -ENOTSUPP;
504 }
505
506 if (msg->tx_len > 8) {
507 dev_warn(priv->dev, "Maximum 8 byte MIPI tx is supported\n");
508 return -ENOTSUPP;
509 }
510
511 ret = mipi_dsi_create_packet(&packet, msg);
512 if (ret)
513 return ret;
514
515 if (mipi_dsi_packet_format_is_short(msg->type)) {
516 tc358768_write(priv, TC358768_DSICMD_TYPE,
517 (0x10 << 8) | (packet.header[0] & 0x3f));
518 tc358768_write(priv, TC358768_DSICMD_WC, 0);
519 tc358768_write(priv, TC358768_DSICMD_WD0,
520 (packet.header[2] << 8) | packet.header[1]);
521 } else {
522 int i;
523
524 tc358768_write(priv, TC358768_DSICMD_TYPE,
525 (0x40 << 8) | (packet.header[0] & 0x3f));
526 tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length);
527 for (i = 0; i < packet.payload_length; i += 2) {
528 u16 val = packet.payload[i];
529
530 if (i + 1 < packet.payload_length)
531 val |= packet.payload[i + 1] << 8;
532
533 tc358768_write(priv, TC358768_DSICMD_WD0 + i, val);
534 }
535 }
536
537 tc358768_dsicmd_tx(priv);
538
539 ret = tc358768_clear_error(priv);
540 if (ret)
541 dev_warn(priv->dev, "Software disable failed: %d\n", ret);
542 else
543 ret = packet.size;
544
545 return ret;
546 }
547
548 static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = {
549 .attach = tc358768_dsi_host_attach,
550 .detach = tc358768_dsi_host_detach,
551 .transfer = tc358768_dsi_host_transfer,
552 };
553
tc358768_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)554 static int tc358768_bridge_attach(struct drm_bridge *bridge,
555 enum drm_bridge_attach_flags flags)
556 {
557 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
558
559 if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) {
560 dev_err(priv->dev, "needs atomic updates support\n");
561 return -ENOTSUPP;
562 }
563
564 return drm_bridge_attach(bridge->encoder, priv->output.bridge, bridge,
565 flags);
566 }
567
568 static enum drm_mode_status
tc358768_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)569 tc358768_bridge_mode_valid(struct drm_bridge *bridge,
570 const struct drm_display_info *info,
571 const struct drm_display_mode *mode)
572 {
573 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
574
575 if (tc358768_calc_pll(priv, mode, true))
576 return MODE_CLOCK_RANGE;
577
578 return MODE_OK;
579 }
580
tc358768_bridge_disable(struct drm_bridge * bridge)581 static void tc358768_bridge_disable(struct drm_bridge *bridge)
582 {
583 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
584 int ret;
585
586 /* set FrmStop */
587 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(15), BIT(15));
588
589 /* wait at least for one frame */
590 msleep(50);
591
592 /* clear PP_en */
593 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), 0);
594
595 /* set RstPtr */
596 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), BIT(14));
597
598 ret = tc358768_clear_error(priv);
599 if (ret)
600 dev_warn(priv->dev, "Software disable failed: %d\n", ret);
601 }
602
tc358768_bridge_post_disable(struct drm_bridge * bridge)603 static void tc358768_bridge_post_disable(struct drm_bridge *bridge)
604 {
605 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
606
607 tc358768_hw_disable(priv);
608 }
609
tc358768_setup_pll(struct tc358768_priv * priv,const struct drm_display_mode * mode)610 static int tc358768_setup_pll(struct tc358768_priv *priv,
611 const struct drm_display_mode *mode)
612 {
613 u32 fbd, prd, frs;
614 int ret;
615
616 ret = tc358768_calc_pll(priv, mode, false);
617 if (ret) {
618 dev_err(priv->dev, "PLL calculation failed: %d\n", ret);
619 return ret;
620 }
621
622 fbd = priv->fbd;
623 prd = priv->prd;
624 frs = priv->frs;
625
626 dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n",
627 clk_get_rate(priv->refclk), fbd, prd, frs);
628 dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, HSByteClk %u\n",
629 priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4);
630 dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n",
631 tc358768_pll_to_pclk(priv, priv->dsiclk * 2),
632 mode->clock * 1000);
633
634 /* PRD[15:12] FBD[8:0] */
635 tc358768_write(priv, TC358768_PLLCTL0, (prd << 12) | fbd);
636
637 /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */
638 tc358768_write(priv, TC358768_PLLCTL1,
639 (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0));
640
641 /* wait for lock */
642 usleep_range(1000, 2000);
643
644 /* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */
645 tc358768_write(priv, TC358768_PLLCTL1,
646 (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0));
647
648 return tc358768_clear_error(priv);
649 }
650
tc358768_ns_to_cnt(u32 ns,u32 period_ps)651 static u32 tc358768_ns_to_cnt(u32 ns, u32 period_ps)
652 {
653 return DIV_ROUND_UP(ns * 1000, period_ps);
654 }
655
tc358768_ps_to_ns(u32 ps)656 static u32 tc358768_ps_to_ns(u32 ps)
657 {
658 return ps / 1000;
659 }
660
tc358768_dpi_to_ns(u32 val,u32 pclk)661 static u32 tc358768_dpi_to_ns(u32 val, u32 pclk)
662 {
663 return (u32)div_u64((u64)val * NANO, pclk);
664 }
665
666 /* Convert value in DPI pixel clock units to DSI byte count */
tc358768_dpi_to_dsi_bytes(struct tc358768_priv * priv,u32 val)667 static u32 tc358768_dpi_to_dsi_bytes(struct tc358768_priv *priv, u32 val)
668 {
669 u64 m = (u64)val * priv->dsiclk / 4 * priv->dsi_lanes;
670 u64 n = priv->pclk;
671
672 return (u32)div_u64(m + n - 1, n);
673 }
674
tc358768_dsi_bytes_to_ns(struct tc358768_priv * priv,u32 val)675 static u32 tc358768_dsi_bytes_to_ns(struct tc358768_priv *priv, u32 val)
676 {
677 u64 m = (u64)val * NANO;
678 u64 n = priv->dsiclk / 4 * priv->dsi_lanes;
679
680 return (u32)div_u64(m, n);
681 }
682
tc358768_bridge_pre_enable(struct drm_bridge * bridge)683 static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
684 {
685 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
686 struct mipi_dsi_device *dsi_dev = priv->output.dev;
687 unsigned long mode_flags = dsi_dev->mode_flags;
688 u32 val, val2, lptxcnt, hact, data_type;
689 s32 raw_val;
690 const struct drm_display_mode *mode;
691 u32 hsbyteclk_ps, dsiclk_ps, ui_ps;
692 u32 dsiclk, hsbyteclk;
693 int ret, i;
694 struct videomode vm;
695 struct device *dev = priv->dev;
696 /* In pixelclock units */
697 u32 dpi_htot, dpi_data_start;
698 /* In byte units */
699 u32 dsi_dpi_htot, dsi_dpi_data_start;
700 u32 dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp;
701 const u32 dsi_hss = 4; /* HSS is a short packet (4 bytes) */
702 /* In hsbyteclk units */
703 u32 dsi_vsdly;
704 const u32 internal_dly = 40;
705
706 if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
707 dev_warn_once(dev, "Non-continuous mode unimplemented, falling back to continuous\n");
708 mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS;
709 }
710
711 tc358768_hw_enable(priv);
712
713 ret = tc358768_sw_reset(priv);
714 if (ret) {
715 dev_err(dev, "Software reset failed: %d\n", ret);
716 tc358768_hw_disable(priv);
717 return;
718 }
719
720 mode = &bridge->encoder->crtc->state->adjusted_mode;
721 ret = tc358768_setup_pll(priv, mode);
722 if (ret) {
723 dev_err(dev, "PLL setup failed: %d\n", ret);
724 tc358768_hw_disable(priv);
725 return;
726 }
727
728 drm_display_mode_to_videomode(mode, &vm);
729
730 dsiclk = priv->dsiclk;
731 hsbyteclk = dsiclk / 4;
732
733 /* Data Format Control Register */
734 val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */
735 switch (dsi_dev->format) {
736 case MIPI_DSI_FMT_RGB888:
737 val |= (0x3 << 4);
738 hact = vm.hactive * 3;
739 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
740 break;
741 case MIPI_DSI_FMT_RGB666:
742 val |= (0x4 << 4);
743 hact = vm.hactive * 3;
744 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
745 break;
746
747 case MIPI_DSI_FMT_RGB666_PACKED:
748 val |= (0x4 << 4) | BIT(3);
749 hact = vm.hactive * 18 / 8;
750 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
751 break;
752
753 case MIPI_DSI_FMT_RGB565:
754 val |= (0x5 << 4);
755 hact = vm.hactive * 2;
756 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
757 break;
758 default:
759 dev_err(dev, "Invalid data format (%u)\n",
760 dsi_dev->format);
761 tc358768_hw_disable(priv);
762 return;
763 }
764
765 /*
766 * There are three important things to make TC358768 work correctly,
767 * which are not trivial to manage:
768 *
769 * 1. Keep the DPI line-time and the DSI line-time as close to each
770 * other as possible.
771 * 2. TC358768 goes to LP mode after each line's active area. The DSI
772 * HFP period has to be long enough for entering and exiting LP mode.
773 * But it is not clear how to calculate this.
774 * 3. VSDly (video start delay) has to be long enough to ensure that the
775 * DSI TX does not start transmitting until we have started receiving
776 * pixel data from the DPI input. It is not clear how to calculate
777 * this either.
778 */
779
780 dpi_htot = vm.hactive + vm.hfront_porch + vm.hsync_len + vm.hback_porch;
781 dpi_data_start = vm.hsync_len + vm.hback_porch;
782
783 dev_dbg(dev, "dpi horiz timing (pclk): %u + %u + %u + %u = %u\n",
784 vm.hsync_len, vm.hback_porch, vm.hactive, vm.hfront_porch,
785 dpi_htot);
786
787 dev_dbg(dev, "dpi horiz timing (ns): %u + %u + %u + %u = %u\n",
788 tc358768_dpi_to_ns(vm.hsync_len, vm.pixelclock),
789 tc358768_dpi_to_ns(vm.hback_porch, vm.pixelclock),
790 tc358768_dpi_to_ns(vm.hactive, vm.pixelclock),
791 tc358768_dpi_to_ns(vm.hfront_porch, vm.pixelclock),
792 tc358768_dpi_to_ns(dpi_htot, vm.pixelclock));
793
794 dev_dbg(dev, "dpi data start (ns): %u + %u = %u\n",
795 tc358768_dpi_to_ns(vm.hsync_len, vm.pixelclock),
796 tc358768_dpi_to_ns(vm.hback_porch, vm.pixelclock),
797 tc358768_dpi_to_ns(dpi_data_start, vm.pixelclock));
798
799 dsi_dpi_htot = tc358768_dpi_to_dsi_bytes(priv, dpi_htot);
800 dsi_dpi_data_start = tc358768_dpi_to_dsi_bytes(priv, dpi_data_start);
801
802 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
803 dsi_hsw = tc358768_dpi_to_dsi_bytes(priv, vm.hsync_len);
804 dsi_hbp = tc358768_dpi_to_dsi_bytes(priv, vm.hback_porch);
805 } else {
806 /* HBP is included in HSW in event mode */
807 dsi_hbp = 0;
808 dsi_hsw = tc358768_dpi_to_dsi_bytes(priv,
809 vm.hsync_len +
810 vm.hback_porch);
811
812 /*
813 * The pixel packet includes the actual pixel data, and:
814 * DSI packet header = 4 bytes
815 * DCS code = 1 byte
816 * DSI packet footer = 2 bytes
817 */
818 dsi_hact = hact + 4 + 1 + 2;
819
820 dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss;
821
822 /*
823 * Here we should check if HFP is long enough for entering LP
824 * and exiting LP, but it's not clear how to calculate that.
825 * Instead, this is a naive algorithm that just adjusts the HFP
826 * and HSW so that HFP is (at least) roughly 2/3 of the total
827 * blanking time.
828 */
829 if (dsi_hfp < (dsi_hfp + dsi_hsw + dsi_hss) * 2 / 3) {
830 u32 old_hfp = dsi_hfp;
831 u32 old_hsw = dsi_hsw;
832 u32 tot = dsi_hfp + dsi_hsw + dsi_hss;
833
834 dsi_hsw = tot / 3;
835
836 /*
837 * Seems like sometimes HSW has to be divisible by num-lanes, but
838 * not always...
839 */
840 dsi_hsw = roundup(dsi_hsw, priv->dsi_lanes);
841
842 dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss;
843
844 dev_dbg(dev,
845 "hfp too short, adjusting dsi hfp and dsi hsw from %u, %u to %u, %u\n",
846 old_hfp, old_hsw, dsi_hfp, dsi_hsw);
847 }
848
849 dev_dbg(dev,
850 "dsi horiz timing (bytes): %u, %u + %u + %u + %u = %u\n",
851 dsi_hss, dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp,
852 dsi_hss + dsi_hsw + dsi_hbp + dsi_hact + dsi_hfp);
853
854 dev_dbg(dev, "dsi horiz timing (ns): %u + %u + %u + %u + %u = %u\n",
855 tc358768_dsi_bytes_to_ns(priv, dsi_hss),
856 tc358768_dsi_bytes_to_ns(priv, dsi_hsw),
857 tc358768_dsi_bytes_to_ns(priv, dsi_hbp),
858 tc358768_dsi_bytes_to_ns(priv, dsi_hact),
859 tc358768_dsi_bytes_to_ns(priv, dsi_hfp),
860 tc358768_dsi_bytes_to_ns(priv, dsi_hss + dsi_hsw +
861 dsi_hbp + dsi_hact + dsi_hfp));
862 }
863
864 /* VSDly calculation */
865
866 /* Start with the HW internal delay */
867 dsi_vsdly = internal_dly;
868
869 /* Convert to byte units as the other variables are in byte units */
870 dsi_vsdly *= priv->dsi_lanes;
871
872 /* Do we need more delay, in addition to the internal? */
873 if (dsi_dpi_data_start > dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp) {
874 dsi_vsdly = dsi_dpi_data_start - dsi_hss - dsi_hsw - dsi_hbp;
875 dsi_vsdly = roundup(dsi_vsdly, priv->dsi_lanes);
876 }
877
878 dev_dbg(dev, "dsi data start (bytes) %u + %u + %u + %u = %u\n",
879 dsi_vsdly, dsi_hss, dsi_hsw, dsi_hbp,
880 dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp);
881
882 dev_dbg(dev, "dsi data start (ns) %u + %u + %u + %u = %u\n",
883 tc358768_dsi_bytes_to_ns(priv, dsi_vsdly),
884 tc358768_dsi_bytes_to_ns(priv, dsi_hss),
885 tc358768_dsi_bytes_to_ns(priv, dsi_hsw),
886 tc358768_dsi_bytes_to_ns(priv, dsi_hbp),
887 tc358768_dsi_bytes_to_ns(priv, dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp));
888
889 /* Convert back to hsbyteclk */
890 dsi_vsdly /= priv->dsi_lanes;
891
892 /*
893 * The docs say that there is an internal delay of 40 cycles.
894 * However, we get underflows if we follow that rule. If we
895 * instead ignore the internal delay, things work. So either
896 * the docs are wrong or the calculations are wrong.
897 *
898 * As a temporary fix, add the internal delay here, to counter
899 * the subtraction when writing the register.
900 */
901 dsi_vsdly += internal_dly;
902
903 /* Clamp to the register max */
904 if (dsi_vsdly - internal_dly > 0x3ff) {
905 dev_warn(dev, "VSDly too high, underflows likely\n");
906 dsi_vsdly = 0x3ff + internal_dly;
907 }
908
909 /* VSDly[9:0] */
910 tc358768_write(priv, TC358768_VSDLY, dsi_vsdly - internal_dly);
911
912 tc358768_write(priv, TC358768_DATAFMT, val);
913 tc358768_write(priv, TC358768_DSITX_DT, data_type);
914
915 /* Enable D-PHY (HiZ->LP11) */
916 tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000);
917 /* Enable lanes */
918 for (i = 0; i < dsi_dev->lanes; i++)
919 tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000);
920
921 /* DSI Timings */
922 hsbyteclk_ps = (u32)div_u64(PICO, hsbyteclk);
923 dsiclk_ps = (u32)div_u64(PICO, dsiclk);
924 ui_ps = dsiclk_ps / 2;
925 dev_dbg(dev, "dsiclk: %u ps, ui %u ps, hsbyteclk %u ps\n", dsiclk_ps,
926 ui_ps, hsbyteclk_ps);
927
928 /* LP11 > 100us for D-PHY Rx Init */
929 val = tc358768_ns_to_cnt(100 * 1000, hsbyteclk_ps) - 1;
930 dev_dbg(dev, "LINEINITCNT: %u\n", val);
931 tc358768_write(priv, TC358768_LINEINITCNT, val);
932
933 /* LPTimeCnt > 50ns */
934 val = tc358768_ns_to_cnt(50, hsbyteclk_ps) - 1;
935 lptxcnt = val;
936 dev_dbg(dev, "LPTXTIMECNT: %u\n", val);
937 tc358768_write(priv, TC358768_LPTXTIMECNT, val);
938
939 /* 38ns < TCLK_PREPARE < 95ns */
940 val = tc358768_ns_to_cnt(65, hsbyteclk_ps) - 1;
941 dev_dbg(dev, "TCLK_PREPARECNT %u\n", val);
942 /* TCLK_PREPARE + TCLK_ZERO > 300ns */
943 val2 = tc358768_ns_to_cnt(300 - tc358768_ps_to_ns(2 * ui_ps),
944 hsbyteclk_ps) - 2;
945 dev_dbg(dev, "TCLK_ZEROCNT %u\n", val2);
946 val |= val2 << 8;
947 tc358768_write(priv, TC358768_TCLK_HEADERCNT, val);
948
949 /* TCLK_TRAIL > 60ns AND TEOT <= 105 ns + 12*UI */
950 raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(2 * ui_ps), hsbyteclk_ps) - 5;
951 val = clamp(raw_val, 0, 127);
952 dev_dbg(dev, "TCLK_TRAILCNT: %u\n", val);
953 tc358768_write(priv, TC358768_TCLK_TRAILCNT, val);
954
955 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */
956 val = 50 + tc358768_ps_to_ns(4 * ui_ps);
957 val = tc358768_ns_to_cnt(val, hsbyteclk_ps) - 1;
958 dev_dbg(dev, "THS_PREPARECNT %u\n", val);
959 /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */
960 raw_val = tc358768_ns_to_cnt(145 - tc358768_ps_to_ns(3 * ui_ps), hsbyteclk_ps) - 10;
961 val2 = clamp(raw_val, 0, 127);
962 dev_dbg(dev, "THS_ZEROCNT %u\n", val2);
963 val |= val2 << 8;
964 tc358768_write(priv, TC358768_THS_HEADERCNT, val);
965
966 /* TWAKEUP > 1ms in lptxcnt steps */
967 val = tc358768_ns_to_cnt(1020000, hsbyteclk_ps);
968 val = val / (lptxcnt + 1) - 1;
969 dev_dbg(dev, "TWAKEUP: %u\n", val);
970 tc358768_write(priv, TC358768_TWAKEUP, val);
971
972 /* TCLK_POSTCNT > 60ns + 52*UI */
973 val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(52 * ui_ps),
974 hsbyteclk_ps) - 3;
975 dev_dbg(dev, "TCLK_POSTCNT: %u\n", val);
976 tc358768_write(priv, TC358768_TCLK_POSTCNT, val);
977
978 /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */
979 raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(18 * ui_ps),
980 hsbyteclk_ps) - 4;
981 val = clamp(raw_val, 0, 15);
982 dev_dbg(dev, "THS_TRAILCNT: %u\n", val);
983 tc358768_write(priv, TC358768_THS_TRAILCNT, val);
984
985 val = BIT(0);
986 for (i = 0; i < dsi_dev->lanes; i++)
987 val |= BIT(i + 1);
988 tc358768_write(priv, TC358768_HSTXVREGEN, val);
989
990 tc358768_write(priv, TC358768_TXOPTIONCNTRL,
991 (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0));
992
993 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */
994 val = tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps * 4);
995 val = tc358768_ns_to_cnt(val, hsbyteclk_ps) / 4 - 1;
996 dev_dbg(dev, "TXTAGOCNT: %u\n", val);
997 val2 = tc358768_ns_to_cnt(tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps),
998 hsbyteclk_ps) - 2;
999 dev_dbg(dev, "RXTASURECNT: %u\n", val2);
1000 val = val << 16 | val2;
1001 tc358768_write(priv, TC358768_BTACNTRL1, val);
1002
1003 /* START[0] */
1004 tc358768_write(priv, TC358768_STARTCNTRL, 1);
1005
1006 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
1007 /* Set pulse mode */
1008 tc358768_write(priv, TC358768_DSI_EVENT, 0);
1009
1010 /* vact */
1011 tc358768_write(priv, TC358768_DSI_VACT, vm.vactive);
1012
1013 /* vsw */
1014 tc358768_write(priv, TC358768_DSI_VSW, vm.vsync_len);
1015
1016 /* vbp */
1017 tc358768_write(priv, TC358768_DSI_VBPR, vm.vback_porch);
1018 } else {
1019 /* Set event mode */
1020 tc358768_write(priv, TC358768_DSI_EVENT, 1);
1021
1022 /* vact */
1023 tc358768_write(priv, TC358768_DSI_VACT, vm.vactive);
1024
1025 /* vsw (+ vbp) */
1026 tc358768_write(priv, TC358768_DSI_VSW,
1027 vm.vsync_len + vm.vback_porch);
1028
1029 /* vbp (not used in event mode) */
1030 tc358768_write(priv, TC358768_DSI_VBPR, 0);
1031 }
1032
1033 /* hsw (bytes) */
1034 tc358768_write(priv, TC358768_DSI_HSW, dsi_hsw);
1035
1036 /* hbp (bytes) */
1037 tc358768_write(priv, TC358768_DSI_HBPR, dsi_hbp);
1038
1039 /* hact (bytes) */
1040 tc358768_write(priv, TC358768_DSI_HACT, hact);
1041
1042 /* VSYNC polarity */
1043 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5),
1044 (mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(5) : 0);
1045
1046 /* HSYNC polarity */
1047 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0),
1048 (mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIT(0) : 0);
1049
1050 /* Start DSI Tx */
1051 tc358768_write(priv, TC358768_DSI_START, 0x1);
1052
1053 /* Configure DSI_Control register */
1054 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
1055 val |= TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD |
1056 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS;
1057 tc358768_write(priv, TC358768_DSI_CONFW, val);
1058
1059 val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
1060 val |= (dsi_dev->lanes - 1) << 1;
1061
1062 val |= TC358768_DSI_CONTROL_TXMD;
1063
1064 if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
1065 val |= TC358768_DSI_CONTROL_HSCKMD;
1066
1067 if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
1068 val |= TC358768_DSI_CONTROL_EOTDIS;
1069
1070 tc358768_write(priv, TC358768_DSI_CONFW, val);
1071
1072 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
1073 val |= TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */
1074 tc358768_write(priv, TC358768_DSI_CONFW, val);
1075
1076 ret = tc358768_clear_error(priv);
1077 if (ret) {
1078 dev_err(dev, "Bridge pre_enable failed: %d\n", ret);
1079 tc358768_bridge_disable(bridge);
1080 tc358768_bridge_post_disable(bridge);
1081 }
1082 }
1083
tc358768_bridge_enable(struct drm_bridge * bridge)1084 static void tc358768_bridge_enable(struct drm_bridge *bridge)
1085 {
1086 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
1087 int ret;
1088
1089 if (!priv->enabled) {
1090 dev_err(priv->dev, "Bridge is not enabled\n");
1091 return;
1092 }
1093
1094 /* clear FrmStop and RstPtr */
1095 tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0);
1096
1097 /* set PP_en */
1098 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), BIT(6));
1099
1100 ret = tc358768_clear_error(priv);
1101 if (ret) {
1102 dev_err(priv->dev, "Bridge enable failed: %d\n", ret);
1103 tc358768_bridge_disable(bridge);
1104 tc358768_bridge_post_disable(bridge);
1105 }
1106 }
1107
1108 #define MAX_INPUT_SEL_FORMATS 1
1109
1110 static u32 *
tc358768_atomic_get_input_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,u32 output_fmt,unsigned int * num_input_fmts)1111 tc358768_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
1112 struct drm_bridge_state *bridge_state,
1113 struct drm_crtc_state *crtc_state,
1114 struct drm_connector_state *conn_state,
1115 u32 output_fmt,
1116 unsigned int *num_input_fmts)
1117 {
1118 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
1119 u32 *input_fmts;
1120
1121 *num_input_fmts = 0;
1122
1123 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
1124 GFP_KERNEL);
1125 if (!input_fmts)
1126 return NULL;
1127
1128 switch (priv->pd_lines) {
1129 case 16:
1130 input_fmts[0] = MEDIA_BUS_FMT_RGB565_1X16;
1131 break;
1132 case 18:
1133 input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X18;
1134 break;
1135 default:
1136 case 24:
1137 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
1138 break;
1139 }
1140
1141 *num_input_fmts = MAX_INPUT_SEL_FORMATS;
1142
1143 return input_fmts;
1144 }
1145
1146 static const struct drm_bridge_funcs tc358768_bridge_funcs = {
1147 .attach = tc358768_bridge_attach,
1148 .mode_valid = tc358768_bridge_mode_valid,
1149 .pre_enable = tc358768_bridge_pre_enable,
1150 .enable = tc358768_bridge_enable,
1151 .disable = tc358768_bridge_disable,
1152 .post_disable = tc358768_bridge_post_disable,
1153
1154 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1155 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1156 .atomic_reset = drm_atomic_helper_bridge_reset,
1157 .atomic_get_input_bus_fmts = tc358768_atomic_get_input_bus_fmts,
1158 };
1159
1160 static const struct drm_bridge_timings default_tc358768_timings = {
1161 .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
1162 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
1163 | DRM_BUS_FLAG_DE_HIGH,
1164 };
1165
tc358768_is_reserved_reg(unsigned int reg)1166 static bool tc358768_is_reserved_reg(unsigned int reg)
1167 {
1168 switch (reg) {
1169 case 0x114 ... 0x13f:
1170 case 0x200:
1171 case 0x20c:
1172 case 0x400 ... 0x408:
1173 case 0x41c ... 0x42f:
1174 return true;
1175 default:
1176 return false;
1177 }
1178 }
1179
tc358768_writeable_reg(struct device * dev,unsigned int reg)1180 static bool tc358768_writeable_reg(struct device *dev, unsigned int reg)
1181 {
1182 if (tc358768_is_reserved_reg(reg))
1183 return false;
1184
1185 switch (reg) {
1186 case TC358768_CHIPID:
1187 case TC358768_FIFOSTATUS:
1188 case TC358768_DSITXSTATUS ... (TC358768_DSITXSTATUS + 2):
1189 case TC358768_DSI_CONTROL ... (TC358768_DSI_INT_ENA + 2):
1190 case TC358768_DSICMD_RDFIFO ... (TC358768_DSI_ERR_HALT + 2):
1191 return false;
1192 default:
1193 return true;
1194 }
1195 }
1196
tc358768_readable_reg(struct device * dev,unsigned int reg)1197 static bool tc358768_readable_reg(struct device *dev, unsigned int reg)
1198 {
1199 if (tc358768_is_reserved_reg(reg))
1200 return false;
1201
1202 switch (reg) {
1203 case TC358768_STARTCNTRL:
1204 case TC358768_DSI_CONFW ... (TC358768_DSI_CONFW + 2):
1205 case TC358768_DSI_INT_CLR ... (TC358768_DSI_INT_CLR + 2):
1206 case TC358768_DSI_START ... (TC358768_DSI_START + 2):
1207 case TC358768_DBG_DATA:
1208 return false;
1209 default:
1210 return true;
1211 }
1212 }
1213
1214 static const struct regmap_config tc358768_regmap_config = {
1215 .name = "tc358768",
1216 .reg_bits = 16,
1217 .val_bits = 16,
1218 .max_register = TC358768_DSI_HACT,
1219 .cache_type = REGCACHE_NONE,
1220 .writeable_reg = tc358768_writeable_reg,
1221 .readable_reg = tc358768_readable_reg,
1222 .reg_format_endian = REGMAP_ENDIAN_BIG,
1223 .val_format_endian = REGMAP_ENDIAN_BIG,
1224 };
1225
1226 static const struct i2c_device_id tc358768_i2c_ids[] = {
1227 { "tc358768", 0 },
1228 { "tc358778", 0 },
1229 { }
1230 };
1231 MODULE_DEVICE_TABLE(i2c, tc358768_i2c_ids);
1232
1233 static const struct of_device_id tc358768_of_ids[] = {
1234 { .compatible = "toshiba,tc358768", },
1235 { .compatible = "toshiba,tc358778", },
1236 { }
1237 };
1238 MODULE_DEVICE_TABLE(of, tc358768_of_ids);
1239
tc358768_get_regulators(struct tc358768_priv * priv)1240 static int tc358768_get_regulators(struct tc358768_priv *priv)
1241 {
1242 int i, ret;
1243
1244 for (i = 0; i < ARRAY_SIZE(priv->supplies); ++i)
1245 priv->supplies[i].supply = tc358768_supplies[i];
1246
1247 ret = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(priv->supplies),
1248 priv->supplies);
1249 if (ret < 0)
1250 dev_err(priv->dev, "failed to get regulators: %d\n", ret);
1251
1252 return ret;
1253 }
1254
tc358768_i2c_probe(struct i2c_client * client)1255 static int tc358768_i2c_probe(struct i2c_client *client)
1256 {
1257 struct tc358768_priv *priv;
1258 struct device *dev = &client->dev;
1259 struct device_node *np = dev->of_node;
1260 int ret;
1261
1262 if (!np)
1263 return -ENODEV;
1264
1265 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1266 if (!priv)
1267 return -ENOMEM;
1268
1269 dev_set_drvdata(dev, priv);
1270 priv->dev = dev;
1271
1272 ret = tc358768_get_regulators(priv);
1273 if (ret)
1274 return ret;
1275
1276 priv->refclk = devm_clk_get(dev, "refclk");
1277 if (IS_ERR(priv->refclk))
1278 return PTR_ERR(priv->refclk);
1279
1280 /*
1281 * RESX is low active, to disable tc358768 initially (keep in reset)
1282 * the gpio line must be LOW. This is the ASSERTED state of
1283 * GPIO_ACTIVE_LOW (GPIOD_OUT_HIGH == ASSERTED).
1284 */
1285 priv->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1286 GPIOD_OUT_HIGH);
1287 if (IS_ERR(priv->reset_gpio))
1288 return PTR_ERR(priv->reset_gpio);
1289
1290 priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config);
1291 if (IS_ERR(priv->regmap)) {
1292 dev_err(dev, "Failed to init regmap\n");
1293 return PTR_ERR(priv->regmap);
1294 }
1295
1296 priv->dsi_host.dev = dev;
1297 priv->dsi_host.ops = &tc358768_dsi_host_ops;
1298
1299 priv->bridge.funcs = &tc358768_bridge_funcs;
1300 priv->bridge.timings = &default_tc358768_timings;
1301 priv->bridge.of_node = np;
1302
1303 i2c_set_clientdata(client, priv);
1304
1305 return mipi_dsi_host_register(&priv->dsi_host);
1306 }
1307
tc358768_i2c_remove(struct i2c_client * client)1308 static void tc358768_i2c_remove(struct i2c_client *client)
1309 {
1310 struct tc358768_priv *priv = i2c_get_clientdata(client);
1311
1312 mipi_dsi_host_unregister(&priv->dsi_host);
1313 }
1314
1315 static struct i2c_driver tc358768_driver = {
1316 .driver = {
1317 .name = "tc358768",
1318 .of_match_table = tc358768_of_ids,
1319 },
1320 .id_table = tc358768_i2c_ids,
1321 .probe = tc358768_i2c_probe,
1322 .remove = tc358768_i2c_remove,
1323 };
1324 module_i2c_driver(tc358768_driver);
1325
1326 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
1327 MODULE_DESCRIPTION("TC358768AXBG/TC358778XBG DSI bridge");
1328 MODULE_LICENSE("GPL v2");
1329