1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * tc358767 eDP bridge driver 4 * 5 * Copyright (C) 2016 CogentEmbedded Inc 6 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com> 7 * 8 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de> 9 * 10 * Copyright (C) 2016 Zodiac Inflight Innovations 11 * 12 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c 13 * 14 * Copyright (C) 2012 Texas Instruments 15 * Author: Rob Clark <robdclark@gmail.com> 16 */ 17 18 #include <linux/clk.h> 19 #include <linux/device.h> 20 #include <linux/gpio/consumer.h> 21 #include <linux/i2c.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/regmap.h> 25 #include <linux/slab.h> 26 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_dp_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_of.h> 31 #include <drm/drm_panel.h> 32 #include <drm/drm_probe_helper.h> 33 34 /* Registers */ 35 36 /* Display Parallel Interface */ 37 #define DPIPXLFMT 0x0440 38 #define VS_POL_ACTIVE_LOW (1 << 10) 39 #define HS_POL_ACTIVE_LOW (1 << 9) 40 #define DE_POL_ACTIVE_HIGH (0 << 8) 41 #define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */ 42 #define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */ 43 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */ 44 #define DPI_BPP_RGB888 (0 << 0) 45 #define DPI_BPP_RGB666 (1 << 0) 46 #define DPI_BPP_RGB565 (2 << 0) 47 48 /* Video Path */ 49 #define VPCTRL0 0x0450 50 #define OPXLFMT_RGB666 (0 << 8) 51 #define OPXLFMT_RGB888 (1 << 8) 52 #define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */ 53 #define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */ 54 #define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */ 55 #define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */ 56 #define HTIM01 0x0454 57 #define HTIM02 0x0458 58 #define VTIM01 0x045c 59 #define VTIM02 0x0460 60 #define VFUEN0 0x0464 61 #define VFUEN BIT(0) /* Video Frame Timing Upload */ 62 63 /* System */ 64 #define TC_IDREG 0x0500 65 #define SYSSTAT 0x0508 66 #define SYSCTRL 0x0510 67 #define DP0_AUDSRC_NO_INPUT (0 << 3) 68 #define DP0_AUDSRC_I2S_RX (1 << 3) 69 #define DP0_VIDSRC_NO_INPUT (0 << 0) 70 #define DP0_VIDSRC_DSI_RX (1 << 0) 71 #define DP0_VIDSRC_DPI_RX (2 << 0) 72 #define DP0_VIDSRC_COLOR_BAR (3 << 0) 73 #define GPIOM 0x0540 74 #define GPIOC 0x0544 75 #define GPIOO 0x0548 76 #define GPIOI 0x054c 77 #define INTCTL_G 0x0560 78 #define INTSTS_G 0x0564 79 80 #define INT_SYSERR BIT(16) 81 #define INT_GPIO_H(x) (1 << (x == 0 ? 2 : 10)) 82 #define INT_GPIO_LC(x) (1 << (x == 0 ? 3 : 11)) 83 84 #define INT_GP0_LCNT 0x0584 85 #define INT_GP1_LCNT 0x0588 86 87 /* Control */ 88 #define DP0CTL 0x0600 89 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */ 90 #define EF_EN BIT(5) /* Enable Enhanced Framing */ 91 #define VID_EN BIT(1) /* Video transmission enable */ 92 #define DP_EN BIT(0) /* Enable DPTX function */ 93 94 /* Clocks */ 95 #define DP0_VIDMNGEN0 0x0610 96 #define DP0_VIDMNGEN1 0x0614 97 #define DP0_VMNGENSTATUS 0x0618 98 99 /* Main Channel */ 100 #define DP0_SECSAMPLE 0x0640 101 #define DP0_VIDSYNCDELAY 0x0644 102 #define DP0_TOTALVAL 0x0648 103 #define DP0_STARTVAL 0x064c 104 #define DP0_ACTIVEVAL 0x0650 105 #define DP0_SYNCVAL 0x0654 106 #define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15) 107 #define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31) 108 #define DP0_MISC 0x0658 109 #define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */ 110 #define BPC_6 (0 << 5) 111 #define BPC_8 (1 << 5) 112 113 /* AUX channel */ 114 #define DP0_AUXCFG0 0x0660 115 #define DP0_AUXCFG1 0x0664 116 #define AUX_RX_FILTER_EN BIT(16) 117 118 #define DP0_AUXADDR 0x0668 119 #define DP0_AUXWDATA(i) (0x066c + (i) * 4) 120 #define DP0_AUXRDATA(i) (0x067c + (i) * 4) 121 #define DP0_AUXSTATUS 0x068c 122 #define AUX_STATUS_MASK 0xf0 123 #define AUX_STATUS_SHIFT 4 124 #define AUX_TIMEOUT BIT(1) 125 #define AUX_BUSY BIT(0) 126 #define DP0_AUXI2CADR 0x0698 127 128 /* Link Training */ 129 #define DP0_SRCCTRL 0x06a0 130 #define DP0_SRCCTRL_SCRMBLDIS BIT(13) 131 #define DP0_SRCCTRL_EN810B BIT(12) 132 #define DP0_SRCCTRL_NOTP (0 << 8) 133 #define DP0_SRCCTRL_TP1 (1 << 8) 134 #define DP0_SRCCTRL_TP2 (2 << 8) 135 #define DP0_SRCCTRL_LANESKEW BIT(7) 136 #define DP0_SRCCTRL_SSCG BIT(3) 137 #define DP0_SRCCTRL_LANES_1 (0 << 2) 138 #define DP0_SRCCTRL_LANES_2 (1 << 2) 139 #define DP0_SRCCTRL_BW27 (1 << 1) 140 #define DP0_SRCCTRL_BW162 (0 << 1) 141 #define DP0_SRCCTRL_AUTOCORRECT BIT(0) 142 #define DP0_LTSTAT 0x06d0 143 #define LT_LOOPDONE BIT(13) 144 #define LT_STATUS_MASK (0x1f << 8) 145 #define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4) 146 #define LT_INTERLANE_ALIGN_DONE BIT(3) 147 #define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS) 148 #define DP0_SNKLTCHGREQ 0x06d4 149 #define DP0_LTLOOPCTRL 0x06d8 150 #define DP0_SNKLTCTRL 0x06e4 151 152 #define DP1_SRCCTRL 0x07a0 153 154 /* PHY */ 155 #define DP_PHY_CTRL 0x0800 156 #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */ 157 #define BGREN BIT(25) /* AUX PHY BGR Enable */ 158 #define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */ 159 #define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */ 160 #define PHY_RDY BIT(16) /* PHY Main Channels Ready */ 161 #define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */ 162 #define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */ 163 #define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */ 164 #define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */ 165 166 /* PLL */ 167 #define DP0_PLLCTRL 0x0900 168 #define DP1_PLLCTRL 0x0904 /* not defined in DS */ 169 #define PXL_PLLCTRL 0x0908 170 #define PLLUPDATE BIT(2) 171 #define PLLBYP BIT(1) 172 #define PLLEN BIT(0) 173 #define PXL_PLLPARAM 0x0914 174 #define IN_SEL_REFCLK (0 << 14) 175 #define SYS_PLLPARAM 0x0918 176 #define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */ 177 #define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */ 178 #define REF_FREQ_26M (2 << 8) /* 26 MHz */ 179 #define REF_FREQ_13M (3 << 8) /* 13 MHz */ 180 #define SYSCLK_SEL_LSCLK (0 << 4) 181 #define LSCLK_DIV_1 (0 << 0) 182 #define LSCLK_DIV_2 (1 << 0) 183 184 /* Test & Debug */ 185 #define TSTCTL 0x0a00 186 #define PLL_DBG 0x0a04 187 188 static bool tc_test_pattern; 189 module_param_named(test, tc_test_pattern, bool, 0644); 190 191 struct tc_edp_link { 192 struct drm_dp_link base; 193 u8 assr; 194 bool scrambler_dis; 195 bool spread; 196 }; 197 198 struct tc_data { 199 struct device *dev; 200 struct regmap *regmap; 201 struct drm_dp_aux aux; 202 203 struct drm_bridge bridge; 204 struct drm_connector connector; 205 struct drm_panel *panel; 206 207 /* link settings */ 208 struct tc_edp_link link; 209 210 /* display edid */ 211 struct edid *edid; 212 /* current mode */ 213 struct drm_display_mode mode; 214 215 u32 rev; 216 u8 assr; 217 218 struct gpio_desc *sd_gpio; 219 struct gpio_desc *reset_gpio; 220 struct clk *refclk; 221 222 /* do we have IRQ */ 223 bool have_irq; 224 225 /* HPD pin number (0 or 1) or -ENODEV */ 226 int hpd_pin; 227 }; 228 229 static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a) 230 { 231 return container_of(a, struct tc_data, aux); 232 } 233 234 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b) 235 { 236 return container_of(b, struct tc_data, bridge); 237 } 238 239 static inline struct tc_data *connector_to_tc(struct drm_connector *c) 240 { 241 return container_of(c, struct tc_data, connector); 242 } 243 244 /* Simple macros to avoid repeated error checks */ 245 #define tc_write(reg, var) \ 246 do { \ 247 ret = regmap_write(tc->regmap, reg, var); \ 248 if (ret) \ 249 goto err; \ 250 } while (0) 251 #define tc_read(reg, var) \ 252 do { \ 253 ret = regmap_read(tc->regmap, reg, var); \ 254 if (ret) \ 255 goto err; \ 256 } while (0) 257 258 static inline int tc_poll_timeout(struct regmap *map, unsigned int addr, 259 unsigned int cond_mask, 260 unsigned int cond_value, 261 unsigned long sleep_us, u64 timeout_us) 262 { 263 ktime_t timeout = ktime_add_us(ktime_get(), timeout_us); 264 unsigned int val; 265 int ret; 266 267 for (;;) { 268 ret = regmap_read(map, addr, &val); 269 if (ret) 270 break; 271 if ((val & cond_mask) == cond_value) 272 break; 273 if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) { 274 ret = regmap_read(map, addr, &val); 275 break; 276 } 277 if (sleep_us) 278 usleep_range((sleep_us >> 2) + 1, sleep_us); 279 } 280 return ret ?: (((val & cond_mask) == cond_value) ? 0 : -ETIMEDOUT); 281 } 282 283 static int tc_aux_wait_busy(struct tc_data *tc, unsigned int timeout_ms) 284 { 285 return tc_poll_timeout(tc->regmap, DP0_AUXSTATUS, AUX_BUSY, 0, 286 1000, 1000 * timeout_ms); 287 } 288 289 static int tc_aux_get_status(struct tc_data *tc, u8 *reply) 290 { 291 int ret; 292 u32 value; 293 294 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &value); 295 if (ret < 0) 296 return ret; 297 298 if (value & AUX_BUSY) { 299 dev_err(tc->dev, "aux busy!\n"); 300 return -EBUSY; 301 } 302 303 if (value & AUX_TIMEOUT) { 304 dev_err(tc->dev, "aux access timeout!\n"); 305 return -ETIMEDOUT; 306 } 307 308 *reply = (value & AUX_STATUS_MASK) >> AUX_STATUS_SHIFT; 309 return 0; 310 } 311 312 static ssize_t tc_aux_transfer(struct drm_dp_aux *aux, 313 struct drm_dp_aux_msg *msg) 314 { 315 struct tc_data *tc = aux_to_tc(aux); 316 size_t size = min_t(size_t, 8, msg->size); 317 u8 request = msg->request & ~DP_AUX_I2C_MOT; 318 u8 *buf = msg->buffer; 319 u32 tmp = 0; 320 int i = 0; 321 int ret; 322 323 if (size == 0) 324 return 0; 325 326 ret = tc_aux_wait_busy(tc, 100); 327 if (ret) 328 goto err; 329 330 if (request == DP_AUX_I2C_WRITE || request == DP_AUX_NATIVE_WRITE) { 331 /* Store data */ 332 while (i < size) { 333 if (request == DP_AUX_NATIVE_WRITE) 334 tmp = tmp | (buf[i] << (8 * (i & 0x3))); 335 else 336 tmp = (tmp << 8) | buf[i]; 337 i++; 338 if (((i % 4) == 0) || (i == size)) { 339 tc_write(DP0_AUXWDATA((i - 1) >> 2), tmp); 340 tmp = 0; 341 } 342 } 343 } else if (request != DP_AUX_I2C_READ && 344 request != DP_AUX_NATIVE_READ) { 345 return -EINVAL; 346 } 347 348 /* Store address */ 349 tc_write(DP0_AUXADDR, msg->address); 350 /* Start transfer */ 351 tc_write(DP0_AUXCFG0, ((size - 1) << 8) | request); 352 353 ret = tc_aux_wait_busy(tc, 100); 354 if (ret) 355 goto err; 356 357 ret = tc_aux_get_status(tc, &msg->reply); 358 if (ret) 359 goto err; 360 361 if (request == DP_AUX_I2C_READ || request == DP_AUX_NATIVE_READ) { 362 /* Read data */ 363 while (i < size) { 364 if ((i % 4) == 0) 365 tc_read(DP0_AUXRDATA(i >> 2), &tmp); 366 buf[i] = tmp & 0xff; 367 tmp = tmp >> 8; 368 i++; 369 } 370 } 371 372 return size; 373 err: 374 return ret; 375 } 376 377 static const char * const training_pattern1_errors[] = { 378 "No errors", 379 "Aux write error", 380 "Aux read error", 381 "Max voltage reached error", 382 "Loop counter expired error", 383 "res", "res", "res" 384 }; 385 386 static const char * const training_pattern2_errors[] = { 387 "No errors", 388 "Aux write error", 389 "Aux read error", 390 "Clock recovery failed error", 391 "Loop counter expired error", 392 "res", "res", "res" 393 }; 394 395 static u32 tc_srcctrl(struct tc_data *tc) 396 { 397 /* 398 * No training pattern, skew lane 1 data by two LSCLK cycles with 399 * respect to lane 0 data, AutoCorrect Mode = 0 400 */ 401 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B; 402 403 if (tc->link.scrambler_dis) 404 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */ 405 if (tc->link.spread) 406 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */ 407 if (tc->link.base.num_lanes == 2) 408 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */ 409 if (tc->link.base.rate != 162000) 410 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */ 411 return reg; 412 } 413 414 static void tc_wait_pll_lock(struct tc_data *tc) 415 { 416 /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */ 417 usleep_range(3000, 6000); 418 } 419 420 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) 421 { 422 int ret; 423 int i_pre, best_pre = 1; 424 int i_post, best_post = 1; 425 int div, best_div = 1; 426 int mul, best_mul = 1; 427 int delta, best_delta; 428 int ext_div[] = {1, 2, 3, 5, 7}; 429 int best_pixelclock = 0; 430 int vco_hi = 0; 431 432 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock, 433 refclk); 434 best_delta = pixelclock; 435 /* Loop over all possible ext_divs, skipping invalid configurations */ 436 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) { 437 /* 438 * refclk / ext_pre_div should be in the 1 to 200 MHz range. 439 * We don't allow any refclk > 200 MHz, only check lower bounds. 440 */ 441 if (refclk / ext_div[i_pre] < 1000000) 442 continue; 443 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) { 444 for (div = 1; div <= 16; div++) { 445 u32 clk; 446 u64 tmp; 447 448 tmp = pixelclock * ext_div[i_pre] * 449 ext_div[i_post] * div; 450 do_div(tmp, refclk); 451 mul = tmp; 452 453 /* Check limits */ 454 if ((mul < 1) || (mul > 128)) 455 continue; 456 457 clk = (refclk / ext_div[i_pre] / div) * mul; 458 /* 459 * refclk * mul / (ext_pre_div * pre_div) 460 * should be in the 150 to 650 MHz range 461 */ 462 if ((clk > 650000000) || (clk < 150000000)) 463 continue; 464 465 clk = clk / ext_div[i_post]; 466 delta = clk - pixelclock; 467 468 if (abs(delta) < abs(best_delta)) { 469 best_pre = i_pre; 470 best_post = i_post; 471 best_div = div; 472 best_mul = mul; 473 best_delta = delta; 474 best_pixelclock = clk; 475 } 476 } 477 } 478 } 479 if (best_pixelclock == 0) { 480 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n", 481 pixelclock); 482 return -EINVAL; 483 } 484 485 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock, 486 best_delta); 487 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk, 488 ext_div[best_pre], best_div, best_mul, ext_div[best_post]); 489 490 /* if VCO >= 300 MHz */ 491 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000) 492 vco_hi = 1; 493 /* see DS */ 494 if (best_div == 16) 495 best_div = 0; 496 if (best_mul == 128) 497 best_mul = 0; 498 499 /* Power up PLL and switch to bypass */ 500 tc_write(PXL_PLLCTRL, PLLBYP | PLLEN); 501 502 tc_write(PXL_PLLPARAM, 503 (vco_hi << 24) | /* For PLL VCO >= 300 MHz = 1 */ 504 (ext_div[best_pre] << 20) | /* External Pre-divider */ 505 (ext_div[best_post] << 16) | /* External Post-divider */ 506 IN_SEL_REFCLK | /* Use RefClk as PLL input */ 507 (best_div << 8) | /* Divider for PLL RefClk */ 508 (best_mul << 0)); /* Multiplier for PLL */ 509 510 /* Force PLL parameter update and disable bypass */ 511 tc_write(PXL_PLLCTRL, PLLUPDATE | PLLEN); 512 513 tc_wait_pll_lock(tc); 514 515 return 0; 516 err: 517 return ret; 518 } 519 520 static int tc_pxl_pll_dis(struct tc_data *tc) 521 { 522 /* Enable PLL bypass, power down PLL */ 523 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP); 524 } 525 526 static int tc_stream_clock_calc(struct tc_data *tc) 527 { 528 int ret; 529 /* 530 * If the Stream clock and Link Symbol clock are 531 * asynchronous with each other, the value of M changes over 532 * time. This way of generating link clock and stream 533 * clock is called Asynchronous Clock mode. The value M 534 * must change while the value N stays constant. The 535 * value of N in this Asynchronous Clock mode must be set 536 * to 2^15 or 32,768. 537 * 538 * LSCLK = 1/10 of high speed link clock 539 * 540 * f_STRMCLK = M/N * f_LSCLK 541 * M/N = f_STRMCLK / f_LSCLK 542 * 543 */ 544 tc_write(DP0_VIDMNGEN1, 32768); 545 546 return 0; 547 err: 548 return ret; 549 } 550 551 static int tc_aux_link_setup(struct tc_data *tc) 552 { 553 unsigned long rate; 554 u32 value; 555 int ret; 556 557 rate = clk_get_rate(tc->refclk); 558 switch (rate) { 559 case 38400000: 560 value = REF_FREQ_38M4; 561 break; 562 case 26000000: 563 value = REF_FREQ_26M; 564 break; 565 case 19200000: 566 value = REF_FREQ_19M2; 567 break; 568 case 13000000: 569 value = REF_FREQ_13M; 570 break; 571 default: 572 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate); 573 return -EINVAL; 574 } 575 576 /* Setup DP-PHY / PLL */ 577 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; 578 tc_write(SYS_PLLPARAM, value); 579 580 tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | PHY_A0_EN); 581 582 /* 583 * Initially PLLs are in bypass. Force PLL parameter update, 584 * disable PLL bypass, enable PLL 585 */ 586 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN); 587 tc_wait_pll_lock(tc); 588 589 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN); 590 tc_wait_pll_lock(tc); 591 592 ret = tc_poll_timeout(tc->regmap, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 593 1000); 594 if (ret == -ETIMEDOUT) { 595 dev_err(tc->dev, "Timeout waiting for PHY to become ready"); 596 return ret; 597 } else if (ret) { 598 goto err; 599 } 600 601 /* Setup AUX link */ 602 tc_write(DP0_AUXCFG1, AUX_RX_FILTER_EN | 603 (0x06 << 8) | /* Aux Bit Period Calculator Threshold */ 604 (0x3f << 0)); /* Aux Response Timeout Timer */ 605 606 return 0; 607 err: 608 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret); 609 return ret; 610 } 611 612 static int tc_get_display_props(struct tc_data *tc) 613 { 614 int ret; 615 /* temp buffer */ 616 u8 tmp[8]; 617 618 /* Read DP Rx Link Capability */ 619 ret = drm_dp_link_probe(&tc->aux, &tc->link.base); 620 if (ret < 0) 621 goto err_dpcd_read; 622 if (tc->link.base.rate != 162000 && tc->link.base.rate != 270000) { 623 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n"); 624 tc->link.base.rate = 270000; 625 } 626 627 if (tc->link.base.num_lanes > 2) { 628 dev_dbg(tc->dev, "Falling to 2 lanes\n"); 629 tc->link.base.num_lanes = 2; 630 } 631 632 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, tmp); 633 if (ret < 0) 634 goto err_dpcd_read; 635 tc->link.spread = tmp[0] & DP_MAX_DOWNSPREAD_0_5; 636 637 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, tmp); 638 if (ret < 0) 639 goto err_dpcd_read; 640 641 tc->link.scrambler_dis = false; 642 /* read assr */ 643 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, tmp); 644 if (ret < 0) 645 goto err_dpcd_read; 646 tc->link.assr = tmp[0] & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; 647 648 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n", 649 tc->link.base.revision >> 4, tc->link.base.revision & 0x0f, 650 (tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps", 651 tc->link.base.num_lanes, 652 (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ? 653 "enhanced" : "non-enhanced"); 654 dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n", 655 tc->link.spread ? "0.5%" : "0.0%", 656 tc->link.scrambler_dis ? "disabled" : "enabled"); 657 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n", 658 tc->link.assr, tc->assr); 659 660 return 0; 661 662 err_dpcd_read: 663 dev_err(tc->dev, "failed to read DPCD: %d\n", ret); 664 return ret; 665 } 666 667 static int tc_set_video_mode(struct tc_data *tc, 668 const struct drm_display_mode *mode) 669 { 670 int ret; 671 int vid_sync_dly; 672 int max_tu_symbol; 673 674 int left_margin = mode->htotal - mode->hsync_end; 675 int right_margin = mode->hsync_start - mode->hdisplay; 676 int hsync_len = mode->hsync_end - mode->hsync_start; 677 int upper_margin = mode->vtotal - mode->vsync_end; 678 int lower_margin = mode->vsync_start - mode->vdisplay; 679 int vsync_len = mode->vsync_end - mode->vsync_start; 680 681 /* 682 * Recommended maximum number of symbols transferred in a transfer unit: 683 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size, 684 * (output active video bandwidth in bytes)) 685 * Must be less than tu_size. 686 */ 687 max_tu_symbol = TU_SIZE_RECOMMENDED - 1; 688 689 dev_dbg(tc->dev, "set mode %dx%d\n", 690 mode->hdisplay, mode->vdisplay); 691 dev_dbg(tc->dev, "H margin %d,%d sync %d\n", 692 left_margin, right_margin, hsync_len); 693 dev_dbg(tc->dev, "V margin %d,%d sync %d\n", 694 upper_margin, lower_margin, vsync_len); 695 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal); 696 697 698 /* 699 * LCD Ctl Frame Size 700 * datasheet is not clear of vsdelay in case of DPI 701 * assume we do not need any delay when DPI is a source of 702 * sync signals 703 */ 704 tc_write(VPCTRL0, (0 << 20) /* VSDELAY */ | 705 OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED); 706 tc_write(HTIM01, (ALIGN(left_margin, 2) << 16) | /* H back porch */ 707 (ALIGN(hsync_len, 2) << 0)); /* Hsync */ 708 tc_write(HTIM02, (ALIGN(right_margin, 2) << 16) | /* H front porch */ 709 (ALIGN(mode->hdisplay, 2) << 0)); /* width */ 710 tc_write(VTIM01, (upper_margin << 16) | /* V back porch */ 711 (vsync_len << 0)); /* Vsync */ 712 tc_write(VTIM02, (lower_margin << 16) | /* V front porch */ 713 (mode->vdisplay << 0)); /* height */ 714 tc_write(VFUEN0, VFUEN); /* update settings */ 715 716 /* Test pattern settings */ 717 tc_write(TSTCTL, 718 (120 << 24) | /* Red Color component value */ 719 (20 << 16) | /* Green Color component value */ 720 (99 << 8) | /* Blue Color component value */ 721 (1 << 4) | /* Enable I2C Filter */ 722 (2 << 0) | /* Color bar Mode */ 723 0); 724 725 /* DP Main Stream Attributes */ 726 vid_sync_dly = hsync_len + left_margin + mode->hdisplay; 727 tc_write(DP0_VIDSYNCDELAY, 728 (max_tu_symbol << 16) | /* thresh_dly */ 729 (vid_sync_dly << 0)); 730 731 tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal)); 732 733 tc_write(DP0_STARTVAL, 734 ((upper_margin + vsync_len) << 16) | 735 ((left_margin + hsync_len) << 0)); 736 737 tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay)); 738 739 tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0) | 740 ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? SYNCVAL_HS_POL_ACTIVE_LOW : 0) | 741 ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? SYNCVAL_VS_POL_ACTIVE_LOW : 0)); 742 743 tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW | 744 DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888); 745 746 tc_write(DP0_MISC, (max_tu_symbol << 23) | (TU_SIZE_RECOMMENDED << 16) | 747 BPC_8); 748 749 return 0; 750 err: 751 return ret; 752 } 753 754 static int tc_wait_link_training(struct tc_data *tc) 755 { 756 u32 timeout = 1000; 757 u32 value; 758 int ret; 759 760 do { 761 udelay(1); 762 tc_read(DP0_LTSTAT, &value); 763 } while ((!(value & LT_LOOPDONE)) && (--timeout)); 764 765 if (timeout == 0) { 766 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n"); 767 return -ETIMEDOUT; 768 } 769 770 return (value >> 8) & 0x7; 771 772 err: 773 return ret; 774 } 775 776 static int tc_main_link_enable(struct tc_data *tc) 777 { 778 struct drm_dp_aux *aux = &tc->aux; 779 struct device *dev = tc->dev; 780 unsigned int rate; 781 u32 dp_phy_ctrl; 782 int timeout; 783 u32 value; 784 int ret; 785 u8 tmp[8]; 786 787 dev_dbg(tc->dev, "link enable\n"); 788 789 tc_read(DP0CTL, &value); 790 if (WARN_ON(value & DP_EN)) 791 tc_write(DP0CTL, 0); 792 793 tc_write(DP0_SRCCTRL, tc_srcctrl(tc)); 794 /* SSCG and BW27 on DP1 must be set to the same as on DP0 */ 795 tc_write(DP1_SRCCTRL, 796 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) | 797 ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0)); 798 799 rate = clk_get_rate(tc->refclk); 800 switch (rate) { 801 case 38400000: 802 value = REF_FREQ_38M4; 803 break; 804 case 26000000: 805 value = REF_FREQ_26M; 806 break; 807 case 19200000: 808 value = REF_FREQ_19M2; 809 break; 810 case 13000000: 811 value = REF_FREQ_13M; 812 break; 813 default: 814 return -EINVAL; 815 } 816 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; 817 tc_write(SYS_PLLPARAM, value); 818 819 /* Setup Main Link */ 820 dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN; 821 if (tc->link.base.num_lanes == 2) 822 dp_phy_ctrl |= PHY_2LANE; 823 tc_write(DP_PHY_CTRL, dp_phy_ctrl); 824 825 /* PLL setup */ 826 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN); 827 tc_wait_pll_lock(tc); 828 829 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN); 830 tc_wait_pll_lock(tc); 831 832 /* Reset/Enable Main Links */ 833 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST; 834 tc_write(DP_PHY_CTRL, dp_phy_ctrl); 835 usleep_range(100, 200); 836 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST); 837 tc_write(DP_PHY_CTRL, dp_phy_ctrl); 838 839 timeout = 1000; 840 do { 841 tc_read(DP_PHY_CTRL, &value); 842 udelay(1); 843 } while ((!(value & PHY_RDY)) && (--timeout)); 844 845 if (timeout == 0) { 846 dev_err(dev, "timeout waiting for phy become ready"); 847 return -ETIMEDOUT; 848 } 849 850 /* Set misc: 8 bits per color */ 851 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8); 852 if (ret) 853 goto err; 854 855 /* 856 * ASSR mode 857 * on TC358767 side ASSR configured through strap pin 858 * seems there is no way to change this setting from SW 859 * 860 * check is tc configured for same mode 861 */ 862 if (tc->assr != tc->link.assr) { 863 dev_dbg(dev, "Trying to set display to ASSR: %d\n", 864 tc->assr); 865 /* try to set ASSR on display side */ 866 tmp[0] = tc->assr; 867 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]); 868 if (ret < 0) 869 goto err_dpcd_read; 870 /* read back */ 871 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp); 872 if (ret < 0) 873 goto err_dpcd_read; 874 875 if (tmp[0] != tc->assr) { 876 dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n", 877 tc->assr); 878 /* trying with disabled scrambler */ 879 tc->link.scrambler_dis = true; 880 } 881 } 882 883 /* Setup Link & DPRx Config for Training */ 884 ret = drm_dp_link_configure(aux, &tc->link.base); 885 if (ret < 0) 886 goto err_dpcd_write; 887 888 /* DOWNSPREAD_CTRL */ 889 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00; 890 /* MAIN_LINK_CHANNEL_CODING_SET */ 891 tmp[1] = DP_SET_ANSI_8B10B; 892 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2); 893 if (ret < 0) 894 goto err_dpcd_write; 895 896 /* Reset voltage-swing & pre-emphasis */ 897 tmp[0] = tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 898 DP_TRAIN_PRE_EMPH_LEVEL_0; 899 ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2); 900 if (ret < 0) 901 goto err_dpcd_write; 902 903 /* Clock-Recovery */ 904 905 /* Set DPCD 0x102 for Training Pattern 1 */ 906 tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | 907 DP_TRAINING_PATTERN_1); 908 909 tc_write(DP0_LTLOOPCTRL, 910 (15 << 28) | /* Defer Iteration Count */ 911 (15 << 24) | /* Loop Iteration Count */ 912 (0xd << 0)); /* Loop Timer Delay */ 913 914 tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | 915 DP0_SRCCTRL_AUTOCORRECT | DP0_SRCCTRL_TP1); 916 917 /* Enable DP0 to start Link Training */ 918 tc_write(DP0CTL, 919 ((tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ? EF_EN : 0) | 920 DP_EN); 921 922 /* wait */ 923 ret = tc_wait_link_training(tc); 924 if (ret < 0) 925 goto err; 926 927 if (ret) { 928 dev_err(tc->dev, "Link training phase 1 failed: %s\n", 929 training_pattern1_errors[ret]); 930 ret = -ENODEV; 931 goto err; 932 } 933 934 /* Channel Equalization */ 935 936 /* Set DPCD 0x102 for Training Pattern 2 */ 937 tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | 938 DP_TRAINING_PATTERN_2); 939 940 tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | 941 DP0_SRCCTRL_AUTOCORRECT | DP0_SRCCTRL_TP2); 942 943 /* wait */ 944 ret = tc_wait_link_training(tc); 945 if (ret < 0) 946 goto err; 947 948 if (ret) { 949 dev_err(tc->dev, "Link training phase 2 failed: %s\n", 950 training_pattern2_errors[ret]); 951 ret = -ENODEV; 952 goto err; 953 } 954 955 /* 956 * Toshiba's documentation suggests to first clear DPCD 0x102, then 957 * clear the training pattern bit in DP0_SRCCTRL. Testing shows 958 * that the link sometimes drops if those steps are done in that order, 959 * but if the steps are done in reverse order, the link stays up. 960 * 961 * So we do the steps differently than documented here. 962 */ 963 964 /* Clear Training Pattern, set AutoCorrect Mode = 1 */ 965 tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_AUTOCORRECT); 966 967 /* Clear DPCD 0x102 */ 968 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */ 969 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00; 970 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]); 971 if (ret < 0) 972 goto err_dpcd_write; 973 974 /* Check link status */ 975 ret = drm_dp_dpcd_read_link_status(aux, tmp); 976 if (ret < 0) 977 goto err_dpcd_read; 978 979 ret = 0; 980 981 value = tmp[0] & DP_CHANNEL_EQ_BITS; 982 983 if (value != DP_CHANNEL_EQ_BITS) { 984 dev_err(tc->dev, "Lane 0 failed: %x\n", value); 985 ret = -ENODEV; 986 } 987 988 if (tc->link.base.num_lanes == 2) { 989 value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS; 990 991 if (value != DP_CHANNEL_EQ_BITS) { 992 dev_err(tc->dev, "Lane 1 failed: %x\n", value); 993 ret = -ENODEV; 994 } 995 996 if (!(tmp[2] & DP_INTERLANE_ALIGN_DONE)) { 997 dev_err(tc->dev, "Interlane align failed\n"); 998 ret = -ENODEV; 999 } 1000 } 1001 1002 if (ret) { 1003 dev_err(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[0]); 1004 dev_err(dev, "0x0203 LANE2_3_STATUS 0x%02x\n", tmp[1]); 1005 dev_err(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", tmp[2]); 1006 dev_err(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[3]); 1007 dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n", tmp[4]); 1008 dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3: 0x%02x\n", tmp[5]); 1009 goto err; 1010 } 1011 1012 return 0; 1013 err_dpcd_read: 1014 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret); 1015 return ret; 1016 err_dpcd_write: 1017 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret); 1018 err: 1019 return ret; 1020 } 1021 1022 static int tc_main_link_disable(struct tc_data *tc) 1023 { 1024 int ret; 1025 1026 dev_dbg(tc->dev, "link disable\n"); 1027 1028 tc_write(DP0_SRCCTRL, 0); 1029 tc_write(DP0CTL, 0); 1030 1031 return 0; 1032 err: 1033 return ret; 1034 } 1035 1036 static int tc_stream_enable(struct tc_data *tc) 1037 { 1038 int ret; 1039 u32 value; 1040 1041 dev_dbg(tc->dev, "enable video stream\n"); 1042 1043 /* PXL PLL setup */ 1044 if (tc_test_pattern) { 1045 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), 1046 1000 * tc->mode.clock); 1047 if (ret) 1048 goto err; 1049 } 1050 1051 ret = tc_set_video_mode(tc, &tc->mode); 1052 if (ret) 1053 return ret; 1054 1055 /* Set M/N */ 1056 ret = tc_stream_clock_calc(tc); 1057 if (ret) 1058 return ret; 1059 1060 value = VID_MN_GEN | DP_EN; 1061 if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 1062 value |= EF_EN; 1063 tc_write(DP0CTL, value); 1064 /* 1065 * VID_EN assertion should be delayed by at least N * LSCLK 1066 * cycles from the time VID_MN_GEN is enabled in order to 1067 * generate stable values for VID_M. LSCLK is 270 MHz or 1068 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(), 1069 * so a delay of at least 203 us should suffice. 1070 */ 1071 usleep_range(500, 1000); 1072 value |= VID_EN; 1073 tc_write(DP0CTL, value); 1074 /* Set input interface */ 1075 value = DP0_AUDSRC_NO_INPUT; 1076 if (tc_test_pattern) 1077 value |= DP0_VIDSRC_COLOR_BAR; 1078 else 1079 value |= DP0_VIDSRC_DPI_RX; 1080 tc_write(SYSCTRL, value); 1081 1082 return 0; 1083 err: 1084 return ret; 1085 } 1086 1087 static int tc_stream_disable(struct tc_data *tc) 1088 { 1089 int ret; 1090 u32 val; 1091 1092 dev_dbg(tc->dev, "disable video stream\n"); 1093 1094 tc_read(DP0CTL, &val); 1095 val &= ~VID_EN; 1096 tc_write(DP0CTL, val); 1097 1098 tc_pxl_pll_dis(tc); 1099 1100 return 0; 1101 err: 1102 return ret; 1103 } 1104 1105 static void tc_bridge_pre_enable(struct drm_bridge *bridge) 1106 { 1107 struct tc_data *tc = bridge_to_tc(bridge); 1108 1109 drm_panel_prepare(tc->panel); 1110 } 1111 1112 static void tc_bridge_enable(struct drm_bridge *bridge) 1113 { 1114 struct tc_data *tc = bridge_to_tc(bridge); 1115 int ret; 1116 1117 ret = tc_get_display_props(tc); 1118 if (ret < 0) { 1119 dev_err(tc->dev, "failed to read display props: %d\n", ret); 1120 return; 1121 } 1122 1123 ret = tc_main_link_enable(tc); 1124 if (ret < 0) { 1125 dev_err(tc->dev, "main link enable error: %d\n", ret); 1126 return; 1127 } 1128 1129 ret = tc_stream_enable(tc); 1130 if (ret < 0) { 1131 dev_err(tc->dev, "main link stream start error: %d\n", ret); 1132 tc_main_link_disable(tc); 1133 return; 1134 } 1135 1136 drm_panel_enable(tc->panel); 1137 } 1138 1139 static void tc_bridge_disable(struct drm_bridge *bridge) 1140 { 1141 struct tc_data *tc = bridge_to_tc(bridge); 1142 int ret; 1143 1144 drm_panel_disable(tc->panel); 1145 1146 ret = tc_stream_disable(tc); 1147 if (ret < 0) 1148 dev_err(tc->dev, "main link stream stop error: %d\n", ret); 1149 1150 ret = tc_main_link_disable(tc); 1151 if (ret < 0) 1152 dev_err(tc->dev, "main link disable error: %d\n", ret); 1153 } 1154 1155 static void tc_bridge_post_disable(struct drm_bridge *bridge) 1156 { 1157 struct tc_data *tc = bridge_to_tc(bridge); 1158 1159 drm_panel_unprepare(tc->panel); 1160 } 1161 1162 static bool tc_bridge_mode_fixup(struct drm_bridge *bridge, 1163 const struct drm_display_mode *mode, 1164 struct drm_display_mode *adj) 1165 { 1166 /* Fixup sync polarities, both hsync and vsync are active low */ 1167 adj->flags = mode->flags; 1168 adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); 1169 adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 1170 1171 return true; 1172 } 1173 1174 static enum drm_mode_status tc_mode_valid(struct drm_bridge *bridge, 1175 const struct drm_display_mode *mode) 1176 { 1177 struct tc_data *tc = bridge_to_tc(bridge); 1178 u32 req, avail; 1179 u32 bits_per_pixel = 24; 1180 1181 /* DPI interface clock limitation: upto 154 MHz */ 1182 if (mode->clock > 154000) 1183 return MODE_CLOCK_HIGH; 1184 1185 req = mode->clock * bits_per_pixel / 8; 1186 avail = tc->link.base.num_lanes * tc->link.base.rate; 1187 1188 if (req > avail) 1189 return MODE_BAD; 1190 1191 return MODE_OK; 1192 } 1193 1194 static void tc_bridge_mode_set(struct drm_bridge *bridge, 1195 const struct drm_display_mode *mode, 1196 const struct drm_display_mode *adj) 1197 { 1198 struct tc_data *tc = bridge_to_tc(bridge); 1199 1200 tc->mode = *mode; 1201 } 1202 1203 static int tc_connector_get_modes(struct drm_connector *connector) 1204 { 1205 struct tc_data *tc = connector_to_tc(connector); 1206 struct edid *edid; 1207 unsigned int count; 1208 int ret; 1209 1210 ret = tc_get_display_props(tc); 1211 if (ret < 0) { 1212 dev_err(tc->dev, "failed to read display props: %d\n", ret); 1213 return 0; 1214 } 1215 1216 if (tc->panel && tc->panel->funcs && tc->panel->funcs->get_modes) { 1217 count = tc->panel->funcs->get_modes(tc->panel); 1218 if (count > 0) 1219 return count; 1220 } 1221 1222 edid = drm_get_edid(connector, &tc->aux.ddc); 1223 1224 kfree(tc->edid); 1225 tc->edid = edid; 1226 if (!edid) 1227 return 0; 1228 1229 drm_connector_update_edid_property(connector, edid); 1230 count = drm_add_edid_modes(connector, edid); 1231 1232 return count; 1233 } 1234 1235 static const struct drm_connector_helper_funcs tc_connector_helper_funcs = { 1236 .get_modes = tc_connector_get_modes, 1237 }; 1238 1239 static enum drm_connector_status tc_connector_detect(struct drm_connector *connector, 1240 bool force) 1241 { 1242 struct tc_data *tc = connector_to_tc(connector); 1243 bool conn; 1244 u32 val; 1245 int ret; 1246 1247 if (tc->hpd_pin < 0) { 1248 if (tc->panel) 1249 return connector_status_connected; 1250 else 1251 return connector_status_unknown; 1252 } 1253 1254 tc_read(GPIOI, &val); 1255 1256 conn = val & BIT(tc->hpd_pin); 1257 1258 if (conn) 1259 return connector_status_connected; 1260 else 1261 return connector_status_disconnected; 1262 1263 err: 1264 return connector_status_unknown; 1265 } 1266 1267 static const struct drm_connector_funcs tc_connector_funcs = { 1268 .detect = tc_connector_detect, 1269 .fill_modes = drm_helper_probe_single_connector_modes, 1270 .destroy = drm_connector_cleanup, 1271 .reset = drm_atomic_helper_connector_reset, 1272 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1273 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1274 }; 1275 1276 static int tc_bridge_attach(struct drm_bridge *bridge) 1277 { 1278 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1279 struct tc_data *tc = bridge_to_tc(bridge); 1280 struct drm_device *drm = bridge->dev; 1281 int ret; 1282 1283 /* Create DP/eDP connector */ 1284 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs); 1285 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, 1286 tc->panel ? DRM_MODE_CONNECTOR_eDP : 1287 DRM_MODE_CONNECTOR_DisplayPort); 1288 if (ret) 1289 return ret; 1290 1291 /* Don't poll if don't have HPD connected */ 1292 if (tc->hpd_pin >= 0) { 1293 if (tc->have_irq) 1294 tc->connector.polled = DRM_CONNECTOR_POLL_HPD; 1295 else 1296 tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT | 1297 DRM_CONNECTOR_POLL_DISCONNECT; 1298 } 1299 1300 if (tc->panel) 1301 drm_panel_attach(tc->panel, &tc->connector); 1302 1303 drm_display_info_set_bus_formats(&tc->connector.display_info, 1304 &bus_format, 1); 1305 tc->connector.display_info.bus_flags = 1306 DRM_BUS_FLAG_DE_HIGH | 1307 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE | 1308 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE; 1309 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder); 1310 1311 return 0; 1312 } 1313 1314 static const struct drm_bridge_funcs tc_bridge_funcs = { 1315 .attach = tc_bridge_attach, 1316 .mode_valid = tc_mode_valid, 1317 .mode_set = tc_bridge_mode_set, 1318 .pre_enable = tc_bridge_pre_enable, 1319 .enable = tc_bridge_enable, 1320 .disable = tc_bridge_disable, 1321 .post_disable = tc_bridge_post_disable, 1322 .mode_fixup = tc_bridge_mode_fixup, 1323 }; 1324 1325 static bool tc_readable_reg(struct device *dev, unsigned int reg) 1326 { 1327 return reg != SYSCTRL; 1328 } 1329 1330 static const struct regmap_range tc_volatile_ranges[] = { 1331 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS), 1332 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ), 1333 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL), 1334 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL), 1335 regmap_reg_range(VFUEN0, VFUEN0), 1336 regmap_reg_range(INTSTS_G, INTSTS_G), 1337 regmap_reg_range(GPIOI, GPIOI), 1338 }; 1339 1340 static const struct regmap_access_table tc_volatile_table = { 1341 .yes_ranges = tc_volatile_ranges, 1342 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges), 1343 }; 1344 1345 static bool tc_writeable_reg(struct device *dev, unsigned int reg) 1346 { 1347 return (reg != TC_IDREG) && 1348 (reg != DP0_LTSTAT) && 1349 (reg != DP0_SNKLTCHGREQ); 1350 } 1351 1352 static const struct regmap_config tc_regmap_config = { 1353 .name = "tc358767", 1354 .reg_bits = 16, 1355 .val_bits = 32, 1356 .reg_stride = 4, 1357 .max_register = PLL_DBG, 1358 .cache_type = REGCACHE_RBTREE, 1359 .readable_reg = tc_readable_reg, 1360 .volatile_table = &tc_volatile_table, 1361 .writeable_reg = tc_writeable_reg, 1362 .reg_format_endian = REGMAP_ENDIAN_BIG, 1363 .val_format_endian = REGMAP_ENDIAN_LITTLE, 1364 }; 1365 1366 static irqreturn_t tc_irq_handler(int irq, void *arg) 1367 { 1368 struct tc_data *tc = arg; 1369 u32 val; 1370 int r; 1371 1372 r = regmap_read(tc->regmap, INTSTS_G, &val); 1373 if (r) 1374 return IRQ_NONE; 1375 1376 if (!val) 1377 return IRQ_NONE; 1378 1379 if (val & INT_SYSERR) { 1380 u32 stat = 0; 1381 1382 regmap_read(tc->regmap, SYSSTAT, &stat); 1383 1384 dev_err(tc->dev, "syserr %x\n", stat); 1385 } 1386 1387 if (tc->hpd_pin >= 0 && tc->bridge.dev) { 1388 /* 1389 * H is triggered when the GPIO goes high. 1390 * 1391 * LC is triggered when the GPIO goes low and stays low for 1392 * the duration of LCNT 1393 */ 1394 bool h = val & INT_GPIO_H(tc->hpd_pin); 1395 bool lc = val & INT_GPIO_LC(tc->hpd_pin); 1396 1397 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin, 1398 h ? "H" : "", lc ? "LC" : ""); 1399 1400 if (h || lc) 1401 drm_kms_helper_hotplug_event(tc->bridge.dev); 1402 } 1403 1404 regmap_write(tc->regmap, INTSTS_G, val); 1405 1406 return IRQ_HANDLED; 1407 } 1408 1409 static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id) 1410 { 1411 struct device *dev = &client->dev; 1412 struct tc_data *tc; 1413 int ret; 1414 1415 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL); 1416 if (!tc) 1417 return -ENOMEM; 1418 1419 tc->dev = dev; 1420 1421 /* port@2 is the output port */ 1422 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL); 1423 if (ret && ret != -ENODEV) 1424 return ret; 1425 1426 /* Shut down GPIO is optional */ 1427 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH); 1428 if (IS_ERR(tc->sd_gpio)) 1429 return PTR_ERR(tc->sd_gpio); 1430 1431 if (tc->sd_gpio) { 1432 gpiod_set_value_cansleep(tc->sd_gpio, 0); 1433 usleep_range(5000, 10000); 1434 } 1435 1436 /* Reset GPIO is optional */ 1437 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1438 if (IS_ERR(tc->reset_gpio)) 1439 return PTR_ERR(tc->reset_gpio); 1440 1441 if (tc->reset_gpio) { 1442 gpiod_set_value_cansleep(tc->reset_gpio, 1); 1443 usleep_range(5000, 10000); 1444 } 1445 1446 tc->refclk = devm_clk_get(dev, "ref"); 1447 if (IS_ERR(tc->refclk)) { 1448 ret = PTR_ERR(tc->refclk); 1449 dev_err(dev, "Failed to get refclk: %d\n", ret); 1450 return ret; 1451 } 1452 1453 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config); 1454 if (IS_ERR(tc->regmap)) { 1455 ret = PTR_ERR(tc->regmap); 1456 dev_err(dev, "Failed to initialize regmap: %d\n", ret); 1457 return ret; 1458 } 1459 1460 ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin", 1461 &tc->hpd_pin); 1462 if (ret) { 1463 tc->hpd_pin = -ENODEV; 1464 } else { 1465 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) { 1466 dev_err(dev, "failed to parse HPD number\n"); 1467 return ret; 1468 } 1469 } 1470 1471 if (client->irq > 0) { 1472 /* enable SysErr */ 1473 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR); 1474 1475 ret = devm_request_threaded_irq(dev, client->irq, 1476 NULL, tc_irq_handler, 1477 IRQF_ONESHOT, 1478 "tc358767-irq", tc); 1479 if (ret) { 1480 dev_err(dev, "failed to register dp interrupt\n"); 1481 return ret; 1482 } 1483 1484 tc->have_irq = true; 1485 } 1486 1487 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev); 1488 if (ret) { 1489 dev_err(tc->dev, "can not read device ID: %d\n", ret); 1490 return ret; 1491 } 1492 1493 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) { 1494 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev); 1495 return -EINVAL; 1496 } 1497 1498 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */ 1499 1500 if (tc->hpd_pin >= 0) { 1501 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT; 1502 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin); 1503 1504 /* Set LCNT to 2ms */ 1505 regmap_write(tc->regmap, lcnt_reg, 1506 clk_get_rate(tc->refclk) * 2 / 1000); 1507 /* We need the "alternate" mode for HPD */ 1508 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin)); 1509 1510 if (tc->have_irq) { 1511 /* enable H & LC */ 1512 regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc); 1513 } 1514 } 1515 1516 ret = tc_aux_link_setup(tc); 1517 if (ret) 1518 return ret; 1519 1520 /* Register DP AUX channel */ 1521 tc->aux.name = "TC358767 AUX i2c adapter"; 1522 tc->aux.dev = tc->dev; 1523 tc->aux.transfer = tc_aux_transfer; 1524 ret = drm_dp_aux_register(&tc->aux); 1525 if (ret) 1526 return ret; 1527 1528 tc->bridge.funcs = &tc_bridge_funcs; 1529 tc->bridge.of_node = dev->of_node; 1530 drm_bridge_add(&tc->bridge); 1531 1532 i2c_set_clientdata(client, tc); 1533 1534 return 0; 1535 } 1536 1537 static int tc_remove(struct i2c_client *client) 1538 { 1539 struct tc_data *tc = i2c_get_clientdata(client); 1540 1541 drm_bridge_remove(&tc->bridge); 1542 drm_dp_aux_unregister(&tc->aux); 1543 1544 return 0; 1545 } 1546 1547 static const struct i2c_device_id tc358767_i2c_ids[] = { 1548 { "tc358767", 0 }, 1549 { } 1550 }; 1551 MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids); 1552 1553 static const struct of_device_id tc358767_of_ids[] = { 1554 { .compatible = "toshiba,tc358767", }, 1555 { } 1556 }; 1557 MODULE_DEVICE_TABLE(of, tc358767_of_ids); 1558 1559 static struct i2c_driver tc358767_driver = { 1560 .driver = { 1561 .name = "tc358767", 1562 .of_match_table = tc358767_of_ids, 1563 }, 1564 .id_table = tc358767_i2c_ids, 1565 .probe = tc_probe, 1566 .remove = tc_remove, 1567 }; 1568 module_i2c_driver(tc358767_driver); 1569 1570 MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>"); 1571 MODULE_DESCRIPTION("tc358767 eDP encoder driver"); 1572 MODULE_LICENSE("GPL"); 1573