1 /* 2 * tc358767 eDP bridge driver 3 * 4 * Copyright (C) 2016 CogentEmbedded Inc 5 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com> 6 * 7 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de> 8 * 9 * Copyright (C) 2016 Zodiac Inflight Innovations 10 * 11 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c 12 * 13 * Copyright (C) 2012 Texas Instruments 14 * Author: Rob Clark <robdclark@gmail.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or 19 * (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 */ 26 27 #include <linux/clk.h> 28 #include <linux/device.h> 29 #include <linux/gpio/consumer.h> 30 #include <linux/i2c.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/regmap.h> 34 #include <linux/slab.h> 35 36 #include <drm/drm_atomic_helper.h> 37 #include <drm/drm_crtc_helper.h> 38 #include <drm/drm_dp_helper.h> 39 #include <drm/drm_edid.h> 40 #include <drm/drm_of.h> 41 #include <drm/drm_panel.h> 42 43 /* Registers */ 44 45 /* Display Parallel Interface */ 46 #define DPIPXLFMT 0x0440 47 #define VS_POL_ACTIVE_LOW (1 << 10) 48 #define HS_POL_ACTIVE_LOW (1 << 9) 49 #define DE_POL_ACTIVE_HIGH (0 << 8) 50 #define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */ 51 #define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */ 52 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */ 53 #define DPI_BPP_RGB888 (0 << 0) 54 #define DPI_BPP_RGB666 (1 << 0) 55 #define DPI_BPP_RGB565 (2 << 0) 56 57 /* Video Path */ 58 #define VPCTRL0 0x0450 59 #define OPXLFMT_RGB666 (0 << 8) 60 #define OPXLFMT_RGB888 (1 << 8) 61 #define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */ 62 #define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */ 63 #define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */ 64 #define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */ 65 #define HTIM01 0x0454 66 #define HTIM02 0x0458 67 #define VTIM01 0x045c 68 #define VTIM02 0x0460 69 #define VFUEN0 0x0464 70 #define VFUEN BIT(0) /* Video Frame Timing Upload */ 71 72 /* System */ 73 #define TC_IDREG 0x0500 74 #define SYSCTRL 0x0510 75 #define DP0_AUDSRC_NO_INPUT (0 << 3) 76 #define DP0_AUDSRC_I2S_RX (1 << 3) 77 #define DP0_VIDSRC_NO_INPUT (0 << 0) 78 #define DP0_VIDSRC_DSI_RX (1 << 0) 79 #define DP0_VIDSRC_DPI_RX (2 << 0) 80 #define DP0_VIDSRC_COLOR_BAR (3 << 0) 81 82 /* Control */ 83 #define DP0CTL 0x0600 84 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */ 85 #define EF_EN BIT(5) /* Enable Enhanced Framing */ 86 #define VID_EN BIT(1) /* Video transmission enable */ 87 #define DP_EN BIT(0) /* Enable DPTX function */ 88 89 /* Clocks */ 90 #define DP0_VIDMNGEN0 0x0610 91 #define DP0_VIDMNGEN1 0x0614 92 #define DP0_VMNGENSTATUS 0x0618 93 94 /* Main Channel */ 95 #define DP0_SECSAMPLE 0x0640 96 #define DP0_VIDSYNCDELAY 0x0644 97 #define DP0_TOTALVAL 0x0648 98 #define DP0_STARTVAL 0x064c 99 #define DP0_ACTIVEVAL 0x0650 100 #define DP0_SYNCVAL 0x0654 101 #define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15) 102 #define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31) 103 #define DP0_MISC 0x0658 104 #define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */ 105 #define BPC_6 (0 << 5) 106 #define BPC_8 (1 << 5) 107 108 /* AUX channel */ 109 #define DP0_AUXCFG0 0x0660 110 #define DP0_AUXCFG1 0x0664 111 #define AUX_RX_FILTER_EN BIT(16) 112 113 #define DP0_AUXADDR 0x0668 114 #define DP0_AUXWDATA(i) (0x066c + (i) * 4) 115 #define DP0_AUXRDATA(i) (0x067c + (i) * 4) 116 #define DP0_AUXSTATUS 0x068c 117 #define AUX_STATUS_MASK 0xf0 118 #define AUX_STATUS_SHIFT 4 119 #define AUX_TIMEOUT BIT(1) 120 #define AUX_BUSY BIT(0) 121 #define DP0_AUXI2CADR 0x0698 122 123 /* Link Training */ 124 #define DP0_SRCCTRL 0x06a0 125 #define DP0_SRCCTRL_SCRMBLDIS BIT(13) 126 #define DP0_SRCCTRL_EN810B BIT(12) 127 #define DP0_SRCCTRL_NOTP (0 << 8) 128 #define DP0_SRCCTRL_TP1 (1 << 8) 129 #define DP0_SRCCTRL_TP2 (2 << 8) 130 #define DP0_SRCCTRL_LANESKEW BIT(7) 131 #define DP0_SRCCTRL_SSCG BIT(3) 132 #define DP0_SRCCTRL_LANES_1 (0 << 2) 133 #define DP0_SRCCTRL_LANES_2 (1 << 2) 134 #define DP0_SRCCTRL_BW27 (1 << 1) 135 #define DP0_SRCCTRL_BW162 (0 << 1) 136 #define DP0_SRCCTRL_AUTOCORRECT BIT(0) 137 #define DP0_LTSTAT 0x06d0 138 #define LT_LOOPDONE BIT(13) 139 #define LT_STATUS_MASK (0x1f << 8) 140 #define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4) 141 #define LT_INTERLANE_ALIGN_DONE BIT(3) 142 #define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS) 143 #define DP0_SNKLTCHGREQ 0x06d4 144 #define DP0_LTLOOPCTRL 0x06d8 145 #define DP0_SNKLTCTRL 0x06e4 146 147 #define DP1_SRCCTRL 0x07a0 148 149 /* PHY */ 150 #define DP_PHY_CTRL 0x0800 151 #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */ 152 #define BGREN BIT(25) /* AUX PHY BGR Enable */ 153 #define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */ 154 #define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */ 155 #define PHY_RDY BIT(16) /* PHY Main Channels Ready */ 156 #define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */ 157 #define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */ 158 #define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */ 159 #define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */ 160 161 /* PLL */ 162 #define DP0_PLLCTRL 0x0900 163 #define DP1_PLLCTRL 0x0904 /* not defined in DS */ 164 #define PXL_PLLCTRL 0x0908 165 #define PLLUPDATE BIT(2) 166 #define PLLBYP BIT(1) 167 #define PLLEN BIT(0) 168 #define PXL_PLLPARAM 0x0914 169 #define IN_SEL_REFCLK (0 << 14) 170 #define SYS_PLLPARAM 0x0918 171 #define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */ 172 #define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */ 173 #define REF_FREQ_26M (2 << 8) /* 26 MHz */ 174 #define REF_FREQ_13M (3 << 8) /* 13 MHz */ 175 #define SYSCLK_SEL_LSCLK (0 << 4) 176 #define LSCLK_DIV_1 (0 << 0) 177 #define LSCLK_DIV_2 (1 << 0) 178 179 /* Test & Debug */ 180 #define TSTCTL 0x0a00 181 #define PLL_DBG 0x0a04 182 183 static bool tc_test_pattern; 184 module_param_named(test, tc_test_pattern, bool, 0644); 185 186 struct tc_edp_link { 187 struct drm_dp_link base; 188 u8 assr; 189 int scrambler_dis; 190 int spread; 191 int coding8b10b; 192 u8 swing; 193 u8 preemp; 194 }; 195 196 struct tc_data { 197 struct device *dev; 198 struct regmap *regmap; 199 struct drm_dp_aux aux; 200 201 struct drm_bridge bridge; 202 struct drm_connector connector; 203 struct drm_panel *panel; 204 205 /* link settings */ 206 struct tc_edp_link link; 207 208 /* display edid */ 209 struct edid *edid; 210 /* current mode */ 211 struct drm_display_mode *mode; 212 213 u32 rev; 214 u8 assr; 215 216 struct gpio_desc *sd_gpio; 217 struct gpio_desc *reset_gpio; 218 struct clk *refclk; 219 }; 220 221 static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a) 222 { 223 return container_of(a, struct tc_data, aux); 224 } 225 226 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b) 227 { 228 return container_of(b, struct tc_data, bridge); 229 } 230 231 static inline struct tc_data *connector_to_tc(struct drm_connector *c) 232 { 233 return container_of(c, struct tc_data, connector); 234 } 235 236 /* Simple macros to avoid repeated error checks */ 237 #define tc_write(reg, var) \ 238 do { \ 239 ret = regmap_write(tc->regmap, reg, var); \ 240 if (ret) \ 241 goto err; \ 242 } while (0) 243 #define tc_read(reg, var) \ 244 do { \ 245 ret = regmap_read(tc->regmap, reg, var); \ 246 if (ret) \ 247 goto err; \ 248 } while (0) 249 250 static inline int tc_poll_timeout(struct regmap *map, unsigned int addr, 251 unsigned int cond_mask, 252 unsigned int cond_value, 253 unsigned long sleep_us, u64 timeout_us) 254 { 255 ktime_t timeout = ktime_add_us(ktime_get(), timeout_us); 256 unsigned int val; 257 int ret; 258 259 for (;;) { 260 ret = regmap_read(map, addr, &val); 261 if (ret) 262 break; 263 if ((val & cond_mask) == cond_value) 264 break; 265 if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) { 266 ret = regmap_read(map, addr, &val); 267 break; 268 } 269 if (sleep_us) 270 usleep_range((sleep_us >> 2) + 1, sleep_us); 271 } 272 return ret ?: (((val & cond_mask) == cond_value) ? 0 : -ETIMEDOUT); 273 } 274 275 static int tc_aux_wait_busy(struct tc_data *tc, unsigned int timeout_ms) 276 { 277 return tc_poll_timeout(tc->regmap, DP0_AUXSTATUS, AUX_BUSY, 0, 278 1000, 1000 * timeout_ms); 279 } 280 281 static int tc_aux_get_status(struct tc_data *tc, u8 *reply) 282 { 283 int ret; 284 u32 value; 285 286 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &value); 287 if (ret < 0) 288 return ret; 289 if (value & AUX_BUSY) { 290 if (value & AUX_TIMEOUT) { 291 dev_err(tc->dev, "i2c access timeout!\n"); 292 return -ETIMEDOUT; 293 } 294 return -EBUSY; 295 } 296 297 *reply = (value & AUX_STATUS_MASK) >> AUX_STATUS_SHIFT; 298 return 0; 299 } 300 301 static ssize_t tc_aux_transfer(struct drm_dp_aux *aux, 302 struct drm_dp_aux_msg *msg) 303 { 304 struct tc_data *tc = aux_to_tc(aux); 305 size_t size = min_t(size_t, 8, msg->size); 306 u8 request = msg->request & ~DP_AUX_I2C_MOT; 307 u8 *buf = msg->buffer; 308 u32 tmp = 0; 309 int i = 0; 310 int ret; 311 312 if (size == 0) 313 return 0; 314 315 ret = tc_aux_wait_busy(tc, 100); 316 if (ret) 317 goto err; 318 319 if (request == DP_AUX_I2C_WRITE || request == DP_AUX_NATIVE_WRITE) { 320 /* Store data */ 321 while (i < size) { 322 if (request == DP_AUX_NATIVE_WRITE) 323 tmp = tmp | (buf[i] << (8 * (i & 0x3))); 324 else 325 tmp = (tmp << 8) | buf[i]; 326 i++; 327 if (((i % 4) == 0) || (i == size)) { 328 tc_write(DP0_AUXWDATA((i - 1) >> 2), tmp); 329 tmp = 0; 330 } 331 } 332 } else if (request != DP_AUX_I2C_READ && 333 request != DP_AUX_NATIVE_READ) { 334 return -EINVAL; 335 } 336 337 /* Store address */ 338 tc_write(DP0_AUXADDR, msg->address); 339 /* Start transfer */ 340 tc_write(DP0_AUXCFG0, ((size - 1) << 8) | request); 341 342 ret = tc_aux_wait_busy(tc, 100); 343 if (ret) 344 goto err; 345 346 ret = tc_aux_get_status(tc, &msg->reply); 347 if (ret) 348 goto err; 349 350 if (request == DP_AUX_I2C_READ || request == DP_AUX_NATIVE_READ) { 351 /* Read data */ 352 while (i < size) { 353 if ((i % 4) == 0) 354 tc_read(DP0_AUXRDATA(i >> 2), &tmp); 355 buf[i] = tmp & 0xff; 356 tmp = tmp >> 8; 357 i++; 358 } 359 } 360 361 return size; 362 err: 363 return ret; 364 } 365 366 static const char * const training_pattern1_errors[] = { 367 "No errors", 368 "Aux write error", 369 "Aux read error", 370 "Max voltage reached error", 371 "Loop counter expired error", 372 "res", "res", "res" 373 }; 374 375 static const char * const training_pattern2_errors[] = { 376 "No errors", 377 "Aux write error", 378 "Aux read error", 379 "Clock recovery failed error", 380 "Loop counter expired error", 381 "res", "res", "res" 382 }; 383 384 static u32 tc_srcctrl(struct tc_data *tc) 385 { 386 /* 387 * No training pattern, skew lane 1 data by two LSCLK cycles with 388 * respect to lane 0 data, AutoCorrect Mode = 0 389 */ 390 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW; 391 392 if (tc->link.scrambler_dis) 393 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */ 394 if (tc->link.coding8b10b) 395 /* Enable 8/10B Encoder (TxData[19:16] not used) */ 396 reg |= DP0_SRCCTRL_EN810B; 397 if (tc->link.spread) 398 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */ 399 if (tc->link.base.num_lanes == 2) 400 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */ 401 if (tc->link.base.rate != 162000) 402 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */ 403 return reg; 404 } 405 406 static void tc_wait_pll_lock(struct tc_data *tc) 407 { 408 /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */ 409 usleep_range(3000, 6000); 410 } 411 412 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) 413 { 414 int ret; 415 int i_pre, best_pre = 1; 416 int i_post, best_post = 1; 417 int div, best_div = 1; 418 int mul, best_mul = 1; 419 int delta, best_delta; 420 int ext_div[] = {1, 2, 3, 5, 7}; 421 int best_pixelclock = 0; 422 int vco_hi = 0; 423 424 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock, 425 refclk); 426 best_delta = pixelclock; 427 /* Loop over all possible ext_divs, skipping invalid configurations */ 428 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) { 429 /* 430 * refclk / ext_pre_div should be in the 1 to 200 MHz range. 431 * We don't allow any refclk > 200 MHz, only check lower bounds. 432 */ 433 if (refclk / ext_div[i_pre] < 1000000) 434 continue; 435 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) { 436 for (div = 1; div <= 16; div++) { 437 u32 clk; 438 u64 tmp; 439 440 tmp = pixelclock * ext_div[i_pre] * 441 ext_div[i_post] * div; 442 do_div(tmp, refclk); 443 mul = tmp; 444 445 /* Check limits */ 446 if ((mul < 1) || (mul > 128)) 447 continue; 448 449 clk = (refclk / ext_div[i_pre] / div) * mul; 450 /* 451 * refclk * mul / (ext_pre_div * pre_div) 452 * should be in the 150 to 650 MHz range 453 */ 454 if ((clk > 650000000) || (clk < 150000000)) 455 continue; 456 457 clk = clk / ext_div[i_post]; 458 delta = clk - pixelclock; 459 460 if (abs(delta) < abs(best_delta)) { 461 best_pre = i_pre; 462 best_post = i_post; 463 best_div = div; 464 best_mul = mul; 465 best_delta = delta; 466 best_pixelclock = clk; 467 } 468 } 469 } 470 } 471 if (best_pixelclock == 0) { 472 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n", 473 pixelclock); 474 return -EINVAL; 475 } 476 477 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock, 478 best_delta); 479 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk, 480 ext_div[best_pre], best_div, best_mul, ext_div[best_post]); 481 482 /* if VCO >= 300 MHz */ 483 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000) 484 vco_hi = 1; 485 /* see DS */ 486 if (best_div == 16) 487 best_div = 0; 488 if (best_mul == 128) 489 best_mul = 0; 490 491 /* Power up PLL and switch to bypass */ 492 tc_write(PXL_PLLCTRL, PLLBYP | PLLEN); 493 494 tc_write(PXL_PLLPARAM, 495 (vco_hi << 24) | /* For PLL VCO >= 300 MHz = 1 */ 496 (ext_div[best_pre] << 20) | /* External Pre-divider */ 497 (ext_div[best_post] << 16) | /* External Post-divider */ 498 IN_SEL_REFCLK | /* Use RefClk as PLL input */ 499 (best_div << 8) | /* Divider for PLL RefClk */ 500 (best_mul << 0)); /* Multiplier for PLL */ 501 502 /* Force PLL parameter update and disable bypass */ 503 tc_write(PXL_PLLCTRL, PLLUPDATE | PLLEN); 504 505 tc_wait_pll_lock(tc); 506 507 return 0; 508 err: 509 return ret; 510 } 511 512 static int tc_pxl_pll_dis(struct tc_data *tc) 513 { 514 /* Enable PLL bypass, power down PLL */ 515 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP); 516 } 517 518 static int tc_stream_clock_calc(struct tc_data *tc) 519 { 520 int ret; 521 /* 522 * If the Stream clock and Link Symbol clock are 523 * asynchronous with each other, the value of M changes over 524 * time. This way of generating link clock and stream 525 * clock is called Asynchronous Clock mode. The value M 526 * must change while the value N stays constant. The 527 * value of N in this Asynchronous Clock mode must be set 528 * to 2^15 or 32,768. 529 * 530 * LSCLK = 1/10 of high speed link clock 531 * 532 * f_STRMCLK = M/N * f_LSCLK 533 * M/N = f_STRMCLK / f_LSCLK 534 * 535 */ 536 tc_write(DP0_VIDMNGEN1, 32768); 537 538 return 0; 539 err: 540 return ret; 541 } 542 543 static int tc_aux_link_setup(struct tc_data *tc) 544 { 545 unsigned long rate; 546 u32 value; 547 int ret; 548 u32 dp_phy_ctrl; 549 550 rate = clk_get_rate(tc->refclk); 551 switch (rate) { 552 case 38400000: 553 value = REF_FREQ_38M4; 554 break; 555 case 26000000: 556 value = REF_FREQ_26M; 557 break; 558 case 19200000: 559 value = REF_FREQ_19M2; 560 break; 561 case 13000000: 562 value = REF_FREQ_13M; 563 break; 564 default: 565 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate); 566 return -EINVAL; 567 } 568 569 /* Setup DP-PHY / PLL */ 570 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; 571 tc_write(SYS_PLLPARAM, value); 572 573 dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN; 574 if (tc->link.base.num_lanes == 2) 575 dp_phy_ctrl |= PHY_2LANE; 576 tc_write(DP_PHY_CTRL, dp_phy_ctrl); 577 578 /* 579 * Initially PLLs are in bypass. Force PLL parameter update, 580 * disable PLL bypass, enable PLL 581 */ 582 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN); 583 tc_wait_pll_lock(tc); 584 585 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN); 586 tc_wait_pll_lock(tc); 587 588 ret = tc_poll_timeout(tc->regmap, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 589 1000); 590 if (ret == -ETIMEDOUT) { 591 dev_err(tc->dev, "Timeout waiting for PHY to become ready"); 592 return ret; 593 } else if (ret) 594 goto err; 595 596 /* Setup AUX link */ 597 tc_write(DP0_AUXCFG1, AUX_RX_FILTER_EN | 598 (0x06 << 8) | /* Aux Bit Period Calculator Threshold */ 599 (0x3f << 0)); /* Aux Response Timeout Timer */ 600 601 return 0; 602 err: 603 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret); 604 return ret; 605 } 606 607 static int tc_get_display_props(struct tc_data *tc) 608 { 609 int ret; 610 /* temp buffer */ 611 u8 tmp[8]; 612 613 /* Read DP Rx Link Capability */ 614 ret = drm_dp_link_probe(&tc->aux, &tc->link.base); 615 if (ret < 0) 616 goto err_dpcd_read; 617 if (tc->link.base.rate != 162000 && tc->link.base.rate != 270000) { 618 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n"); 619 tc->link.base.rate = 270000; 620 } 621 622 if (tc->link.base.num_lanes > 2) { 623 dev_dbg(tc->dev, "Falling to 2 lanes\n"); 624 tc->link.base.num_lanes = 2; 625 } 626 627 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, tmp); 628 if (ret < 0) 629 goto err_dpcd_read; 630 tc->link.spread = tmp[0] & BIT(0); /* 0.5% down spread */ 631 632 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, tmp); 633 if (ret < 0) 634 goto err_dpcd_read; 635 tc->link.coding8b10b = tmp[0] & BIT(0); 636 tc->link.scrambler_dis = 0; 637 /* read assr */ 638 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, tmp); 639 if (ret < 0) 640 goto err_dpcd_read; 641 tc->link.assr = tmp[0] & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; 642 643 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n", 644 tc->link.base.revision >> 4, tc->link.base.revision & 0x0f, 645 (tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps", 646 tc->link.base.num_lanes, 647 (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ? 648 "enhanced" : "non-enhanced"); 649 dev_dbg(tc->dev, "ANSI 8B/10B: %d\n", tc->link.coding8b10b); 650 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n", 651 tc->link.assr, tc->assr); 652 653 return 0; 654 655 err_dpcd_read: 656 dev_err(tc->dev, "failed to read DPCD: %d\n", ret); 657 return ret; 658 } 659 660 static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode) 661 { 662 int ret; 663 int vid_sync_dly; 664 int max_tu_symbol; 665 666 int left_margin = mode->htotal - mode->hsync_end; 667 int right_margin = mode->hsync_start - mode->hdisplay; 668 int hsync_len = mode->hsync_end - mode->hsync_start; 669 int upper_margin = mode->vtotal - mode->vsync_end; 670 int lower_margin = mode->vsync_start - mode->vdisplay; 671 int vsync_len = mode->vsync_end - mode->vsync_start; 672 673 /* 674 * Recommended maximum number of symbols transferred in a transfer unit: 675 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size, 676 * (output active video bandwidth in bytes)) 677 * Must be less than tu_size. 678 */ 679 max_tu_symbol = TU_SIZE_RECOMMENDED - 1; 680 681 dev_dbg(tc->dev, "set mode %dx%d\n", 682 mode->hdisplay, mode->vdisplay); 683 dev_dbg(tc->dev, "H margin %d,%d sync %d\n", 684 left_margin, right_margin, hsync_len); 685 dev_dbg(tc->dev, "V margin %d,%d sync %d\n", 686 upper_margin, lower_margin, vsync_len); 687 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal); 688 689 690 /* 691 * LCD Ctl Frame Size 692 * datasheet is not clear of vsdelay in case of DPI 693 * assume we do not need any delay when DPI is a source of 694 * sync signals 695 */ 696 tc_write(VPCTRL0, (0 << 20) /* VSDELAY */ | 697 OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED); 698 tc_write(HTIM01, (ALIGN(left_margin, 2) << 16) | /* H back porch */ 699 (ALIGN(hsync_len, 2) << 0)); /* Hsync */ 700 tc_write(HTIM02, (ALIGN(right_margin, 2) << 16) | /* H front porch */ 701 (ALIGN(mode->hdisplay, 2) << 0)); /* width */ 702 tc_write(VTIM01, (upper_margin << 16) | /* V back porch */ 703 (vsync_len << 0)); /* Vsync */ 704 tc_write(VTIM02, (lower_margin << 16) | /* V front porch */ 705 (mode->vdisplay << 0)); /* height */ 706 tc_write(VFUEN0, VFUEN); /* update settings */ 707 708 /* Test pattern settings */ 709 tc_write(TSTCTL, 710 (120 << 24) | /* Red Color component value */ 711 (20 << 16) | /* Green Color component value */ 712 (99 << 8) | /* Blue Color component value */ 713 (1 << 4) | /* Enable I2C Filter */ 714 (2 << 0) | /* Color bar Mode */ 715 0); 716 717 /* DP Main Stream Attributes */ 718 vid_sync_dly = hsync_len + left_margin + mode->hdisplay; 719 tc_write(DP0_VIDSYNCDELAY, 720 (max_tu_symbol << 16) | /* thresh_dly */ 721 (vid_sync_dly << 0)); 722 723 tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal)); 724 725 tc_write(DP0_STARTVAL, 726 ((upper_margin + vsync_len) << 16) | 727 ((left_margin + hsync_len) << 0)); 728 729 tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay)); 730 731 tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0) | 732 ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? SYNCVAL_HS_POL_ACTIVE_LOW : 0) | 733 ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? SYNCVAL_VS_POL_ACTIVE_LOW : 0)); 734 735 tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW | 736 DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888); 737 738 tc_write(DP0_MISC, (max_tu_symbol << 23) | (TU_SIZE_RECOMMENDED << 16) | 739 BPC_8); 740 741 return 0; 742 err: 743 return ret; 744 } 745 746 static int tc_link_training(struct tc_data *tc, int pattern) 747 { 748 const char * const *errors; 749 u32 srcctrl = tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | 750 DP0_SRCCTRL_AUTOCORRECT; 751 int timeout; 752 int retry; 753 u32 value; 754 int ret; 755 756 if (pattern == DP_TRAINING_PATTERN_1) { 757 srcctrl |= DP0_SRCCTRL_TP1; 758 errors = training_pattern1_errors; 759 } else { 760 srcctrl |= DP0_SRCCTRL_TP2; 761 errors = training_pattern2_errors; 762 } 763 764 /* Set DPCD 0x102 for Training Part 1 or 2 */ 765 tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | pattern); 766 767 tc_write(DP0_LTLOOPCTRL, 768 (0x0f << 28) | /* Defer Iteration Count */ 769 (0x0f << 24) | /* Loop Iteration Count */ 770 (0x0d << 0)); /* Loop Timer Delay */ 771 772 retry = 5; 773 do { 774 /* Set DP0 Training Pattern */ 775 tc_write(DP0_SRCCTRL, srcctrl); 776 777 /* Enable DP0 to start Link Training */ 778 tc_write(DP0CTL, DP_EN); 779 780 /* wait */ 781 timeout = 1000; 782 do { 783 tc_read(DP0_LTSTAT, &value); 784 udelay(1); 785 } while ((!(value & LT_LOOPDONE)) && (--timeout)); 786 if (timeout == 0) { 787 dev_err(tc->dev, "Link training timeout!\n"); 788 } else { 789 int pattern = (value >> 11) & 0x3; 790 int error = (value >> 8) & 0x7; 791 792 dev_dbg(tc->dev, 793 "Link training phase %d done after %d uS: %s\n", 794 pattern, 1000 - timeout, errors[error]); 795 if (pattern == DP_TRAINING_PATTERN_1 && error == 0) 796 break; 797 if (pattern == DP_TRAINING_PATTERN_2) { 798 value &= LT_CHANNEL1_EQ_BITS | 799 LT_INTERLANE_ALIGN_DONE | 800 LT_CHANNEL0_EQ_BITS; 801 /* in case of two lanes */ 802 if ((tc->link.base.num_lanes == 2) && 803 (value == (LT_CHANNEL1_EQ_BITS | 804 LT_INTERLANE_ALIGN_DONE | 805 LT_CHANNEL0_EQ_BITS))) 806 break; 807 /* in case of one line */ 808 if ((tc->link.base.num_lanes == 1) && 809 (value == (LT_INTERLANE_ALIGN_DONE | 810 LT_CHANNEL0_EQ_BITS))) 811 break; 812 } 813 } 814 /* restart */ 815 tc_write(DP0CTL, 0); 816 usleep_range(10, 20); 817 } while (--retry); 818 if (retry == 0) { 819 dev_err(tc->dev, "Failed to finish training phase %d\n", 820 pattern); 821 } 822 823 return 0; 824 err: 825 return ret; 826 } 827 828 static int tc_main_link_setup(struct tc_data *tc) 829 { 830 struct drm_dp_aux *aux = &tc->aux; 831 struct device *dev = tc->dev; 832 unsigned int rate; 833 u32 dp_phy_ctrl; 834 int timeout; 835 u32 value; 836 int ret; 837 u8 tmp[8]; 838 839 /* display mode should be set at this point */ 840 if (!tc->mode) 841 return -EINVAL; 842 843 tc_write(DP0_SRCCTRL, tc_srcctrl(tc)); 844 /* SSCG and BW27 on DP1 must be set to the same as on DP0 */ 845 tc_write(DP1_SRCCTRL, 846 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) | 847 ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0)); 848 849 rate = clk_get_rate(tc->refclk); 850 switch (rate) { 851 case 38400000: 852 value = REF_FREQ_38M4; 853 break; 854 case 26000000: 855 value = REF_FREQ_26M; 856 break; 857 case 19200000: 858 value = REF_FREQ_19M2; 859 break; 860 case 13000000: 861 value = REF_FREQ_13M; 862 break; 863 default: 864 return -EINVAL; 865 } 866 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; 867 tc_write(SYS_PLLPARAM, value); 868 869 /* Setup Main Link */ 870 dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN; 871 if (tc->link.base.num_lanes == 2) 872 dp_phy_ctrl |= PHY_2LANE; 873 tc_write(DP_PHY_CTRL, dp_phy_ctrl); 874 msleep(100); 875 876 /* PLL setup */ 877 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN); 878 tc_wait_pll_lock(tc); 879 880 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN); 881 tc_wait_pll_lock(tc); 882 883 /* PXL PLL setup */ 884 if (tc_test_pattern) { 885 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), 886 1000 * tc->mode->clock); 887 if (ret) 888 goto err; 889 } 890 891 /* Reset/Enable Main Links */ 892 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST; 893 tc_write(DP_PHY_CTRL, dp_phy_ctrl); 894 usleep_range(100, 200); 895 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST); 896 tc_write(DP_PHY_CTRL, dp_phy_ctrl); 897 898 timeout = 1000; 899 do { 900 tc_read(DP_PHY_CTRL, &value); 901 udelay(1); 902 } while ((!(value & PHY_RDY)) && (--timeout)); 903 904 if (timeout == 0) { 905 dev_err(dev, "timeout waiting for phy become ready"); 906 return -ETIMEDOUT; 907 } 908 909 /* Set misc: 8 bits per color */ 910 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8); 911 if (ret) 912 goto err; 913 914 /* 915 * ASSR mode 916 * on TC358767 side ASSR configured through strap pin 917 * seems there is no way to change this setting from SW 918 * 919 * check is tc configured for same mode 920 */ 921 if (tc->assr != tc->link.assr) { 922 dev_dbg(dev, "Trying to set display to ASSR: %d\n", 923 tc->assr); 924 /* try to set ASSR on display side */ 925 tmp[0] = tc->assr; 926 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]); 927 if (ret < 0) 928 goto err_dpcd_read; 929 /* read back */ 930 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp); 931 if (ret < 0) 932 goto err_dpcd_read; 933 934 if (tmp[0] != tc->assr) { 935 dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n", 936 tc->assr); 937 /* trying with disabled scrambler */ 938 tc->link.scrambler_dis = 1; 939 } 940 } 941 942 /* Setup Link & DPRx Config for Training */ 943 ret = drm_dp_link_configure(aux, &tc->link.base); 944 if (ret < 0) 945 goto err_dpcd_write; 946 947 /* DOWNSPREAD_CTRL */ 948 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00; 949 /* MAIN_LINK_CHANNEL_CODING_SET */ 950 tmp[1] = tc->link.coding8b10b ? DP_SET_ANSI_8B10B : 0x00; 951 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2); 952 if (ret < 0) 953 goto err_dpcd_write; 954 955 ret = tc_link_training(tc, DP_TRAINING_PATTERN_1); 956 if (ret) 957 goto err; 958 959 ret = tc_link_training(tc, DP_TRAINING_PATTERN_2); 960 if (ret) 961 goto err; 962 963 /* Clear DPCD 0x102 */ 964 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */ 965 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00; 966 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]); 967 if (ret < 0) 968 goto err_dpcd_write; 969 970 /* Clear Training Pattern, set AutoCorrect Mode = 1 */ 971 tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_AUTOCORRECT); 972 973 /* Wait */ 974 timeout = 100; 975 do { 976 udelay(1); 977 /* Read DPCD 0x202-0x207 */ 978 ret = drm_dp_dpcd_read_link_status(aux, tmp + 2); 979 if (ret < 0) 980 goto err_dpcd_read; 981 } while ((--timeout) && 982 !(drm_dp_channel_eq_ok(tmp + 2, tc->link.base.num_lanes))); 983 984 if (timeout == 0) { 985 /* Read DPCD 0x200-0x201 */ 986 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT, tmp, 2); 987 if (ret < 0) 988 goto err_dpcd_read; 989 dev_err(dev, "channel(s) EQ not ok\n"); 990 dev_info(dev, "0x0200 SINK_COUNT: 0x%02x\n", tmp[0]); 991 dev_info(dev, "0x0201 DEVICE_SERVICE_IRQ_VECTOR: 0x%02x\n", 992 tmp[1]); 993 dev_info(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[2]); 994 dev_info(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", 995 tmp[4]); 996 dev_info(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[5]); 997 dev_info(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n", 998 tmp[6]); 999 1000 return -EAGAIN; 1001 } 1002 1003 ret = tc_set_video_mode(tc, tc->mode); 1004 if (ret) 1005 goto err; 1006 1007 /* Set M/N */ 1008 ret = tc_stream_clock_calc(tc); 1009 if (ret) 1010 goto err; 1011 1012 return 0; 1013 err_dpcd_read: 1014 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret); 1015 return ret; 1016 err_dpcd_write: 1017 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret); 1018 err: 1019 return ret; 1020 } 1021 1022 static int tc_main_link_stream(struct tc_data *tc, int state) 1023 { 1024 int ret; 1025 u32 value; 1026 1027 dev_dbg(tc->dev, "stream: %d\n", state); 1028 1029 if (state) { 1030 value = VID_MN_GEN | DP_EN; 1031 if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 1032 value |= EF_EN; 1033 tc_write(DP0CTL, value); 1034 /* 1035 * VID_EN assertion should be delayed by at least N * LSCLK 1036 * cycles from the time VID_MN_GEN is enabled in order to 1037 * generate stable values for VID_M. LSCLK is 270 MHz or 1038 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(), 1039 * so a delay of at least 203 us should suffice. 1040 */ 1041 usleep_range(500, 1000); 1042 value |= VID_EN; 1043 tc_write(DP0CTL, value); 1044 /* Set input interface */ 1045 value = DP0_AUDSRC_NO_INPUT; 1046 if (tc_test_pattern) 1047 value |= DP0_VIDSRC_COLOR_BAR; 1048 else 1049 value |= DP0_VIDSRC_DPI_RX; 1050 tc_write(SYSCTRL, value); 1051 } else { 1052 tc_write(DP0CTL, 0); 1053 } 1054 1055 return 0; 1056 err: 1057 return ret; 1058 } 1059 1060 static void tc_bridge_pre_enable(struct drm_bridge *bridge) 1061 { 1062 struct tc_data *tc = bridge_to_tc(bridge); 1063 1064 drm_panel_prepare(tc->panel); 1065 } 1066 1067 static void tc_bridge_enable(struct drm_bridge *bridge) 1068 { 1069 struct tc_data *tc = bridge_to_tc(bridge); 1070 int ret; 1071 1072 ret = tc_main_link_setup(tc); 1073 if (ret < 0) { 1074 dev_err(tc->dev, "main link setup error: %d\n", ret); 1075 return; 1076 } 1077 1078 ret = tc_main_link_stream(tc, 1); 1079 if (ret < 0) { 1080 dev_err(tc->dev, "main link stream start error: %d\n", ret); 1081 return; 1082 } 1083 1084 drm_panel_enable(tc->panel); 1085 } 1086 1087 static void tc_bridge_disable(struct drm_bridge *bridge) 1088 { 1089 struct tc_data *tc = bridge_to_tc(bridge); 1090 int ret; 1091 1092 drm_panel_disable(tc->panel); 1093 1094 ret = tc_main_link_stream(tc, 0); 1095 if (ret < 0) 1096 dev_err(tc->dev, "main link stream stop error: %d\n", ret); 1097 } 1098 1099 static void tc_bridge_post_disable(struct drm_bridge *bridge) 1100 { 1101 struct tc_data *tc = bridge_to_tc(bridge); 1102 1103 drm_panel_unprepare(tc->panel); 1104 } 1105 1106 static bool tc_bridge_mode_fixup(struct drm_bridge *bridge, 1107 const struct drm_display_mode *mode, 1108 struct drm_display_mode *adj) 1109 { 1110 /* Fixup sync polarities, both hsync and vsync are active low */ 1111 adj->flags = mode->flags; 1112 adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); 1113 adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 1114 1115 return true; 1116 } 1117 1118 static enum drm_mode_status tc_connector_mode_valid(struct drm_connector *connector, 1119 struct drm_display_mode *mode) 1120 { 1121 struct tc_data *tc = connector_to_tc(connector); 1122 u32 req, avail; 1123 u32 bits_per_pixel = 24; 1124 1125 /* DPI interface clock limitation: upto 154 MHz */ 1126 if (mode->clock > 154000) 1127 return MODE_CLOCK_HIGH; 1128 1129 req = mode->clock * bits_per_pixel / 8; 1130 avail = tc->link.base.num_lanes * tc->link.base.rate; 1131 1132 if (req > avail) 1133 return MODE_BAD; 1134 1135 return MODE_OK; 1136 } 1137 1138 static void tc_bridge_mode_set(struct drm_bridge *bridge, 1139 struct drm_display_mode *mode, 1140 struct drm_display_mode *adj) 1141 { 1142 struct tc_data *tc = bridge_to_tc(bridge); 1143 1144 tc->mode = mode; 1145 } 1146 1147 static int tc_connector_get_modes(struct drm_connector *connector) 1148 { 1149 struct tc_data *tc = connector_to_tc(connector); 1150 struct edid *edid; 1151 unsigned int count; 1152 1153 if (tc->panel && tc->panel->funcs && tc->panel->funcs->get_modes) { 1154 count = tc->panel->funcs->get_modes(tc->panel); 1155 if (count > 0) 1156 return count; 1157 } 1158 1159 edid = drm_get_edid(connector, &tc->aux.ddc); 1160 1161 kfree(tc->edid); 1162 tc->edid = edid; 1163 if (!edid) 1164 return 0; 1165 1166 drm_connector_update_edid_property(connector, edid); 1167 count = drm_add_edid_modes(connector, edid); 1168 1169 return count; 1170 } 1171 1172 static void tc_connector_set_polling(struct tc_data *tc, 1173 struct drm_connector *connector) 1174 { 1175 /* TODO: add support for HPD */ 1176 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1177 DRM_CONNECTOR_POLL_DISCONNECT; 1178 } 1179 1180 static struct drm_encoder * 1181 tc_connector_best_encoder(struct drm_connector *connector) 1182 { 1183 struct tc_data *tc = connector_to_tc(connector); 1184 1185 return tc->bridge.encoder; 1186 } 1187 1188 static const struct drm_connector_helper_funcs tc_connector_helper_funcs = { 1189 .get_modes = tc_connector_get_modes, 1190 .mode_valid = tc_connector_mode_valid, 1191 .best_encoder = tc_connector_best_encoder, 1192 }; 1193 1194 static const struct drm_connector_funcs tc_connector_funcs = { 1195 .fill_modes = drm_helper_probe_single_connector_modes, 1196 .destroy = drm_connector_cleanup, 1197 .reset = drm_atomic_helper_connector_reset, 1198 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1199 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1200 }; 1201 1202 static int tc_bridge_attach(struct drm_bridge *bridge) 1203 { 1204 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1205 struct tc_data *tc = bridge_to_tc(bridge); 1206 struct drm_device *drm = bridge->dev; 1207 int ret; 1208 1209 /* Create eDP connector */ 1210 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs); 1211 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, 1212 tc->panel ? DRM_MODE_CONNECTOR_eDP : 1213 DRM_MODE_CONNECTOR_DisplayPort); 1214 if (ret) 1215 return ret; 1216 1217 if (tc->panel) 1218 drm_panel_attach(tc->panel, &tc->connector); 1219 1220 drm_display_info_set_bus_formats(&tc->connector.display_info, 1221 &bus_format, 1); 1222 tc->connector.display_info.bus_flags = 1223 DRM_BUS_FLAG_DE_HIGH | 1224 DRM_BUS_FLAG_PIXDATA_NEGEDGE | 1225 DRM_BUS_FLAG_SYNC_NEGEDGE; 1226 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder); 1227 1228 return 0; 1229 } 1230 1231 static const struct drm_bridge_funcs tc_bridge_funcs = { 1232 .attach = tc_bridge_attach, 1233 .mode_set = tc_bridge_mode_set, 1234 .pre_enable = tc_bridge_pre_enable, 1235 .enable = tc_bridge_enable, 1236 .disable = tc_bridge_disable, 1237 .post_disable = tc_bridge_post_disable, 1238 .mode_fixup = tc_bridge_mode_fixup, 1239 }; 1240 1241 static bool tc_readable_reg(struct device *dev, unsigned int reg) 1242 { 1243 return reg != SYSCTRL; 1244 } 1245 1246 static const struct regmap_range tc_volatile_ranges[] = { 1247 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS), 1248 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ), 1249 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL), 1250 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL), 1251 regmap_reg_range(VFUEN0, VFUEN0), 1252 }; 1253 1254 static const struct regmap_access_table tc_volatile_table = { 1255 .yes_ranges = tc_volatile_ranges, 1256 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges), 1257 }; 1258 1259 static bool tc_writeable_reg(struct device *dev, unsigned int reg) 1260 { 1261 return (reg != TC_IDREG) && 1262 (reg != DP0_LTSTAT) && 1263 (reg != DP0_SNKLTCHGREQ); 1264 } 1265 1266 static const struct regmap_config tc_regmap_config = { 1267 .name = "tc358767", 1268 .reg_bits = 16, 1269 .val_bits = 32, 1270 .reg_stride = 4, 1271 .max_register = PLL_DBG, 1272 .cache_type = REGCACHE_RBTREE, 1273 .readable_reg = tc_readable_reg, 1274 .volatile_table = &tc_volatile_table, 1275 .writeable_reg = tc_writeable_reg, 1276 .reg_format_endian = REGMAP_ENDIAN_BIG, 1277 .val_format_endian = REGMAP_ENDIAN_LITTLE, 1278 }; 1279 1280 static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id) 1281 { 1282 struct device *dev = &client->dev; 1283 struct tc_data *tc; 1284 int ret; 1285 1286 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL); 1287 if (!tc) 1288 return -ENOMEM; 1289 1290 tc->dev = dev; 1291 1292 /* port@2 is the output port */ 1293 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL); 1294 if (ret && ret != -ENODEV) 1295 return ret; 1296 1297 /* Shut down GPIO is optional */ 1298 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH); 1299 if (IS_ERR(tc->sd_gpio)) 1300 return PTR_ERR(tc->sd_gpio); 1301 1302 if (tc->sd_gpio) { 1303 gpiod_set_value_cansleep(tc->sd_gpio, 0); 1304 usleep_range(5000, 10000); 1305 } 1306 1307 /* Reset GPIO is optional */ 1308 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1309 if (IS_ERR(tc->reset_gpio)) 1310 return PTR_ERR(tc->reset_gpio); 1311 1312 if (tc->reset_gpio) { 1313 gpiod_set_value_cansleep(tc->reset_gpio, 1); 1314 usleep_range(5000, 10000); 1315 } 1316 1317 tc->refclk = devm_clk_get(dev, "ref"); 1318 if (IS_ERR(tc->refclk)) { 1319 ret = PTR_ERR(tc->refclk); 1320 dev_err(dev, "Failed to get refclk: %d\n", ret); 1321 return ret; 1322 } 1323 1324 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config); 1325 if (IS_ERR(tc->regmap)) { 1326 ret = PTR_ERR(tc->regmap); 1327 dev_err(dev, "Failed to initialize regmap: %d\n", ret); 1328 return ret; 1329 } 1330 1331 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev); 1332 if (ret) { 1333 dev_err(tc->dev, "can not read device ID: %d\n", ret); 1334 return ret; 1335 } 1336 1337 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) { 1338 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev); 1339 return -EINVAL; 1340 } 1341 1342 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */ 1343 1344 ret = tc_aux_link_setup(tc); 1345 if (ret) 1346 return ret; 1347 1348 /* Register DP AUX channel */ 1349 tc->aux.name = "TC358767 AUX i2c adapter"; 1350 tc->aux.dev = tc->dev; 1351 tc->aux.transfer = tc_aux_transfer; 1352 ret = drm_dp_aux_register(&tc->aux); 1353 if (ret) 1354 return ret; 1355 1356 ret = tc_get_display_props(tc); 1357 if (ret) 1358 goto err_unregister_aux; 1359 1360 tc_connector_set_polling(tc, &tc->connector); 1361 1362 tc->bridge.funcs = &tc_bridge_funcs; 1363 tc->bridge.of_node = dev->of_node; 1364 drm_bridge_add(&tc->bridge); 1365 1366 i2c_set_clientdata(client, tc); 1367 1368 return 0; 1369 err_unregister_aux: 1370 drm_dp_aux_unregister(&tc->aux); 1371 return ret; 1372 } 1373 1374 static int tc_remove(struct i2c_client *client) 1375 { 1376 struct tc_data *tc = i2c_get_clientdata(client); 1377 1378 drm_bridge_remove(&tc->bridge); 1379 drm_dp_aux_unregister(&tc->aux); 1380 1381 tc_pxl_pll_dis(tc); 1382 1383 return 0; 1384 } 1385 1386 static const struct i2c_device_id tc358767_i2c_ids[] = { 1387 { "tc358767", 0 }, 1388 { } 1389 }; 1390 MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids); 1391 1392 static const struct of_device_id tc358767_of_ids[] = { 1393 { .compatible = "toshiba,tc358767", }, 1394 { } 1395 }; 1396 MODULE_DEVICE_TABLE(of, tc358767_of_ids); 1397 1398 static struct i2c_driver tc358767_driver = { 1399 .driver = { 1400 .name = "tc358767", 1401 .of_match_table = tc358767_of_ids, 1402 }, 1403 .id_table = tc358767_i2c_ids, 1404 .probe = tc_probe, 1405 .remove = tc_remove, 1406 }; 1407 module_i2c_driver(tc358767_driver); 1408 1409 MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>"); 1410 MODULE_DESCRIPTION("tc358767 eDP encoder driver"); 1411 MODULE_LICENSE("GPL"); 1412