1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * tc358767 eDP bridge driver 4 * 5 * Copyright (C) 2016 CogentEmbedded Inc 6 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com> 7 * 8 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de> 9 * 10 * Copyright (C) 2016 Zodiac Inflight Innovations 11 * 12 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c 13 * 14 * Copyright (C) 2012 Texas Instruments 15 * Author: Rob Clark <robdclark@gmail.com> 16 */ 17 18 #include <linux/bitfield.h> 19 #include <linux/clk.h> 20 #include <linux/device.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/i2c.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/regmap.h> 26 #include <linux/slab.h> 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_dp_helper.h> 30 #include <drm/drm_edid.h> 31 #include <drm/drm_of.h> 32 #include <drm/drm_panel.h> 33 #include <drm/drm_probe_helper.h> 34 35 /* Registers */ 36 37 /* Display Parallel Interface */ 38 #define DPIPXLFMT 0x0440 39 #define VS_POL_ACTIVE_LOW (1 << 10) 40 #define HS_POL_ACTIVE_LOW (1 << 9) 41 #define DE_POL_ACTIVE_HIGH (0 << 8) 42 #define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */ 43 #define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */ 44 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */ 45 #define DPI_BPP_RGB888 (0 << 0) 46 #define DPI_BPP_RGB666 (1 << 0) 47 #define DPI_BPP_RGB565 (2 << 0) 48 49 /* Video Path */ 50 #define VPCTRL0 0x0450 51 #define VSDELAY GENMASK(31, 20) 52 #define OPXLFMT_RGB666 (0 << 8) 53 #define OPXLFMT_RGB888 (1 << 8) 54 #define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */ 55 #define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */ 56 #define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */ 57 #define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */ 58 #define HTIM01 0x0454 59 #define HPW GENMASK(8, 0) 60 #define HBPR GENMASK(24, 16) 61 #define HTIM02 0x0458 62 #define HDISPR GENMASK(10, 0) 63 #define HFPR GENMASK(24, 16) 64 #define VTIM01 0x045c 65 #define VSPR GENMASK(7, 0) 66 #define VBPR GENMASK(23, 16) 67 #define VTIM02 0x0460 68 #define VFPR GENMASK(23, 16) 69 #define VDISPR GENMASK(10, 0) 70 #define VFUEN0 0x0464 71 #define VFUEN BIT(0) /* Video Frame Timing Upload */ 72 73 /* System */ 74 #define TC_IDREG 0x0500 75 #define SYSSTAT 0x0508 76 #define SYSCTRL 0x0510 77 #define DP0_AUDSRC_NO_INPUT (0 << 3) 78 #define DP0_AUDSRC_I2S_RX (1 << 3) 79 #define DP0_VIDSRC_NO_INPUT (0 << 0) 80 #define DP0_VIDSRC_DSI_RX (1 << 0) 81 #define DP0_VIDSRC_DPI_RX (2 << 0) 82 #define DP0_VIDSRC_COLOR_BAR (3 << 0) 83 #define SYSRSTENB 0x050c 84 #define ENBI2C (1 << 0) 85 #define ENBLCD0 (1 << 2) 86 #define ENBBM (1 << 3) 87 #define ENBDSIRX (1 << 4) 88 #define ENBREG (1 << 5) 89 #define ENBHDCP (1 << 8) 90 #define GPIOM 0x0540 91 #define GPIOC 0x0544 92 #define GPIOO 0x0548 93 #define GPIOI 0x054c 94 #define INTCTL_G 0x0560 95 #define INTSTS_G 0x0564 96 97 #define INT_SYSERR BIT(16) 98 #define INT_GPIO_H(x) (1 << (x == 0 ? 2 : 10)) 99 #define INT_GPIO_LC(x) (1 << (x == 0 ? 3 : 11)) 100 101 #define INT_GP0_LCNT 0x0584 102 #define INT_GP1_LCNT 0x0588 103 104 /* Control */ 105 #define DP0CTL 0x0600 106 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */ 107 #define EF_EN BIT(5) /* Enable Enhanced Framing */ 108 #define VID_EN BIT(1) /* Video transmission enable */ 109 #define DP_EN BIT(0) /* Enable DPTX function */ 110 111 /* Clocks */ 112 #define DP0_VIDMNGEN0 0x0610 113 #define DP0_VIDMNGEN1 0x0614 114 #define DP0_VMNGENSTATUS 0x0618 115 116 /* Main Channel */ 117 #define DP0_SECSAMPLE 0x0640 118 #define DP0_VIDSYNCDELAY 0x0644 119 #define VID_SYNC_DLY GENMASK(15, 0) 120 #define THRESH_DLY GENMASK(31, 16) 121 122 #define DP0_TOTALVAL 0x0648 123 #define H_TOTAL GENMASK(15, 0) 124 #define V_TOTAL GENMASK(31, 16) 125 #define DP0_STARTVAL 0x064c 126 #define H_START GENMASK(15, 0) 127 #define V_START GENMASK(31, 16) 128 #define DP0_ACTIVEVAL 0x0650 129 #define H_ACT GENMASK(15, 0) 130 #define V_ACT GENMASK(31, 16) 131 132 #define DP0_SYNCVAL 0x0654 133 #define VS_WIDTH GENMASK(30, 16) 134 #define HS_WIDTH GENMASK(14, 0) 135 #define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15) 136 #define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31) 137 #define DP0_MISC 0x0658 138 #define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */ 139 #define MAX_TU_SYMBOL GENMASK(28, 23) 140 #define TU_SIZE GENMASK(21, 16) 141 #define BPC_6 (0 << 5) 142 #define BPC_8 (1 << 5) 143 144 /* AUX channel */ 145 #define DP0_AUXCFG0 0x0660 146 #define DP0_AUXCFG0_BSIZE GENMASK(11, 8) 147 #define DP0_AUXCFG0_ADDR_ONLY BIT(4) 148 #define DP0_AUXCFG1 0x0664 149 #define AUX_RX_FILTER_EN BIT(16) 150 151 #define DP0_AUXADDR 0x0668 152 #define DP0_AUXWDATA(i) (0x066c + (i) * 4) 153 #define DP0_AUXRDATA(i) (0x067c + (i) * 4) 154 #define DP0_AUXSTATUS 0x068c 155 #define AUX_BYTES GENMASK(15, 8) 156 #define AUX_STATUS GENMASK(7, 4) 157 #define AUX_TIMEOUT BIT(1) 158 #define AUX_BUSY BIT(0) 159 #define DP0_AUXI2CADR 0x0698 160 161 /* Link Training */ 162 #define DP0_SRCCTRL 0x06a0 163 #define DP0_SRCCTRL_SCRMBLDIS BIT(13) 164 #define DP0_SRCCTRL_EN810B BIT(12) 165 #define DP0_SRCCTRL_NOTP (0 << 8) 166 #define DP0_SRCCTRL_TP1 (1 << 8) 167 #define DP0_SRCCTRL_TP2 (2 << 8) 168 #define DP0_SRCCTRL_LANESKEW BIT(7) 169 #define DP0_SRCCTRL_SSCG BIT(3) 170 #define DP0_SRCCTRL_LANES_1 (0 << 2) 171 #define DP0_SRCCTRL_LANES_2 (1 << 2) 172 #define DP0_SRCCTRL_BW27 (1 << 1) 173 #define DP0_SRCCTRL_BW162 (0 << 1) 174 #define DP0_SRCCTRL_AUTOCORRECT BIT(0) 175 #define DP0_LTSTAT 0x06d0 176 #define LT_LOOPDONE BIT(13) 177 #define LT_STATUS_MASK (0x1f << 8) 178 #define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4) 179 #define LT_INTERLANE_ALIGN_DONE BIT(3) 180 #define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS) 181 #define DP0_SNKLTCHGREQ 0x06d4 182 #define DP0_LTLOOPCTRL 0x06d8 183 #define DP0_SNKLTCTRL 0x06e4 184 185 #define DP1_SRCCTRL 0x07a0 186 187 /* PHY */ 188 #define DP_PHY_CTRL 0x0800 189 #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */ 190 #define BGREN BIT(25) /* AUX PHY BGR Enable */ 191 #define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */ 192 #define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */ 193 #define PHY_RDY BIT(16) /* PHY Main Channels Ready */ 194 #define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */ 195 #define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */ 196 #define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */ 197 #define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */ 198 199 /* PLL */ 200 #define DP0_PLLCTRL 0x0900 201 #define DP1_PLLCTRL 0x0904 /* not defined in DS */ 202 #define PXL_PLLCTRL 0x0908 203 #define PLLUPDATE BIT(2) 204 #define PLLBYP BIT(1) 205 #define PLLEN BIT(0) 206 #define PXL_PLLPARAM 0x0914 207 #define IN_SEL_REFCLK (0 << 14) 208 #define SYS_PLLPARAM 0x0918 209 #define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */ 210 #define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */ 211 #define REF_FREQ_26M (2 << 8) /* 26 MHz */ 212 #define REF_FREQ_13M (3 << 8) /* 13 MHz */ 213 #define SYSCLK_SEL_LSCLK (0 << 4) 214 #define LSCLK_DIV_1 (0 << 0) 215 #define LSCLK_DIV_2 (1 << 0) 216 217 /* Test & Debug */ 218 #define TSTCTL 0x0a00 219 #define COLOR_R GENMASK(31, 24) 220 #define COLOR_G GENMASK(23, 16) 221 #define COLOR_B GENMASK(15, 8) 222 #define ENI2CFILTER BIT(4) 223 #define COLOR_BAR_MODE GENMASK(1, 0) 224 #define COLOR_BAR_MODE_BARS 2 225 #define PLL_DBG 0x0a04 226 227 static bool tc_test_pattern; 228 module_param_named(test, tc_test_pattern, bool, 0644); 229 230 struct tc_edp_link { 231 struct drm_dp_link base; 232 u8 assr; 233 bool scrambler_dis; 234 bool spread; 235 }; 236 237 struct tc_data { 238 struct device *dev; 239 struct regmap *regmap; 240 struct drm_dp_aux aux; 241 242 struct drm_bridge bridge; 243 struct drm_connector connector; 244 struct drm_panel *panel; 245 246 /* link settings */ 247 struct tc_edp_link link; 248 249 /* display edid */ 250 struct edid *edid; 251 /* current mode */ 252 struct drm_display_mode mode; 253 254 u32 rev; 255 u8 assr; 256 257 struct gpio_desc *sd_gpio; 258 struct gpio_desc *reset_gpio; 259 struct clk *refclk; 260 261 /* do we have IRQ */ 262 bool have_irq; 263 264 /* HPD pin number (0 or 1) or -ENODEV */ 265 int hpd_pin; 266 }; 267 268 static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a) 269 { 270 return container_of(a, struct tc_data, aux); 271 } 272 273 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b) 274 { 275 return container_of(b, struct tc_data, bridge); 276 } 277 278 static inline struct tc_data *connector_to_tc(struct drm_connector *c) 279 { 280 return container_of(c, struct tc_data, connector); 281 } 282 283 static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr, 284 unsigned int cond_mask, 285 unsigned int cond_value, 286 unsigned long sleep_us, u64 timeout_us) 287 { 288 unsigned int val; 289 290 return regmap_read_poll_timeout(tc->regmap, addr, val, 291 (val & cond_mask) == cond_value, 292 sleep_us, timeout_us); 293 } 294 295 static int tc_aux_wait_busy(struct tc_data *tc) 296 { 297 return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 1000, 100000); 298 } 299 300 static int tc_aux_write_data(struct tc_data *tc, const void *data, 301 size_t size) 302 { 303 u32 auxwdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)] = { 0 }; 304 int ret, count = ALIGN(size, sizeof(u32)); 305 306 memcpy(auxwdata, data, size); 307 308 ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count); 309 if (ret) 310 return ret; 311 312 return size; 313 } 314 315 static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size) 316 { 317 u32 auxrdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)]; 318 int ret, count = ALIGN(size, sizeof(u32)); 319 320 ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count); 321 if (ret) 322 return ret; 323 324 memcpy(data, auxrdata, size); 325 326 return size; 327 } 328 329 static u32 tc_auxcfg0(struct drm_dp_aux_msg *msg, size_t size) 330 { 331 u32 auxcfg0 = msg->request; 332 333 if (size) 334 auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1); 335 else 336 auxcfg0 |= DP0_AUXCFG0_ADDR_ONLY; 337 338 return auxcfg0; 339 } 340 341 static ssize_t tc_aux_transfer(struct drm_dp_aux *aux, 342 struct drm_dp_aux_msg *msg) 343 { 344 struct tc_data *tc = aux_to_tc(aux); 345 size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size); 346 u8 request = msg->request & ~DP_AUX_I2C_MOT; 347 u32 auxstatus; 348 int ret; 349 350 ret = tc_aux_wait_busy(tc); 351 if (ret) 352 return ret; 353 354 switch (request) { 355 case DP_AUX_NATIVE_READ: 356 case DP_AUX_I2C_READ: 357 break; 358 case DP_AUX_NATIVE_WRITE: 359 case DP_AUX_I2C_WRITE: 360 if (size) { 361 ret = tc_aux_write_data(tc, msg->buffer, size); 362 if (ret < 0) 363 return ret; 364 } 365 break; 366 default: 367 return -EINVAL; 368 } 369 370 /* Store address */ 371 ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address); 372 if (ret) 373 return ret; 374 /* Start transfer */ 375 ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size)); 376 if (ret) 377 return ret; 378 379 ret = tc_aux_wait_busy(tc); 380 if (ret) 381 return ret; 382 383 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus); 384 if (ret) 385 return ret; 386 387 if (auxstatus & AUX_TIMEOUT) 388 return -ETIMEDOUT; 389 /* 390 * For some reason address-only DP_AUX_I2C_WRITE (MOT), still 391 * reports 1 byte transferred in its status. To deal we that 392 * we ignore aux_bytes field if we know that this was an 393 * address-only transfer 394 */ 395 if (size) 396 size = FIELD_GET(AUX_BYTES, auxstatus); 397 msg->reply = FIELD_GET(AUX_STATUS, auxstatus); 398 399 switch (request) { 400 case DP_AUX_NATIVE_READ: 401 case DP_AUX_I2C_READ: 402 if (size) 403 return tc_aux_read_data(tc, msg->buffer, size); 404 break; 405 } 406 407 return size; 408 } 409 410 static const char * const training_pattern1_errors[] = { 411 "No errors", 412 "Aux write error", 413 "Aux read error", 414 "Max voltage reached error", 415 "Loop counter expired error", 416 "res", "res", "res" 417 }; 418 419 static const char * const training_pattern2_errors[] = { 420 "No errors", 421 "Aux write error", 422 "Aux read error", 423 "Clock recovery failed error", 424 "Loop counter expired error", 425 "res", "res", "res" 426 }; 427 428 static u32 tc_srcctrl(struct tc_data *tc) 429 { 430 /* 431 * No training pattern, skew lane 1 data by two LSCLK cycles with 432 * respect to lane 0 data, AutoCorrect Mode = 0 433 */ 434 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B; 435 436 if (tc->link.scrambler_dis) 437 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */ 438 if (tc->link.spread) 439 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */ 440 if (tc->link.base.num_lanes == 2) 441 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */ 442 if (tc->link.base.rate != 162000) 443 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */ 444 return reg; 445 } 446 447 static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl) 448 { 449 int ret; 450 451 ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN); 452 if (ret) 453 return ret; 454 455 /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */ 456 usleep_range(3000, 6000); 457 458 return 0; 459 } 460 461 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) 462 { 463 int ret; 464 int i_pre, best_pre = 1; 465 int i_post, best_post = 1; 466 int div, best_div = 1; 467 int mul, best_mul = 1; 468 int delta, best_delta; 469 int ext_div[] = {1, 2, 3, 5, 7}; 470 int best_pixelclock = 0; 471 int vco_hi = 0; 472 u32 pxl_pllparam; 473 474 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock, 475 refclk); 476 best_delta = pixelclock; 477 /* Loop over all possible ext_divs, skipping invalid configurations */ 478 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) { 479 /* 480 * refclk / ext_pre_div should be in the 1 to 200 MHz range. 481 * We don't allow any refclk > 200 MHz, only check lower bounds. 482 */ 483 if (refclk / ext_div[i_pre] < 1000000) 484 continue; 485 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) { 486 for (div = 1; div <= 16; div++) { 487 u32 clk; 488 u64 tmp; 489 490 tmp = pixelclock * ext_div[i_pre] * 491 ext_div[i_post] * div; 492 do_div(tmp, refclk); 493 mul = tmp; 494 495 /* Check limits */ 496 if ((mul < 1) || (mul > 128)) 497 continue; 498 499 clk = (refclk / ext_div[i_pre] / div) * mul; 500 /* 501 * refclk * mul / (ext_pre_div * pre_div) 502 * should be in the 150 to 650 MHz range 503 */ 504 if ((clk > 650000000) || (clk < 150000000)) 505 continue; 506 507 clk = clk / ext_div[i_post]; 508 delta = clk - pixelclock; 509 510 if (abs(delta) < abs(best_delta)) { 511 best_pre = i_pre; 512 best_post = i_post; 513 best_div = div; 514 best_mul = mul; 515 best_delta = delta; 516 best_pixelclock = clk; 517 } 518 } 519 } 520 } 521 if (best_pixelclock == 0) { 522 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n", 523 pixelclock); 524 return -EINVAL; 525 } 526 527 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock, 528 best_delta); 529 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk, 530 ext_div[best_pre], best_div, best_mul, ext_div[best_post]); 531 532 /* if VCO >= 300 MHz */ 533 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000) 534 vco_hi = 1; 535 /* see DS */ 536 if (best_div == 16) 537 best_div = 0; 538 if (best_mul == 128) 539 best_mul = 0; 540 541 /* Power up PLL and switch to bypass */ 542 ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN); 543 if (ret) 544 return ret; 545 546 pxl_pllparam = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */ 547 pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */ 548 pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */ 549 pxl_pllparam |= IN_SEL_REFCLK; /* Use RefClk as PLL input */ 550 pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */ 551 pxl_pllparam |= best_mul; /* Multiplier for PLL */ 552 553 ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam); 554 if (ret) 555 return ret; 556 557 /* Force PLL parameter update and disable bypass */ 558 return tc_pllupdate(tc, PXL_PLLCTRL); 559 } 560 561 static int tc_pxl_pll_dis(struct tc_data *tc) 562 { 563 /* Enable PLL bypass, power down PLL */ 564 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP); 565 } 566 567 static int tc_stream_clock_calc(struct tc_data *tc) 568 { 569 /* 570 * If the Stream clock and Link Symbol clock are 571 * asynchronous with each other, the value of M changes over 572 * time. This way of generating link clock and stream 573 * clock is called Asynchronous Clock mode. The value M 574 * must change while the value N stays constant. The 575 * value of N in this Asynchronous Clock mode must be set 576 * to 2^15 or 32,768. 577 * 578 * LSCLK = 1/10 of high speed link clock 579 * 580 * f_STRMCLK = M/N * f_LSCLK 581 * M/N = f_STRMCLK / f_LSCLK 582 * 583 */ 584 return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768); 585 } 586 587 static int tc_set_syspllparam(struct tc_data *tc) 588 { 589 unsigned long rate; 590 u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2; 591 592 rate = clk_get_rate(tc->refclk); 593 switch (rate) { 594 case 38400000: 595 pllparam |= REF_FREQ_38M4; 596 break; 597 case 26000000: 598 pllparam |= REF_FREQ_26M; 599 break; 600 case 19200000: 601 pllparam |= REF_FREQ_19M2; 602 break; 603 case 13000000: 604 pllparam |= REF_FREQ_13M; 605 break; 606 default: 607 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate); 608 return -EINVAL; 609 } 610 611 return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam); 612 } 613 614 static int tc_aux_link_setup(struct tc_data *tc) 615 { 616 int ret; 617 u32 dp0_auxcfg1; 618 619 /* Setup DP-PHY / PLL */ 620 ret = tc_set_syspllparam(tc); 621 if (ret) 622 goto err; 623 624 ret = regmap_write(tc->regmap, DP_PHY_CTRL, 625 BGREN | PWR_SW_EN | PHY_A0_EN); 626 if (ret) 627 goto err; 628 /* 629 * Initially PLLs are in bypass. Force PLL parameter update, 630 * disable PLL bypass, enable PLL 631 */ 632 ret = tc_pllupdate(tc, DP0_PLLCTRL); 633 if (ret) 634 goto err; 635 636 ret = tc_pllupdate(tc, DP1_PLLCTRL); 637 if (ret) 638 goto err; 639 640 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 1000); 641 if (ret == -ETIMEDOUT) { 642 dev_err(tc->dev, "Timeout waiting for PHY to become ready"); 643 return ret; 644 } else if (ret) { 645 goto err; 646 } 647 648 /* Setup AUX link */ 649 dp0_auxcfg1 = AUX_RX_FILTER_EN; 650 dp0_auxcfg1 |= 0x06 << 8; /* Aux Bit Period Calculator Threshold */ 651 dp0_auxcfg1 |= 0x3f << 0; /* Aux Response Timeout Timer */ 652 653 ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1); 654 if (ret) 655 goto err; 656 657 return 0; 658 err: 659 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret); 660 return ret; 661 } 662 663 static int tc_get_display_props(struct tc_data *tc) 664 { 665 int ret; 666 u8 reg; 667 668 /* Read DP Rx Link Capability */ 669 ret = drm_dp_link_probe(&tc->aux, &tc->link.base); 670 if (ret < 0) 671 goto err_dpcd_read; 672 if (tc->link.base.rate != 162000 && tc->link.base.rate != 270000) { 673 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n"); 674 tc->link.base.rate = 270000; 675 } 676 677 if (tc->link.base.num_lanes > 2) { 678 dev_dbg(tc->dev, "Falling to 2 lanes\n"); 679 tc->link.base.num_lanes = 2; 680 } 681 682 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, ®); 683 if (ret < 0) 684 goto err_dpcd_read; 685 tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5; 686 687 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, ®); 688 if (ret < 0) 689 goto err_dpcd_read; 690 691 tc->link.scrambler_dis = false; 692 /* read assr */ 693 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, ®); 694 if (ret < 0) 695 goto err_dpcd_read; 696 tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; 697 698 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n", 699 tc->link.base.revision >> 4, tc->link.base.revision & 0x0f, 700 (tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps", 701 tc->link.base.num_lanes, 702 (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ? 703 "enhanced" : "non-enhanced"); 704 dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n", 705 tc->link.spread ? "0.5%" : "0.0%", 706 tc->link.scrambler_dis ? "disabled" : "enabled"); 707 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n", 708 tc->link.assr, tc->assr); 709 710 return 0; 711 712 err_dpcd_read: 713 dev_err(tc->dev, "failed to read DPCD: %d\n", ret); 714 return ret; 715 } 716 717 static int tc_set_video_mode(struct tc_data *tc, 718 const struct drm_display_mode *mode) 719 { 720 int ret; 721 int vid_sync_dly; 722 int max_tu_symbol; 723 724 int left_margin = mode->htotal - mode->hsync_end; 725 int right_margin = mode->hsync_start - mode->hdisplay; 726 int hsync_len = mode->hsync_end - mode->hsync_start; 727 int upper_margin = mode->vtotal - mode->vsync_end; 728 int lower_margin = mode->vsync_start - mode->vdisplay; 729 int vsync_len = mode->vsync_end - mode->vsync_start; 730 u32 dp0_syncval; 731 732 /* 733 * Recommended maximum number of symbols transferred in a transfer unit: 734 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size, 735 * (output active video bandwidth in bytes)) 736 * Must be less than tu_size. 737 */ 738 max_tu_symbol = TU_SIZE_RECOMMENDED - 1; 739 740 dev_dbg(tc->dev, "set mode %dx%d\n", 741 mode->hdisplay, mode->vdisplay); 742 dev_dbg(tc->dev, "H margin %d,%d sync %d\n", 743 left_margin, right_margin, hsync_len); 744 dev_dbg(tc->dev, "V margin %d,%d sync %d\n", 745 upper_margin, lower_margin, vsync_len); 746 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal); 747 748 749 /* 750 * LCD Ctl Frame Size 751 * datasheet is not clear of vsdelay in case of DPI 752 * assume we do not need any delay when DPI is a source of 753 * sync signals 754 */ 755 ret = regmap_write(tc->regmap, VPCTRL0, 756 FIELD_PREP(VSDELAY, 0) | 757 OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED); 758 if (ret) 759 return ret; 760 761 ret = regmap_write(tc->regmap, HTIM01, 762 FIELD_PREP(HBPR, ALIGN(left_margin, 2)) | 763 FIELD_PREP(HPW, ALIGN(hsync_len, 2))); 764 if (ret) 765 return ret; 766 767 ret = regmap_write(tc->regmap, HTIM02, 768 FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) | 769 FIELD_PREP(HFPR, ALIGN(right_margin, 2))); 770 if (ret) 771 return ret; 772 773 ret = regmap_write(tc->regmap, VTIM01, 774 FIELD_PREP(VBPR, upper_margin) | 775 FIELD_PREP(VSPR, vsync_len)); 776 if (ret) 777 return ret; 778 779 ret = regmap_write(tc->regmap, VTIM02, 780 FIELD_PREP(VFPR, lower_margin) | 781 FIELD_PREP(VDISPR, mode->vdisplay)); 782 if (ret) 783 return ret; 784 785 ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */ 786 if (ret) 787 return ret; 788 789 /* Test pattern settings */ 790 ret = regmap_write(tc->regmap, TSTCTL, 791 FIELD_PREP(COLOR_R, 120) | 792 FIELD_PREP(COLOR_G, 20) | 793 FIELD_PREP(COLOR_B, 99) | 794 ENI2CFILTER | 795 FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS)); 796 if (ret) 797 return ret; 798 799 /* DP Main Stream Attributes */ 800 vid_sync_dly = hsync_len + left_margin + mode->hdisplay; 801 ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY, 802 FIELD_PREP(THRESH_DLY, max_tu_symbol) | 803 FIELD_PREP(VID_SYNC_DLY, vid_sync_dly)); 804 805 ret = regmap_write(tc->regmap, DP0_TOTALVAL, 806 FIELD_PREP(H_TOTAL, mode->htotal) | 807 FIELD_PREP(V_TOTAL, mode->vtotal)); 808 if (ret) 809 return ret; 810 811 ret = regmap_write(tc->regmap, DP0_STARTVAL, 812 FIELD_PREP(H_START, left_margin + hsync_len) | 813 FIELD_PREP(V_START, upper_margin + vsync_len)); 814 if (ret) 815 return ret; 816 817 ret = regmap_write(tc->regmap, DP0_ACTIVEVAL, 818 FIELD_PREP(V_ACT, mode->vdisplay) | 819 FIELD_PREP(H_ACT, mode->hdisplay)); 820 if (ret) 821 return ret; 822 823 dp0_syncval = FIELD_PREP(VS_WIDTH, vsync_len) | 824 FIELD_PREP(HS_WIDTH, hsync_len); 825 826 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 827 dp0_syncval |= SYNCVAL_VS_POL_ACTIVE_LOW; 828 829 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 830 dp0_syncval |= SYNCVAL_HS_POL_ACTIVE_LOW; 831 832 ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval); 833 if (ret) 834 return ret; 835 836 ret = regmap_write(tc->regmap, DPIPXLFMT, 837 VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW | 838 DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | 839 DPI_BPP_RGB888); 840 if (ret) 841 return ret; 842 843 ret = regmap_write(tc->regmap, DP0_MISC, 844 FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) | 845 FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) | 846 BPC_8); 847 if (ret) 848 return ret; 849 850 return 0; 851 } 852 853 static int tc_wait_link_training(struct tc_data *tc) 854 { 855 u32 value; 856 int ret; 857 858 ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE, 859 LT_LOOPDONE, 1, 1000); 860 if (ret) { 861 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n"); 862 return ret; 863 } 864 865 ret = regmap_read(tc->regmap, DP0_LTSTAT, &value); 866 if (ret) 867 return ret; 868 869 return (value >> 8) & 0x7; 870 } 871 872 static int tc_main_link_enable(struct tc_data *tc) 873 { 874 struct drm_dp_aux *aux = &tc->aux; 875 struct device *dev = tc->dev; 876 u32 dp_phy_ctrl; 877 u32 value; 878 int ret; 879 u8 tmp[DP_LINK_STATUS_SIZE]; 880 881 dev_dbg(tc->dev, "link enable\n"); 882 883 ret = regmap_read(tc->regmap, DP0CTL, &value); 884 if (ret) 885 return ret; 886 887 if (WARN_ON(value & DP_EN)) { 888 ret = regmap_write(tc->regmap, DP0CTL, 0); 889 if (ret) 890 return ret; 891 } 892 893 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc)); 894 if (ret) 895 return ret; 896 /* SSCG and BW27 on DP1 must be set to the same as on DP0 */ 897 ret = regmap_write(tc->regmap, DP1_SRCCTRL, 898 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) | 899 ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0)); 900 if (ret) 901 return ret; 902 903 ret = tc_set_syspllparam(tc); 904 if (ret) 905 return ret; 906 907 /* Setup Main Link */ 908 dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN; 909 if (tc->link.base.num_lanes == 2) 910 dp_phy_ctrl |= PHY_2LANE; 911 912 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); 913 if (ret) 914 return ret; 915 916 /* PLL setup */ 917 ret = tc_pllupdate(tc, DP0_PLLCTRL); 918 if (ret) 919 return ret; 920 921 ret = tc_pllupdate(tc, DP1_PLLCTRL); 922 if (ret) 923 return ret; 924 925 /* Reset/Enable Main Links */ 926 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST; 927 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); 928 usleep_range(100, 200); 929 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST); 930 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); 931 932 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 1000); 933 if (ret) { 934 dev_err(dev, "timeout waiting for phy become ready"); 935 return ret; 936 } 937 938 /* Set misc: 8 bits per color */ 939 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8); 940 if (ret) 941 return ret; 942 943 /* 944 * ASSR mode 945 * on TC358767 side ASSR configured through strap pin 946 * seems there is no way to change this setting from SW 947 * 948 * check is tc configured for same mode 949 */ 950 if (tc->assr != tc->link.assr) { 951 dev_dbg(dev, "Trying to set display to ASSR: %d\n", 952 tc->assr); 953 /* try to set ASSR on display side */ 954 tmp[0] = tc->assr; 955 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]); 956 if (ret < 0) 957 goto err_dpcd_read; 958 /* read back */ 959 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp); 960 if (ret < 0) 961 goto err_dpcd_read; 962 963 if (tmp[0] != tc->assr) { 964 dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n", 965 tc->assr); 966 /* trying with disabled scrambler */ 967 tc->link.scrambler_dis = true; 968 } 969 } 970 971 /* Setup Link & DPRx Config for Training */ 972 ret = drm_dp_link_configure(aux, &tc->link.base); 973 if (ret < 0) 974 goto err_dpcd_write; 975 976 /* DOWNSPREAD_CTRL */ 977 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00; 978 /* MAIN_LINK_CHANNEL_CODING_SET */ 979 tmp[1] = DP_SET_ANSI_8B10B; 980 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2); 981 if (ret < 0) 982 goto err_dpcd_write; 983 984 /* Reset voltage-swing & pre-emphasis */ 985 tmp[0] = tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 986 DP_TRAIN_PRE_EMPH_LEVEL_0; 987 ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2); 988 if (ret < 0) 989 goto err_dpcd_write; 990 991 /* Clock-Recovery */ 992 993 /* Set DPCD 0x102 for Training Pattern 1 */ 994 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL, 995 DP_LINK_SCRAMBLING_DISABLE | 996 DP_TRAINING_PATTERN_1); 997 if (ret) 998 return ret; 999 1000 ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL, 1001 (15 << 28) | /* Defer Iteration Count */ 1002 (15 << 24) | /* Loop Iteration Count */ 1003 (0xd << 0)); /* Loop Timer Delay */ 1004 if (ret) 1005 return ret; 1006 1007 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 1008 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | 1009 DP0_SRCCTRL_AUTOCORRECT | 1010 DP0_SRCCTRL_TP1); 1011 if (ret) 1012 return ret; 1013 1014 /* Enable DP0 to start Link Training */ 1015 ret = regmap_write(tc->regmap, DP0CTL, 1016 ((tc->link.base.capabilities & 1017 DP_LINK_CAP_ENHANCED_FRAMING) ? EF_EN : 0) | 1018 DP_EN); 1019 if (ret) 1020 return ret; 1021 1022 /* wait */ 1023 1024 ret = tc_wait_link_training(tc); 1025 if (ret < 0) 1026 return ret; 1027 1028 if (ret) { 1029 dev_err(tc->dev, "Link training phase 1 failed: %s\n", 1030 training_pattern1_errors[ret]); 1031 return -ENODEV; 1032 } 1033 1034 /* Channel Equalization */ 1035 1036 /* Set DPCD 0x102 for Training Pattern 2 */ 1037 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL, 1038 DP_LINK_SCRAMBLING_DISABLE | 1039 DP_TRAINING_PATTERN_2); 1040 if (ret) 1041 return ret; 1042 1043 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 1044 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | 1045 DP0_SRCCTRL_AUTOCORRECT | 1046 DP0_SRCCTRL_TP2); 1047 if (ret) 1048 return ret; 1049 1050 /* wait */ 1051 ret = tc_wait_link_training(tc); 1052 if (ret < 0) 1053 return ret; 1054 1055 if (ret) { 1056 dev_err(tc->dev, "Link training phase 2 failed: %s\n", 1057 training_pattern2_errors[ret]); 1058 return -ENODEV; 1059 } 1060 1061 /* 1062 * Toshiba's documentation suggests to first clear DPCD 0x102, then 1063 * clear the training pattern bit in DP0_SRCCTRL. Testing shows 1064 * that the link sometimes drops if those steps are done in that order, 1065 * but if the steps are done in reverse order, the link stays up. 1066 * 1067 * So we do the steps differently than documented here. 1068 */ 1069 1070 /* Clear Training Pattern, set AutoCorrect Mode = 1 */ 1071 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) | 1072 DP0_SRCCTRL_AUTOCORRECT); 1073 if (ret) 1074 return ret; 1075 1076 /* Clear DPCD 0x102 */ 1077 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */ 1078 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00; 1079 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]); 1080 if (ret < 0) 1081 goto err_dpcd_write; 1082 1083 /* Check link status */ 1084 ret = drm_dp_dpcd_read_link_status(aux, tmp); 1085 if (ret < 0) 1086 goto err_dpcd_read; 1087 1088 ret = 0; 1089 1090 value = tmp[0] & DP_CHANNEL_EQ_BITS; 1091 1092 if (value != DP_CHANNEL_EQ_BITS) { 1093 dev_err(tc->dev, "Lane 0 failed: %x\n", value); 1094 ret = -ENODEV; 1095 } 1096 1097 if (tc->link.base.num_lanes == 2) { 1098 value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS; 1099 1100 if (value != DP_CHANNEL_EQ_BITS) { 1101 dev_err(tc->dev, "Lane 1 failed: %x\n", value); 1102 ret = -ENODEV; 1103 } 1104 1105 if (!(tmp[2] & DP_INTERLANE_ALIGN_DONE)) { 1106 dev_err(tc->dev, "Interlane align failed\n"); 1107 ret = -ENODEV; 1108 } 1109 } 1110 1111 if (ret) { 1112 dev_err(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[0]); 1113 dev_err(dev, "0x0203 LANE2_3_STATUS 0x%02x\n", tmp[1]); 1114 dev_err(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", tmp[2]); 1115 dev_err(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[3]); 1116 dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n", tmp[4]); 1117 dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3: 0x%02x\n", tmp[5]); 1118 return ret; 1119 } 1120 1121 return 0; 1122 err_dpcd_read: 1123 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret); 1124 return ret; 1125 err_dpcd_write: 1126 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret); 1127 return ret; 1128 } 1129 1130 static int tc_main_link_disable(struct tc_data *tc) 1131 { 1132 int ret; 1133 1134 dev_dbg(tc->dev, "link disable\n"); 1135 1136 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0); 1137 if (ret) 1138 return ret; 1139 1140 return regmap_write(tc->regmap, DP0CTL, 0); 1141 } 1142 1143 static int tc_stream_enable(struct tc_data *tc) 1144 { 1145 int ret; 1146 u32 value; 1147 1148 dev_dbg(tc->dev, "enable video stream\n"); 1149 1150 /* PXL PLL setup */ 1151 if (tc_test_pattern) { 1152 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), 1153 1000 * tc->mode.clock); 1154 if (ret) 1155 return ret; 1156 } 1157 1158 ret = tc_set_video_mode(tc, &tc->mode); 1159 if (ret) 1160 return ret; 1161 1162 /* Set M/N */ 1163 ret = tc_stream_clock_calc(tc); 1164 if (ret) 1165 return ret; 1166 1167 value = VID_MN_GEN | DP_EN; 1168 if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 1169 value |= EF_EN; 1170 ret = regmap_write(tc->regmap, DP0CTL, value); 1171 if (ret) 1172 return ret; 1173 /* 1174 * VID_EN assertion should be delayed by at least N * LSCLK 1175 * cycles from the time VID_MN_GEN is enabled in order to 1176 * generate stable values for VID_M. LSCLK is 270 MHz or 1177 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(), 1178 * so a delay of at least 203 us should suffice. 1179 */ 1180 usleep_range(500, 1000); 1181 value |= VID_EN; 1182 ret = regmap_write(tc->regmap, DP0CTL, value); 1183 if (ret) 1184 return ret; 1185 /* Set input interface */ 1186 value = DP0_AUDSRC_NO_INPUT; 1187 if (tc_test_pattern) 1188 value |= DP0_VIDSRC_COLOR_BAR; 1189 else 1190 value |= DP0_VIDSRC_DPI_RX; 1191 ret = regmap_write(tc->regmap, SYSCTRL, value); 1192 if (ret) 1193 return ret; 1194 1195 return 0; 1196 } 1197 1198 static int tc_stream_disable(struct tc_data *tc) 1199 { 1200 int ret; 1201 1202 dev_dbg(tc->dev, "disable video stream\n"); 1203 1204 ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0); 1205 if (ret) 1206 return ret; 1207 1208 tc_pxl_pll_dis(tc); 1209 1210 return 0; 1211 } 1212 1213 static void tc_bridge_pre_enable(struct drm_bridge *bridge) 1214 { 1215 struct tc_data *tc = bridge_to_tc(bridge); 1216 1217 drm_panel_prepare(tc->panel); 1218 } 1219 1220 static void tc_bridge_enable(struct drm_bridge *bridge) 1221 { 1222 struct tc_data *tc = bridge_to_tc(bridge); 1223 int ret; 1224 1225 ret = tc_get_display_props(tc); 1226 if (ret < 0) { 1227 dev_err(tc->dev, "failed to read display props: %d\n", ret); 1228 return; 1229 } 1230 1231 ret = tc_main_link_enable(tc); 1232 if (ret < 0) { 1233 dev_err(tc->dev, "main link enable error: %d\n", ret); 1234 return; 1235 } 1236 1237 ret = tc_stream_enable(tc); 1238 if (ret < 0) { 1239 dev_err(tc->dev, "main link stream start error: %d\n", ret); 1240 tc_main_link_disable(tc); 1241 return; 1242 } 1243 1244 drm_panel_enable(tc->panel); 1245 } 1246 1247 static void tc_bridge_disable(struct drm_bridge *bridge) 1248 { 1249 struct tc_data *tc = bridge_to_tc(bridge); 1250 int ret; 1251 1252 drm_panel_disable(tc->panel); 1253 1254 ret = tc_stream_disable(tc); 1255 if (ret < 0) 1256 dev_err(tc->dev, "main link stream stop error: %d\n", ret); 1257 1258 ret = tc_main_link_disable(tc); 1259 if (ret < 0) 1260 dev_err(tc->dev, "main link disable error: %d\n", ret); 1261 } 1262 1263 static void tc_bridge_post_disable(struct drm_bridge *bridge) 1264 { 1265 struct tc_data *tc = bridge_to_tc(bridge); 1266 1267 drm_panel_unprepare(tc->panel); 1268 } 1269 1270 static bool tc_bridge_mode_fixup(struct drm_bridge *bridge, 1271 const struct drm_display_mode *mode, 1272 struct drm_display_mode *adj) 1273 { 1274 /* Fixup sync polarities, both hsync and vsync are active low */ 1275 adj->flags = mode->flags; 1276 adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); 1277 adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 1278 1279 return true; 1280 } 1281 1282 static enum drm_mode_status tc_mode_valid(struct drm_bridge *bridge, 1283 const struct drm_display_mode *mode) 1284 { 1285 struct tc_data *tc = bridge_to_tc(bridge); 1286 u32 req, avail; 1287 u32 bits_per_pixel = 24; 1288 1289 /* DPI interface clock limitation: upto 154 MHz */ 1290 if (mode->clock > 154000) 1291 return MODE_CLOCK_HIGH; 1292 1293 req = mode->clock * bits_per_pixel / 8; 1294 avail = tc->link.base.num_lanes * tc->link.base.rate; 1295 1296 if (req > avail) 1297 return MODE_BAD; 1298 1299 return MODE_OK; 1300 } 1301 1302 static void tc_bridge_mode_set(struct drm_bridge *bridge, 1303 const struct drm_display_mode *mode, 1304 const struct drm_display_mode *adj) 1305 { 1306 struct tc_data *tc = bridge_to_tc(bridge); 1307 1308 tc->mode = *mode; 1309 } 1310 1311 static int tc_connector_get_modes(struct drm_connector *connector) 1312 { 1313 struct tc_data *tc = connector_to_tc(connector); 1314 struct edid *edid; 1315 int count; 1316 int ret; 1317 1318 ret = tc_get_display_props(tc); 1319 if (ret < 0) { 1320 dev_err(tc->dev, "failed to read display props: %d\n", ret); 1321 return 0; 1322 } 1323 1324 count = drm_panel_get_modes(tc->panel); 1325 if (count > 0) 1326 return count; 1327 1328 edid = drm_get_edid(connector, &tc->aux.ddc); 1329 1330 kfree(tc->edid); 1331 tc->edid = edid; 1332 if (!edid) 1333 return 0; 1334 1335 drm_connector_update_edid_property(connector, edid); 1336 count = drm_add_edid_modes(connector, edid); 1337 1338 return count; 1339 } 1340 1341 static const struct drm_connector_helper_funcs tc_connector_helper_funcs = { 1342 .get_modes = tc_connector_get_modes, 1343 }; 1344 1345 static enum drm_connector_status tc_connector_detect(struct drm_connector *connector, 1346 bool force) 1347 { 1348 struct tc_data *tc = connector_to_tc(connector); 1349 bool conn; 1350 u32 val; 1351 int ret; 1352 1353 if (tc->hpd_pin < 0) { 1354 if (tc->panel) 1355 return connector_status_connected; 1356 else 1357 return connector_status_unknown; 1358 } 1359 1360 ret = regmap_read(tc->regmap, GPIOI, &val); 1361 if (ret) 1362 return connector_status_unknown; 1363 1364 conn = val & BIT(tc->hpd_pin); 1365 1366 if (conn) 1367 return connector_status_connected; 1368 else 1369 return connector_status_disconnected; 1370 } 1371 1372 static const struct drm_connector_funcs tc_connector_funcs = { 1373 .detect = tc_connector_detect, 1374 .fill_modes = drm_helper_probe_single_connector_modes, 1375 .destroy = drm_connector_cleanup, 1376 .reset = drm_atomic_helper_connector_reset, 1377 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1378 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1379 }; 1380 1381 static int tc_bridge_attach(struct drm_bridge *bridge) 1382 { 1383 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1384 struct tc_data *tc = bridge_to_tc(bridge); 1385 struct drm_device *drm = bridge->dev; 1386 int ret; 1387 1388 /* Create DP/eDP connector */ 1389 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs); 1390 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, 1391 tc->panel ? DRM_MODE_CONNECTOR_eDP : 1392 DRM_MODE_CONNECTOR_DisplayPort); 1393 if (ret) 1394 return ret; 1395 1396 /* Don't poll if don't have HPD connected */ 1397 if (tc->hpd_pin >= 0) { 1398 if (tc->have_irq) 1399 tc->connector.polled = DRM_CONNECTOR_POLL_HPD; 1400 else 1401 tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT | 1402 DRM_CONNECTOR_POLL_DISCONNECT; 1403 } 1404 1405 if (tc->panel) 1406 drm_panel_attach(tc->panel, &tc->connector); 1407 1408 drm_display_info_set_bus_formats(&tc->connector.display_info, 1409 &bus_format, 1); 1410 tc->connector.display_info.bus_flags = 1411 DRM_BUS_FLAG_DE_HIGH | 1412 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE | 1413 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE; 1414 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder); 1415 1416 return 0; 1417 } 1418 1419 static const struct drm_bridge_funcs tc_bridge_funcs = { 1420 .attach = tc_bridge_attach, 1421 .mode_valid = tc_mode_valid, 1422 .mode_set = tc_bridge_mode_set, 1423 .pre_enable = tc_bridge_pre_enable, 1424 .enable = tc_bridge_enable, 1425 .disable = tc_bridge_disable, 1426 .post_disable = tc_bridge_post_disable, 1427 .mode_fixup = tc_bridge_mode_fixup, 1428 }; 1429 1430 static bool tc_readable_reg(struct device *dev, unsigned int reg) 1431 { 1432 return reg != SYSCTRL; 1433 } 1434 1435 static const struct regmap_range tc_volatile_ranges[] = { 1436 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS), 1437 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ), 1438 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL), 1439 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL), 1440 regmap_reg_range(VFUEN0, VFUEN0), 1441 regmap_reg_range(INTSTS_G, INTSTS_G), 1442 regmap_reg_range(GPIOI, GPIOI), 1443 }; 1444 1445 static const struct regmap_access_table tc_volatile_table = { 1446 .yes_ranges = tc_volatile_ranges, 1447 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges), 1448 }; 1449 1450 static bool tc_writeable_reg(struct device *dev, unsigned int reg) 1451 { 1452 return (reg != TC_IDREG) && 1453 (reg != DP0_LTSTAT) && 1454 (reg != DP0_SNKLTCHGREQ); 1455 } 1456 1457 static const struct regmap_config tc_regmap_config = { 1458 .name = "tc358767", 1459 .reg_bits = 16, 1460 .val_bits = 32, 1461 .reg_stride = 4, 1462 .max_register = PLL_DBG, 1463 .cache_type = REGCACHE_RBTREE, 1464 .readable_reg = tc_readable_reg, 1465 .volatile_table = &tc_volatile_table, 1466 .writeable_reg = tc_writeable_reg, 1467 .reg_format_endian = REGMAP_ENDIAN_BIG, 1468 .val_format_endian = REGMAP_ENDIAN_LITTLE, 1469 }; 1470 1471 static irqreturn_t tc_irq_handler(int irq, void *arg) 1472 { 1473 struct tc_data *tc = arg; 1474 u32 val; 1475 int r; 1476 1477 r = regmap_read(tc->regmap, INTSTS_G, &val); 1478 if (r) 1479 return IRQ_NONE; 1480 1481 if (!val) 1482 return IRQ_NONE; 1483 1484 if (val & INT_SYSERR) { 1485 u32 stat = 0; 1486 1487 regmap_read(tc->regmap, SYSSTAT, &stat); 1488 1489 dev_err(tc->dev, "syserr %x\n", stat); 1490 } 1491 1492 if (tc->hpd_pin >= 0 && tc->bridge.dev) { 1493 /* 1494 * H is triggered when the GPIO goes high. 1495 * 1496 * LC is triggered when the GPIO goes low and stays low for 1497 * the duration of LCNT 1498 */ 1499 bool h = val & INT_GPIO_H(tc->hpd_pin); 1500 bool lc = val & INT_GPIO_LC(tc->hpd_pin); 1501 1502 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin, 1503 h ? "H" : "", lc ? "LC" : ""); 1504 1505 if (h || lc) 1506 drm_kms_helper_hotplug_event(tc->bridge.dev); 1507 } 1508 1509 regmap_write(tc->regmap, INTSTS_G, val); 1510 1511 return IRQ_HANDLED; 1512 } 1513 1514 static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id) 1515 { 1516 struct device *dev = &client->dev; 1517 struct tc_data *tc; 1518 int ret; 1519 1520 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL); 1521 if (!tc) 1522 return -ENOMEM; 1523 1524 tc->dev = dev; 1525 1526 /* port@2 is the output port */ 1527 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL); 1528 if (ret && ret != -ENODEV) 1529 return ret; 1530 1531 /* Shut down GPIO is optional */ 1532 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH); 1533 if (IS_ERR(tc->sd_gpio)) 1534 return PTR_ERR(tc->sd_gpio); 1535 1536 if (tc->sd_gpio) { 1537 gpiod_set_value_cansleep(tc->sd_gpio, 0); 1538 usleep_range(5000, 10000); 1539 } 1540 1541 /* Reset GPIO is optional */ 1542 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1543 if (IS_ERR(tc->reset_gpio)) 1544 return PTR_ERR(tc->reset_gpio); 1545 1546 if (tc->reset_gpio) { 1547 gpiod_set_value_cansleep(tc->reset_gpio, 1); 1548 usleep_range(5000, 10000); 1549 } 1550 1551 tc->refclk = devm_clk_get(dev, "ref"); 1552 if (IS_ERR(tc->refclk)) { 1553 ret = PTR_ERR(tc->refclk); 1554 dev_err(dev, "Failed to get refclk: %d\n", ret); 1555 return ret; 1556 } 1557 1558 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config); 1559 if (IS_ERR(tc->regmap)) { 1560 ret = PTR_ERR(tc->regmap); 1561 dev_err(dev, "Failed to initialize regmap: %d\n", ret); 1562 return ret; 1563 } 1564 1565 ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin", 1566 &tc->hpd_pin); 1567 if (ret) { 1568 tc->hpd_pin = -ENODEV; 1569 } else { 1570 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) { 1571 dev_err(dev, "failed to parse HPD number\n"); 1572 return ret; 1573 } 1574 } 1575 1576 if (client->irq > 0) { 1577 /* enable SysErr */ 1578 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR); 1579 1580 ret = devm_request_threaded_irq(dev, client->irq, 1581 NULL, tc_irq_handler, 1582 IRQF_ONESHOT, 1583 "tc358767-irq", tc); 1584 if (ret) { 1585 dev_err(dev, "failed to register dp interrupt\n"); 1586 return ret; 1587 } 1588 1589 tc->have_irq = true; 1590 } 1591 1592 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev); 1593 if (ret) { 1594 dev_err(tc->dev, "can not read device ID: %d\n", ret); 1595 return ret; 1596 } 1597 1598 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) { 1599 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev); 1600 return -EINVAL; 1601 } 1602 1603 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */ 1604 1605 if (!tc->reset_gpio) { 1606 /* 1607 * If the reset pin isn't present, do a software reset. It isn't 1608 * as thorough as the hardware reset, as we can't reset the I2C 1609 * communication block for obvious reasons, but it's getting the 1610 * chip into a defined state. 1611 */ 1612 regmap_update_bits(tc->regmap, SYSRSTENB, 1613 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP, 1614 0); 1615 regmap_update_bits(tc->regmap, SYSRSTENB, 1616 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP, 1617 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP); 1618 usleep_range(5000, 10000); 1619 } 1620 1621 if (tc->hpd_pin >= 0) { 1622 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT; 1623 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin); 1624 1625 /* Set LCNT to 2ms */ 1626 regmap_write(tc->regmap, lcnt_reg, 1627 clk_get_rate(tc->refclk) * 2 / 1000); 1628 /* We need the "alternate" mode for HPD */ 1629 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin)); 1630 1631 if (tc->have_irq) { 1632 /* enable H & LC */ 1633 regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc); 1634 } 1635 } 1636 1637 ret = tc_aux_link_setup(tc); 1638 if (ret) 1639 return ret; 1640 1641 /* Register DP AUX channel */ 1642 tc->aux.name = "TC358767 AUX i2c adapter"; 1643 tc->aux.dev = tc->dev; 1644 tc->aux.transfer = tc_aux_transfer; 1645 ret = drm_dp_aux_register(&tc->aux); 1646 if (ret) 1647 return ret; 1648 1649 tc->bridge.funcs = &tc_bridge_funcs; 1650 tc->bridge.of_node = dev->of_node; 1651 drm_bridge_add(&tc->bridge); 1652 1653 i2c_set_clientdata(client, tc); 1654 1655 return 0; 1656 } 1657 1658 static int tc_remove(struct i2c_client *client) 1659 { 1660 struct tc_data *tc = i2c_get_clientdata(client); 1661 1662 drm_bridge_remove(&tc->bridge); 1663 drm_dp_aux_unregister(&tc->aux); 1664 1665 return 0; 1666 } 1667 1668 static const struct i2c_device_id tc358767_i2c_ids[] = { 1669 { "tc358767", 0 }, 1670 { } 1671 }; 1672 MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids); 1673 1674 static const struct of_device_id tc358767_of_ids[] = { 1675 { .compatible = "toshiba,tc358767", }, 1676 { } 1677 }; 1678 MODULE_DEVICE_TABLE(of, tc358767_of_ids); 1679 1680 static struct i2c_driver tc358767_driver = { 1681 .driver = { 1682 .name = "tc358767", 1683 .of_match_table = tc358767_of_ids, 1684 }, 1685 .id_table = tc358767_i2c_ids, 1686 .probe = tc_probe, 1687 .remove = tc_remove, 1688 }; 1689 module_i2c_driver(tc358767_driver); 1690 1691 MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>"); 1692 MODULE_DESCRIPTION("tc358767 eDP encoder driver"); 1693 MODULE_LICENSE("GPL"); 1694