1 /* 2 * tc358767 eDP bridge driver 3 * 4 * Copyright (C) 2016 CogentEmbedded Inc 5 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com> 6 * 7 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de> 8 * 9 * Copyright (C) 2016 Zodiac Inflight Innovations 10 * 11 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c 12 * 13 * Copyright (C) 2012 Texas Instruments 14 * Author: Rob Clark <robdclark@gmail.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or 19 * (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 */ 26 27 #include <linux/clk.h> 28 #include <linux/device.h> 29 #include <linux/gpio/consumer.h> 30 #include <linux/i2c.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/regmap.h> 34 #include <linux/slab.h> 35 36 #include <drm/drm_atomic_helper.h> 37 #include <drm/drm_dp_helper.h> 38 #include <drm/drm_edid.h> 39 #include <drm/drm_of.h> 40 #include <drm/drm_panel.h> 41 #include <drm/drm_probe_helper.h> 42 43 /* Registers */ 44 45 /* Display Parallel Interface */ 46 #define DPIPXLFMT 0x0440 47 #define VS_POL_ACTIVE_LOW (1 << 10) 48 #define HS_POL_ACTIVE_LOW (1 << 9) 49 #define DE_POL_ACTIVE_HIGH (0 << 8) 50 #define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */ 51 #define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */ 52 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */ 53 #define DPI_BPP_RGB888 (0 << 0) 54 #define DPI_BPP_RGB666 (1 << 0) 55 #define DPI_BPP_RGB565 (2 << 0) 56 57 /* Video Path */ 58 #define VPCTRL0 0x0450 59 #define OPXLFMT_RGB666 (0 << 8) 60 #define OPXLFMT_RGB888 (1 << 8) 61 #define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */ 62 #define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */ 63 #define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */ 64 #define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */ 65 #define HTIM01 0x0454 66 #define HTIM02 0x0458 67 #define VTIM01 0x045c 68 #define VTIM02 0x0460 69 #define VFUEN0 0x0464 70 #define VFUEN BIT(0) /* Video Frame Timing Upload */ 71 72 /* System */ 73 #define TC_IDREG 0x0500 74 #define SYSCTRL 0x0510 75 #define DP0_AUDSRC_NO_INPUT (0 << 3) 76 #define DP0_AUDSRC_I2S_RX (1 << 3) 77 #define DP0_VIDSRC_NO_INPUT (0 << 0) 78 #define DP0_VIDSRC_DSI_RX (1 << 0) 79 #define DP0_VIDSRC_DPI_RX (2 << 0) 80 #define DP0_VIDSRC_COLOR_BAR (3 << 0) 81 82 /* Control */ 83 #define DP0CTL 0x0600 84 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */ 85 #define EF_EN BIT(5) /* Enable Enhanced Framing */ 86 #define VID_EN BIT(1) /* Video transmission enable */ 87 #define DP_EN BIT(0) /* Enable DPTX function */ 88 89 /* Clocks */ 90 #define DP0_VIDMNGEN0 0x0610 91 #define DP0_VIDMNGEN1 0x0614 92 #define DP0_VMNGENSTATUS 0x0618 93 94 /* Main Channel */ 95 #define DP0_SECSAMPLE 0x0640 96 #define DP0_VIDSYNCDELAY 0x0644 97 #define DP0_TOTALVAL 0x0648 98 #define DP0_STARTVAL 0x064c 99 #define DP0_ACTIVEVAL 0x0650 100 #define DP0_SYNCVAL 0x0654 101 #define DP0_MISC 0x0658 102 #define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */ 103 #define BPC_6 (0 << 5) 104 #define BPC_8 (1 << 5) 105 106 /* AUX channel */ 107 #define DP0_AUXCFG0 0x0660 108 #define DP0_AUXCFG1 0x0664 109 #define AUX_RX_FILTER_EN BIT(16) 110 111 #define DP0_AUXADDR 0x0668 112 #define DP0_AUXWDATA(i) (0x066c + (i) * 4) 113 #define DP0_AUXRDATA(i) (0x067c + (i) * 4) 114 #define DP0_AUXSTATUS 0x068c 115 #define AUX_STATUS_MASK 0xf0 116 #define AUX_STATUS_SHIFT 4 117 #define AUX_TIMEOUT BIT(1) 118 #define AUX_BUSY BIT(0) 119 #define DP0_AUXI2CADR 0x0698 120 121 /* Link Training */ 122 #define DP0_SRCCTRL 0x06a0 123 #define DP0_SRCCTRL_SCRMBLDIS BIT(13) 124 #define DP0_SRCCTRL_EN810B BIT(12) 125 #define DP0_SRCCTRL_NOTP (0 << 8) 126 #define DP0_SRCCTRL_TP1 (1 << 8) 127 #define DP0_SRCCTRL_TP2 (2 << 8) 128 #define DP0_SRCCTRL_LANESKEW BIT(7) 129 #define DP0_SRCCTRL_SSCG BIT(3) 130 #define DP0_SRCCTRL_LANES_1 (0 << 2) 131 #define DP0_SRCCTRL_LANES_2 (1 << 2) 132 #define DP0_SRCCTRL_BW27 (1 << 1) 133 #define DP0_SRCCTRL_BW162 (0 << 1) 134 #define DP0_SRCCTRL_AUTOCORRECT BIT(0) 135 #define DP0_LTSTAT 0x06d0 136 #define LT_LOOPDONE BIT(13) 137 #define LT_STATUS_MASK (0x1f << 8) 138 #define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4) 139 #define LT_INTERLANE_ALIGN_DONE BIT(3) 140 #define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS) 141 #define DP0_SNKLTCHGREQ 0x06d4 142 #define DP0_LTLOOPCTRL 0x06d8 143 #define DP0_SNKLTCTRL 0x06e4 144 145 /* PHY */ 146 #define DP_PHY_CTRL 0x0800 147 #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */ 148 #define BGREN BIT(25) /* AUX PHY BGR Enable */ 149 #define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */ 150 #define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */ 151 #define PHY_RDY BIT(16) /* PHY Main Channels Ready */ 152 #define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */ 153 #define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */ 154 #define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */ 155 156 /* PLL */ 157 #define DP0_PLLCTRL 0x0900 158 #define DP1_PLLCTRL 0x0904 /* not defined in DS */ 159 #define PXL_PLLCTRL 0x0908 160 #define PLLUPDATE BIT(2) 161 #define PLLBYP BIT(1) 162 #define PLLEN BIT(0) 163 #define PXL_PLLPARAM 0x0914 164 #define IN_SEL_REFCLK (0 << 14) 165 #define SYS_PLLPARAM 0x0918 166 #define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */ 167 #define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */ 168 #define REF_FREQ_26M (2 << 8) /* 26 MHz */ 169 #define REF_FREQ_13M (3 << 8) /* 13 MHz */ 170 #define SYSCLK_SEL_LSCLK (0 << 4) 171 #define LSCLK_DIV_1 (0 << 0) 172 #define LSCLK_DIV_2 (1 << 0) 173 174 /* Test & Debug */ 175 #define TSTCTL 0x0a00 176 #define PLL_DBG 0x0a04 177 178 static bool tc_test_pattern; 179 module_param_named(test, tc_test_pattern, bool, 0644); 180 181 struct tc_edp_link { 182 struct drm_dp_link base; 183 u8 assr; 184 int scrambler_dis; 185 int spread; 186 int coding8b10b; 187 u8 swing; 188 u8 preemp; 189 }; 190 191 struct tc_data { 192 struct device *dev; 193 struct regmap *regmap; 194 struct drm_dp_aux aux; 195 196 struct drm_bridge bridge; 197 struct drm_connector connector; 198 struct drm_panel *panel; 199 200 /* link settings */ 201 struct tc_edp_link link; 202 203 /* display edid */ 204 struct edid *edid; 205 /* current mode */ 206 const struct drm_display_mode *mode; 207 208 u32 rev; 209 u8 assr; 210 211 struct gpio_desc *sd_gpio; 212 struct gpio_desc *reset_gpio; 213 struct clk *refclk; 214 }; 215 216 static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a) 217 { 218 return container_of(a, struct tc_data, aux); 219 } 220 221 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b) 222 { 223 return container_of(b, struct tc_data, bridge); 224 } 225 226 static inline struct tc_data *connector_to_tc(struct drm_connector *c) 227 { 228 return container_of(c, struct tc_data, connector); 229 } 230 231 /* Simple macros to avoid repeated error checks */ 232 #define tc_write(reg, var) \ 233 do { \ 234 ret = regmap_write(tc->regmap, reg, var); \ 235 if (ret) \ 236 goto err; \ 237 } while (0) 238 #define tc_read(reg, var) \ 239 do { \ 240 ret = regmap_read(tc->regmap, reg, var); \ 241 if (ret) \ 242 goto err; \ 243 } while (0) 244 245 static inline int tc_poll_timeout(struct regmap *map, unsigned int addr, 246 unsigned int cond_mask, 247 unsigned int cond_value, 248 unsigned long sleep_us, u64 timeout_us) 249 { 250 ktime_t timeout = ktime_add_us(ktime_get(), timeout_us); 251 unsigned int val; 252 int ret; 253 254 for (;;) { 255 ret = regmap_read(map, addr, &val); 256 if (ret) 257 break; 258 if ((val & cond_mask) == cond_value) 259 break; 260 if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) { 261 ret = regmap_read(map, addr, &val); 262 break; 263 } 264 if (sleep_us) 265 usleep_range((sleep_us >> 2) + 1, sleep_us); 266 } 267 return ret ?: (((val & cond_mask) == cond_value) ? 0 : -ETIMEDOUT); 268 } 269 270 static int tc_aux_wait_busy(struct tc_data *tc, unsigned int timeout_ms) 271 { 272 return tc_poll_timeout(tc->regmap, DP0_AUXSTATUS, AUX_BUSY, 0, 273 1000, 1000 * timeout_ms); 274 } 275 276 static int tc_aux_get_status(struct tc_data *tc, u8 *reply) 277 { 278 int ret; 279 u32 value; 280 281 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &value); 282 if (ret < 0) 283 return ret; 284 if (value & AUX_BUSY) { 285 if (value & AUX_TIMEOUT) { 286 dev_err(tc->dev, "i2c access timeout!\n"); 287 return -ETIMEDOUT; 288 } 289 return -EBUSY; 290 } 291 292 *reply = (value & AUX_STATUS_MASK) >> AUX_STATUS_SHIFT; 293 return 0; 294 } 295 296 static ssize_t tc_aux_transfer(struct drm_dp_aux *aux, 297 struct drm_dp_aux_msg *msg) 298 { 299 struct tc_data *tc = aux_to_tc(aux); 300 size_t size = min_t(size_t, 8, msg->size); 301 u8 request = msg->request & ~DP_AUX_I2C_MOT; 302 u8 *buf = msg->buffer; 303 u32 tmp = 0; 304 int i = 0; 305 int ret; 306 307 if (size == 0) 308 return 0; 309 310 ret = tc_aux_wait_busy(tc, 100); 311 if (ret) 312 goto err; 313 314 if (request == DP_AUX_I2C_WRITE || request == DP_AUX_NATIVE_WRITE) { 315 /* Store data */ 316 while (i < size) { 317 if (request == DP_AUX_NATIVE_WRITE) 318 tmp = tmp | (buf[i] << (8 * (i & 0x3))); 319 else 320 tmp = (tmp << 8) | buf[i]; 321 i++; 322 if (((i % 4) == 0) || (i == size)) { 323 tc_write(DP0_AUXWDATA((i - 1) >> 2), tmp); 324 tmp = 0; 325 } 326 } 327 } else if (request != DP_AUX_I2C_READ && 328 request != DP_AUX_NATIVE_READ) { 329 return -EINVAL; 330 } 331 332 /* Store address */ 333 tc_write(DP0_AUXADDR, msg->address); 334 /* Start transfer */ 335 tc_write(DP0_AUXCFG0, ((size - 1) << 8) | request); 336 337 ret = tc_aux_wait_busy(tc, 100); 338 if (ret) 339 goto err; 340 341 ret = tc_aux_get_status(tc, &msg->reply); 342 if (ret) 343 goto err; 344 345 if (request == DP_AUX_I2C_READ || request == DP_AUX_NATIVE_READ) { 346 /* Read data */ 347 while (i < size) { 348 if ((i % 4) == 0) 349 tc_read(DP0_AUXRDATA(i >> 2), &tmp); 350 buf[i] = tmp & 0xff; 351 tmp = tmp >> 8; 352 i++; 353 } 354 } 355 356 return size; 357 err: 358 return ret; 359 } 360 361 static const char * const training_pattern1_errors[] = { 362 "No errors", 363 "Aux write error", 364 "Aux read error", 365 "Max voltage reached error", 366 "Loop counter expired error", 367 "res", "res", "res" 368 }; 369 370 static const char * const training_pattern2_errors[] = { 371 "No errors", 372 "Aux write error", 373 "Aux read error", 374 "Clock recovery failed error", 375 "Loop counter expired error", 376 "res", "res", "res" 377 }; 378 379 static u32 tc_srcctrl(struct tc_data *tc) 380 { 381 /* 382 * No training pattern, skew lane 1 data by two LSCLK cycles with 383 * respect to lane 0 data, AutoCorrect Mode = 0 384 */ 385 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW; 386 387 if (tc->link.scrambler_dis) 388 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */ 389 if (tc->link.coding8b10b) 390 /* Enable 8/10B Encoder (TxData[19:16] not used) */ 391 reg |= DP0_SRCCTRL_EN810B; 392 if (tc->link.spread) 393 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */ 394 if (tc->link.base.num_lanes == 2) 395 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */ 396 if (tc->link.base.rate != 162000) 397 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */ 398 return reg; 399 } 400 401 static void tc_wait_pll_lock(struct tc_data *tc) 402 { 403 /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */ 404 usleep_range(3000, 6000); 405 } 406 407 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) 408 { 409 int ret; 410 int i_pre, best_pre = 1; 411 int i_post, best_post = 1; 412 int div, best_div = 1; 413 int mul, best_mul = 1; 414 int delta, best_delta; 415 int ext_div[] = {1, 2, 3, 5, 7}; 416 int best_pixelclock = 0; 417 int vco_hi = 0; 418 419 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock, 420 refclk); 421 best_delta = pixelclock; 422 /* Loop over all possible ext_divs, skipping invalid configurations */ 423 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) { 424 /* 425 * refclk / ext_pre_div should be in the 1 to 200 MHz range. 426 * We don't allow any refclk > 200 MHz, only check lower bounds. 427 */ 428 if (refclk / ext_div[i_pre] < 1000000) 429 continue; 430 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) { 431 for (div = 1; div <= 16; div++) { 432 u32 clk; 433 u64 tmp; 434 435 tmp = pixelclock * ext_div[i_pre] * 436 ext_div[i_post] * div; 437 do_div(tmp, refclk); 438 mul = tmp; 439 440 /* Check limits */ 441 if ((mul < 1) || (mul > 128)) 442 continue; 443 444 clk = (refclk / ext_div[i_pre] / div) * mul; 445 /* 446 * refclk * mul / (ext_pre_div * pre_div) 447 * should be in the 150 to 650 MHz range 448 */ 449 if ((clk > 650000000) || (clk < 150000000)) 450 continue; 451 452 clk = clk / ext_div[i_post]; 453 delta = clk - pixelclock; 454 455 if (abs(delta) < abs(best_delta)) { 456 best_pre = i_pre; 457 best_post = i_post; 458 best_div = div; 459 best_mul = mul; 460 best_delta = delta; 461 best_pixelclock = clk; 462 } 463 } 464 } 465 } 466 if (best_pixelclock == 0) { 467 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n", 468 pixelclock); 469 return -EINVAL; 470 } 471 472 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock, 473 best_delta); 474 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk, 475 ext_div[best_pre], best_div, best_mul, ext_div[best_post]); 476 477 /* if VCO >= 300 MHz */ 478 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000) 479 vco_hi = 1; 480 /* see DS */ 481 if (best_div == 16) 482 best_div = 0; 483 if (best_mul == 128) 484 best_mul = 0; 485 486 /* Power up PLL and switch to bypass */ 487 tc_write(PXL_PLLCTRL, PLLBYP | PLLEN); 488 489 tc_write(PXL_PLLPARAM, 490 (vco_hi << 24) | /* For PLL VCO >= 300 MHz = 1 */ 491 (ext_div[best_pre] << 20) | /* External Pre-divider */ 492 (ext_div[best_post] << 16) | /* External Post-divider */ 493 IN_SEL_REFCLK | /* Use RefClk as PLL input */ 494 (best_div << 8) | /* Divider for PLL RefClk */ 495 (best_mul << 0)); /* Multiplier for PLL */ 496 497 /* Force PLL parameter update and disable bypass */ 498 tc_write(PXL_PLLCTRL, PLLUPDATE | PLLEN); 499 500 tc_wait_pll_lock(tc); 501 502 return 0; 503 err: 504 return ret; 505 } 506 507 static int tc_pxl_pll_dis(struct tc_data *tc) 508 { 509 /* Enable PLL bypass, power down PLL */ 510 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP); 511 } 512 513 static int tc_stream_clock_calc(struct tc_data *tc) 514 { 515 int ret; 516 /* 517 * If the Stream clock and Link Symbol clock are 518 * asynchronous with each other, the value of M changes over 519 * time. This way of generating link clock and stream 520 * clock is called Asynchronous Clock mode. The value M 521 * must change while the value N stays constant. The 522 * value of N in this Asynchronous Clock mode must be set 523 * to 2^15 or 32,768. 524 * 525 * LSCLK = 1/10 of high speed link clock 526 * 527 * f_STRMCLK = M/N * f_LSCLK 528 * M/N = f_STRMCLK / f_LSCLK 529 * 530 */ 531 tc_write(DP0_VIDMNGEN1, 32768); 532 533 return 0; 534 err: 535 return ret; 536 } 537 538 static int tc_aux_link_setup(struct tc_data *tc) 539 { 540 unsigned long rate; 541 u32 value; 542 int ret; 543 544 rate = clk_get_rate(tc->refclk); 545 switch (rate) { 546 case 38400000: 547 value = REF_FREQ_38M4; 548 break; 549 case 26000000: 550 value = REF_FREQ_26M; 551 break; 552 case 19200000: 553 value = REF_FREQ_19M2; 554 break; 555 case 13000000: 556 value = REF_FREQ_13M; 557 break; 558 default: 559 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate); 560 return -EINVAL; 561 } 562 563 /* Setup DP-PHY / PLL */ 564 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; 565 tc_write(SYS_PLLPARAM, value); 566 567 tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | BIT(2) | PHY_A0_EN); 568 569 /* 570 * Initially PLLs are in bypass. Force PLL parameter update, 571 * disable PLL bypass, enable PLL 572 */ 573 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN); 574 tc_wait_pll_lock(tc); 575 576 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN); 577 tc_wait_pll_lock(tc); 578 579 ret = tc_poll_timeout(tc->regmap, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 580 1000); 581 if (ret == -ETIMEDOUT) { 582 dev_err(tc->dev, "Timeout waiting for PHY to become ready"); 583 return ret; 584 } else if (ret) 585 goto err; 586 587 /* Setup AUX link */ 588 tc_write(DP0_AUXCFG1, AUX_RX_FILTER_EN | 589 (0x06 << 8) | /* Aux Bit Period Calculator Threshold */ 590 (0x3f << 0)); /* Aux Response Timeout Timer */ 591 592 return 0; 593 err: 594 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret); 595 return ret; 596 } 597 598 static int tc_get_display_props(struct tc_data *tc) 599 { 600 int ret; 601 /* temp buffer */ 602 u8 tmp[8]; 603 604 /* Read DP Rx Link Capability */ 605 ret = drm_dp_link_probe(&tc->aux, &tc->link.base); 606 if (ret < 0) 607 goto err_dpcd_read; 608 if (tc->link.base.rate != 162000 && tc->link.base.rate != 270000) { 609 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n"); 610 tc->link.base.rate = 270000; 611 } 612 613 if (tc->link.base.num_lanes > 2) { 614 dev_dbg(tc->dev, "Falling to 2 lanes\n"); 615 tc->link.base.num_lanes = 2; 616 } 617 618 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, tmp); 619 if (ret < 0) 620 goto err_dpcd_read; 621 tc->link.spread = tmp[0] & BIT(0); /* 0.5% down spread */ 622 623 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, tmp); 624 if (ret < 0) 625 goto err_dpcd_read; 626 tc->link.coding8b10b = tmp[0] & BIT(0); 627 tc->link.scrambler_dis = 0; 628 /* read assr */ 629 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, tmp); 630 if (ret < 0) 631 goto err_dpcd_read; 632 tc->link.assr = tmp[0] & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; 633 634 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n", 635 tc->link.base.revision >> 4, tc->link.base.revision & 0x0f, 636 (tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps", 637 tc->link.base.num_lanes, 638 (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ? 639 "enhanced" : "non-enhanced"); 640 dev_dbg(tc->dev, "ANSI 8B/10B: %d\n", tc->link.coding8b10b); 641 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n", 642 tc->link.assr, tc->assr); 643 644 return 0; 645 646 err_dpcd_read: 647 dev_err(tc->dev, "failed to read DPCD: %d\n", ret); 648 return ret; 649 } 650 651 static int tc_set_video_mode(struct tc_data *tc, 652 const struct drm_display_mode *mode) 653 { 654 int ret; 655 int vid_sync_dly; 656 int max_tu_symbol; 657 658 int left_margin = mode->htotal - mode->hsync_end; 659 int right_margin = mode->hsync_start - mode->hdisplay; 660 int hsync_len = mode->hsync_end - mode->hsync_start; 661 int upper_margin = mode->vtotal - mode->vsync_end; 662 int lower_margin = mode->vsync_start - mode->vdisplay; 663 int vsync_len = mode->vsync_end - mode->vsync_start; 664 665 /* 666 * Recommended maximum number of symbols transferred in a transfer unit: 667 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size, 668 * (output active video bandwidth in bytes)) 669 * Must be less than tu_size. 670 */ 671 max_tu_symbol = TU_SIZE_RECOMMENDED - 1; 672 673 dev_dbg(tc->dev, "set mode %dx%d\n", 674 mode->hdisplay, mode->vdisplay); 675 dev_dbg(tc->dev, "H margin %d,%d sync %d\n", 676 left_margin, right_margin, hsync_len); 677 dev_dbg(tc->dev, "V margin %d,%d sync %d\n", 678 upper_margin, lower_margin, vsync_len); 679 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal); 680 681 682 /* 683 * LCD Ctl Frame Size 684 * datasheet is not clear of vsdelay in case of DPI 685 * assume we do not need any delay when DPI is a source of 686 * sync signals 687 */ 688 tc_write(VPCTRL0, (0 << 20) /* VSDELAY */ | 689 OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED); 690 tc_write(HTIM01, (ALIGN(left_margin, 2) << 16) | /* H back porch */ 691 (ALIGN(hsync_len, 2) << 0)); /* Hsync */ 692 tc_write(HTIM02, (ALIGN(right_margin, 2) << 16) | /* H front porch */ 693 (ALIGN(mode->hdisplay, 2) << 0)); /* width */ 694 tc_write(VTIM01, (upper_margin << 16) | /* V back porch */ 695 (vsync_len << 0)); /* Vsync */ 696 tc_write(VTIM02, (lower_margin << 16) | /* V front porch */ 697 (mode->vdisplay << 0)); /* height */ 698 tc_write(VFUEN0, VFUEN); /* update settings */ 699 700 /* Test pattern settings */ 701 tc_write(TSTCTL, 702 (120 << 24) | /* Red Color component value */ 703 (20 << 16) | /* Green Color component value */ 704 (99 << 8) | /* Blue Color component value */ 705 (1 << 4) | /* Enable I2C Filter */ 706 (2 << 0) | /* Color bar Mode */ 707 0); 708 709 /* DP Main Stream Attributes */ 710 vid_sync_dly = hsync_len + left_margin + mode->hdisplay; 711 tc_write(DP0_VIDSYNCDELAY, 712 (max_tu_symbol << 16) | /* thresh_dly */ 713 (vid_sync_dly << 0)); 714 715 tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal)); 716 717 tc_write(DP0_STARTVAL, 718 ((upper_margin + vsync_len) << 16) | 719 ((left_margin + hsync_len) << 0)); 720 721 tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay)); 722 723 tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0)); 724 725 tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW | 726 DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888); 727 728 tc_write(DP0_MISC, (max_tu_symbol << 23) | (TU_SIZE_RECOMMENDED << 16) | 729 BPC_8); 730 731 return 0; 732 err: 733 return ret; 734 } 735 736 static int tc_link_training(struct tc_data *tc, int pattern) 737 { 738 const char * const *errors; 739 u32 srcctrl = tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | 740 DP0_SRCCTRL_AUTOCORRECT; 741 int timeout; 742 int retry; 743 u32 value; 744 int ret; 745 746 if (pattern == DP_TRAINING_PATTERN_1) { 747 srcctrl |= DP0_SRCCTRL_TP1; 748 errors = training_pattern1_errors; 749 } else { 750 srcctrl |= DP0_SRCCTRL_TP2; 751 errors = training_pattern2_errors; 752 } 753 754 /* Set DPCD 0x102 for Training Part 1 or 2 */ 755 tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | pattern); 756 757 tc_write(DP0_LTLOOPCTRL, 758 (0x0f << 28) | /* Defer Iteration Count */ 759 (0x0f << 24) | /* Loop Iteration Count */ 760 (0x0d << 0)); /* Loop Timer Delay */ 761 762 retry = 5; 763 do { 764 /* Set DP0 Training Pattern */ 765 tc_write(DP0_SRCCTRL, srcctrl); 766 767 /* Enable DP0 to start Link Training */ 768 tc_write(DP0CTL, DP_EN); 769 770 /* wait */ 771 timeout = 1000; 772 do { 773 tc_read(DP0_LTSTAT, &value); 774 udelay(1); 775 } while ((!(value & LT_LOOPDONE)) && (--timeout)); 776 if (timeout == 0) { 777 dev_err(tc->dev, "Link training timeout!\n"); 778 } else { 779 int pattern = (value >> 11) & 0x3; 780 int error = (value >> 8) & 0x7; 781 782 dev_dbg(tc->dev, 783 "Link training phase %d done after %d uS: %s\n", 784 pattern, 1000 - timeout, errors[error]); 785 if (pattern == DP_TRAINING_PATTERN_1 && error == 0) 786 break; 787 if (pattern == DP_TRAINING_PATTERN_2) { 788 value &= LT_CHANNEL1_EQ_BITS | 789 LT_INTERLANE_ALIGN_DONE | 790 LT_CHANNEL0_EQ_BITS; 791 /* in case of two lanes */ 792 if ((tc->link.base.num_lanes == 2) && 793 (value == (LT_CHANNEL1_EQ_BITS | 794 LT_INTERLANE_ALIGN_DONE | 795 LT_CHANNEL0_EQ_BITS))) 796 break; 797 /* in case of one line */ 798 if ((tc->link.base.num_lanes == 1) && 799 (value == (LT_INTERLANE_ALIGN_DONE | 800 LT_CHANNEL0_EQ_BITS))) 801 break; 802 } 803 } 804 /* restart */ 805 tc_write(DP0CTL, 0); 806 usleep_range(10, 20); 807 } while (--retry); 808 if (retry == 0) { 809 dev_err(tc->dev, "Failed to finish training phase %d\n", 810 pattern); 811 } 812 813 return 0; 814 err: 815 return ret; 816 } 817 818 static int tc_main_link_setup(struct tc_data *tc) 819 { 820 struct drm_dp_aux *aux = &tc->aux; 821 struct device *dev = tc->dev; 822 unsigned int rate; 823 u32 dp_phy_ctrl; 824 int timeout; 825 u32 value; 826 int ret; 827 u8 tmp[8]; 828 829 /* display mode should be set at this point */ 830 if (!tc->mode) 831 return -EINVAL; 832 833 /* from excel file - DP0_SrcCtrl */ 834 tc_write(DP0_SRCCTRL, DP0_SRCCTRL_SCRMBLDIS | DP0_SRCCTRL_EN810B | 835 DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_LANES_2 | 836 DP0_SRCCTRL_BW27 | DP0_SRCCTRL_AUTOCORRECT); 837 /* from excel file - DP1_SrcCtrl */ 838 tc_write(0x07a0, 0x00003083); 839 840 rate = clk_get_rate(tc->refclk); 841 switch (rate) { 842 case 38400000: 843 value = REF_FREQ_38M4; 844 break; 845 case 26000000: 846 value = REF_FREQ_26M; 847 break; 848 case 19200000: 849 value = REF_FREQ_19M2; 850 break; 851 case 13000000: 852 value = REF_FREQ_13M; 853 break; 854 default: 855 return -EINVAL; 856 } 857 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; 858 tc_write(SYS_PLLPARAM, value); 859 /* Setup Main Link */ 860 dp_phy_ctrl = BGREN | PWR_SW_EN | BIT(2) | PHY_A0_EN | PHY_M0_EN; 861 tc_write(DP_PHY_CTRL, dp_phy_ctrl); 862 msleep(100); 863 864 /* PLL setup */ 865 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN); 866 tc_wait_pll_lock(tc); 867 868 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN); 869 tc_wait_pll_lock(tc); 870 871 /* PXL PLL setup */ 872 if (tc_test_pattern) { 873 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), 874 1000 * tc->mode->clock); 875 if (ret) 876 goto err; 877 } 878 879 /* Reset/Enable Main Links */ 880 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST; 881 tc_write(DP_PHY_CTRL, dp_phy_ctrl); 882 usleep_range(100, 200); 883 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST); 884 tc_write(DP_PHY_CTRL, dp_phy_ctrl); 885 886 timeout = 1000; 887 do { 888 tc_read(DP_PHY_CTRL, &value); 889 udelay(1); 890 } while ((!(value & PHY_RDY)) && (--timeout)); 891 892 if (timeout == 0) { 893 dev_err(dev, "timeout waiting for phy become ready"); 894 return -ETIMEDOUT; 895 } 896 897 /* Set misc: 8 bits per color */ 898 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8); 899 if (ret) 900 goto err; 901 902 /* 903 * ASSR mode 904 * on TC358767 side ASSR configured through strap pin 905 * seems there is no way to change this setting from SW 906 * 907 * check is tc configured for same mode 908 */ 909 if (tc->assr != tc->link.assr) { 910 dev_dbg(dev, "Trying to set display to ASSR: %d\n", 911 tc->assr); 912 /* try to set ASSR on display side */ 913 tmp[0] = tc->assr; 914 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]); 915 if (ret < 0) 916 goto err_dpcd_read; 917 /* read back */ 918 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp); 919 if (ret < 0) 920 goto err_dpcd_read; 921 922 if (tmp[0] != tc->assr) { 923 dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n", 924 tc->assr); 925 /* trying with disabled scrambler */ 926 tc->link.scrambler_dis = 1; 927 } 928 } 929 930 /* Setup Link & DPRx Config for Training */ 931 ret = drm_dp_link_configure(aux, &tc->link.base); 932 if (ret < 0) 933 goto err_dpcd_write; 934 935 /* DOWNSPREAD_CTRL */ 936 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00; 937 /* MAIN_LINK_CHANNEL_CODING_SET */ 938 tmp[1] = tc->link.coding8b10b ? DP_SET_ANSI_8B10B : 0x00; 939 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2); 940 if (ret < 0) 941 goto err_dpcd_write; 942 943 ret = tc_link_training(tc, DP_TRAINING_PATTERN_1); 944 if (ret) 945 goto err; 946 947 ret = tc_link_training(tc, DP_TRAINING_PATTERN_2); 948 if (ret) 949 goto err; 950 951 /* Clear DPCD 0x102 */ 952 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */ 953 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00; 954 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]); 955 if (ret < 0) 956 goto err_dpcd_write; 957 958 /* Clear Training Pattern, set AutoCorrect Mode = 1 */ 959 tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_AUTOCORRECT); 960 961 /* Wait */ 962 timeout = 100; 963 do { 964 udelay(1); 965 /* Read DPCD 0x202-0x207 */ 966 ret = drm_dp_dpcd_read_link_status(aux, tmp + 2); 967 if (ret < 0) 968 goto err_dpcd_read; 969 } while ((--timeout) && 970 !(drm_dp_channel_eq_ok(tmp + 2, tc->link.base.num_lanes))); 971 972 if (timeout == 0) { 973 /* Read DPCD 0x200-0x201 */ 974 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT, tmp, 2); 975 if (ret < 0) 976 goto err_dpcd_read; 977 dev_err(dev, "channel(s) EQ not ok\n"); 978 dev_info(dev, "0x0200 SINK_COUNT: 0x%02x\n", tmp[0]); 979 dev_info(dev, "0x0201 DEVICE_SERVICE_IRQ_VECTOR: 0x%02x\n", 980 tmp[1]); 981 dev_info(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[2]); 982 dev_info(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", 983 tmp[4]); 984 dev_info(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[5]); 985 dev_info(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n", 986 tmp[6]); 987 988 return -EAGAIN; 989 } 990 991 ret = tc_set_video_mode(tc, tc->mode); 992 if (ret) 993 goto err; 994 995 /* Set M/N */ 996 ret = tc_stream_clock_calc(tc); 997 if (ret) 998 goto err; 999 1000 return 0; 1001 err_dpcd_read: 1002 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret); 1003 return ret; 1004 err_dpcd_write: 1005 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret); 1006 err: 1007 return ret; 1008 } 1009 1010 static int tc_main_link_stream(struct tc_data *tc, int state) 1011 { 1012 int ret; 1013 u32 value; 1014 1015 dev_dbg(tc->dev, "stream: %d\n", state); 1016 1017 if (state) { 1018 value = VID_MN_GEN | DP_EN; 1019 if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 1020 value |= EF_EN; 1021 tc_write(DP0CTL, value); 1022 /* 1023 * VID_EN assertion should be delayed by at least N * LSCLK 1024 * cycles from the time VID_MN_GEN is enabled in order to 1025 * generate stable values for VID_M. LSCLK is 270 MHz or 1026 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(), 1027 * so a delay of at least 203 us should suffice. 1028 */ 1029 usleep_range(500, 1000); 1030 value |= VID_EN; 1031 tc_write(DP0CTL, value); 1032 /* Set input interface */ 1033 value = DP0_AUDSRC_NO_INPUT; 1034 if (tc_test_pattern) 1035 value |= DP0_VIDSRC_COLOR_BAR; 1036 else 1037 value |= DP0_VIDSRC_DPI_RX; 1038 tc_write(SYSCTRL, value); 1039 } else { 1040 tc_write(DP0CTL, 0); 1041 } 1042 1043 return 0; 1044 err: 1045 return ret; 1046 } 1047 1048 static void tc_bridge_pre_enable(struct drm_bridge *bridge) 1049 { 1050 struct tc_data *tc = bridge_to_tc(bridge); 1051 1052 drm_panel_prepare(tc->panel); 1053 } 1054 1055 static void tc_bridge_enable(struct drm_bridge *bridge) 1056 { 1057 struct tc_data *tc = bridge_to_tc(bridge); 1058 int ret; 1059 1060 ret = tc_main_link_setup(tc); 1061 if (ret < 0) { 1062 dev_err(tc->dev, "main link setup error: %d\n", ret); 1063 return; 1064 } 1065 1066 ret = tc_main_link_stream(tc, 1); 1067 if (ret < 0) { 1068 dev_err(tc->dev, "main link stream start error: %d\n", ret); 1069 return; 1070 } 1071 1072 drm_panel_enable(tc->panel); 1073 } 1074 1075 static void tc_bridge_disable(struct drm_bridge *bridge) 1076 { 1077 struct tc_data *tc = bridge_to_tc(bridge); 1078 int ret; 1079 1080 drm_panel_disable(tc->panel); 1081 1082 ret = tc_main_link_stream(tc, 0); 1083 if (ret < 0) 1084 dev_err(tc->dev, "main link stream stop error: %d\n", ret); 1085 } 1086 1087 static void tc_bridge_post_disable(struct drm_bridge *bridge) 1088 { 1089 struct tc_data *tc = bridge_to_tc(bridge); 1090 1091 drm_panel_unprepare(tc->panel); 1092 } 1093 1094 static bool tc_bridge_mode_fixup(struct drm_bridge *bridge, 1095 const struct drm_display_mode *mode, 1096 struct drm_display_mode *adj) 1097 { 1098 /* Fixup sync polarities, both hsync and vsync are active low */ 1099 adj->flags = mode->flags; 1100 adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); 1101 adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 1102 1103 return true; 1104 } 1105 1106 static enum drm_mode_status tc_connector_mode_valid(struct drm_connector *connector, 1107 struct drm_display_mode *mode) 1108 { 1109 /* DPI interface clock limitation: upto 154 MHz */ 1110 if (mode->clock > 154000) 1111 return MODE_CLOCK_HIGH; 1112 1113 return MODE_OK; 1114 } 1115 1116 static void tc_bridge_mode_set(struct drm_bridge *bridge, 1117 const struct drm_display_mode *mode, 1118 const struct drm_display_mode *adj) 1119 { 1120 struct tc_data *tc = bridge_to_tc(bridge); 1121 1122 tc->mode = mode; 1123 } 1124 1125 static int tc_connector_get_modes(struct drm_connector *connector) 1126 { 1127 struct tc_data *tc = connector_to_tc(connector); 1128 struct edid *edid; 1129 unsigned int count; 1130 1131 if (tc->panel && tc->panel->funcs && tc->panel->funcs->get_modes) { 1132 count = tc->panel->funcs->get_modes(tc->panel); 1133 if (count > 0) 1134 return count; 1135 } 1136 1137 edid = drm_get_edid(connector, &tc->aux.ddc); 1138 1139 kfree(tc->edid); 1140 tc->edid = edid; 1141 if (!edid) 1142 return 0; 1143 1144 drm_connector_update_edid_property(connector, edid); 1145 count = drm_add_edid_modes(connector, edid); 1146 1147 return count; 1148 } 1149 1150 static void tc_connector_set_polling(struct tc_data *tc, 1151 struct drm_connector *connector) 1152 { 1153 /* TODO: add support for HPD */ 1154 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1155 DRM_CONNECTOR_POLL_DISCONNECT; 1156 } 1157 1158 static struct drm_encoder * 1159 tc_connector_best_encoder(struct drm_connector *connector) 1160 { 1161 struct tc_data *tc = connector_to_tc(connector); 1162 1163 return tc->bridge.encoder; 1164 } 1165 1166 static const struct drm_connector_helper_funcs tc_connector_helper_funcs = { 1167 .get_modes = tc_connector_get_modes, 1168 .mode_valid = tc_connector_mode_valid, 1169 .best_encoder = tc_connector_best_encoder, 1170 }; 1171 1172 static const struct drm_connector_funcs tc_connector_funcs = { 1173 .fill_modes = drm_helper_probe_single_connector_modes, 1174 .destroy = drm_connector_cleanup, 1175 .reset = drm_atomic_helper_connector_reset, 1176 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1177 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1178 }; 1179 1180 static int tc_bridge_attach(struct drm_bridge *bridge) 1181 { 1182 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1183 struct tc_data *tc = bridge_to_tc(bridge); 1184 struct drm_device *drm = bridge->dev; 1185 int ret; 1186 1187 /* Create eDP connector */ 1188 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs); 1189 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, 1190 DRM_MODE_CONNECTOR_eDP); 1191 if (ret) 1192 return ret; 1193 1194 if (tc->panel) 1195 drm_panel_attach(tc->panel, &tc->connector); 1196 1197 drm_display_info_set_bus_formats(&tc->connector.display_info, 1198 &bus_format, 1); 1199 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder); 1200 1201 return 0; 1202 } 1203 1204 static const struct drm_bridge_funcs tc_bridge_funcs = { 1205 .attach = tc_bridge_attach, 1206 .mode_set = tc_bridge_mode_set, 1207 .pre_enable = tc_bridge_pre_enable, 1208 .enable = tc_bridge_enable, 1209 .disable = tc_bridge_disable, 1210 .post_disable = tc_bridge_post_disable, 1211 .mode_fixup = tc_bridge_mode_fixup, 1212 }; 1213 1214 static bool tc_readable_reg(struct device *dev, unsigned int reg) 1215 { 1216 return reg != SYSCTRL; 1217 } 1218 1219 static const struct regmap_range tc_volatile_ranges[] = { 1220 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS), 1221 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ), 1222 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL), 1223 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL), 1224 regmap_reg_range(VFUEN0, VFUEN0), 1225 }; 1226 1227 static const struct regmap_access_table tc_volatile_table = { 1228 .yes_ranges = tc_volatile_ranges, 1229 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges), 1230 }; 1231 1232 static bool tc_writeable_reg(struct device *dev, unsigned int reg) 1233 { 1234 return (reg != TC_IDREG) && 1235 (reg != DP0_LTSTAT) && 1236 (reg != DP0_SNKLTCHGREQ); 1237 } 1238 1239 static const struct regmap_config tc_regmap_config = { 1240 .name = "tc358767", 1241 .reg_bits = 16, 1242 .val_bits = 32, 1243 .reg_stride = 4, 1244 .max_register = PLL_DBG, 1245 .cache_type = REGCACHE_RBTREE, 1246 .readable_reg = tc_readable_reg, 1247 .volatile_table = &tc_volatile_table, 1248 .writeable_reg = tc_writeable_reg, 1249 .reg_format_endian = REGMAP_ENDIAN_BIG, 1250 .val_format_endian = REGMAP_ENDIAN_LITTLE, 1251 }; 1252 1253 static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id) 1254 { 1255 struct device *dev = &client->dev; 1256 struct tc_data *tc; 1257 int ret; 1258 1259 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL); 1260 if (!tc) 1261 return -ENOMEM; 1262 1263 tc->dev = dev; 1264 1265 /* port@2 is the output port */ 1266 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL); 1267 if (ret && ret != -ENODEV) 1268 return ret; 1269 1270 /* Shut down GPIO is optional */ 1271 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH); 1272 if (IS_ERR(tc->sd_gpio)) 1273 return PTR_ERR(tc->sd_gpio); 1274 1275 if (tc->sd_gpio) { 1276 gpiod_set_value_cansleep(tc->sd_gpio, 0); 1277 usleep_range(5000, 10000); 1278 } 1279 1280 /* Reset GPIO is optional */ 1281 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1282 if (IS_ERR(tc->reset_gpio)) 1283 return PTR_ERR(tc->reset_gpio); 1284 1285 if (tc->reset_gpio) { 1286 gpiod_set_value_cansleep(tc->reset_gpio, 1); 1287 usleep_range(5000, 10000); 1288 } 1289 1290 tc->refclk = devm_clk_get(dev, "ref"); 1291 if (IS_ERR(tc->refclk)) { 1292 ret = PTR_ERR(tc->refclk); 1293 dev_err(dev, "Failed to get refclk: %d\n", ret); 1294 return ret; 1295 } 1296 1297 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config); 1298 if (IS_ERR(tc->regmap)) { 1299 ret = PTR_ERR(tc->regmap); 1300 dev_err(dev, "Failed to initialize regmap: %d\n", ret); 1301 return ret; 1302 } 1303 1304 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev); 1305 if (ret) { 1306 dev_err(tc->dev, "can not read device ID: %d\n", ret); 1307 return ret; 1308 } 1309 1310 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) { 1311 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev); 1312 return -EINVAL; 1313 } 1314 1315 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */ 1316 1317 ret = tc_aux_link_setup(tc); 1318 if (ret) 1319 return ret; 1320 1321 /* Register DP AUX channel */ 1322 tc->aux.name = "TC358767 AUX i2c adapter"; 1323 tc->aux.dev = tc->dev; 1324 tc->aux.transfer = tc_aux_transfer; 1325 ret = drm_dp_aux_register(&tc->aux); 1326 if (ret) 1327 return ret; 1328 1329 ret = tc_get_display_props(tc); 1330 if (ret) 1331 goto err_unregister_aux; 1332 1333 tc_connector_set_polling(tc, &tc->connector); 1334 1335 tc->bridge.funcs = &tc_bridge_funcs; 1336 tc->bridge.of_node = dev->of_node; 1337 drm_bridge_add(&tc->bridge); 1338 1339 i2c_set_clientdata(client, tc); 1340 1341 return 0; 1342 err_unregister_aux: 1343 drm_dp_aux_unregister(&tc->aux); 1344 return ret; 1345 } 1346 1347 static int tc_remove(struct i2c_client *client) 1348 { 1349 struct tc_data *tc = i2c_get_clientdata(client); 1350 1351 drm_bridge_remove(&tc->bridge); 1352 drm_dp_aux_unregister(&tc->aux); 1353 1354 tc_pxl_pll_dis(tc); 1355 1356 return 0; 1357 } 1358 1359 static const struct i2c_device_id tc358767_i2c_ids[] = { 1360 { "tc358767", 0 }, 1361 { } 1362 }; 1363 MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids); 1364 1365 static const struct of_device_id tc358767_of_ids[] = { 1366 { .compatible = "toshiba,tc358767", }, 1367 { } 1368 }; 1369 MODULE_DEVICE_TABLE(of, tc358767_of_ids); 1370 1371 static struct i2c_driver tc358767_driver = { 1372 .driver = { 1373 .name = "tc358767", 1374 .of_match_table = tc358767_of_ids, 1375 }, 1376 .id_table = tc358767_i2c_ids, 1377 .probe = tc_probe, 1378 .remove = tc_remove, 1379 }; 1380 module_i2c_driver(tc358767_driver); 1381 1382 MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>"); 1383 MODULE_DESCRIPTION("tc358767 eDP encoder driver"); 1384 MODULE_LICENSE("GPL"); 1385