1 /* 2 * tc358767 eDP bridge driver 3 * 4 * Copyright (C) 2016 CogentEmbedded Inc 5 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com> 6 * 7 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de> 8 * 9 * Copyright (C) 2016 Zodiac Inflight Innovations 10 * 11 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c 12 * 13 * Copyright (C) 2012 Texas Instruments 14 * Author: Rob Clark <robdclark@gmail.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or 19 * (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 */ 26 27 #include <linux/clk.h> 28 #include <linux/device.h> 29 #include <linux/gpio/consumer.h> 30 #include <linux/i2c.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/regmap.h> 34 #include <linux/slab.h> 35 36 #include <drm/drm_atomic_helper.h> 37 #include <drm/drm_dp_helper.h> 38 #include <drm/drm_edid.h> 39 #include <drm/drm_of.h> 40 #include <drm/drm_panel.h> 41 #include <drm/drm_probe_helper.h> 42 43 /* Registers */ 44 45 /* Display Parallel Interface */ 46 #define DPIPXLFMT 0x0440 47 #define VS_POL_ACTIVE_LOW (1 << 10) 48 #define HS_POL_ACTIVE_LOW (1 << 9) 49 #define DE_POL_ACTIVE_HIGH (0 << 8) 50 #define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */ 51 #define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */ 52 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */ 53 #define DPI_BPP_RGB888 (0 << 0) 54 #define DPI_BPP_RGB666 (1 << 0) 55 #define DPI_BPP_RGB565 (2 << 0) 56 57 /* Video Path */ 58 #define VPCTRL0 0x0450 59 #define OPXLFMT_RGB666 (0 << 8) 60 #define OPXLFMT_RGB888 (1 << 8) 61 #define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */ 62 #define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */ 63 #define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */ 64 #define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */ 65 #define HTIM01 0x0454 66 #define HTIM02 0x0458 67 #define VTIM01 0x045c 68 #define VTIM02 0x0460 69 #define VFUEN0 0x0464 70 #define VFUEN BIT(0) /* Video Frame Timing Upload */ 71 72 /* System */ 73 #define TC_IDREG 0x0500 74 #define SYSSTAT 0x0508 75 #define SYSCTRL 0x0510 76 #define DP0_AUDSRC_NO_INPUT (0 << 3) 77 #define DP0_AUDSRC_I2S_RX (1 << 3) 78 #define DP0_VIDSRC_NO_INPUT (0 << 0) 79 #define DP0_VIDSRC_DSI_RX (1 << 0) 80 #define DP0_VIDSRC_DPI_RX (2 << 0) 81 #define DP0_VIDSRC_COLOR_BAR (3 << 0) 82 #define GPIOM 0x0540 83 #define GPIOC 0x0544 84 #define GPIOO 0x0548 85 #define GPIOI 0x054c 86 #define INTCTL_G 0x0560 87 #define INTSTS_G 0x0564 88 89 #define INT_SYSERR BIT(16) 90 #define INT_GPIO_H(x) (1 << (x == 0 ? 2 : 10)) 91 #define INT_GPIO_LC(x) (1 << (x == 0 ? 3 : 11)) 92 93 #define INT_GP0_LCNT 0x0584 94 #define INT_GP1_LCNT 0x0588 95 96 /* Control */ 97 #define DP0CTL 0x0600 98 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */ 99 #define EF_EN BIT(5) /* Enable Enhanced Framing */ 100 #define VID_EN BIT(1) /* Video transmission enable */ 101 #define DP_EN BIT(0) /* Enable DPTX function */ 102 103 /* Clocks */ 104 #define DP0_VIDMNGEN0 0x0610 105 #define DP0_VIDMNGEN1 0x0614 106 #define DP0_VMNGENSTATUS 0x0618 107 108 /* Main Channel */ 109 #define DP0_SECSAMPLE 0x0640 110 #define DP0_VIDSYNCDELAY 0x0644 111 #define DP0_TOTALVAL 0x0648 112 #define DP0_STARTVAL 0x064c 113 #define DP0_ACTIVEVAL 0x0650 114 #define DP0_SYNCVAL 0x0654 115 #define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15) 116 #define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31) 117 #define DP0_MISC 0x0658 118 #define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */ 119 #define BPC_6 (0 << 5) 120 #define BPC_8 (1 << 5) 121 122 /* AUX channel */ 123 #define DP0_AUXCFG0 0x0660 124 #define DP0_AUXCFG1 0x0664 125 #define AUX_RX_FILTER_EN BIT(16) 126 127 #define DP0_AUXADDR 0x0668 128 #define DP0_AUXWDATA(i) (0x066c + (i) * 4) 129 #define DP0_AUXRDATA(i) (0x067c + (i) * 4) 130 #define DP0_AUXSTATUS 0x068c 131 #define AUX_STATUS_MASK 0xf0 132 #define AUX_STATUS_SHIFT 4 133 #define AUX_TIMEOUT BIT(1) 134 #define AUX_BUSY BIT(0) 135 #define DP0_AUXI2CADR 0x0698 136 137 /* Link Training */ 138 #define DP0_SRCCTRL 0x06a0 139 #define DP0_SRCCTRL_SCRMBLDIS BIT(13) 140 #define DP0_SRCCTRL_EN810B BIT(12) 141 #define DP0_SRCCTRL_NOTP (0 << 8) 142 #define DP0_SRCCTRL_TP1 (1 << 8) 143 #define DP0_SRCCTRL_TP2 (2 << 8) 144 #define DP0_SRCCTRL_LANESKEW BIT(7) 145 #define DP0_SRCCTRL_SSCG BIT(3) 146 #define DP0_SRCCTRL_LANES_1 (0 << 2) 147 #define DP0_SRCCTRL_LANES_2 (1 << 2) 148 #define DP0_SRCCTRL_BW27 (1 << 1) 149 #define DP0_SRCCTRL_BW162 (0 << 1) 150 #define DP0_SRCCTRL_AUTOCORRECT BIT(0) 151 #define DP0_LTSTAT 0x06d0 152 #define LT_LOOPDONE BIT(13) 153 #define LT_STATUS_MASK (0x1f << 8) 154 #define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4) 155 #define LT_INTERLANE_ALIGN_DONE BIT(3) 156 #define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS) 157 #define DP0_SNKLTCHGREQ 0x06d4 158 #define DP0_LTLOOPCTRL 0x06d8 159 #define DP0_SNKLTCTRL 0x06e4 160 161 #define DP1_SRCCTRL 0x07a0 162 163 /* PHY */ 164 #define DP_PHY_CTRL 0x0800 165 #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */ 166 #define BGREN BIT(25) /* AUX PHY BGR Enable */ 167 #define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */ 168 #define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */ 169 #define PHY_RDY BIT(16) /* PHY Main Channels Ready */ 170 #define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */ 171 #define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */ 172 #define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */ 173 #define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */ 174 175 /* PLL */ 176 #define DP0_PLLCTRL 0x0900 177 #define DP1_PLLCTRL 0x0904 /* not defined in DS */ 178 #define PXL_PLLCTRL 0x0908 179 #define PLLUPDATE BIT(2) 180 #define PLLBYP BIT(1) 181 #define PLLEN BIT(0) 182 #define PXL_PLLPARAM 0x0914 183 #define IN_SEL_REFCLK (0 << 14) 184 #define SYS_PLLPARAM 0x0918 185 #define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */ 186 #define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */ 187 #define REF_FREQ_26M (2 << 8) /* 26 MHz */ 188 #define REF_FREQ_13M (3 << 8) /* 13 MHz */ 189 #define SYSCLK_SEL_LSCLK (0 << 4) 190 #define LSCLK_DIV_1 (0 << 0) 191 #define LSCLK_DIV_2 (1 << 0) 192 193 /* Test & Debug */ 194 #define TSTCTL 0x0a00 195 #define PLL_DBG 0x0a04 196 197 static bool tc_test_pattern; 198 module_param_named(test, tc_test_pattern, bool, 0644); 199 200 struct tc_edp_link { 201 struct drm_dp_link base; 202 u8 assr; 203 bool scrambler_dis; 204 bool spread; 205 }; 206 207 struct tc_data { 208 struct device *dev; 209 struct regmap *regmap; 210 struct drm_dp_aux aux; 211 212 struct drm_bridge bridge; 213 struct drm_connector connector; 214 struct drm_panel *panel; 215 216 /* link settings */ 217 struct tc_edp_link link; 218 219 /* display edid */ 220 struct edid *edid; 221 /* current mode */ 222 struct drm_display_mode mode; 223 224 u32 rev; 225 u8 assr; 226 227 struct gpio_desc *sd_gpio; 228 struct gpio_desc *reset_gpio; 229 struct clk *refclk; 230 231 /* do we have IRQ */ 232 bool have_irq; 233 234 /* HPD pin number (0 or 1) or -ENODEV */ 235 int hpd_pin; 236 }; 237 238 static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a) 239 { 240 return container_of(a, struct tc_data, aux); 241 } 242 243 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b) 244 { 245 return container_of(b, struct tc_data, bridge); 246 } 247 248 static inline struct tc_data *connector_to_tc(struct drm_connector *c) 249 { 250 return container_of(c, struct tc_data, connector); 251 } 252 253 /* Simple macros to avoid repeated error checks */ 254 #define tc_write(reg, var) \ 255 do { \ 256 ret = regmap_write(tc->regmap, reg, var); \ 257 if (ret) \ 258 goto err; \ 259 } while (0) 260 #define tc_read(reg, var) \ 261 do { \ 262 ret = regmap_read(tc->regmap, reg, var); \ 263 if (ret) \ 264 goto err; \ 265 } while (0) 266 267 static inline int tc_poll_timeout(struct regmap *map, unsigned int addr, 268 unsigned int cond_mask, 269 unsigned int cond_value, 270 unsigned long sleep_us, u64 timeout_us) 271 { 272 ktime_t timeout = ktime_add_us(ktime_get(), timeout_us); 273 unsigned int val; 274 int ret; 275 276 for (;;) { 277 ret = regmap_read(map, addr, &val); 278 if (ret) 279 break; 280 if ((val & cond_mask) == cond_value) 281 break; 282 if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) { 283 ret = regmap_read(map, addr, &val); 284 break; 285 } 286 if (sleep_us) 287 usleep_range((sleep_us >> 2) + 1, sleep_us); 288 } 289 return ret ?: (((val & cond_mask) == cond_value) ? 0 : -ETIMEDOUT); 290 } 291 292 static int tc_aux_wait_busy(struct tc_data *tc, unsigned int timeout_ms) 293 { 294 return tc_poll_timeout(tc->regmap, DP0_AUXSTATUS, AUX_BUSY, 0, 295 1000, 1000 * timeout_ms); 296 } 297 298 static int tc_aux_get_status(struct tc_data *tc, u8 *reply) 299 { 300 int ret; 301 u32 value; 302 303 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &value); 304 if (ret < 0) 305 return ret; 306 307 if (value & AUX_BUSY) { 308 dev_err(tc->dev, "aux busy!\n"); 309 return -EBUSY; 310 } 311 312 if (value & AUX_TIMEOUT) { 313 dev_err(tc->dev, "aux access timeout!\n"); 314 return -ETIMEDOUT; 315 } 316 317 *reply = (value & AUX_STATUS_MASK) >> AUX_STATUS_SHIFT; 318 return 0; 319 } 320 321 static ssize_t tc_aux_transfer(struct drm_dp_aux *aux, 322 struct drm_dp_aux_msg *msg) 323 { 324 struct tc_data *tc = aux_to_tc(aux); 325 size_t size = min_t(size_t, 8, msg->size); 326 u8 request = msg->request & ~DP_AUX_I2C_MOT; 327 u8 *buf = msg->buffer; 328 u32 tmp = 0; 329 int i = 0; 330 int ret; 331 332 if (size == 0) 333 return 0; 334 335 ret = tc_aux_wait_busy(tc, 100); 336 if (ret) 337 goto err; 338 339 if (request == DP_AUX_I2C_WRITE || request == DP_AUX_NATIVE_WRITE) { 340 /* Store data */ 341 while (i < size) { 342 if (request == DP_AUX_NATIVE_WRITE) 343 tmp = tmp | (buf[i] << (8 * (i & 0x3))); 344 else 345 tmp = (tmp << 8) | buf[i]; 346 i++; 347 if (((i % 4) == 0) || (i == size)) { 348 tc_write(DP0_AUXWDATA((i - 1) >> 2), tmp); 349 tmp = 0; 350 } 351 } 352 } else if (request != DP_AUX_I2C_READ && 353 request != DP_AUX_NATIVE_READ) { 354 return -EINVAL; 355 } 356 357 /* Store address */ 358 tc_write(DP0_AUXADDR, msg->address); 359 /* Start transfer */ 360 tc_write(DP0_AUXCFG0, ((size - 1) << 8) | request); 361 362 ret = tc_aux_wait_busy(tc, 100); 363 if (ret) 364 goto err; 365 366 ret = tc_aux_get_status(tc, &msg->reply); 367 if (ret) 368 goto err; 369 370 if (request == DP_AUX_I2C_READ || request == DP_AUX_NATIVE_READ) { 371 /* Read data */ 372 while (i < size) { 373 if ((i % 4) == 0) 374 tc_read(DP0_AUXRDATA(i >> 2), &tmp); 375 buf[i] = tmp & 0xff; 376 tmp = tmp >> 8; 377 i++; 378 } 379 } 380 381 return size; 382 err: 383 return ret; 384 } 385 386 static const char * const training_pattern1_errors[] = { 387 "No errors", 388 "Aux write error", 389 "Aux read error", 390 "Max voltage reached error", 391 "Loop counter expired error", 392 "res", "res", "res" 393 }; 394 395 static const char * const training_pattern2_errors[] = { 396 "No errors", 397 "Aux write error", 398 "Aux read error", 399 "Clock recovery failed error", 400 "Loop counter expired error", 401 "res", "res", "res" 402 }; 403 404 static u32 tc_srcctrl(struct tc_data *tc) 405 { 406 /* 407 * No training pattern, skew lane 1 data by two LSCLK cycles with 408 * respect to lane 0 data, AutoCorrect Mode = 0 409 */ 410 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B; 411 412 if (tc->link.scrambler_dis) 413 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */ 414 if (tc->link.spread) 415 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */ 416 if (tc->link.base.num_lanes == 2) 417 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */ 418 if (tc->link.base.rate != 162000) 419 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */ 420 return reg; 421 } 422 423 static void tc_wait_pll_lock(struct tc_data *tc) 424 { 425 /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */ 426 usleep_range(3000, 6000); 427 } 428 429 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) 430 { 431 int ret; 432 int i_pre, best_pre = 1; 433 int i_post, best_post = 1; 434 int div, best_div = 1; 435 int mul, best_mul = 1; 436 int delta, best_delta; 437 int ext_div[] = {1, 2, 3, 5, 7}; 438 int best_pixelclock = 0; 439 int vco_hi = 0; 440 441 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock, 442 refclk); 443 best_delta = pixelclock; 444 /* Loop over all possible ext_divs, skipping invalid configurations */ 445 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) { 446 /* 447 * refclk / ext_pre_div should be in the 1 to 200 MHz range. 448 * We don't allow any refclk > 200 MHz, only check lower bounds. 449 */ 450 if (refclk / ext_div[i_pre] < 1000000) 451 continue; 452 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) { 453 for (div = 1; div <= 16; div++) { 454 u32 clk; 455 u64 tmp; 456 457 tmp = pixelclock * ext_div[i_pre] * 458 ext_div[i_post] * div; 459 do_div(tmp, refclk); 460 mul = tmp; 461 462 /* Check limits */ 463 if ((mul < 1) || (mul > 128)) 464 continue; 465 466 clk = (refclk / ext_div[i_pre] / div) * mul; 467 /* 468 * refclk * mul / (ext_pre_div * pre_div) 469 * should be in the 150 to 650 MHz range 470 */ 471 if ((clk > 650000000) || (clk < 150000000)) 472 continue; 473 474 clk = clk / ext_div[i_post]; 475 delta = clk - pixelclock; 476 477 if (abs(delta) < abs(best_delta)) { 478 best_pre = i_pre; 479 best_post = i_post; 480 best_div = div; 481 best_mul = mul; 482 best_delta = delta; 483 best_pixelclock = clk; 484 } 485 } 486 } 487 } 488 if (best_pixelclock == 0) { 489 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n", 490 pixelclock); 491 return -EINVAL; 492 } 493 494 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock, 495 best_delta); 496 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk, 497 ext_div[best_pre], best_div, best_mul, ext_div[best_post]); 498 499 /* if VCO >= 300 MHz */ 500 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000) 501 vco_hi = 1; 502 /* see DS */ 503 if (best_div == 16) 504 best_div = 0; 505 if (best_mul == 128) 506 best_mul = 0; 507 508 /* Power up PLL and switch to bypass */ 509 tc_write(PXL_PLLCTRL, PLLBYP | PLLEN); 510 511 tc_write(PXL_PLLPARAM, 512 (vco_hi << 24) | /* For PLL VCO >= 300 MHz = 1 */ 513 (ext_div[best_pre] << 20) | /* External Pre-divider */ 514 (ext_div[best_post] << 16) | /* External Post-divider */ 515 IN_SEL_REFCLK | /* Use RefClk as PLL input */ 516 (best_div << 8) | /* Divider for PLL RefClk */ 517 (best_mul << 0)); /* Multiplier for PLL */ 518 519 /* Force PLL parameter update and disable bypass */ 520 tc_write(PXL_PLLCTRL, PLLUPDATE | PLLEN); 521 522 tc_wait_pll_lock(tc); 523 524 return 0; 525 err: 526 return ret; 527 } 528 529 static int tc_pxl_pll_dis(struct tc_data *tc) 530 { 531 /* Enable PLL bypass, power down PLL */ 532 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP); 533 } 534 535 static int tc_stream_clock_calc(struct tc_data *tc) 536 { 537 int ret; 538 /* 539 * If the Stream clock and Link Symbol clock are 540 * asynchronous with each other, the value of M changes over 541 * time. This way of generating link clock and stream 542 * clock is called Asynchronous Clock mode. The value M 543 * must change while the value N stays constant. The 544 * value of N in this Asynchronous Clock mode must be set 545 * to 2^15 or 32,768. 546 * 547 * LSCLK = 1/10 of high speed link clock 548 * 549 * f_STRMCLK = M/N * f_LSCLK 550 * M/N = f_STRMCLK / f_LSCLK 551 * 552 */ 553 tc_write(DP0_VIDMNGEN1, 32768); 554 555 return 0; 556 err: 557 return ret; 558 } 559 560 static int tc_aux_link_setup(struct tc_data *tc) 561 { 562 unsigned long rate; 563 u32 value; 564 int ret; 565 566 rate = clk_get_rate(tc->refclk); 567 switch (rate) { 568 case 38400000: 569 value = REF_FREQ_38M4; 570 break; 571 case 26000000: 572 value = REF_FREQ_26M; 573 break; 574 case 19200000: 575 value = REF_FREQ_19M2; 576 break; 577 case 13000000: 578 value = REF_FREQ_13M; 579 break; 580 default: 581 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate); 582 return -EINVAL; 583 } 584 585 /* Setup DP-PHY / PLL */ 586 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; 587 tc_write(SYS_PLLPARAM, value); 588 589 tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | PHY_A0_EN); 590 591 /* 592 * Initially PLLs are in bypass. Force PLL parameter update, 593 * disable PLL bypass, enable PLL 594 */ 595 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN); 596 tc_wait_pll_lock(tc); 597 598 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN); 599 tc_wait_pll_lock(tc); 600 601 ret = tc_poll_timeout(tc->regmap, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 602 1000); 603 if (ret == -ETIMEDOUT) { 604 dev_err(tc->dev, "Timeout waiting for PHY to become ready"); 605 return ret; 606 } else if (ret) { 607 goto err; 608 } 609 610 /* Setup AUX link */ 611 tc_write(DP0_AUXCFG1, AUX_RX_FILTER_EN | 612 (0x06 << 8) | /* Aux Bit Period Calculator Threshold */ 613 (0x3f << 0)); /* Aux Response Timeout Timer */ 614 615 return 0; 616 err: 617 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret); 618 return ret; 619 } 620 621 static int tc_get_display_props(struct tc_data *tc) 622 { 623 int ret; 624 /* temp buffer */ 625 u8 tmp[8]; 626 627 /* Read DP Rx Link Capability */ 628 ret = drm_dp_link_probe(&tc->aux, &tc->link.base); 629 if (ret < 0) 630 goto err_dpcd_read; 631 if (tc->link.base.rate != 162000 && tc->link.base.rate != 270000) { 632 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n"); 633 tc->link.base.rate = 270000; 634 } 635 636 if (tc->link.base.num_lanes > 2) { 637 dev_dbg(tc->dev, "Falling to 2 lanes\n"); 638 tc->link.base.num_lanes = 2; 639 } 640 641 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, tmp); 642 if (ret < 0) 643 goto err_dpcd_read; 644 tc->link.spread = tmp[0] & DP_MAX_DOWNSPREAD_0_5; 645 646 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, tmp); 647 if (ret < 0) 648 goto err_dpcd_read; 649 650 tc->link.scrambler_dis = false; 651 /* read assr */ 652 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, tmp); 653 if (ret < 0) 654 goto err_dpcd_read; 655 tc->link.assr = tmp[0] & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; 656 657 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n", 658 tc->link.base.revision >> 4, tc->link.base.revision & 0x0f, 659 (tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps", 660 tc->link.base.num_lanes, 661 (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ? 662 "enhanced" : "non-enhanced"); 663 dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n", 664 tc->link.spread ? "0.5%" : "0.0%", 665 tc->link.scrambler_dis ? "disabled" : "enabled"); 666 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n", 667 tc->link.assr, tc->assr); 668 669 return 0; 670 671 err_dpcd_read: 672 dev_err(tc->dev, "failed to read DPCD: %d\n", ret); 673 return ret; 674 } 675 676 static int tc_set_video_mode(struct tc_data *tc, 677 const struct drm_display_mode *mode) 678 { 679 int ret; 680 int vid_sync_dly; 681 int max_tu_symbol; 682 683 int left_margin = mode->htotal - mode->hsync_end; 684 int right_margin = mode->hsync_start - mode->hdisplay; 685 int hsync_len = mode->hsync_end - mode->hsync_start; 686 int upper_margin = mode->vtotal - mode->vsync_end; 687 int lower_margin = mode->vsync_start - mode->vdisplay; 688 int vsync_len = mode->vsync_end - mode->vsync_start; 689 690 /* 691 * Recommended maximum number of symbols transferred in a transfer unit: 692 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size, 693 * (output active video bandwidth in bytes)) 694 * Must be less than tu_size. 695 */ 696 max_tu_symbol = TU_SIZE_RECOMMENDED - 1; 697 698 dev_dbg(tc->dev, "set mode %dx%d\n", 699 mode->hdisplay, mode->vdisplay); 700 dev_dbg(tc->dev, "H margin %d,%d sync %d\n", 701 left_margin, right_margin, hsync_len); 702 dev_dbg(tc->dev, "V margin %d,%d sync %d\n", 703 upper_margin, lower_margin, vsync_len); 704 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal); 705 706 707 /* 708 * LCD Ctl Frame Size 709 * datasheet is not clear of vsdelay in case of DPI 710 * assume we do not need any delay when DPI is a source of 711 * sync signals 712 */ 713 tc_write(VPCTRL0, (0 << 20) /* VSDELAY */ | 714 OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED); 715 tc_write(HTIM01, (ALIGN(left_margin, 2) << 16) | /* H back porch */ 716 (ALIGN(hsync_len, 2) << 0)); /* Hsync */ 717 tc_write(HTIM02, (ALIGN(right_margin, 2) << 16) | /* H front porch */ 718 (ALIGN(mode->hdisplay, 2) << 0)); /* width */ 719 tc_write(VTIM01, (upper_margin << 16) | /* V back porch */ 720 (vsync_len << 0)); /* Vsync */ 721 tc_write(VTIM02, (lower_margin << 16) | /* V front porch */ 722 (mode->vdisplay << 0)); /* height */ 723 tc_write(VFUEN0, VFUEN); /* update settings */ 724 725 /* Test pattern settings */ 726 tc_write(TSTCTL, 727 (120 << 24) | /* Red Color component value */ 728 (20 << 16) | /* Green Color component value */ 729 (99 << 8) | /* Blue Color component value */ 730 (1 << 4) | /* Enable I2C Filter */ 731 (2 << 0) | /* Color bar Mode */ 732 0); 733 734 /* DP Main Stream Attributes */ 735 vid_sync_dly = hsync_len + left_margin + mode->hdisplay; 736 tc_write(DP0_VIDSYNCDELAY, 737 (max_tu_symbol << 16) | /* thresh_dly */ 738 (vid_sync_dly << 0)); 739 740 tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal)); 741 742 tc_write(DP0_STARTVAL, 743 ((upper_margin + vsync_len) << 16) | 744 ((left_margin + hsync_len) << 0)); 745 746 tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay)); 747 748 tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0) | 749 ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? SYNCVAL_HS_POL_ACTIVE_LOW : 0) | 750 ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? SYNCVAL_VS_POL_ACTIVE_LOW : 0)); 751 752 tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW | 753 DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888); 754 755 tc_write(DP0_MISC, (max_tu_symbol << 23) | (TU_SIZE_RECOMMENDED << 16) | 756 BPC_8); 757 758 return 0; 759 err: 760 return ret; 761 } 762 763 static int tc_wait_link_training(struct tc_data *tc) 764 { 765 u32 timeout = 1000; 766 u32 value; 767 int ret; 768 769 do { 770 udelay(1); 771 tc_read(DP0_LTSTAT, &value); 772 } while ((!(value & LT_LOOPDONE)) && (--timeout)); 773 774 if (timeout == 0) { 775 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n"); 776 return -ETIMEDOUT; 777 } 778 779 return (value >> 8) & 0x7; 780 781 err: 782 return ret; 783 } 784 785 static int tc_main_link_enable(struct tc_data *tc) 786 { 787 struct drm_dp_aux *aux = &tc->aux; 788 struct device *dev = tc->dev; 789 unsigned int rate; 790 u32 dp_phy_ctrl; 791 int timeout; 792 u32 value; 793 int ret; 794 u8 tmp[8]; 795 796 dev_dbg(tc->dev, "link enable\n"); 797 798 tc_read(DP0CTL, &value); 799 if (WARN_ON(value & DP_EN)) 800 tc_write(DP0CTL, 0); 801 802 tc_write(DP0_SRCCTRL, tc_srcctrl(tc)); 803 /* SSCG and BW27 on DP1 must be set to the same as on DP0 */ 804 tc_write(DP1_SRCCTRL, 805 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) | 806 ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0)); 807 808 rate = clk_get_rate(tc->refclk); 809 switch (rate) { 810 case 38400000: 811 value = REF_FREQ_38M4; 812 break; 813 case 26000000: 814 value = REF_FREQ_26M; 815 break; 816 case 19200000: 817 value = REF_FREQ_19M2; 818 break; 819 case 13000000: 820 value = REF_FREQ_13M; 821 break; 822 default: 823 return -EINVAL; 824 } 825 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; 826 tc_write(SYS_PLLPARAM, value); 827 828 /* Setup Main Link */ 829 dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN; 830 if (tc->link.base.num_lanes == 2) 831 dp_phy_ctrl |= PHY_2LANE; 832 tc_write(DP_PHY_CTRL, dp_phy_ctrl); 833 834 /* PLL setup */ 835 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN); 836 tc_wait_pll_lock(tc); 837 838 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN); 839 tc_wait_pll_lock(tc); 840 841 /* Reset/Enable Main Links */ 842 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST; 843 tc_write(DP_PHY_CTRL, dp_phy_ctrl); 844 usleep_range(100, 200); 845 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST); 846 tc_write(DP_PHY_CTRL, dp_phy_ctrl); 847 848 timeout = 1000; 849 do { 850 tc_read(DP_PHY_CTRL, &value); 851 udelay(1); 852 } while ((!(value & PHY_RDY)) && (--timeout)); 853 854 if (timeout == 0) { 855 dev_err(dev, "timeout waiting for phy become ready"); 856 return -ETIMEDOUT; 857 } 858 859 /* Set misc: 8 bits per color */ 860 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8); 861 if (ret) 862 goto err; 863 864 /* 865 * ASSR mode 866 * on TC358767 side ASSR configured through strap pin 867 * seems there is no way to change this setting from SW 868 * 869 * check is tc configured for same mode 870 */ 871 if (tc->assr != tc->link.assr) { 872 dev_dbg(dev, "Trying to set display to ASSR: %d\n", 873 tc->assr); 874 /* try to set ASSR on display side */ 875 tmp[0] = tc->assr; 876 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]); 877 if (ret < 0) 878 goto err_dpcd_read; 879 /* read back */ 880 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp); 881 if (ret < 0) 882 goto err_dpcd_read; 883 884 if (tmp[0] != tc->assr) { 885 dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n", 886 tc->assr); 887 /* trying with disabled scrambler */ 888 tc->link.scrambler_dis = true; 889 } 890 } 891 892 /* Setup Link & DPRx Config for Training */ 893 ret = drm_dp_link_configure(aux, &tc->link.base); 894 if (ret < 0) 895 goto err_dpcd_write; 896 897 /* DOWNSPREAD_CTRL */ 898 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00; 899 /* MAIN_LINK_CHANNEL_CODING_SET */ 900 tmp[1] = DP_SET_ANSI_8B10B; 901 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2); 902 if (ret < 0) 903 goto err_dpcd_write; 904 905 /* Reset voltage-swing & pre-emphasis */ 906 tmp[0] = tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 907 DP_TRAIN_PRE_EMPH_LEVEL_0; 908 ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2); 909 if (ret < 0) 910 goto err_dpcd_write; 911 912 /* Clock-Recovery */ 913 914 /* Set DPCD 0x102 for Training Pattern 1 */ 915 tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | 916 DP_TRAINING_PATTERN_1); 917 918 tc_write(DP0_LTLOOPCTRL, 919 (15 << 28) | /* Defer Iteration Count */ 920 (15 << 24) | /* Loop Iteration Count */ 921 (0xd << 0)); /* Loop Timer Delay */ 922 923 tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | 924 DP0_SRCCTRL_AUTOCORRECT | DP0_SRCCTRL_TP1); 925 926 /* Enable DP0 to start Link Training */ 927 tc_write(DP0CTL, 928 ((tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ? EF_EN : 0) | 929 DP_EN); 930 931 /* wait */ 932 ret = tc_wait_link_training(tc); 933 if (ret < 0) 934 goto err; 935 936 if (ret) { 937 dev_err(tc->dev, "Link training phase 1 failed: %s\n", 938 training_pattern1_errors[ret]); 939 ret = -ENODEV; 940 goto err; 941 } 942 943 /* Channel Equalization */ 944 945 /* Set DPCD 0x102 for Training Pattern 2 */ 946 tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | 947 DP_TRAINING_PATTERN_2); 948 949 tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | 950 DP0_SRCCTRL_AUTOCORRECT | DP0_SRCCTRL_TP2); 951 952 /* wait */ 953 ret = tc_wait_link_training(tc); 954 if (ret < 0) 955 goto err; 956 957 if (ret) { 958 dev_err(tc->dev, "Link training phase 2 failed: %s\n", 959 training_pattern2_errors[ret]); 960 ret = -ENODEV; 961 goto err; 962 } 963 964 /* 965 * Toshiba's documentation suggests to first clear DPCD 0x102, then 966 * clear the training pattern bit in DP0_SRCCTRL. Testing shows 967 * that the link sometimes drops if those steps are done in that order, 968 * but if the steps are done in reverse order, the link stays up. 969 * 970 * So we do the steps differently than documented here. 971 */ 972 973 /* Clear Training Pattern, set AutoCorrect Mode = 1 */ 974 tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_AUTOCORRECT); 975 976 /* Clear DPCD 0x102 */ 977 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */ 978 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00; 979 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]); 980 if (ret < 0) 981 goto err_dpcd_write; 982 983 /* Check link status */ 984 ret = drm_dp_dpcd_read_link_status(aux, tmp); 985 if (ret < 0) 986 goto err_dpcd_read; 987 988 ret = 0; 989 990 value = tmp[0] & DP_CHANNEL_EQ_BITS; 991 992 if (value != DP_CHANNEL_EQ_BITS) { 993 dev_err(tc->dev, "Lane 0 failed: %x\n", value); 994 ret = -ENODEV; 995 } 996 997 if (tc->link.base.num_lanes == 2) { 998 value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS; 999 1000 if (value != DP_CHANNEL_EQ_BITS) { 1001 dev_err(tc->dev, "Lane 1 failed: %x\n", value); 1002 ret = -ENODEV; 1003 } 1004 1005 if (!(tmp[2] & DP_INTERLANE_ALIGN_DONE)) { 1006 dev_err(tc->dev, "Interlane align failed\n"); 1007 ret = -ENODEV; 1008 } 1009 } 1010 1011 if (ret) { 1012 dev_err(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[0]); 1013 dev_err(dev, "0x0203 LANE2_3_STATUS 0x%02x\n", tmp[1]); 1014 dev_err(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", tmp[2]); 1015 dev_err(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[3]); 1016 dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n", tmp[4]); 1017 dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3: 0x%02x\n", tmp[5]); 1018 goto err; 1019 } 1020 1021 return 0; 1022 err_dpcd_read: 1023 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret); 1024 return ret; 1025 err_dpcd_write: 1026 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret); 1027 err: 1028 return ret; 1029 } 1030 1031 static int tc_main_link_disable(struct tc_data *tc) 1032 { 1033 int ret; 1034 1035 dev_dbg(tc->dev, "link disable\n"); 1036 1037 tc_write(DP0_SRCCTRL, 0); 1038 tc_write(DP0CTL, 0); 1039 1040 return 0; 1041 err: 1042 return ret; 1043 } 1044 1045 static int tc_stream_enable(struct tc_data *tc) 1046 { 1047 int ret; 1048 u32 value; 1049 1050 dev_dbg(tc->dev, "enable video stream\n"); 1051 1052 /* PXL PLL setup */ 1053 if (tc_test_pattern) { 1054 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), 1055 1000 * tc->mode.clock); 1056 if (ret) 1057 goto err; 1058 } 1059 1060 ret = tc_set_video_mode(tc, &tc->mode); 1061 if (ret) 1062 return ret; 1063 1064 /* Set M/N */ 1065 ret = tc_stream_clock_calc(tc); 1066 if (ret) 1067 return ret; 1068 1069 value = VID_MN_GEN | DP_EN; 1070 if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 1071 value |= EF_EN; 1072 tc_write(DP0CTL, value); 1073 /* 1074 * VID_EN assertion should be delayed by at least N * LSCLK 1075 * cycles from the time VID_MN_GEN is enabled in order to 1076 * generate stable values for VID_M. LSCLK is 270 MHz or 1077 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(), 1078 * so a delay of at least 203 us should suffice. 1079 */ 1080 usleep_range(500, 1000); 1081 value |= VID_EN; 1082 tc_write(DP0CTL, value); 1083 /* Set input interface */ 1084 value = DP0_AUDSRC_NO_INPUT; 1085 if (tc_test_pattern) 1086 value |= DP0_VIDSRC_COLOR_BAR; 1087 else 1088 value |= DP0_VIDSRC_DPI_RX; 1089 tc_write(SYSCTRL, value); 1090 1091 return 0; 1092 err: 1093 return ret; 1094 } 1095 1096 static int tc_stream_disable(struct tc_data *tc) 1097 { 1098 int ret; 1099 u32 val; 1100 1101 dev_dbg(tc->dev, "disable video stream\n"); 1102 1103 tc_read(DP0CTL, &val); 1104 val &= ~VID_EN; 1105 tc_write(DP0CTL, val); 1106 1107 tc_pxl_pll_dis(tc); 1108 1109 return 0; 1110 err: 1111 return ret; 1112 } 1113 1114 static void tc_bridge_pre_enable(struct drm_bridge *bridge) 1115 { 1116 struct tc_data *tc = bridge_to_tc(bridge); 1117 1118 drm_panel_prepare(tc->panel); 1119 } 1120 1121 static void tc_bridge_enable(struct drm_bridge *bridge) 1122 { 1123 struct tc_data *tc = bridge_to_tc(bridge); 1124 int ret; 1125 1126 ret = tc_get_display_props(tc); 1127 if (ret < 0) { 1128 dev_err(tc->dev, "failed to read display props: %d\n", ret); 1129 return; 1130 } 1131 1132 ret = tc_main_link_enable(tc); 1133 if (ret < 0) { 1134 dev_err(tc->dev, "main link enable error: %d\n", ret); 1135 return; 1136 } 1137 1138 ret = tc_stream_enable(tc); 1139 if (ret < 0) { 1140 dev_err(tc->dev, "main link stream start error: %d\n", ret); 1141 tc_main_link_disable(tc); 1142 return; 1143 } 1144 1145 drm_panel_enable(tc->panel); 1146 } 1147 1148 static void tc_bridge_disable(struct drm_bridge *bridge) 1149 { 1150 struct tc_data *tc = bridge_to_tc(bridge); 1151 int ret; 1152 1153 drm_panel_disable(tc->panel); 1154 1155 ret = tc_stream_disable(tc); 1156 if (ret < 0) 1157 dev_err(tc->dev, "main link stream stop error: %d\n", ret); 1158 1159 ret = tc_main_link_disable(tc); 1160 if (ret < 0) 1161 dev_err(tc->dev, "main link disable error: %d\n", ret); 1162 } 1163 1164 static void tc_bridge_post_disable(struct drm_bridge *bridge) 1165 { 1166 struct tc_data *tc = bridge_to_tc(bridge); 1167 1168 drm_panel_unprepare(tc->panel); 1169 } 1170 1171 static bool tc_bridge_mode_fixup(struct drm_bridge *bridge, 1172 const struct drm_display_mode *mode, 1173 struct drm_display_mode *adj) 1174 { 1175 /* Fixup sync polarities, both hsync and vsync are active low */ 1176 adj->flags = mode->flags; 1177 adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); 1178 adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 1179 1180 return true; 1181 } 1182 1183 static enum drm_mode_status tc_mode_valid(struct drm_bridge *bridge, 1184 const struct drm_display_mode *mode) 1185 { 1186 struct tc_data *tc = bridge_to_tc(bridge); 1187 u32 req, avail; 1188 u32 bits_per_pixel = 24; 1189 1190 /* DPI interface clock limitation: upto 154 MHz */ 1191 if (mode->clock > 154000) 1192 return MODE_CLOCK_HIGH; 1193 1194 req = mode->clock * bits_per_pixel / 8; 1195 avail = tc->link.base.num_lanes * tc->link.base.rate; 1196 1197 if (req > avail) 1198 return MODE_BAD; 1199 1200 return MODE_OK; 1201 } 1202 1203 static void tc_bridge_mode_set(struct drm_bridge *bridge, 1204 const struct drm_display_mode *mode, 1205 const struct drm_display_mode *adj) 1206 { 1207 struct tc_data *tc = bridge_to_tc(bridge); 1208 1209 tc->mode = *mode; 1210 } 1211 1212 static int tc_connector_get_modes(struct drm_connector *connector) 1213 { 1214 struct tc_data *tc = connector_to_tc(connector); 1215 struct edid *edid; 1216 unsigned int count; 1217 int ret; 1218 1219 ret = tc_get_display_props(tc); 1220 if (ret < 0) { 1221 dev_err(tc->dev, "failed to read display props: %d\n", ret); 1222 return 0; 1223 } 1224 1225 if (tc->panel && tc->panel->funcs && tc->panel->funcs->get_modes) { 1226 count = tc->panel->funcs->get_modes(tc->panel); 1227 if (count > 0) 1228 return count; 1229 } 1230 1231 edid = drm_get_edid(connector, &tc->aux.ddc); 1232 1233 kfree(tc->edid); 1234 tc->edid = edid; 1235 if (!edid) 1236 return 0; 1237 1238 drm_connector_update_edid_property(connector, edid); 1239 count = drm_add_edid_modes(connector, edid); 1240 1241 return count; 1242 } 1243 1244 static const struct drm_connector_helper_funcs tc_connector_helper_funcs = { 1245 .get_modes = tc_connector_get_modes, 1246 }; 1247 1248 static enum drm_connector_status tc_connector_detect(struct drm_connector *connector, 1249 bool force) 1250 { 1251 struct tc_data *tc = connector_to_tc(connector); 1252 bool conn; 1253 u32 val; 1254 int ret; 1255 1256 if (tc->hpd_pin < 0) { 1257 if (tc->panel) 1258 return connector_status_connected; 1259 else 1260 return connector_status_unknown; 1261 } 1262 1263 tc_read(GPIOI, &val); 1264 1265 conn = val & BIT(tc->hpd_pin); 1266 1267 if (conn) 1268 return connector_status_connected; 1269 else 1270 return connector_status_disconnected; 1271 1272 err: 1273 return connector_status_unknown; 1274 } 1275 1276 static const struct drm_connector_funcs tc_connector_funcs = { 1277 .detect = tc_connector_detect, 1278 .fill_modes = drm_helper_probe_single_connector_modes, 1279 .destroy = drm_connector_cleanup, 1280 .reset = drm_atomic_helper_connector_reset, 1281 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1282 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1283 }; 1284 1285 static int tc_bridge_attach(struct drm_bridge *bridge) 1286 { 1287 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1288 struct tc_data *tc = bridge_to_tc(bridge); 1289 struct drm_device *drm = bridge->dev; 1290 int ret; 1291 1292 /* Create DP/eDP connector */ 1293 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs); 1294 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, 1295 tc->panel ? DRM_MODE_CONNECTOR_eDP : 1296 DRM_MODE_CONNECTOR_DisplayPort); 1297 if (ret) 1298 return ret; 1299 1300 /* Don't poll if don't have HPD connected */ 1301 if (tc->hpd_pin >= 0) { 1302 if (tc->have_irq) 1303 tc->connector.polled = DRM_CONNECTOR_POLL_HPD; 1304 else 1305 tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT | 1306 DRM_CONNECTOR_POLL_DISCONNECT; 1307 } 1308 1309 if (tc->panel) 1310 drm_panel_attach(tc->panel, &tc->connector); 1311 1312 drm_display_info_set_bus_formats(&tc->connector.display_info, 1313 &bus_format, 1); 1314 tc->connector.display_info.bus_flags = 1315 DRM_BUS_FLAG_DE_HIGH | 1316 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE | 1317 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE; 1318 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder); 1319 1320 return 0; 1321 } 1322 1323 static const struct drm_bridge_funcs tc_bridge_funcs = { 1324 .attach = tc_bridge_attach, 1325 .mode_valid = tc_mode_valid, 1326 .mode_set = tc_bridge_mode_set, 1327 .pre_enable = tc_bridge_pre_enable, 1328 .enable = tc_bridge_enable, 1329 .disable = tc_bridge_disable, 1330 .post_disable = tc_bridge_post_disable, 1331 .mode_fixup = tc_bridge_mode_fixup, 1332 }; 1333 1334 static bool tc_readable_reg(struct device *dev, unsigned int reg) 1335 { 1336 return reg != SYSCTRL; 1337 } 1338 1339 static const struct regmap_range tc_volatile_ranges[] = { 1340 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS), 1341 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ), 1342 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL), 1343 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL), 1344 regmap_reg_range(VFUEN0, VFUEN0), 1345 regmap_reg_range(INTSTS_G, INTSTS_G), 1346 regmap_reg_range(GPIOI, GPIOI), 1347 }; 1348 1349 static const struct regmap_access_table tc_volatile_table = { 1350 .yes_ranges = tc_volatile_ranges, 1351 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges), 1352 }; 1353 1354 static bool tc_writeable_reg(struct device *dev, unsigned int reg) 1355 { 1356 return (reg != TC_IDREG) && 1357 (reg != DP0_LTSTAT) && 1358 (reg != DP0_SNKLTCHGREQ); 1359 } 1360 1361 static const struct regmap_config tc_regmap_config = { 1362 .name = "tc358767", 1363 .reg_bits = 16, 1364 .val_bits = 32, 1365 .reg_stride = 4, 1366 .max_register = PLL_DBG, 1367 .cache_type = REGCACHE_RBTREE, 1368 .readable_reg = tc_readable_reg, 1369 .volatile_table = &tc_volatile_table, 1370 .writeable_reg = tc_writeable_reg, 1371 .reg_format_endian = REGMAP_ENDIAN_BIG, 1372 .val_format_endian = REGMAP_ENDIAN_LITTLE, 1373 }; 1374 1375 static irqreturn_t tc_irq_handler(int irq, void *arg) 1376 { 1377 struct tc_data *tc = arg; 1378 u32 val; 1379 int r; 1380 1381 r = regmap_read(tc->regmap, INTSTS_G, &val); 1382 if (r) 1383 return IRQ_NONE; 1384 1385 if (!val) 1386 return IRQ_NONE; 1387 1388 if (val & INT_SYSERR) { 1389 u32 stat = 0; 1390 1391 regmap_read(tc->regmap, SYSSTAT, &stat); 1392 1393 dev_err(tc->dev, "syserr %x\n", stat); 1394 } 1395 1396 if (tc->hpd_pin >= 0 && tc->bridge.dev) { 1397 /* 1398 * H is triggered when the GPIO goes high. 1399 * 1400 * LC is triggered when the GPIO goes low and stays low for 1401 * the duration of LCNT 1402 */ 1403 bool h = val & INT_GPIO_H(tc->hpd_pin); 1404 bool lc = val & INT_GPIO_LC(tc->hpd_pin); 1405 1406 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin, 1407 h ? "H" : "", lc ? "LC" : ""); 1408 1409 if (h || lc) 1410 drm_kms_helper_hotplug_event(tc->bridge.dev); 1411 } 1412 1413 regmap_write(tc->regmap, INTSTS_G, val); 1414 1415 return IRQ_HANDLED; 1416 } 1417 1418 static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id) 1419 { 1420 struct device *dev = &client->dev; 1421 struct tc_data *tc; 1422 int ret; 1423 1424 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL); 1425 if (!tc) 1426 return -ENOMEM; 1427 1428 tc->dev = dev; 1429 1430 /* port@2 is the output port */ 1431 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL); 1432 if (ret && ret != -ENODEV) 1433 return ret; 1434 1435 /* Shut down GPIO is optional */ 1436 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH); 1437 if (IS_ERR(tc->sd_gpio)) 1438 return PTR_ERR(tc->sd_gpio); 1439 1440 if (tc->sd_gpio) { 1441 gpiod_set_value_cansleep(tc->sd_gpio, 0); 1442 usleep_range(5000, 10000); 1443 } 1444 1445 /* Reset GPIO is optional */ 1446 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1447 if (IS_ERR(tc->reset_gpio)) 1448 return PTR_ERR(tc->reset_gpio); 1449 1450 if (tc->reset_gpio) { 1451 gpiod_set_value_cansleep(tc->reset_gpio, 1); 1452 usleep_range(5000, 10000); 1453 } 1454 1455 tc->refclk = devm_clk_get(dev, "ref"); 1456 if (IS_ERR(tc->refclk)) { 1457 ret = PTR_ERR(tc->refclk); 1458 dev_err(dev, "Failed to get refclk: %d\n", ret); 1459 return ret; 1460 } 1461 1462 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config); 1463 if (IS_ERR(tc->regmap)) { 1464 ret = PTR_ERR(tc->regmap); 1465 dev_err(dev, "Failed to initialize regmap: %d\n", ret); 1466 return ret; 1467 } 1468 1469 ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin", 1470 &tc->hpd_pin); 1471 if (ret) { 1472 tc->hpd_pin = -ENODEV; 1473 } else { 1474 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) { 1475 dev_err(dev, "failed to parse HPD number\n"); 1476 return ret; 1477 } 1478 } 1479 1480 if (client->irq > 0) { 1481 /* enable SysErr */ 1482 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR); 1483 1484 ret = devm_request_threaded_irq(dev, client->irq, 1485 NULL, tc_irq_handler, 1486 IRQF_ONESHOT, 1487 "tc358767-irq", tc); 1488 if (ret) { 1489 dev_err(dev, "failed to register dp interrupt\n"); 1490 return ret; 1491 } 1492 1493 tc->have_irq = true; 1494 } 1495 1496 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev); 1497 if (ret) { 1498 dev_err(tc->dev, "can not read device ID: %d\n", ret); 1499 return ret; 1500 } 1501 1502 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) { 1503 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev); 1504 return -EINVAL; 1505 } 1506 1507 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */ 1508 1509 if (tc->hpd_pin >= 0) { 1510 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT; 1511 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin); 1512 1513 /* Set LCNT to 2ms */ 1514 regmap_write(tc->regmap, lcnt_reg, 1515 clk_get_rate(tc->refclk) * 2 / 1000); 1516 /* We need the "alternate" mode for HPD */ 1517 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin)); 1518 1519 if (tc->have_irq) { 1520 /* enable H & LC */ 1521 regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc); 1522 } 1523 } 1524 1525 ret = tc_aux_link_setup(tc); 1526 if (ret) 1527 return ret; 1528 1529 /* Register DP AUX channel */ 1530 tc->aux.name = "TC358767 AUX i2c adapter"; 1531 tc->aux.dev = tc->dev; 1532 tc->aux.transfer = tc_aux_transfer; 1533 ret = drm_dp_aux_register(&tc->aux); 1534 if (ret) 1535 return ret; 1536 1537 tc->bridge.funcs = &tc_bridge_funcs; 1538 tc->bridge.of_node = dev->of_node; 1539 drm_bridge_add(&tc->bridge); 1540 1541 i2c_set_clientdata(client, tc); 1542 1543 return 0; 1544 } 1545 1546 static int tc_remove(struct i2c_client *client) 1547 { 1548 struct tc_data *tc = i2c_get_clientdata(client); 1549 1550 drm_bridge_remove(&tc->bridge); 1551 drm_dp_aux_unregister(&tc->aux); 1552 1553 return 0; 1554 } 1555 1556 static const struct i2c_device_id tc358767_i2c_ids[] = { 1557 { "tc358767", 0 }, 1558 { } 1559 }; 1560 MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids); 1561 1562 static const struct of_device_id tc358767_of_ids[] = { 1563 { .compatible = "toshiba,tc358767", }, 1564 { } 1565 }; 1566 MODULE_DEVICE_TABLE(of, tc358767_of_ids); 1567 1568 static struct i2c_driver tc358767_driver = { 1569 .driver = { 1570 .name = "tc358767", 1571 .of_match_table = tc358767_of_ids, 1572 }, 1573 .id_table = tc358767_i2c_ids, 1574 .probe = tc_probe, 1575 .remove = tc_remove, 1576 }; 1577 module_i2c_driver(tc358767_driver); 1578 1579 MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>"); 1580 MODULE_DESCRIPTION("tc358767 eDP encoder driver"); 1581 MODULE_LICENSE("GPL"); 1582