1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * tc358767 eDP bridge driver 4 * 5 * Copyright (C) 2016 CogentEmbedded Inc 6 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com> 7 * 8 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de> 9 * 10 * Copyright (C) 2016 Zodiac Inflight Innovations 11 * 12 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c 13 * 14 * Copyright (C) 2012 Texas Instruments 15 * Author: Rob Clark <robdclark@gmail.com> 16 */ 17 18 #include <linux/bitfield.h> 19 #include <linux/clk.h> 20 #include <linux/device.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/i2c.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/regmap.h> 26 #include <linux/slab.h> 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_bridge.h> 30 #include <drm/drm_dp_helper.h> 31 #include <drm/drm_edid.h> 32 #include <drm/drm_of.h> 33 #include <drm/drm_panel.h> 34 #include <drm/drm_probe_helper.h> 35 36 /* Registers */ 37 38 /* Display Parallel Interface */ 39 #define DPIPXLFMT 0x0440 40 #define VS_POL_ACTIVE_LOW (1 << 10) 41 #define HS_POL_ACTIVE_LOW (1 << 9) 42 #define DE_POL_ACTIVE_HIGH (0 << 8) 43 #define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */ 44 #define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */ 45 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */ 46 #define DPI_BPP_RGB888 (0 << 0) 47 #define DPI_BPP_RGB666 (1 << 0) 48 #define DPI_BPP_RGB565 (2 << 0) 49 50 /* Video Path */ 51 #define VPCTRL0 0x0450 52 #define VSDELAY GENMASK(31, 20) 53 #define OPXLFMT_RGB666 (0 << 8) 54 #define OPXLFMT_RGB888 (1 << 8) 55 #define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */ 56 #define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */ 57 #define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */ 58 #define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */ 59 #define HTIM01 0x0454 60 #define HPW GENMASK(8, 0) 61 #define HBPR GENMASK(24, 16) 62 #define HTIM02 0x0458 63 #define HDISPR GENMASK(10, 0) 64 #define HFPR GENMASK(24, 16) 65 #define VTIM01 0x045c 66 #define VSPR GENMASK(7, 0) 67 #define VBPR GENMASK(23, 16) 68 #define VTIM02 0x0460 69 #define VFPR GENMASK(23, 16) 70 #define VDISPR GENMASK(10, 0) 71 #define VFUEN0 0x0464 72 #define VFUEN BIT(0) /* Video Frame Timing Upload */ 73 74 /* System */ 75 #define TC_IDREG 0x0500 76 #define SYSSTAT 0x0508 77 #define SYSCTRL 0x0510 78 #define DP0_AUDSRC_NO_INPUT (0 << 3) 79 #define DP0_AUDSRC_I2S_RX (1 << 3) 80 #define DP0_VIDSRC_NO_INPUT (0 << 0) 81 #define DP0_VIDSRC_DSI_RX (1 << 0) 82 #define DP0_VIDSRC_DPI_RX (2 << 0) 83 #define DP0_VIDSRC_COLOR_BAR (3 << 0) 84 #define SYSRSTENB 0x050c 85 #define ENBI2C (1 << 0) 86 #define ENBLCD0 (1 << 2) 87 #define ENBBM (1 << 3) 88 #define ENBDSIRX (1 << 4) 89 #define ENBREG (1 << 5) 90 #define ENBHDCP (1 << 8) 91 #define GPIOM 0x0540 92 #define GPIOC 0x0544 93 #define GPIOO 0x0548 94 #define GPIOI 0x054c 95 #define INTCTL_G 0x0560 96 #define INTSTS_G 0x0564 97 98 #define INT_SYSERR BIT(16) 99 #define INT_GPIO_H(x) (1 << (x == 0 ? 2 : 10)) 100 #define INT_GPIO_LC(x) (1 << (x == 0 ? 3 : 11)) 101 102 #define INT_GP0_LCNT 0x0584 103 #define INT_GP1_LCNT 0x0588 104 105 /* Control */ 106 #define DP0CTL 0x0600 107 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */ 108 #define EF_EN BIT(5) /* Enable Enhanced Framing */ 109 #define VID_EN BIT(1) /* Video transmission enable */ 110 #define DP_EN BIT(0) /* Enable DPTX function */ 111 112 /* Clocks */ 113 #define DP0_VIDMNGEN0 0x0610 114 #define DP0_VIDMNGEN1 0x0614 115 #define DP0_VMNGENSTATUS 0x0618 116 117 /* Main Channel */ 118 #define DP0_SECSAMPLE 0x0640 119 #define DP0_VIDSYNCDELAY 0x0644 120 #define VID_SYNC_DLY GENMASK(15, 0) 121 #define THRESH_DLY GENMASK(31, 16) 122 123 #define DP0_TOTALVAL 0x0648 124 #define H_TOTAL GENMASK(15, 0) 125 #define V_TOTAL GENMASK(31, 16) 126 #define DP0_STARTVAL 0x064c 127 #define H_START GENMASK(15, 0) 128 #define V_START GENMASK(31, 16) 129 #define DP0_ACTIVEVAL 0x0650 130 #define H_ACT GENMASK(15, 0) 131 #define V_ACT GENMASK(31, 16) 132 133 #define DP0_SYNCVAL 0x0654 134 #define VS_WIDTH GENMASK(30, 16) 135 #define HS_WIDTH GENMASK(14, 0) 136 #define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15) 137 #define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31) 138 #define DP0_MISC 0x0658 139 #define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */ 140 #define MAX_TU_SYMBOL GENMASK(28, 23) 141 #define TU_SIZE GENMASK(21, 16) 142 #define BPC_6 (0 << 5) 143 #define BPC_8 (1 << 5) 144 145 /* AUX channel */ 146 #define DP0_AUXCFG0 0x0660 147 #define DP0_AUXCFG0_BSIZE GENMASK(11, 8) 148 #define DP0_AUXCFG0_ADDR_ONLY BIT(4) 149 #define DP0_AUXCFG1 0x0664 150 #define AUX_RX_FILTER_EN BIT(16) 151 152 #define DP0_AUXADDR 0x0668 153 #define DP0_AUXWDATA(i) (0x066c + (i) * 4) 154 #define DP0_AUXRDATA(i) (0x067c + (i) * 4) 155 #define DP0_AUXSTATUS 0x068c 156 #define AUX_BYTES GENMASK(15, 8) 157 #define AUX_STATUS GENMASK(7, 4) 158 #define AUX_TIMEOUT BIT(1) 159 #define AUX_BUSY BIT(0) 160 #define DP0_AUXI2CADR 0x0698 161 162 /* Link Training */ 163 #define DP0_SRCCTRL 0x06a0 164 #define DP0_SRCCTRL_SCRMBLDIS BIT(13) 165 #define DP0_SRCCTRL_EN810B BIT(12) 166 #define DP0_SRCCTRL_NOTP (0 << 8) 167 #define DP0_SRCCTRL_TP1 (1 << 8) 168 #define DP0_SRCCTRL_TP2 (2 << 8) 169 #define DP0_SRCCTRL_LANESKEW BIT(7) 170 #define DP0_SRCCTRL_SSCG BIT(3) 171 #define DP0_SRCCTRL_LANES_1 (0 << 2) 172 #define DP0_SRCCTRL_LANES_2 (1 << 2) 173 #define DP0_SRCCTRL_BW27 (1 << 1) 174 #define DP0_SRCCTRL_BW162 (0 << 1) 175 #define DP0_SRCCTRL_AUTOCORRECT BIT(0) 176 #define DP0_LTSTAT 0x06d0 177 #define LT_LOOPDONE BIT(13) 178 #define LT_STATUS_MASK (0x1f << 8) 179 #define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4) 180 #define LT_INTERLANE_ALIGN_DONE BIT(3) 181 #define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS) 182 #define DP0_SNKLTCHGREQ 0x06d4 183 #define DP0_LTLOOPCTRL 0x06d8 184 #define DP0_SNKLTCTRL 0x06e4 185 186 #define DP1_SRCCTRL 0x07a0 187 188 /* PHY */ 189 #define DP_PHY_CTRL 0x0800 190 #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */ 191 #define BGREN BIT(25) /* AUX PHY BGR Enable */ 192 #define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */ 193 #define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */ 194 #define PHY_RDY BIT(16) /* PHY Main Channels Ready */ 195 #define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */ 196 #define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */ 197 #define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */ 198 #define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */ 199 200 /* PLL */ 201 #define DP0_PLLCTRL 0x0900 202 #define DP1_PLLCTRL 0x0904 /* not defined in DS */ 203 #define PXL_PLLCTRL 0x0908 204 #define PLLUPDATE BIT(2) 205 #define PLLBYP BIT(1) 206 #define PLLEN BIT(0) 207 #define PXL_PLLPARAM 0x0914 208 #define IN_SEL_REFCLK (0 << 14) 209 #define SYS_PLLPARAM 0x0918 210 #define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */ 211 #define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */ 212 #define REF_FREQ_26M (2 << 8) /* 26 MHz */ 213 #define REF_FREQ_13M (3 << 8) /* 13 MHz */ 214 #define SYSCLK_SEL_LSCLK (0 << 4) 215 #define LSCLK_DIV_1 (0 << 0) 216 #define LSCLK_DIV_2 (1 << 0) 217 218 /* Test & Debug */ 219 #define TSTCTL 0x0a00 220 #define COLOR_R GENMASK(31, 24) 221 #define COLOR_G GENMASK(23, 16) 222 #define COLOR_B GENMASK(15, 8) 223 #define ENI2CFILTER BIT(4) 224 #define COLOR_BAR_MODE GENMASK(1, 0) 225 #define COLOR_BAR_MODE_BARS 2 226 #define PLL_DBG 0x0a04 227 228 static bool tc_test_pattern; 229 module_param_named(test, tc_test_pattern, bool, 0644); 230 231 struct tc_edp_link { 232 struct drm_dp_link base; 233 u8 assr; 234 bool scrambler_dis; 235 bool spread; 236 }; 237 238 struct tc_data { 239 struct device *dev; 240 struct regmap *regmap; 241 struct drm_dp_aux aux; 242 243 struct drm_bridge bridge; 244 struct drm_connector connector; 245 struct drm_panel *panel; 246 247 /* link settings */ 248 struct tc_edp_link link; 249 250 /* display edid */ 251 struct edid *edid; 252 /* current mode */ 253 struct drm_display_mode mode; 254 255 u32 rev; 256 u8 assr; 257 258 struct gpio_desc *sd_gpio; 259 struct gpio_desc *reset_gpio; 260 struct clk *refclk; 261 262 /* do we have IRQ */ 263 bool have_irq; 264 265 /* HPD pin number (0 or 1) or -ENODEV */ 266 int hpd_pin; 267 }; 268 269 static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a) 270 { 271 return container_of(a, struct tc_data, aux); 272 } 273 274 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b) 275 { 276 return container_of(b, struct tc_data, bridge); 277 } 278 279 static inline struct tc_data *connector_to_tc(struct drm_connector *c) 280 { 281 return container_of(c, struct tc_data, connector); 282 } 283 284 static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr, 285 unsigned int cond_mask, 286 unsigned int cond_value, 287 unsigned long sleep_us, u64 timeout_us) 288 { 289 unsigned int val; 290 291 return regmap_read_poll_timeout(tc->regmap, addr, val, 292 (val & cond_mask) == cond_value, 293 sleep_us, timeout_us); 294 } 295 296 static int tc_aux_wait_busy(struct tc_data *tc) 297 { 298 return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 1000, 100000); 299 } 300 301 static int tc_aux_write_data(struct tc_data *tc, const void *data, 302 size_t size) 303 { 304 u32 auxwdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)] = { 0 }; 305 int ret, count = ALIGN(size, sizeof(u32)); 306 307 memcpy(auxwdata, data, size); 308 309 ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count); 310 if (ret) 311 return ret; 312 313 return size; 314 } 315 316 static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size) 317 { 318 u32 auxrdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)]; 319 int ret, count = ALIGN(size, sizeof(u32)); 320 321 ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count); 322 if (ret) 323 return ret; 324 325 memcpy(data, auxrdata, size); 326 327 return size; 328 } 329 330 static u32 tc_auxcfg0(struct drm_dp_aux_msg *msg, size_t size) 331 { 332 u32 auxcfg0 = msg->request; 333 334 if (size) 335 auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1); 336 else 337 auxcfg0 |= DP0_AUXCFG0_ADDR_ONLY; 338 339 return auxcfg0; 340 } 341 342 static ssize_t tc_aux_transfer(struct drm_dp_aux *aux, 343 struct drm_dp_aux_msg *msg) 344 { 345 struct tc_data *tc = aux_to_tc(aux); 346 size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size); 347 u8 request = msg->request & ~DP_AUX_I2C_MOT; 348 u32 auxstatus; 349 int ret; 350 351 ret = tc_aux_wait_busy(tc); 352 if (ret) 353 return ret; 354 355 switch (request) { 356 case DP_AUX_NATIVE_READ: 357 case DP_AUX_I2C_READ: 358 break; 359 case DP_AUX_NATIVE_WRITE: 360 case DP_AUX_I2C_WRITE: 361 if (size) { 362 ret = tc_aux_write_data(tc, msg->buffer, size); 363 if (ret < 0) 364 return ret; 365 } 366 break; 367 default: 368 return -EINVAL; 369 } 370 371 /* Store address */ 372 ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address); 373 if (ret) 374 return ret; 375 /* Start transfer */ 376 ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size)); 377 if (ret) 378 return ret; 379 380 ret = tc_aux_wait_busy(tc); 381 if (ret) 382 return ret; 383 384 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus); 385 if (ret) 386 return ret; 387 388 if (auxstatus & AUX_TIMEOUT) 389 return -ETIMEDOUT; 390 /* 391 * For some reason address-only DP_AUX_I2C_WRITE (MOT), still 392 * reports 1 byte transferred in its status. To deal we that 393 * we ignore aux_bytes field if we know that this was an 394 * address-only transfer 395 */ 396 if (size) 397 size = FIELD_GET(AUX_BYTES, auxstatus); 398 msg->reply = FIELD_GET(AUX_STATUS, auxstatus); 399 400 switch (request) { 401 case DP_AUX_NATIVE_READ: 402 case DP_AUX_I2C_READ: 403 if (size) 404 return tc_aux_read_data(tc, msg->buffer, size); 405 break; 406 } 407 408 return size; 409 } 410 411 static const char * const training_pattern1_errors[] = { 412 "No errors", 413 "Aux write error", 414 "Aux read error", 415 "Max voltage reached error", 416 "Loop counter expired error", 417 "res", "res", "res" 418 }; 419 420 static const char * const training_pattern2_errors[] = { 421 "No errors", 422 "Aux write error", 423 "Aux read error", 424 "Clock recovery failed error", 425 "Loop counter expired error", 426 "res", "res", "res" 427 }; 428 429 static u32 tc_srcctrl(struct tc_data *tc) 430 { 431 /* 432 * No training pattern, skew lane 1 data by two LSCLK cycles with 433 * respect to lane 0 data, AutoCorrect Mode = 0 434 */ 435 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B; 436 437 if (tc->link.scrambler_dis) 438 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */ 439 if (tc->link.spread) 440 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */ 441 if (tc->link.base.num_lanes == 2) 442 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */ 443 if (tc->link.base.rate != 162000) 444 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */ 445 return reg; 446 } 447 448 static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl) 449 { 450 int ret; 451 452 ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN); 453 if (ret) 454 return ret; 455 456 /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */ 457 usleep_range(3000, 6000); 458 459 return 0; 460 } 461 462 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) 463 { 464 int ret; 465 int i_pre, best_pre = 1; 466 int i_post, best_post = 1; 467 int div, best_div = 1; 468 int mul, best_mul = 1; 469 int delta, best_delta; 470 int ext_div[] = {1, 2, 3, 5, 7}; 471 int best_pixelclock = 0; 472 int vco_hi = 0; 473 u32 pxl_pllparam; 474 475 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock, 476 refclk); 477 best_delta = pixelclock; 478 /* Loop over all possible ext_divs, skipping invalid configurations */ 479 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) { 480 /* 481 * refclk / ext_pre_div should be in the 1 to 200 MHz range. 482 * We don't allow any refclk > 200 MHz, only check lower bounds. 483 */ 484 if (refclk / ext_div[i_pre] < 1000000) 485 continue; 486 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) { 487 for (div = 1; div <= 16; div++) { 488 u32 clk; 489 u64 tmp; 490 491 tmp = pixelclock * ext_div[i_pre] * 492 ext_div[i_post] * div; 493 do_div(tmp, refclk); 494 mul = tmp; 495 496 /* Check limits */ 497 if ((mul < 1) || (mul > 128)) 498 continue; 499 500 clk = (refclk / ext_div[i_pre] / div) * mul; 501 /* 502 * refclk * mul / (ext_pre_div * pre_div) 503 * should be in the 150 to 650 MHz range 504 */ 505 if ((clk > 650000000) || (clk < 150000000)) 506 continue; 507 508 clk = clk / ext_div[i_post]; 509 delta = clk - pixelclock; 510 511 if (abs(delta) < abs(best_delta)) { 512 best_pre = i_pre; 513 best_post = i_post; 514 best_div = div; 515 best_mul = mul; 516 best_delta = delta; 517 best_pixelclock = clk; 518 } 519 } 520 } 521 } 522 if (best_pixelclock == 0) { 523 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n", 524 pixelclock); 525 return -EINVAL; 526 } 527 528 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock, 529 best_delta); 530 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk, 531 ext_div[best_pre], best_div, best_mul, ext_div[best_post]); 532 533 /* if VCO >= 300 MHz */ 534 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000) 535 vco_hi = 1; 536 /* see DS */ 537 if (best_div == 16) 538 best_div = 0; 539 if (best_mul == 128) 540 best_mul = 0; 541 542 /* Power up PLL and switch to bypass */ 543 ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN); 544 if (ret) 545 return ret; 546 547 pxl_pllparam = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */ 548 pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */ 549 pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */ 550 pxl_pllparam |= IN_SEL_REFCLK; /* Use RefClk as PLL input */ 551 pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */ 552 pxl_pllparam |= best_mul; /* Multiplier for PLL */ 553 554 ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam); 555 if (ret) 556 return ret; 557 558 /* Force PLL parameter update and disable bypass */ 559 return tc_pllupdate(tc, PXL_PLLCTRL); 560 } 561 562 static int tc_pxl_pll_dis(struct tc_data *tc) 563 { 564 /* Enable PLL bypass, power down PLL */ 565 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP); 566 } 567 568 static int tc_stream_clock_calc(struct tc_data *tc) 569 { 570 /* 571 * If the Stream clock and Link Symbol clock are 572 * asynchronous with each other, the value of M changes over 573 * time. This way of generating link clock and stream 574 * clock is called Asynchronous Clock mode. The value M 575 * must change while the value N stays constant. The 576 * value of N in this Asynchronous Clock mode must be set 577 * to 2^15 or 32,768. 578 * 579 * LSCLK = 1/10 of high speed link clock 580 * 581 * f_STRMCLK = M/N * f_LSCLK 582 * M/N = f_STRMCLK / f_LSCLK 583 * 584 */ 585 return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768); 586 } 587 588 static int tc_set_syspllparam(struct tc_data *tc) 589 { 590 unsigned long rate; 591 u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2; 592 593 rate = clk_get_rate(tc->refclk); 594 switch (rate) { 595 case 38400000: 596 pllparam |= REF_FREQ_38M4; 597 break; 598 case 26000000: 599 pllparam |= REF_FREQ_26M; 600 break; 601 case 19200000: 602 pllparam |= REF_FREQ_19M2; 603 break; 604 case 13000000: 605 pllparam |= REF_FREQ_13M; 606 break; 607 default: 608 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate); 609 return -EINVAL; 610 } 611 612 return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam); 613 } 614 615 static int tc_aux_link_setup(struct tc_data *tc) 616 { 617 int ret; 618 u32 dp0_auxcfg1; 619 620 /* Setup DP-PHY / PLL */ 621 ret = tc_set_syspllparam(tc); 622 if (ret) 623 goto err; 624 625 ret = regmap_write(tc->regmap, DP_PHY_CTRL, 626 BGREN | PWR_SW_EN | PHY_A0_EN); 627 if (ret) 628 goto err; 629 /* 630 * Initially PLLs are in bypass. Force PLL parameter update, 631 * disable PLL bypass, enable PLL 632 */ 633 ret = tc_pllupdate(tc, DP0_PLLCTRL); 634 if (ret) 635 goto err; 636 637 ret = tc_pllupdate(tc, DP1_PLLCTRL); 638 if (ret) 639 goto err; 640 641 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 1000); 642 if (ret == -ETIMEDOUT) { 643 dev_err(tc->dev, "Timeout waiting for PHY to become ready"); 644 return ret; 645 } else if (ret) { 646 goto err; 647 } 648 649 /* Setup AUX link */ 650 dp0_auxcfg1 = AUX_RX_FILTER_EN; 651 dp0_auxcfg1 |= 0x06 << 8; /* Aux Bit Period Calculator Threshold */ 652 dp0_auxcfg1 |= 0x3f << 0; /* Aux Response Timeout Timer */ 653 654 ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1); 655 if (ret) 656 goto err; 657 658 return 0; 659 err: 660 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret); 661 return ret; 662 } 663 664 static int tc_get_display_props(struct tc_data *tc) 665 { 666 int ret; 667 u8 reg; 668 669 /* Read DP Rx Link Capability */ 670 ret = drm_dp_link_probe(&tc->aux, &tc->link.base); 671 if (ret < 0) 672 goto err_dpcd_read; 673 if (tc->link.base.rate != 162000 && tc->link.base.rate != 270000) { 674 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n"); 675 tc->link.base.rate = 270000; 676 } 677 678 if (tc->link.base.num_lanes > 2) { 679 dev_dbg(tc->dev, "Falling to 2 lanes\n"); 680 tc->link.base.num_lanes = 2; 681 } 682 683 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, ®); 684 if (ret < 0) 685 goto err_dpcd_read; 686 tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5; 687 688 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, ®); 689 if (ret < 0) 690 goto err_dpcd_read; 691 692 tc->link.scrambler_dis = false; 693 /* read assr */ 694 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, ®); 695 if (ret < 0) 696 goto err_dpcd_read; 697 tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; 698 699 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n", 700 tc->link.base.revision >> 4, tc->link.base.revision & 0x0f, 701 (tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps", 702 tc->link.base.num_lanes, 703 (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ? 704 "enhanced" : "non-enhanced"); 705 dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n", 706 tc->link.spread ? "0.5%" : "0.0%", 707 tc->link.scrambler_dis ? "disabled" : "enabled"); 708 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n", 709 tc->link.assr, tc->assr); 710 711 return 0; 712 713 err_dpcd_read: 714 dev_err(tc->dev, "failed to read DPCD: %d\n", ret); 715 return ret; 716 } 717 718 static int tc_set_video_mode(struct tc_data *tc, 719 const struct drm_display_mode *mode) 720 { 721 int ret; 722 int vid_sync_dly; 723 int max_tu_symbol; 724 725 int left_margin = mode->htotal - mode->hsync_end; 726 int right_margin = mode->hsync_start - mode->hdisplay; 727 int hsync_len = mode->hsync_end - mode->hsync_start; 728 int upper_margin = mode->vtotal - mode->vsync_end; 729 int lower_margin = mode->vsync_start - mode->vdisplay; 730 int vsync_len = mode->vsync_end - mode->vsync_start; 731 u32 dp0_syncval; 732 733 /* 734 * Recommended maximum number of symbols transferred in a transfer unit: 735 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size, 736 * (output active video bandwidth in bytes)) 737 * Must be less than tu_size. 738 */ 739 max_tu_symbol = TU_SIZE_RECOMMENDED - 1; 740 741 dev_dbg(tc->dev, "set mode %dx%d\n", 742 mode->hdisplay, mode->vdisplay); 743 dev_dbg(tc->dev, "H margin %d,%d sync %d\n", 744 left_margin, right_margin, hsync_len); 745 dev_dbg(tc->dev, "V margin %d,%d sync %d\n", 746 upper_margin, lower_margin, vsync_len); 747 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal); 748 749 750 /* 751 * LCD Ctl Frame Size 752 * datasheet is not clear of vsdelay in case of DPI 753 * assume we do not need any delay when DPI is a source of 754 * sync signals 755 */ 756 ret = regmap_write(tc->regmap, VPCTRL0, 757 FIELD_PREP(VSDELAY, 0) | 758 OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED); 759 if (ret) 760 return ret; 761 762 ret = regmap_write(tc->regmap, HTIM01, 763 FIELD_PREP(HBPR, ALIGN(left_margin, 2)) | 764 FIELD_PREP(HPW, ALIGN(hsync_len, 2))); 765 if (ret) 766 return ret; 767 768 ret = regmap_write(tc->regmap, HTIM02, 769 FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) | 770 FIELD_PREP(HFPR, ALIGN(right_margin, 2))); 771 if (ret) 772 return ret; 773 774 ret = regmap_write(tc->regmap, VTIM01, 775 FIELD_PREP(VBPR, upper_margin) | 776 FIELD_PREP(VSPR, vsync_len)); 777 if (ret) 778 return ret; 779 780 ret = regmap_write(tc->regmap, VTIM02, 781 FIELD_PREP(VFPR, lower_margin) | 782 FIELD_PREP(VDISPR, mode->vdisplay)); 783 if (ret) 784 return ret; 785 786 ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */ 787 if (ret) 788 return ret; 789 790 /* Test pattern settings */ 791 ret = regmap_write(tc->regmap, TSTCTL, 792 FIELD_PREP(COLOR_R, 120) | 793 FIELD_PREP(COLOR_G, 20) | 794 FIELD_PREP(COLOR_B, 99) | 795 ENI2CFILTER | 796 FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS)); 797 if (ret) 798 return ret; 799 800 /* DP Main Stream Attributes */ 801 vid_sync_dly = hsync_len + left_margin + mode->hdisplay; 802 ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY, 803 FIELD_PREP(THRESH_DLY, max_tu_symbol) | 804 FIELD_PREP(VID_SYNC_DLY, vid_sync_dly)); 805 806 ret = regmap_write(tc->regmap, DP0_TOTALVAL, 807 FIELD_PREP(H_TOTAL, mode->htotal) | 808 FIELD_PREP(V_TOTAL, mode->vtotal)); 809 if (ret) 810 return ret; 811 812 ret = regmap_write(tc->regmap, DP0_STARTVAL, 813 FIELD_PREP(H_START, left_margin + hsync_len) | 814 FIELD_PREP(V_START, upper_margin + vsync_len)); 815 if (ret) 816 return ret; 817 818 ret = regmap_write(tc->regmap, DP0_ACTIVEVAL, 819 FIELD_PREP(V_ACT, mode->vdisplay) | 820 FIELD_PREP(H_ACT, mode->hdisplay)); 821 if (ret) 822 return ret; 823 824 dp0_syncval = FIELD_PREP(VS_WIDTH, vsync_len) | 825 FIELD_PREP(HS_WIDTH, hsync_len); 826 827 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 828 dp0_syncval |= SYNCVAL_VS_POL_ACTIVE_LOW; 829 830 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 831 dp0_syncval |= SYNCVAL_HS_POL_ACTIVE_LOW; 832 833 ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval); 834 if (ret) 835 return ret; 836 837 ret = regmap_write(tc->regmap, DPIPXLFMT, 838 VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW | 839 DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | 840 DPI_BPP_RGB888); 841 if (ret) 842 return ret; 843 844 ret = regmap_write(tc->regmap, DP0_MISC, 845 FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) | 846 FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) | 847 BPC_8); 848 if (ret) 849 return ret; 850 851 return 0; 852 } 853 854 static int tc_wait_link_training(struct tc_data *tc) 855 { 856 u32 value; 857 int ret; 858 859 ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE, 860 LT_LOOPDONE, 1, 1000); 861 if (ret) { 862 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n"); 863 return ret; 864 } 865 866 ret = regmap_read(tc->regmap, DP0_LTSTAT, &value); 867 if (ret) 868 return ret; 869 870 return (value >> 8) & 0x7; 871 } 872 873 static int tc_main_link_enable(struct tc_data *tc) 874 { 875 struct drm_dp_aux *aux = &tc->aux; 876 struct device *dev = tc->dev; 877 u32 dp_phy_ctrl; 878 u32 value; 879 int ret; 880 u8 tmp[DP_LINK_STATUS_SIZE]; 881 882 dev_dbg(tc->dev, "link enable\n"); 883 884 ret = regmap_read(tc->regmap, DP0CTL, &value); 885 if (ret) 886 return ret; 887 888 if (WARN_ON(value & DP_EN)) { 889 ret = regmap_write(tc->regmap, DP0CTL, 0); 890 if (ret) 891 return ret; 892 } 893 894 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc)); 895 if (ret) 896 return ret; 897 /* SSCG and BW27 on DP1 must be set to the same as on DP0 */ 898 ret = regmap_write(tc->regmap, DP1_SRCCTRL, 899 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) | 900 ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0)); 901 if (ret) 902 return ret; 903 904 ret = tc_set_syspllparam(tc); 905 if (ret) 906 return ret; 907 908 /* Setup Main Link */ 909 dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN; 910 if (tc->link.base.num_lanes == 2) 911 dp_phy_ctrl |= PHY_2LANE; 912 913 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); 914 if (ret) 915 return ret; 916 917 /* PLL setup */ 918 ret = tc_pllupdate(tc, DP0_PLLCTRL); 919 if (ret) 920 return ret; 921 922 ret = tc_pllupdate(tc, DP1_PLLCTRL); 923 if (ret) 924 return ret; 925 926 /* Reset/Enable Main Links */ 927 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST; 928 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); 929 usleep_range(100, 200); 930 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST); 931 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); 932 933 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 1000); 934 if (ret) { 935 dev_err(dev, "timeout waiting for phy become ready"); 936 return ret; 937 } 938 939 /* Set misc: 8 bits per color */ 940 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8); 941 if (ret) 942 return ret; 943 944 /* 945 * ASSR mode 946 * on TC358767 side ASSR configured through strap pin 947 * seems there is no way to change this setting from SW 948 * 949 * check is tc configured for same mode 950 */ 951 if (tc->assr != tc->link.assr) { 952 dev_dbg(dev, "Trying to set display to ASSR: %d\n", 953 tc->assr); 954 /* try to set ASSR on display side */ 955 tmp[0] = tc->assr; 956 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]); 957 if (ret < 0) 958 goto err_dpcd_read; 959 /* read back */ 960 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp); 961 if (ret < 0) 962 goto err_dpcd_read; 963 964 if (tmp[0] != tc->assr) { 965 dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n", 966 tc->assr); 967 /* trying with disabled scrambler */ 968 tc->link.scrambler_dis = true; 969 } 970 } 971 972 /* Setup Link & DPRx Config for Training */ 973 ret = drm_dp_link_configure(aux, &tc->link.base); 974 if (ret < 0) 975 goto err_dpcd_write; 976 977 /* DOWNSPREAD_CTRL */ 978 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00; 979 /* MAIN_LINK_CHANNEL_CODING_SET */ 980 tmp[1] = DP_SET_ANSI_8B10B; 981 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2); 982 if (ret < 0) 983 goto err_dpcd_write; 984 985 /* Reset voltage-swing & pre-emphasis */ 986 tmp[0] = tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 987 DP_TRAIN_PRE_EMPH_LEVEL_0; 988 ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2); 989 if (ret < 0) 990 goto err_dpcd_write; 991 992 /* Clock-Recovery */ 993 994 /* Set DPCD 0x102 for Training Pattern 1 */ 995 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL, 996 DP_LINK_SCRAMBLING_DISABLE | 997 DP_TRAINING_PATTERN_1); 998 if (ret) 999 return ret; 1000 1001 ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL, 1002 (15 << 28) | /* Defer Iteration Count */ 1003 (15 << 24) | /* Loop Iteration Count */ 1004 (0xd << 0)); /* Loop Timer Delay */ 1005 if (ret) 1006 return ret; 1007 1008 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 1009 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | 1010 DP0_SRCCTRL_AUTOCORRECT | 1011 DP0_SRCCTRL_TP1); 1012 if (ret) 1013 return ret; 1014 1015 /* Enable DP0 to start Link Training */ 1016 ret = regmap_write(tc->regmap, DP0CTL, 1017 ((tc->link.base.capabilities & 1018 DP_LINK_CAP_ENHANCED_FRAMING) ? EF_EN : 0) | 1019 DP_EN); 1020 if (ret) 1021 return ret; 1022 1023 /* wait */ 1024 1025 ret = tc_wait_link_training(tc); 1026 if (ret < 0) 1027 return ret; 1028 1029 if (ret) { 1030 dev_err(tc->dev, "Link training phase 1 failed: %s\n", 1031 training_pattern1_errors[ret]); 1032 return -ENODEV; 1033 } 1034 1035 /* Channel Equalization */ 1036 1037 /* Set DPCD 0x102 for Training Pattern 2 */ 1038 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL, 1039 DP_LINK_SCRAMBLING_DISABLE | 1040 DP_TRAINING_PATTERN_2); 1041 if (ret) 1042 return ret; 1043 1044 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 1045 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | 1046 DP0_SRCCTRL_AUTOCORRECT | 1047 DP0_SRCCTRL_TP2); 1048 if (ret) 1049 return ret; 1050 1051 /* wait */ 1052 ret = tc_wait_link_training(tc); 1053 if (ret < 0) 1054 return ret; 1055 1056 if (ret) { 1057 dev_err(tc->dev, "Link training phase 2 failed: %s\n", 1058 training_pattern2_errors[ret]); 1059 return -ENODEV; 1060 } 1061 1062 /* 1063 * Toshiba's documentation suggests to first clear DPCD 0x102, then 1064 * clear the training pattern bit in DP0_SRCCTRL. Testing shows 1065 * that the link sometimes drops if those steps are done in that order, 1066 * but if the steps are done in reverse order, the link stays up. 1067 * 1068 * So we do the steps differently than documented here. 1069 */ 1070 1071 /* Clear Training Pattern, set AutoCorrect Mode = 1 */ 1072 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) | 1073 DP0_SRCCTRL_AUTOCORRECT); 1074 if (ret) 1075 return ret; 1076 1077 /* Clear DPCD 0x102 */ 1078 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */ 1079 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00; 1080 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]); 1081 if (ret < 0) 1082 goto err_dpcd_write; 1083 1084 /* Check link status */ 1085 ret = drm_dp_dpcd_read_link_status(aux, tmp); 1086 if (ret < 0) 1087 goto err_dpcd_read; 1088 1089 ret = 0; 1090 1091 value = tmp[0] & DP_CHANNEL_EQ_BITS; 1092 1093 if (value != DP_CHANNEL_EQ_BITS) { 1094 dev_err(tc->dev, "Lane 0 failed: %x\n", value); 1095 ret = -ENODEV; 1096 } 1097 1098 if (tc->link.base.num_lanes == 2) { 1099 value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS; 1100 1101 if (value != DP_CHANNEL_EQ_BITS) { 1102 dev_err(tc->dev, "Lane 1 failed: %x\n", value); 1103 ret = -ENODEV; 1104 } 1105 1106 if (!(tmp[2] & DP_INTERLANE_ALIGN_DONE)) { 1107 dev_err(tc->dev, "Interlane align failed\n"); 1108 ret = -ENODEV; 1109 } 1110 } 1111 1112 if (ret) { 1113 dev_err(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[0]); 1114 dev_err(dev, "0x0203 LANE2_3_STATUS 0x%02x\n", tmp[1]); 1115 dev_err(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", tmp[2]); 1116 dev_err(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[3]); 1117 dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n", tmp[4]); 1118 dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3: 0x%02x\n", tmp[5]); 1119 return ret; 1120 } 1121 1122 return 0; 1123 err_dpcd_read: 1124 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret); 1125 return ret; 1126 err_dpcd_write: 1127 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret); 1128 return ret; 1129 } 1130 1131 static int tc_main_link_disable(struct tc_data *tc) 1132 { 1133 int ret; 1134 1135 dev_dbg(tc->dev, "link disable\n"); 1136 1137 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0); 1138 if (ret) 1139 return ret; 1140 1141 return regmap_write(tc->regmap, DP0CTL, 0); 1142 } 1143 1144 static int tc_stream_enable(struct tc_data *tc) 1145 { 1146 int ret; 1147 u32 value; 1148 1149 dev_dbg(tc->dev, "enable video stream\n"); 1150 1151 /* PXL PLL setup */ 1152 if (tc_test_pattern) { 1153 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), 1154 1000 * tc->mode.clock); 1155 if (ret) 1156 return ret; 1157 } 1158 1159 ret = tc_set_video_mode(tc, &tc->mode); 1160 if (ret) 1161 return ret; 1162 1163 /* Set M/N */ 1164 ret = tc_stream_clock_calc(tc); 1165 if (ret) 1166 return ret; 1167 1168 value = VID_MN_GEN | DP_EN; 1169 if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 1170 value |= EF_EN; 1171 ret = regmap_write(tc->regmap, DP0CTL, value); 1172 if (ret) 1173 return ret; 1174 /* 1175 * VID_EN assertion should be delayed by at least N * LSCLK 1176 * cycles from the time VID_MN_GEN is enabled in order to 1177 * generate stable values for VID_M. LSCLK is 270 MHz or 1178 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(), 1179 * so a delay of at least 203 us should suffice. 1180 */ 1181 usleep_range(500, 1000); 1182 value |= VID_EN; 1183 ret = regmap_write(tc->regmap, DP0CTL, value); 1184 if (ret) 1185 return ret; 1186 /* Set input interface */ 1187 value = DP0_AUDSRC_NO_INPUT; 1188 if (tc_test_pattern) 1189 value |= DP0_VIDSRC_COLOR_BAR; 1190 else 1191 value |= DP0_VIDSRC_DPI_RX; 1192 ret = regmap_write(tc->regmap, SYSCTRL, value); 1193 if (ret) 1194 return ret; 1195 1196 return 0; 1197 } 1198 1199 static int tc_stream_disable(struct tc_data *tc) 1200 { 1201 int ret; 1202 1203 dev_dbg(tc->dev, "disable video stream\n"); 1204 1205 ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0); 1206 if (ret) 1207 return ret; 1208 1209 tc_pxl_pll_dis(tc); 1210 1211 return 0; 1212 } 1213 1214 static void tc_bridge_pre_enable(struct drm_bridge *bridge) 1215 { 1216 struct tc_data *tc = bridge_to_tc(bridge); 1217 1218 drm_panel_prepare(tc->panel); 1219 } 1220 1221 static void tc_bridge_enable(struct drm_bridge *bridge) 1222 { 1223 struct tc_data *tc = bridge_to_tc(bridge); 1224 int ret; 1225 1226 ret = tc_get_display_props(tc); 1227 if (ret < 0) { 1228 dev_err(tc->dev, "failed to read display props: %d\n", ret); 1229 return; 1230 } 1231 1232 ret = tc_main_link_enable(tc); 1233 if (ret < 0) { 1234 dev_err(tc->dev, "main link enable error: %d\n", ret); 1235 return; 1236 } 1237 1238 ret = tc_stream_enable(tc); 1239 if (ret < 0) { 1240 dev_err(tc->dev, "main link stream start error: %d\n", ret); 1241 tc_main_link_disable(tc); 1242 return; 1243 } 1244 1245 drm_panel_enable(tc->panel); 1246 } 1247 1248 static void tc_bridge_disable(struct drm_bridge *bridge) 1249 { 1250 struct tc_data *tc = bridge_to_tc(bridge); 1251 int ret; 1252 1253 drm_panel_disable(tc->panel); 1254 1255 ret = tc_stream_disable(tc); 1256 if (ret < 0) 1257 dev_err(tc->dev, "main link stream stop error: %d\n", ret); 1258 1259 ret = tc_main_link_disable(tc); 1260 if (ret < 0) 1261 dev_err(tc->dev, "main link disable error: %d\n", ret); 1262 } 1263 1264 static void tc_bridge_post_disable(struct drm_bridge *bridge) 1265 { 1266 struct tc_data *tc = bridge_to_tc(bridge); 1267 1268 drm_panel_unprepare(tc->panel); 1269 } 1270 1271 static bool tc_bridge_mode_fixup(struct drm_bridge *bridge, 1272 const struct drm_display_mode *mode, 1273 struct drm_display_mode *adj) 1274 { 1275 /* Fixup sync polarities, both hsync and vsync are active low */ 1276 adj->flags = mode->flags; 1277 adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); 1278 adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 1279 1280 return true; 1281 } 1282 1283 static enum drm_mode_status tc_mode_valid(struct drm_bridge *bridge, 1284 const struct drm_display_mode *mode) 1285 { 1286 struct tc_data *tc = bridge_to_tc(bridge); 1287 u32 req, avail; 1288 u32 bits_per_pixel = 24; 1289 1290 /* DPI interface clock limitation: upto 154 MHz */ 1291 if (mode->clock > 154000) 1292 return MODE_CLOCK_HIGH; 1293 1294 req = mode->clock * bits_per_pixel / 8; 1295 avail = tc->link.base.num_lanes * tc->link.base.rate; 1296 1297 if (req > avail) 1298 return MODE_BAD; 1299 1300 return MODE_OK; 1301 } 1302 1303 static void tc_bridge_mode_set(struct drm_bridge *bridge, 1304 const struct drm_display_mode *mode, 1305 const struct drm_display_mode *adj) 1306 { 1307 struct tc_data *tc = bridge_to_tc(bridge); 1308 1309 tc->mode = *mode; 1310 } 1311 1312 static int tc_connector_get_modes(struct drm_connector *connector) 1313 { 1314 struct tc_data *tc = connector_to_tc(connector); 1315 struct edid *edid; 1316 int count; 1317 int ret; 1318 1319 ret = tc_get_display_props(tc); 1320 if (ret < 0) { 1321 dev_err(tc->dev, "failed to read display props: %d\n", ret); 1322 return 0; 1323 } 1324 1325 count = drm_panel_get_modes(tc->panel); 1326 if (count > 0) 1327 return count; 1328 1329 edid = drm_get_edid(connector, &tc->aux.ddc); 1330 1331 kfree(tc->edid); 1332 tc->edid = edid; 1333 if (!edid) 1334 return 0; 1335 1336 drm_connector_update_edid_property(connector, edid); 1337 count = drm_add_edid_modes(connector, edid); 1338 1339 return count; 1340 } 1341 1342 static const struct drm_connector_helper_funcs tc_connector_helper_funcs = { 1343 .get_modes = tc_connector_get_modes, 1344 }; 1345 1346 static enum drm_connector_status tc_connector_detect(struct drm_connector *connector, 1347 bool force) 1348 { 1349 struct tc_data *tc = connector_to_tc(connector); 1350 bool conn; 1351 u32 val; 1352 int ret; 1353 1354 if (tc->hpd_pin < 0) { 1355 if (tc->panel) 1356 return connector_status_connected; 1357 else 1358 return connector_status_unknown; 1359 } 1360 1361 ret = regmap_read(tc->regmap, GPIOI, &val); 1362 if (ret) 1363 return connector_status_unknown; 1364 1365 conn = val & BIT(tc->hpd_pin); 1366 1367 if (conn) 1368 return connector_status_connected; 1369 else 1370 return connector_status_disconnected; 1371 } 1372 1373 static const struct drm_connector_funcs tc_connector_funcs = { 1374 .detect = tc_connector_detect, 1375 .fill_modes = drm_helper_probe_single_connector_modes, 1376 .destroy = drm_connector_cleanup, 1377 .reset = drm_atomic_helper_connector_reset, 1378 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1379 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1380 }; 1381 1382 static int tc_bridge_attach(struct drm_bridge *bridge) 1383 { 1384 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1385 struct tc_data *tc = bridge_to_tc(bridge); 1386 struct drm_device *drm = bridge->dev; 1387 int ret; 1388 1389 /* Create DP/eDP connector */ 1390 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs); 1391 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, 1392 tc->panel ? DRM_MODE_CONNECTOR_eDP : 1393 DRM_MODE_CONNECTOR_DisplayPort); 1394 if (ret) 1395 return ret; 1396 1397 /* Don't poll if don't have HPD connected */ 1398 if (tc->hpd_pin >= 0) { 1399 if (tc->have_irq) 1400 tc->connector.polled = DRM_CONNECTOR_POLL_HPD; 1401 else 1402 tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT | 1403 DRM_CONNECTOR_POLL_DISCONNECT; 1404 } 1405 1406 if (tc->panel) 1407 drm_panel_attach(tc->panel, &tc->connector); 1408 1409 drm_display_info_set_bus_formats(&tc->connector.display_info, 1410 &bus_format, 1); 1411 tc->connector.display_info.bus_flags = 1412 DRM_BUS_FLAG_DE_HIGH | 1413 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE | 1414 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE; 1415 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder); 1416 1417 return 0; 1418 } 1419 1420 static const struct drm_bridge_funcs tc_bridge_funcs = { 1421 .attach = tc_bridge_attach, 1422 .mode_valid = tc_mode_valid, 1423 .mode_set = tc_bridge_mode_set, 1424 .pre_enable = tc_bridge_pre_enable, 1425 .enable = tc_bridge_enable, 1426 .disable = tc_bridge_disable, 1427 .post_disable = tc_bridge_post_disable, 1428 .mode_fixup = tc_bridge_mode_fixup, 1429 }; 1430 1431 static bool tc_readable_reg(struct device *dev, unsigned int reg) 1432 { 1433 return reg != SYSCTRL; 1434 } 1435 1436 static const struct regmap_range tc_volatile_ranges[] = { 1437 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS), 1438 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ), 1439 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL), 1440 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL), 1441 regmap_reg_range(VFUEN0, VFUEN0), 1442 regmap_reg_range(INTSTS_G, INTSTS_G), 1443 regmap_reg_range(GPIOI, GPIOI), 1444 }; 1445 1446 static const struct regmap_access_table tc_volatile_table = { 1447 .yes_ranges = tc_volatile_ranges, 1448 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges), 1449 }; 1450 1451 static bool tc_writeable_reg(struct device *dev, unsigned int reg) 1452 { 1453 return (reg != TC_IDREG) && 1454 (reg != DP0_LTSTAT) && 1455 (reg != DP0_SNKLTCHGREQ); 1456 } 1457 1458 static const struct regmap_config tc_regmap_config = { 1459 .name = "tc358767", 1460 .reg_bits = 16, 1461 .val_bits = 32, 1462 .reg_stride = 4, 1463 .max_register = PLL_DBG, 1464 .cache_type = REGCACHE_RBTREE, 1465 .readable_reg = tc_readable_reg, 1466 .volatile_table = &tc_volatile_table, 1467 .writeable_reg = tc_writeable_reg, 1468 .reg_format_endian = REGMAP_ENDIAN_BIG, 1469 .val_format_endian = REGMAP_ENDIAN_LITTLE, 1470 }; 1471 1472 static irqreturn_t tc_irq_handler(int irq, void *arg) 1473 { 1474 struct tc_data *tc = arg; 1475 u32 val; 1476 int r; 1477 1478 r = regmap_read(tc->regmap, INTSTS_G, &val); 1479 if (r) 1480 return IRQ_NONE; 1481 1482 if (!val) 1483 return IRQ_NONE; 1484 1485 if (val & INT_SYSERR) { 1486 u32 stat = 0; 1487 1488 regmap_read(tc->regmap, SYSSTAT, &stat); 1489 1490 dev_err(tc->dev, "syserr %x\n", stat); 1491 } 1492 1493 if (tc->hpd_pin >= 0 && tc->bridge.dev) { 1494 /* 1495 * H is triggered when the GPIO goes high. 1496 * 1497 * LC is triggered when the GPIO goes low and stays low for 1498 * the duration of LCNT 1499 */ 1500 bool h = val & INT_GPIO_H(tc->hpd_pin); 1501 bool lc = val & INT_GPIO_LC(tc->hpd_pin); 1502 1503 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin, 1504 h ? "H" : "", lc ? "LC" : ""); 1505 1506 if (h || lc) 1507 drm_kms_helper_hotplug_event(tc->bridge.dev); 1508 } 1509 1510 regmap_write(tc->regmap, INTSTS_G, val); 1511 1512 return IRQ_HANDLED; 1513 } 1514 1515 static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id) 1516 { 1517 struct device *dev = &client->dev; 1518 struct tc_data *tc; 1519 int ret; 1520 1521 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL); 1522 if (!tc) 1523 return -ENOMEM; 1524 1525 tc->dev = dev; 1526 1527 /* port@2 is the output port */ 1528 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL); 1529 if (ret && ret != -ENODEV) 1530 return ret; 1531 1532 /* Shut down GPIO is optional */ 1533 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH); 1534 if (IS_ERR(tc->sd_gpio)) 1535 return PTR_ERR(tc->sd_gpio); 1536 1537 if (tc->sd_gpio) { 1538 gpiod_set_value_cansleep(tc->sd_gpio, 0); 1539 usleep_range(5000, 10000); 1540 } 1541 1542 /* Reset GPIO is optional */ 1543 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1544 if (IS_ERR(tc->reset_gpio)) 1545 return PTR_ERR(tc->reset_gpio); 1546 1547 if (tc->reset_gpio) { 1548 gpiod_set_value_cansleep(tc->reset_gpio, 1); 1549 usleep_range(5000, 10000); 1550 } 1551 1552 tc->refclk = devm_clk_get(dev, "ref"); 1553 if (IS_ERR(tc->refclk)) { 1554 ret = PTR_ERR(tc->refclk); 1555 dev_err(dev, "Failed to get refclk: %d\n", ret); 1556 return ret; 1557 } 1558 1559 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config); 1560 if (IS_ERR(tc->regmap)) { 1561 ret = PTR_ERR(tc->regmap); 1562 dev_err(dev, "Failed to initialize regmap: %d\n", ret); 1563 return ret; 1564 } 1565 1566 ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin", 1567 &tc->hpd_pin); 1568 if (ret) { 1569 tc->hpd_pin = -ENODEV; 1570 } else { 1571 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) { 1572 dev_err(dev, "failed to parse HPD number\n"); 1573 return ret; 1574 } 1575 } 1576 1577 if (client->irq > 0) { 1578 /* enable SysErr */ 1579 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR); 1580 1581 ret = devm_request_threaded_irq(dev, client->irq, 1582 NULL, tc_irq_handler, 1583 IRQF_ONESHOT, 1584 "tc358767-irq", tc); 1585 if (ret) { 1586 dev_err(dev, "failed to register dp interrupt\n"); 1587 return ret; 1588 } 1589 1590 tc->have_irq = true; 1591 } 1592 1593 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev); 1594 if (ret) { 1595 dev_err(tc->dev, "can not read device ID: %d\n", ret); 1596 return ret; 1597 } 1598 1599 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) { 1600 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev); 1601 return -EINVAL; 1602 } 1603 1604 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */ 1605 1606 if (!tc->reset_gpio) { 1607 /* 1608 * If the reset pin isn't present, do a software reset. It isn't 1609 * as thorough as the hardware reset, as we can't reset the I2C 1610 * communication block for obvious reasons, but it's getting the 1611 * chip into a defined state. 1612 */ 1613 regmap_update_bits(tc->regmap, SYSRSTENB, 1614 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP, 1615 0); 1616 regmap_update_bits(tc->regmap, SYSRSTENB, 1617 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP, 1618 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP); 1619 usleep_range(5000, 10000); 1620 } 1621 1622 if (tc->hpd_pin >= 0) { 1623 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT; 1624 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin); 1625 1626 /* Set LCNT to 2ms */ 1627 regmap_write(tc->regmap, lcnt_reg, 1628 clk_get_rate(tc->refclk) * 2 / 1000); 1629 /* We need the "alternate" mode for HPD */ 1630 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin)); 1631 1632 if (tc->have_irq) { 1633 /* enable H & LC */ 1634 regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc); 1635 } 1636 } 1637 1638 ret = tc_aux_link_setup(tc); 1639 if (ret) 1640 return ret; 1641 1642 /* Register DP AUX channel */ 1643 tc->aux.name = "TC358767 AUX i2c adapter"; 1644 tc->aux.dev = tc->dev; 1645 tc->aux.transfer = tc_aux_transfer; 1646 ret = drm_dp_aux_register(&tc->aux); 1647 if (ret) 1648 return ret; 1649 1650 tc->bridge.funcs = &tc_bridge_funcs; 1651 tc->bridge.of_node = dev->of_node; 1652 drm_bridge_add(&tc->bridge); 1653 1654 i2c_set_clientdata(client, tc); 1655 1656 return 0; 1657 } 1658 1659 static int tc_remove(struct i2c_client *client) 1660 { 1661 struct tc_data *tc = i2c_get_clientdata(client); 1662 1663 drm_bridge_remove(&tc->bridge); 1664 drm_dp_aux_unregister(&tc->aux); 1665 1666 return 0; 1667 } 1668 1669 static const struct i2c_device_id tc358767_i2c_ids[] = { 1670 { "tc358767", 0 }, 1671 { } 1672 }; 1673 MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids); 1674 1675 static const struct of_device_id tc358767_of_ids[] = { 1676 { .compatible = "toshiba,tc358767", }, 1677 { } 1678 }; 1679 MODULE_DEVICE_TABLE(of, tc358767_of_ids); 1680 1681 static struct i2c_driver tc358767_driver = { 1682 .driver = { 1683 .name = "tc358767", 1684 .of_match_table = tc358767_of_ids, 1685 }, 1686 .id_table = tc358767_i2c_ids, 1687 .probe = tc_probe, 1688 .remove = tc_remove, 1689 }; 1690 module_i2c_driver(tc358767_driver); 1691 1692 MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>"); 1693 MODULE_DESCRIPTION("tc358767 eDP encoder driver"); 1694 MODULE_LICENSE("GPL"); 1695