1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Samsung Electronics Co., Ltd 4 * 5 * Authors: 6 * Andrzej Hajda <a.hajda@samsung.com> 7 * Maciej Purski <m.purski@samsung.com> 8 */ 9 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/module.h> 13 #include <linux/of_graph.h> 14 #include <linux/regulator/consumer.h> 15 16 #include <video/mipi_display.h> 17 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_bridge.h> 20 #include <drm/drm_crtc.h> 21 #include <drm/drm_fb_helper.h> 22 #include <drm/drm_mipi_dsi.h> 23 #include <drm/drm_of.h> 24 #include <drm/drm_panel.h> 25 #include <drm/drm_print.h> 26 #include <drm/drm_probe_helper.h> 27 28 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) 29 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) 30 31 /* PPI layer registers */ 32 #define PPI_STARTPPI 0x0104 /* START control bit */ 33 #define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */ 34 #define PPI_LANEENABLE 0x0134 /* Enables each lane */ 35 #define PPI_TX_RX_TA 0x013C /* BTA timing parameters */ 36 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */ 37 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */ 38 #define PPI_D2S_CLRSIPOCOUNT 0x016C /* Assertion timer for Lane 2 */ 39 #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */ 40 #define PPI_START_FUNCTION 1 41 42 /* DSI layer registers */ 43 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */ 44 #define DSI_LANEENABLE 0x0210 /* Enables each lane */ 45 #define DSI_RX_START 1 46 47 /* Video path registers */ 48 #define VP_CTRL 0x0450 /* Video Path Control */ 49 #define VP_CTRL_MSF(v) FLD_VAL(v, 0, 0) /* Magic square in RGB666 */ 50 #define VP_CTRL_VTGEN(v) FLD_VAL(v, 4, 4) /* Use chip clock for timing */ 51 #define VP_CTRL_EVTMODE(v) FLD_VAL(v, 5, 5) /* Event mode */ 52 #define VP_CTRL_RGB888(v) FLD_VAL(v, 8, 8) /* RGB888 mode */ 53 #define VP_CTRL_VSDELAY(v) FLD_VAL(v, 31, 20) /* VSYNC delay */ 54 #define VP_CTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */ 55 #define VP_CTRL_DEPOL BIT(18) /* Polarity of DE signal */ 56 #define VP_CTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */ 57 #define VP_HTIM1 0x0454 /* Horizontal Timing Control 1 */ 58 #define VP_HTIM1_HBP(v) FLD_VAL(v, 24, 16) 59 #define VP_HTIM1_HSYNC(v) FLD_VAL(v, 8, 0) 60 #define VP_HTIM2 0x0458 /* Horizontal Timing Control 2 */ 61 #define VP_HTIM2_HFP(v) FLD_VAL(v, 24, 16) 62 #define VP_HTIM2_HACT(v) FLD_VAL(v, 10, 0) 63 #define VP_VTIM1 0x045C /* Vertical Timing Control 1 */ 64 #define VP_VTIM1_VBP(v) FLD_VAL(v, 23, 16) 65 #define VP_VTIM1_VSYNC(v) FLD_VAL(v, 7, 0) 66 #define VP_VTIM2 0x0460 /* Vertical Timing Control 2 */ 67 #define VP_VTIM2_VFP(v) FLD_VAL(v, 23, 16) 68 #define VP_VTIM2_VACT(v) FLD_VAL(v, 10, 0) 69 #define VP_VFUEN 0x0464 /* Video Frame Timing Update Enable */ 70 71 /* LVDS registers */ 72 #define LV_MX0003 0x0480 /* Mux input bit 0 to 3 */ 73 #define LV_MX0407 0x0484 /* Mux input bit 4 to 7 */ 74 #define LV_MX0811 0x0488 /* Mux input bit 8 to 11 */ 75 #define LV_MX1215 0x048C /* Mux input bit 12 to 15 */ 76 #define LV_MX1619 0x0490 /* Mux input bit 16 to 19 */ 77 #define LV_MX2023 0x0494 /* Mux input bit 20 to 23 */ 78 #define LV_MX2427 0x0498 /* Mux input bit 24 to 27 */ 79 #define LV_MX(b0, b1, b2, b3) (FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \ 80 FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24)) 81 82 /* Input bit numbers used in mux registers */ 83 enum { 84 LVI_R0, 85 LVI_R1, 86 LVI_R2, 87 LVI_R3, 88 LVI_R4, 89 LVI_R5, 90 LVI_R6, 91 LVI_R7, 92 LVI_G0, 93 LVI_G1, 94 LVI_G2, 95 LVI_G3, 96 LVI_G4, 97 LVI_G5, 98 LVI_G6, 99 LVI_G7, 100 LVI_B0, 101 LVI_B1, 102 LVI_B2, 103 LVI_B3, 104 LVI_B4, 105 LVI_B5, 106 LVI_B6, 107 LVI_B7, 108 LVI_HS, 109 LVI_VS, 110 LVI_DE, 111 LVI_L0 112 }; 113 114 #define LV_CFG 0x049C /* LVDS Configuration */ 115 #define LV_PHY0 0x04A0 /* LVDS PHY 0 */ 116 #define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */ 117 #define LV_PHY0_IS(v) FLD_VAL(v, 15, 14) 118 #define LV_PHY0_ND(v) FLD_VAL(v, 4, 0) /* Frequency range select */ 119 #define LV_PHY0_PRBS_ON(v) FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */ 120 121 /* System registers */ 122 #define SYS_RST 0x0504 /* System Reset */ 123 #define SYS_ID 0x0580 /* System ID */ 124 125 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */ 126 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */ 127 #define SYS_RST_LCD BIT(2) /* Reset LCD controller */ 128 #define SYS_RST_BM BIT(3) /* Reset Bus Management controller */ 129 #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */ 130 #define SYS_RST_REG BIT(5) /* Reset Register module */ 131 132 #define LPX_PERIOD 2 133 #define TTA_SURE 3 134 #define TTA_GET 0x20000 135 136 /* Lane enable PPI and DSI register bits */ 137 #define LANEENABLE_CLEN BIT(0) 138 #define LANEENABLE_L0EN BIT(1) 139 #define LANEENABLE_L1EN BIT(2) 140 #define LANEENABLE_L2EN BIT(3) 141 #define LANEENABLE_L3EN BIT(4) 142 143 /* LVCFG fields */ 144 #define LV_CFG_LVEN BIT(0) 145 #define LV_CFG_LVDLINK BIT(1) 146 #define LV_CFG_CLKPOL1 BIT(2) 147 #define LV_CFG_CLKPOL2 BIT(3) 148 149 static const char * const tc358764_supplies[] = { 150 "vddc", "vddio", "vddlvds" 151 }; 152 153 struct tc358764 { 154 struct device *dev; 155 struct drm_bridge bridge; 156 struct drm_connector connector; 157 struct regulator_bulk_data supplies[ARRAY_SIZE(tc358764_supplies)]; 158 struct gpio_desc *gpio_reset; 159 struct drm_panel *panel; 160 int error; 161 }; 162 163 static int tc358764_clear_error(struct tc358764 *ctx) 164 { 165 int ret = ctx->error; 166 167 ctx->error = 0; 168 return ret; 169 } 170 171 static void tc358764_read(struct tc358764 *ctx, u16 addr, u32 *val) 172 { 173 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 174 ssize_t ret; 175 176 if (ctx->error) 177 return; 178 179 cpu_to_le16s(&addr); 180 ret = mipi_dsi_generic_read(dsi, &addr, sizeof(addr), val, sizeof(*val)); 181 if (ret >= 0) 182 le32_to_cpus(val); 183 184 dev_dbg(ctx->dev, "read: %d, addr: %d\n", addr, *val); 185 } 186 187 static void tc358764_write(struct tc358764 *ctx, u16 addr, u32 val) 188 { 189 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 190 ssize_t ret; 191 u8 data[6]; 192 193 if (ctx->error) 194 return; 195 196 data[0] = addr; 197 data[1] = addr >> 8; 198 data[2] = val; 199 data[3] = val >> 8; 200 data[4] = val >> 16; 201 data[5] = val >> 24; 202 203 ret = mipi_dsi_generic_write(dsi, data, sizeof(data)); 204 if (ret < 0) 205 ctx->error = ret; 206 } 207 208 static inline struct tc358764 *bridge_to_tc358764(struct drm_bridge *bridge) 209 { 210 return container_of(bridge, struct tc358764, bridge); 211 } 212 213 static inline 214 struct tc358764 *connector_to_tc358764(struct drm_connector *connector) 215 { 216 return container_of(connector, struct tc358764, connector); 217 } 218 219 static int tc358764_init(struct tc358764 *ctx) 220 { 221 u32 v = 0; 222 223 tc358764_read(ctx, SYS_ID, &v); 224 if (ctx->error) 225 return tc358764_clear_error(ctx); 226 dev_info(ctx->dev, "ID: %#x\n", v); 227 228 /* configure PPI counters */ 229 tc358764_write(ctx, PPI_TX_RX_TA, TTA_GET | TTA_SURE); 230 tc358764_write(ctx, PPI_LPTXTIMECNT, LPX_PERIOD); 231 tc358764_write(ctx, PPI_D0S_CLRSIPOCOUNT, 5); 232 tc358764_write(ctx, PPI_D1S_CLRSIPOCOUNT, 5); 233 tc358764_write(ctx, PPI_D2S_CLRSIPOCOUNT, 5); 234 tc358764_write(ctx, PPI_D3S_CLRSIPOCOUNT, 5); 235 236 /* enable four data lanes and clock lane */ 237 tc358764_write(ctx, PPI_LANEENABLE, LANEENABLE_L3EN | LANEENABLE_L2EN | 238 LANEENABLE_L1EN | LANEENABLE_L0EN | LANEENABLE_CLEN); 239 tc358764_write(ctx, DSI_LANEENABLE, LANEENABLE_L3EN | LANEENABLE_L2EN | 240 LANEENABLE_L1EN | LANEENABLE_L0EN | LANEENABLE_CLEN); 241 242 /* start */ 243 tc358764_write(ctx, PPI_STARTPPI, PPI_START_FUNCTION); 244 tc358764_write(ctx, DSI_STARTDSI, DSI_RX_START); 245 246 /* configure video path */ 247 tc358764_write(ctx, VP_CTRL, VP_CTRL_VSDELAY(15) | VP_CTRL_RGB888(1) | 248 VP_CTRL_EVTMODE(1) | VP_CTRL_HSPOL | VP_CTRL_VSPOL); 249 250 /* reset PHY */ 251 tc358764_write(ctx, LV_PHY0, LV_PHY0_RST(1) | 252 LV_PHY0_PRBS_ON(4) | LV_PHY0_IS(2) | LV_PHY0_ND(6)); 253 tc358764_write(ctx, LV_PHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_IS(2) | 254 LV_PHY0_ND(6)); 255 256 /* reset bridge */ 257 tc358764_write(ctx, SYS_RST, SYS_RST_LCD); 258 259 /* set bit order */ 260 tc358764_write(ctx, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3)); 261 tc358764_write(ctx, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0)); 262 tc358764_write(ctx, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7)); 263 tc358764_write(ctx, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0)); 264 tc358764_write(ctx, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2)); 265 tc358764_write(ctx, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0)); 266 tc358764_write(ctx, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6)); 267 tc358764_write(ctx, LV_CFG, LV_CFG_CLKPOL2 | LV_CFG_CLKPOL1 | 268 LV_CFG_LVEN); 269 270 return tc358764_clear_error(ctx); 271 } 272 273 static void tc358764_reset(struct tc358764 *ctx) 274 { 275 gpiod_set_value(ctx->gpio_reset, 1); 276 usleep_range(1000, 2000); 277 gpiod_set_value(ctx->gpio_reset, 0); 278 usleep_range(1000, 2000); 279 } 280 281 static int tc358764_get_modes(struct drm_connector *connector) 282 { 283 struct tc358764 *ctx = connector_to_tc358764(connector); 284 285 return drm_panel_get_modes(ctx->panel, connector); 286 } 287 288 static const 289 struct drm_connector_helper_funcs tc358764_connector_helper_funcs = { 290 .get_modes = tc358764_get_modes, 291 }; 292 293 static const struct drm_connector_funcs tc358764_connector_funcs = { 294 .fill_modes = drm_helper_probe_single_connector_modes, 295 .destroy = drm_connector_cleanup, 296 .reset = drm_atomic_helper_connector_reset, 297 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 298 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 299 }; 300 301 static void tc358764_disable(struct drm_bridge *bridge) 302 { 303 struct tc358764 *ctx = bridge_to_tc358764(bridge); 304 int ret = drm_panel_disable(bridge_to_tc358764(bridge)->panel); 305 306 if (ret < 0) 307 dev_err(ctx->dev, "error disabling panel (%d)\n", ret); 308 } 309 310 static void tc358764_post_disable(struct drm_bridge *bridge) 311 { 312 struct tc358764 *ctx = bridge_to_tc358764(bridge); 313 int ret; 314 315 ret = drm_panel_unprepare(ctx->panel); 316 if (ret < 0) 317 dev_err(ctx->dev, "error unpreparing panel (%d)\n", ret); 318 tc358764_reset(ctx); 319 usleep_range(10000, 15000); 320 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 321 if (ret < 0) 322 dev_err(ctx->dev, "error disabling regulators (%d)\n", ret); 323 } 324 325 static void tc358764_pre_enable(struct drm_bridge *bridge) 326 { 327 struct tc358764 *ctx = bridge_to_tc358764(bridge); 328 int ret; 329 330 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 331 if (ret < 0) 332 dev_err(ctx->dev, "error enabling regulators (%d)\n", ret); 333 usleep_range(10000, 15000); 334 tc358764_reset(ctx); 335 ret = tc358764_init(ctx); 336 if (ret < 0) 337 dev_err(ctx->dev, "error initializing bridge (%d)\n", ret); 338 ret = drm_panel_prepare(ctx->panel); 339 if (ret < 0) 340 dev_err(ctx->dev, "error preparing panel (%d)\n", ret); 341 } 342 343 static void tc358764_enable(struct drm_bridge *bridge) 344 { 345 struct tc358764 *ctx = bridge_to_tc358764(bridge); 346 int ret = drm_panel_enable(ctx->panel); 347 348 if (ret < 0) 349 dev_err(ctx->dev, "error enabling panel (%d)\n", ret); 350 } 351 352 static int tc358764_attach(struct drm_bridge *bridge, 353 enum drm_bridge_attach_flags flags) 354 { 355 struct tc358764 *ctx = bridge_to_tc358764(bridge); 356 struct drm_device *drm = bridge->dev; 357 int ret; 358 359 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) { 360 DRM_ERROR("Fix bridge driver to make connector optional!"); 361 return -EINVAL; 362 } 363 364 ctx->connector.polled = DRM_CONNECTOR_POLL_HPD; 365 ret = drm_connector_init(drm, &ctx->connector, 366 &tc358764_connector_funcs, 367 DRM_MODE_CONNECTOR_LVDS); 368 if (ret) { 369 DRM_ERROR("Failed to initialize connector\n"); 370 return ret; 371 } 372 373 drm_connector_helper_add(&ctx->connector, 374 &tc358764_connector_helper_funcs); 375 drm_connector_attach_encoder(&ctx->connector, bridge->encoder); 376 ctx->connector.funcs->reset(&ctx->connector); 377 drm_connector_register(&ctx->connector); 378 379 return 0; 380 } 381 382 static void tc358764_detach(struct drm_bridge *bridge) 383 { 384 struct tc358764 *ctx = bridge_to_tc358764(bridge); 385 386 drm_connector_unregister(&ctx->connector); 387 ctx->panel = NULL; 388 drm_connector_put(&ctx->connector); 389 } 390 391 static const struct drm_bridge_funcs tc358764_bridge_funcs = { 392 .disable = tc358764_disable, 393 .post_disable = tc358764_post_disable, 394 .enable = tc358764_enable, 395 .pre_enable = tc358764_pre_enable, 396 .attach = tc358764_attach, 397 .detach = tc358764_detach, 398 }; 399 400 static int tc358764_parse_dt(struct tc358764 *ctx) 401 { 402 struct device *dev = ctx->dev; 403 int ret; 404 405 ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 406 if (IS_ERR(ctx->gpio_reset)) { 407 dev_err(dev, "no reset GPIO pin provided\n"); 408 return PTR_ERR(ctx->gpio_reset); 409 } 410 411 ret = drm_of_find_panel_or_bridge(ctx->dev->of_node, 1, 0, &ctx->panel, 412 NULL); 413 if (ret && ret != -EPROBE_DEFER) 414 dev_err(dev, "cannot find panel (%d)\n", ret); 415 416 return ret; 417 } 418 419 static int tc358764_configure_regulators(struct tc358764 *ctx) 420 { 421 int i, ret; 422 423 for (i = 0; i < ARRAY_SIZE(ctx->supplies); ++i) 424 ctx->supplies[i].supply = tc358764_supplies[i]; 425 426 ret = devm_regulator_bulk_get(ctx->dev, ARRAY_SIZE(ctx->supplies), 427 ctx->supplies); 428 if (ret < 0) 429 dev_err(ctx->dev, "failed to get regulators: %d\n", ret); 430 431 return ret; 432 } 433 434 static int tc358764_probe(struct mipi_dsi_device *dsi) 435 { 436 struct device *dev = &dsi->dev; 437 struct tc358764 *ctx; 438 int ret; 439 440 ctx = devm_kzalloc(dev, sizeof(struct tc358764), GFP_KERNEL); 441 if (!ctx) 442 return -ENOMEM; 443 444 mipi_dsi_set_drvdata(dsi, ctx); 445 446 ctx->dev = dev; 447 448 dsi->lanes = 4; 449 dsi->format = MIPI_DSI_FMT_RGB888; 450 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST 451 | MIPI_DSI_MODE_VIDEO_AUTO_VERT | MIPI_DSI_MODE_LPM; 452 453 ret = tc358764_parse_dt(ctx); 454 if (ret < 0) 455 return ret; 456 457 ret = tc358764_configure_regulators(ctx); 458 if (ret < 0) 459 return ret; 460 461 ctx->bridge.funcs = &tc358764_bridge_funcs; 462 ctx->bridge.of_node = dev->of_node; 463 464 drm_bridge_add(&ctx->bridge); 465 466 ret = mipi_dsi_attach(dsi); 467 if (ret < 0) { 468 drm_bridge_remove(&ctx->bridge); 469 dev_err(dev, "failed to attach dsi\n"); 470 } 471 472 return ret; 473 } 474 475 static int tc358764_remove(struct mipi_dsi_device *dsi) 476 { 477 struct tc358764 *ctx = mipi_dsi_get_drvdata(dsi); 478 479 mipi_dsi_detach(dsi); 480 drm_bridge_remove(&ctx->bridge); 481 482 return 0; 483 } 484 485 static const struct of_device_id tc358764_of_match[] = { 486 { .compatible = "toshiba,tc358764" }, 487 { } 488 }; 489 MODULE_DEVICE_TABLE(of, tc358764_of_match); 490 491 static struct mipi_dsi_driver tc358764_driver = { 492 .probe = tc358764_probe, 493 .remove = tc358764_remove, 494 .driver = { 495 .name = "tc358764", 496 .owner = THIS_MODULE, 497 .of_match_table = tc358764_of_match, 498 }, 499 }; 500 module_mipi_dsi_driver(tc358764_driver); 501 502 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); 503 MODULE_AUTHOR("Maciej Purski <m.purski@samsung.com>"); 504 MODULE_DESCRIPTION("MIPI-DSI based Driver for TC358764 DSI/LVDS Bridge"); 505 MODULE_LICENSE("GPL v2"); 506