1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Samsung Electronics Co., Ltd 4 * 5 * Authors: 6 * Andrzej Hajda <a.hajda@samsung.com> 7 * Maciej Purski <m.purski@samsung.com> 8 */ 9 10 #include <drm/drm_atomic_helper.h> 11 #include <drm/drm_crtc.h> 12 #include <drm/drm_crtc_helper.h> 13 #include <drm/drm_fb_helper.h> 14 #include <drm/drm_mipi_dsi.h> 15 #include <drm/drm_of.h> 16 #include <drm/drm_panel.h> 17 #include <drm/drmP.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/of_graph.h> 20 #include <linux/regulator/consumer.h> 21 #include <video/mipi_display.h> 22 23 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) 24 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) 25 26 /* PPI layer registers */ 27 #define PPI_STARTPPI 0x0104 /* START control bit */ 28 #define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */ 29 #define PPI_LANEENABLE 0x0134 /* Enables each lane */ 30 #define PPI_TX_RX_TA 0x013C /* BTA timing parameters */ 31 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */ 32 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */ 33 #define PPI_D2S_CLRSIPOCOUNT 0x016C /* Assertion timer for Lane 2 */ 34 #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */ 35 #define PPI_START_FUNCTION 1 36 37 /* DSI layer registers */ 38 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */ 39 #define DSI_LANEENABLE 0x0210 /* Enables each lane */ 40 #define DSI_RX_START 1 41 42 /* Video path registers */ 43 #define VP_CTRL 0x0450 /* Video Path Control */ 44 #define VP_CTRL_MSF(v) FLD_VAL(v, 0, 0) /* Magic square in RGB666 */ 45 #define VP_CTRL_VTGEN(v) FLD_VAL(v, 4, 4) /* Use chip clock for timing */ 46 #define VP_CTRL_EVTMODE(v) FLD_VAL(v, 5, 5) /* Event mode */ 47 #define VP_CTRL_RGB888(v) FLD_VAL(v, 8, 8) /* RGB888 mode */ 48 #define VP_CTRL_VSDELAY(v) FLD_VAL(v, 31, 20) /* VSYNC delay */ 49 #define VP_CTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */ 50 #define VP_CTRL_DEPOL BIT(18) /* Polarity of DE signal */ 51 #define VP_CTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */ 52 #define VP_HTIM1 0x0454 /* Horizontal Timing Control 1 */ 53 #define VP_HTIM1_HBP(v) FLD_VAL(v, 24, 16) 54 #define VP_HTIM1_HSYNC(v) FLD_VAL(v, 8, 0) 55 #define VP_HTIM2 0x0458 /* Horizontal Timing Control 2 */ 56 #define VP_HTIM2_HFP(v) FLD_VAL(v, 24, 16) 57 #define VP_HTIM2_HACT(v) FLD_VAL(v, 10, 0) 58 #define VP_VTIM1 0x045C /* Vertical Timing Control 1 */ 59 #define VP_VTIM1_VBP(v) FLD_VAL(v, 23, 16) 60 #define VP_VTIM1_VSYNC(v) FLD_VAL(v, 7, 0) 61 #define VP_VTIM2 0x0460 /* Vertical Timing Control 2 */ 62 #define VP_VTIM2_VFP(v) FLD_VAL(v, 23, 16) 63 #define VP_VTIM2_VACT(v) FLD_VAL(v, 10, 0) 64 #define VP_VFUEN 0x0464 /* Video Frame Timing Update Enable */ 65 66 /* LVDS registers */ 67 #define LV_MX0003 0x0480 /* Mux input bit 0 to 3 */ 68 #define LV_MX0407 0x0484 /* Mux input bit 4 to 7 */ 69 #define LV_MX0811 0x0488 /* Mux input bit 8 to 11 */ 70 #define LV_MX1215 0x048C /* Mux input bit 12 to 15 */ 71 #define LV_MX1619 0x0490 /* Mux input bit 16 to 19 */ 72 #define LV_MX2023 0x0494 /* Mux input bit 20 to 23 */ 73 #define LV_MX2427 0x0498 /* Mux input bit 24 to 27 */ 74 #define LV_MX(b0, b1, b2, b3) (FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \ 75 FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24)) 76 77 /* Input bit numbers used in mux registers */ 78 enum { 79 LVI_R0, 80 LVI_R1, 81 LVI_R2, 82 LVI_R3, 83 LVI_R4, 84 LVI_R5, 85 LVI_R6, 86 LVI_R7, 87 LVI_G0, 88 LVI_G1, 89 LVI_G2, 90 LVI_G3, 91 LVI_G4, 92 LVI_G5, 93 LVI_G6, 94 LVI_G7, 95 LVI_B0, 96 LVI_B1, 97 LVI_B2, 98 LVI_B3, 99 LVI_B4, 100 LVI_B5, 101 LVI_B6, 102 LVI_B7, 103 LVI_HS, 104 LVI_VS, 105 LVI_DE, 106 LVI_L0 107 }; 108 109 #define LV_CFG 0x049C /* LVDS Configuration */ 110 #define LV_PHY0 0x04A0 /* LVDS PHY 0 */ 111 #define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */ 112 #define LV_PHY0_IS(v) FLD_VAL(v, 15, 14) 113 #define LV_PHY0_ND(v) FLD_VAL(v, 4, 0) /* Frequency range select */ 114 #define LV_PHY0_PRBS_ON(v) FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */ 115 116 /* System registers */ 117 #define SYS_RST 0x0504 /* System Reset */ 118 #define SYS_ID 0x0580 /* System ID */ 119 120 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */ 121 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */ 122 #define SYS_RST_LCD BIT(2) /* Reset LCD controller */ 123 #define SYS_RST_BM BIT(3) /* Reset Bus Management controller */ 124 #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */ 125 #define SYS_RST_REG BIT(5) /* Reset Register module */ 126 127 #define LPX_PERIOD 2 128 #define TTA_SURE 3 129 #define TTA_GET 0x20000 130 131 /* Lane enable PPI and DSI register bits */ 132 #define LANEENABLE_CLEN BIT(0) 133 #define LANEENABLE_L0EN BIT(1) 134 #define LANEENABLE_L1EN BIT(2) 135 #define LANEENABLE_L2EN BIT(3) 136 #define LANEENABLE_L3EN BIT(4) 137 138 /* LVCFG fields */ 139 #define LV_CFG_LVEN BIT(0) 140 #define LV_CFG_LVDLINK BIT(1) 141 #define LV_CFG_CLKPOL1 BIT(2) 142 #define LV_CFG_CLKPOL2 BIT(3) 143 144 static const char * const tc358764_supplies[] = { 145 "vddc", "vddio", "vddlvds" 146 }; 147 148 struct tc358764 { 149 struct device *dev; 150 struct drm_bridge bridge; 151 struct drm_connector connector; 152 struct regulator_bulk_data supplies[ARRAY_SIZE(tc358764_supplies)]; 153 struct gpio_desc *gpio_reset; 154 struct drm_panel *panel; 155 int error; 156 }; 157 158 static int tc358764_clear_error(struct tc358764 *ctx) 159 { 160 int ret = ctx->error; 161 162 ctx->error = 0; 163 return ret; 164 } 165 166 static void tc358764_read(struct tc358764 *ctx, u16 addr, u32 *val) 167 { 168 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 169 ssize_t ret; 170 171 if (ctx->error) 172 return; 173 174 cpu_to_le16s(&addr); 175 ret = mipi_dsi_generic_read(dsi, &addr, sizeof(addr), val, sizeof(*val)); 176 if (ret >= 0) 177 le32_to_cpus(val); 178 179 dev_dbg(ctx->dev, "read: %d, addr: %d\n", addr, *val); 180 } 181 182 static void tc358764_write(struct tc358764 *ctx, u16 addr, u32 val) 183 { 184 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 185 ssize_t ret; 186 u8 data[6]; 187 188 if (ctx->error) 189 return; 190 191 data[0] = addr; 192 data[1] = addr >> 8; 193 data[2] = val; 194 data[3] = val >> 8; 195 data[4] = val >> 16; 196 data[5] = val >> 24; 197 198 ret = mipi_dsi_generic_write(dsi, data, sizeof(data)); 199 if (ret < 0) 200 ctx->error = ret; 201 } 202 203 static inline struct tc358764 *bridge_to_tc358764(struct drm_bridge *bridge) 204 { 205 return container_of(bridge, struct tc358764, bridge); 206 } 207 208 static inline 209 struct tc358764 *connector_to_tc358764(struct drm_connector *connector) 210 { 211 return container_of(connector, struct tc358764, connector); 212 } 213 214 static int tc358764_init(struct tc358764 *ctx) 215 { 216 u32 v = 0; 217 218 tc358764_read(ctx, SYS_ID, &v); 219 if (ctx->error) 220 return tc358764_clear_error(ctx); 221 dev_info(ctx->dev, "ID: %#x\n", v); 222 223 /* configure PPI counters */ 224 tc358764_write(ctx, PPI_TX_RX_TA, TTA_GET | TTA_SURE); 225 tc358764_write(ctx, PPI_LPTXTIMECNT, LPX_PERIOD); 226 tc358764_write(ctx, PPI_D0S_CLRSIPOCOUNT, 5); 227 tc358764_write(ctx, PPI_D1S_CLRSIPOCOUNT, 5); 228 tc358764_write(ctx, PPI_D2S_CLRSIPOCOUNT, 5); 229 tc358764_write(ctx, PPI_D3S_CLRSIPOCOUNT, 5); 230 231 /* enable four data lanes and clock lane */ 232 tc358764_write(ctx, PPI_LANEENABLE, LANEENABLE_L3EN | LANEENABLE_L2EN | 233 LANEENABLE_L1EN | LANEENABLE_L0EN | LANEENABLE_CLEN); 234 tc358764_write(ctx, DSI_LANEENABLE, LANEENABLE_L3EN | LANEENABLE_L2EN | 235 LANEENABLE_L1EN | LANEENABLE_L0EN | LANEENABLE_CLEN); 236 237 /* start */ 238 tc358764_write(ctx, PPI_STARTPPI, PPI_START_FUNCTION); 239 tc358764_write(ctx, DSI_STARTDSI, DSI_RX_START); 240 241 /* configure video path */ 242 tc358764_write(ctx, VP_CTRL, VP_CTRL_VSDELAY(15) | VP_CTRL_RGB888(1) | 243 VP_CTRL_EVTMODE(1) | VP_CTRL_HSPOL | VP_CTRL_VSPOL); 244 245 /* reset PHY */ 246 tc358764_write(ctx, LV_PHY0, LV_PHY0_RST(1) | 247 LV_PHY0_PRBS_ON(4) | LV_PHY0_IS(2) | LV_PHY0_ND(6)); 248 tc358764_write(ctx, LV_PHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_IS(2) | 249 LV_PHY0_ND(6)); 250 251 /* reset bridge */ 252 tc358764_write(ctx, SYS_RST, SYS_RST_LCD); 253 254 /* set bit order */ 255 tc358764_write(ctx, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3)); 256 tc358764_write(ctx, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0)); 257 tc358764_write(ctx, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7)); 258 tc358764_write(ctx, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0)); 259 tc358764_write(ctx, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2)); 260 tc358764_write(ctx, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0)); 261 tc358764_write(ctx, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6)); 262 tc358764_write(ctx, LV_CFG, LV_CFG_CLKPOL2 | LV_CFG_CLKPOL1 | 263 LV_CFG_LVEN); 264 265 return tc358764_clear_error(ctx); 266 } 267 268 static void tc358764_reset(struct tc358764 *ctx) 269 { 270 gpiod_set_value(ctx->gpio_reset, 1); 271 usleep_range(1000, 2000); 272 gpiod_set_value(ctx->gpio_reset, 0); 273 usleep_range(1000, 2000); 274 } 275 276 static int tc358764_get_modes(struct drm_connector *connector) 277 { 278 struct tc358764 *ctx = connector_to_tc358764(connector); 279 280 return drm_panel_get_modes(ctx->panel); 281 } 282 283 static const 284 struct drm_connector_helper_funcs tc358764_connector_helper_funcs = { 285 .get_modes = tc358764_get_modes, 286 }; 287 288 static const struct drm_connector_funcs tc358764_connector_funcs = { 289 .fill_modes = drm_helper_probe_single_connector_modes, 290 .destroy = drm_connector_cleanup, 291 .reset = drm_atomic_helper_connector_reset, 292 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 293 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 294 }; 295 296 static void tc358764_disable(struct drm_bridge *bridge) 297 { 298 struct tc358764 *ctx = bridge_to_tc358764(bridge); 299 int ret = drm_panel_disable(bridge_to_tc358764(bridge)->panel); 300 301 if (ret < 0) 302 dev_err(ctx->dev, "error disabling panel (%d)\n", ret); 303 } 304 305 static void tc358764_post_disable(struct drm_bridge *bridge) 306 { 307 struct tc358764 *ctx = bridge_to_tc358764(bridge); 308 int ret; 309 310 ret = drm_panel_unprepare(ctx->panel); 311 if (ret < 0) 312 dev_err(ctx->dev, "error unpreparing panel (%d)\n", ret); 313 tc358764_reset(ctx); 314 usleep_range(10000, 15000); 315 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 316 if (ret < 0) 317 dev_err(ctx->dev, "error disabling regulators (%d)\n", ret); 318 } 319 320 static void tc358764_pre_enable(struct drm_bridge *bridge) 321 { 322 struct tc358764 *ctx = bridge_to_tc358764(bridge); 323 int ret; 324 325 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 326 if (ret < 0) 327 dev_err(ctx->dev, "error enabling regulators (%d)\n", ret); 328 usleep_range(10000, 15000); 329 tc358764_reset(ctx); 330 ret = tc358764_init(ctx); 331 if (ret < 0) 332 dev_err(ctx->dev, "error initializing bridge (%d)\n", ret); 333 ret = drm_panel_prepare(ctx->panel); 334 if (ret < 0) 335 dev_err(ctx->dev, "error preparing panel (%d)\n", ret); 336 } 337 338 static void tc358764_enable(struct drm_bridge *bridge) 339 { 340 struct tc358764 *ctx = bridge_to_tc358764(bridge); 341 int ret = drm_panel_enable(ctx->panel); 342 343 if (ret < 0) 344 dev_err(ctx->dev, "error enabling panel (%d)\n", ret); 345 } 346 347 static int tc358764_attach(struct drm_bridge *bridge) 348 { 349 struct tc358764 *ctx = bridge_to_tc358764(bridge); 350 struct drm_device *drm = bridge->dev; 351 int ret; 352 353 ctx->connector.polled = DRM_CONNECTOR_POLL_HPD; 354 ret = drm_connector_init(drm, &ctx->connector, 355 &tc358764_connector_funcs, 356 DRM_MODE_CONNECTOR_LVDS); 357 if (ret) { 358 DRM_ERROR("Failed to initialize connector\n"); 359 return ret; 360 } 361 362 drm_connector_helper_add(&ctx->connector, 363 &tc358764_connector_helper_funcs); 364 drm_connector_attach_encoder(&ctx->connector, bridge->encoder); 365 drm_panel_attach(ctx->panel, &ctx->connector); 366 ctx->connector.funcs->reset(&ctx->connector); 367 drm_fb_helper_add_one_connector(drm->fb_helper, &ctx->connector); 368 drm_connector_register(&ctx->connector); 369 370 return 0; 371 } 372 373 static void tc358764_detach(struct drm_bridge *bridge) 374 { 375 struct tc358764 *ctx = bridge_to_tc358764(bridge); 376 struct drm_device *drm = bridge->dev; 377 378 drm_connector_unregister(&ctx->connector); 379 drm_fb_helper_remove_one_connector(drm->fb_helper, &ctx->connector); 380 drm_panel_detach(ctx->panel); 381 ctx->panel = NULL; 382 drm_connector_put(&ctx->connector); 383 } 384 385 static const struct drm_bridge_funcs tc358764_bridge_funcs = { 386 .disable = tc358764_disable, 387 .post_disable = tc358764_post_disable, 388 .enable = tc358764_enable, 389 .pre_enable = tc358764_pre_enable, 390 .attach = tc358764_attach, 391 .detach = tc358764_detach, 392 }; 393 394 static int tc358764_parse_dt(struct tc358764 *ctx) 395 { 396 struct device *dev = ctx->dev; 397 int ret; 398 399 ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 400 if (IS_ERR(ctx->gpio_reset)) { 401 dev_err(dev, "no reset GPIO pin provided\n"); 402 return PTR_ERR(ctx->gpio_reset); 403 } 404 405 ret = drm_of_find_panel_or_bridge(ctx->dev->of_node, 1, 0, &ctx->panel, 406 NULL); 407 if (ret && ret != -EPROBE_DEFER) 408 dev_err(dev, "cannot find panel (%d)\n", ret); 409 410 return ret; 411 } 412 413 static int tc358764_configure_regulators(struct tc358764 *ctx) 414 { 415 int i, ret; 416 417 for (i = 0; i < ARRAY_SIZE(ctx->supplies); ++i) 418 ctx->supplies[i].supply = tc358764_supplies[i]; 419 420 ret = devm_regulator_bulk_get(ctx->dev, ARRAY_SIZE(ctx->supplies), 421 ctx->supplies); 422 if (ret < 0) 423 dev_err(ctx->dev, "failed to get regulators: %d\n", ret); 424 425 return ret; 426 } 427 428 static int tc358764_probe(struct mipi_dsi_device *dsi) 429 { 430 struct device *dev = &dsi->dev; 431 struct tc358764 *ctx; 432 int ret; 433 434 ctx = devm_kzalloc(dev, sizeof(struct tc358764), GFP_KERNEL); 435 if (!ctx) 436 return -ENOMEM; 437 438 mipi_dsi_set_drvdata(dsi, ctx); 439 440 ctx->dev = dev; 441 442 dsi->lanes = 4; 443 dsi->format = MIPI_DSI_FMT_RGB888; 444 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST 445 | MIPI_DSI_MODE_VIDEO_AUTO_VERT | MIPI_DSI_MODE_LPM; 446 447 ret = tc358764_parse_dt(ctx); 448 if (ret < 0) 449 return ret; 450 451 ret = tc358764_configure_regulators(ctx); 452 if (ret < 0) 453 return ret; 454 455 ctx->bridge.funcs = &tc358764_bridge_funcs; 456 ctx->bridge.of_node = dev->of_node; 457 458 drm_bridge_add(&ctx->bridge); 459 460 ret = mipi_dsi_attach(dsi); 461 if (ret < 0) { 462 drm_bridge_remove(&ctx->bridge); 463 dev_err(dev, "failed to attach dsi\n"); 464 } 465 466 return ret; 467 } 468 469 static int tc358764_remove(struct mipi_dsi_device *dsi) 470 { 471 struct tc358764 *ctx = mipi_dsi_get_drvdata(dsi); 472 473 mipi_dsi_detach(dsi); 474 drm_bridge_remove(&ctx->bridge); 475 476 return 0; 477 } 478 479 static const struct of_device_id tc358764_of_match[] = { 480 { .compatible = "toshiba,tc358764" }, 481 { } 482 }; 483 MODULE_DEVICE_TABLE(of, tc358764_of_match); 484 485 static struct mipi_dsi_driver tc358764_driver = { 486 .probe = tc358764_probe, 487 .remove = tc358764_remove, 488 .driver = { 489 .name = "tc358764", 490 .owner = THIS_MODULE, 491 .of_match_table = tc358764_of_match, 492 }, 493 }; 494 module_mipi_dsi_driver(tc358764_driver); 495 496 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); 497 MODULE_AUTHOR("Maciej Purski <m.purski@samsung.com>"); 498 MODULE_DESCRIPTION("MIPI-DSI based Driver for TC358764 DSI/LVDS Bridge"); 499 MODULE_LICENSE("GPL v2"); 500