1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Samsung Electronics Co., Ltd 4 * 5 * Authors: 6 * Andrzej Hajda <a.hajda@samsung.com> 7 * Maciej Purski <m.purski@samsung.com> 8 */ 9 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/module.h> 13 #include <linux/of_graph.h> 14 #include <linux/regulator/consumer.h> 15 16 #include <video/mipi_display.h> 17 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_mipi_dsi.h> 20 #include <drm/drm_of.h> 21 #include <drm/drm_print.h> 22 23 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) 24 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) 25 26 /* PPI layer registers */ 27 #define PPI_STARTPPI 0x0104 /* START control bit */ 28 #define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */ 29 #define PPI_LANEENABLE 0x0134 /* Enables each lane */ 30 #define PPI_TX_RX_TA 0x013C /* BTA timing parameters */ 31 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */ 32 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */ 33 #define PPI_D2S_CLRSIPOCOUNT 0x016C /* Assertion timer for Lane 2 */ 34 #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */ 35 #define PPI_START_FUNCTION 1 36 37 /* DSI layer registers */ 38 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */ 39 #define DSI_LANEENABLE 0x0210 /* Enables each lane */ 40 #define DSI_RX_START 1 41 42 /* Video path registers */ 43 #define VP_CTRL 0x0450 /* Video Path Control */ 44 #define VP_CTRL_MSF(v) FLD_VAL(v, 0, 0) /* Magic square in RGB666 */ 45 #define VP_CTRL_VTGEN(v) FLD_VAL(v, 4, 4) /* Use chip clock for timing */ 46 #define VP_CTRL_EVTMODE(v) FLD_VAL(v, 5, 5) /* Event mode */ 47 #define VP_CTRL_RGB888(v) FLD_VAL(v, 8, 8) /* RGB888 mode */ 48 #define VP_CTRL_VSDELAY(v) FLD_VAL(v, 31, 20) /* VSYNC delay */ 49 #define VP_CTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */ 50 #define VP_CTRL_DEPOL BIT(18) /* Polarity of DE signal */ 51 #define VP_CTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */ 52 #define VP_HTIM1 0x0454 /* Horizontal Timing Control 1 */ 53 #define VP_HTIM1_HBP(v) FLD_VAL(v, 24, 16) 54 #define VP_HTIM1_HSYNC(v) FLD_VAL(v, 8, 0) 55 #define VP_HTIM2 0x0458 /* Horizontal Timing Control 2 */ 56 #define VP_HTIM2_HFP(v) FLD_VAL(v, 24, 16) 57 #define VP_HTIM2_HACT(v) FLD_VAL(v, 10, 0) 58 #define VP_VTIM1 0x045C /* Vertical Timing Control 1 */ 59 #define VP_VTIM1_VBP(v) FLD_VAL(v, 23, 16) 60 #define VP_VTIM1_VSYNC(v) FLD_VAL(v, 7, 0) 61 #define VP_VTIM2 0x0460 /* Vertical Timing Control 2 */ 62 #define VP_VTIM2_VFP(v) FLD_VAL(v, 23, 16) 63 #define VP_VTIM2_VACT(v) FLD_VAL(v, 10, 0) 64 #define VP_VFUEN 0x0464 /* Video Frame Timing Update Enable */ 65 66 /* LVDS registers */ 67 #define LV_MX0003 0x0480 /* Mux input bit 0 to 3 */ 68 #define LV_MX0407 0x0484 /* Mux input bit 4 to 7 */ 69 #define LV_MX0811 0x0488 /* Mux input bit 8 to 11 */ 70 #define LV_MX1215 0x048C /* Mux input bit 12 to 15 */ 71 #define LV_MX1619 0x0490 /* Mux input bit 16 to 19 */ 72 #define LV_MX2023 0x0494 /* Mux input bit 20 to 23 */ 73 #define LV_MX2427 0x0498 /* Mux input bit 24 to 27 */ 74 #define LV_MX(b0, b1, b2, b3) (FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \ 75 FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24)) 76 77 /* Input bit numbers used in mux registers */ 78 enum { 79 LVI_R0, 80 LVI_R1, 81 LVI_R2, 82 LVI_R3, 83 LVI_R4, 84 LVI_R5, 85 LVI_R6, 86 LVI_R7, 87 LVI_G0, 88 LVI_G1, 89 LVI_G2, 90 LVI_G3, 91 LVI_G4, 92 LVI_G5, 93 LVI_G6, 94 LVI_G7, 95 LVI_B0, 96 LVI_B1, 97 LVI_B2, 98 LVI_B3, 99 LVI_B4, 100 LVI_B5, 101 LVI_B6, 102 LVI_B7, 103 LVI_HS, 104 LVI_VS, 105 LVI_DE, 106 LVI_L0 107 }; 108 109 #define LV_CFG 0x049C /* LVDS Configuration */ 110 #define LV_PHY0 0x04A0 /* LVDS PHY 0 */ 111 #define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */ 112 #define LV_PHY0_IS(v) FLD_VAL(v, 15, 14) 113 #define LV_PHY0_ND(v) FLD_VAL(v, 4, 0) /* Frequency range select */ 114 #define LV_PHY0_PRBS_ON(v) FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */ 115 116 /* System registers */ 117 #define SYS_RST 0x0504 /* System Reset */ 118 #define SYS_ID 0x0580 /* System ID */ 119 120 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */ 121 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */ 122 #define SYS_RST_LCD BIT(2) /* Reset LCD controller */ 123 #define SYS_RST_BM BIT(3) /* Reset Bus Management controller */ 124 #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */ 125 #define SYS_RST_REG BIT(5) /* Reset Register module */ 126 127 #define LPX_PERIOD 2 128 #define TTA_SURE 3 129 #define TTA_GET 0x20000 130 131 /* Lane enable PPI and DSI register bits */ 132 #define LANEENABLE_CLEN BIT(0) 133 #define LANEENABLE_L0EN BIT(1) 134 #define LANEENABLE_L1EN BIT(2) 135 #define LANEENABLE_L2EN BIT(3) 136 #define LANEENABLE_L3EN BIT(4) 137 138 /* LVCFG fields */ 139 #define LV_CFG_LVEN BIT(0) 140 #define LV_CFG_LVDLINK BIT(1) 141 #define LV_CFG_CLKPOL1 BIT(2) 142 #define LV_CFG_CLKPOL2 BIT(3) 143 144 static const char * const tc358764_supplies[] = { 145 "vddc", "vddio", "vddlvds" 146 }; 147 148 struct tc358764 { 149 struct device *dev; 150 struct drm_bridge bridge; 151 struct drm_bridge *next_bridge; 152 struct regulator_bulk_data supplies[ARRAY_SIZE(tc358764_supplies)]; 153 struct gpio_desc *gpio_reset; 154 int error; 155 }; 156 157 static int tc358764_clear_error(struct tc358764 *ctx) 158 { 159 int ret = ctx->error; 160 161 ctx->error = 0; 162 return ret; 163 } 164 165 static void tc358764_read(struct tc358764 *ctx, u16 addr, u32 *val) 166 { 167 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 168 ssize_t ret; 169 170 if (ctx->error) 171 return; 172 173 cpu_to_le16s(&addr); 174 ret = mipi_dsi_generic_read(dsi, &addr, sizeof(addr), val, sizeof(*val)); 175 if (ret >= 0) 176 le32_to_cpus(val); 177 178 dev_dbg(ctx->dev, "read: %d, addr: %d\n", addr, *val); 179 } 180 181 static void tc358764_write(struct tc358764 *ctx, u16 addr, u32 val) 182 { 183 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 184 ssize_t ret; 185 u8 data[6]; 186 187 if (ctx->error) 188 return; 189 190 data[0] = addr; 191 data[1] = addr >> 8; 192 data[2] = val; 193 data[3] = val >> 8; 194 data[4] = val >> 16; 195 data[5] = val >> 24; 196 197 ret = mipi_dsi_generic_write(dsi, data, sizeof(data)); 198 if (ret < 0) 199 ctx->error = ret; 200 } 201 202 static inline struct tc358764 *bridge_to_tc358764(struct drm_bridge *bridge) 203 { 204 return container_of(bridge, struct tc358764, bridge); 205 } 206 207 static int tc358764_init(struct tc358764 *ctx) 208 { 209 u32 v = 0; 210 211 tc358764_read(ctx, SYS_ID, &v); 212 if (ctx->error) 213 return tc358764_clear_error(ctx); 214 dev_info(ctx->dev, "ID: %#x\n", v); 215 216 /* configure PPI counters */ 217 tc358764_write(ctx, PPI_TX_RX_TA, TTA_GET | TTA_SURE); 218 tc358764_write(ctx, PPI_LPTXTIMECNT, LPX_PERIOD); 219 tc358764_write(ctx, PPI_D0S_CLRSIPOCOUNT, 5); 220 tc358764_write(ctx, PPI_D1S_CLRSIPOCOUNT, 5); 221 tc358764_write(ctx, PPI_D2S_CLRSIPOCOUNT, 5); 222 tc358764_write(ctx, PPI_D3S_CLRSIPOCOUNT, 5); 223 224 /* enable four data lanes and clock lane */ 225 tc358764_write(ctx, PPI_LANEENABLE, LANEENABLE_L3EN | LANEENABLE_L2EN | 226 LANEENABLE_L1EN | LANEENABLE_L0EN | LANEENABLE_CLEN); 227 tc358764_write(ctx, DSI_LANEENABLE, LANEENABLE_L3EN | LANEENABLE_L2EN | 228 LANEENABLE_L1EN | LANEENABLE_L0EN | LANEENABLE_CLEN); 229 230 /* start */ 231 tc358764_write(ctx, PPI_STARTPPI, PPI_START_FUNCTION); 232 tc358764_write(ctx, DSI_STARTDSI, DSI_RX_START); 233 234 /* configure video path */ 235 tc358764_write(ctx, VP_CTRL, VP_CTRL_VSDELAY(15) | VP_CTRL_RGB888(1) | 236 VP_CTRL_EVTMODE(1) | VP_CTRL_HSPOL | VP_CTRL_VSPOL); 237 238 /* reset PHY */ 239 tc358764_write(ctx, LV_PHY0, LV_PHY0_RST(1) | 240 LV_PHY0_PRBS_ON(4) | LV_PHY0_IS(2) | LV_PHY0_ND(6)); 241 tc358764_write(ctx, LV_PHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_IS(2) | 242 LV_PHY0_ND(6)); 243 244 /* reset bridge */ 245 tc358764_write(ctx, SYS_RST, SYS_RST_LCD); 246 247 /* set bit order */ 248 tc358764_write(ctx, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3)); 249 tc358764_write(ctx, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0)); 250 tc358764_write(ctx, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7)); 251 tc358764_write(ctx, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0)); 252 tc358764_write(ctx, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2)); 253 tc358764_write(ctx, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0)); 254 tc358764_write(ctx, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6)); 255 tc358764_write(ctx, LV_CFG, LV_CFG_CLKPOL2 | LV_CFG_CLKPOL1 | 256 LV_CFG_LVEN); 257 258 return tc358764_clear_error(ctx); 259 } 260 261 static void tc358764_reset(struct tc358764 *ctx) 262 { 263 gpiod_set_value(ctx->gpio_reset, 1); 264 usleep_range(1000, 2000); 265 gpiod_set_value(ctx->gpio_reset, 0); 266 usleep_range(1000, 2000); 267 } 268 269 static void tc358764_post_disable(struct drm_bridge *bridge) 270 { 271 struct tc358764 *ctx = bridge_to_tc358764(bridge); 272 int ret; 273 274 tc358764_reset(ctx); 275 usleep_range(10000, 15000); 276 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 277 if (ret < 0) 278 dev_err(ctx->dev, "error disabling regulators (%d)\n", ret); 279 } 280 281 static void tc358764_pre_enable(struct drm_bridge *bridge) 282 { 283 struct tc358764 *ctx = bridge_to_tc358764(bridge); 284 int ret; 285 286 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 287 if (ret < 0) 288 dev_err(ctx->dev, "error enabling regulators (%d)\n", ret); 289 usleep_range(10000, 15000); 290 tc358764_reset(ctx); 291 ret = tc358764_init(ctx); 292 if (ret < 0) 293 dev_err(ctx->dev, "error initializing bridge (%d)\n", ret); 294 } 295 296 static int tc358764_attach(struct drm_bridge *bridge, 297 enum drm_bridge_attach_flags flags) 298 { 299 struct tc358764 *ctx = bridge_to_tc358764(bridge); 300 301 return drm_bridge_attach(bridge->encoder, ctx->next_bridge, bridge, flags); 302 } 303 304 static const struct drm_bridge_funcs tc358764_bridge_funcs = { 305 .post_disable = tc358764_post_disable, 306 .pre_enable = tc358764_pre_enable, 307 .attach = tc358764_attach, 308 }; 309 310 static int tc358764_parse_dt(struct tc358764 *ctx) 311 { 312 struct device *dev = ctx->dev; 313 314 ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 315 if (IS_ERR(ctx->gpio_reset)) { 316 dev_err(dev, "no reset GPIO pin provided\n"); 317 return PTR_ERR(ctx->gpio_reset); 318 } 319 320 ctx->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0); 321 if (IS_ERR(ctx->next_bridge)) 322 return PTR_ERR(ctx->next_bridge); 323 324 return 0; 325 } 326 327 static int tc358764_configure_regulators(struct tc358764 *ctx) 328 { 329 int i, ret; 330 331 for (i = 0; i < ARRAY_SIZE(ctx->supplies); ++i) 332 ctx->supplies[i].supply = tc358764_supplies[i]; 333 334 ret = devm_regulator_bulk_get(ctx->dev, ARRAY_SIZE(ctx->supplies), 335 ctx->supplies); 336 if (ret < 0) 337 dev_err(ctx->dev, "failed to get regulators: %d\n", ret); 338 339 return ret; 340 } 341 342 static int tc358764_probe(struct mipi_dsi_device *dsi) 343 { 344 struct device *dev = &dsi->dev; 345 struct tc358764 *ctx; 346 int ret; 347 348 ctx = devm_kzalloc(dev, sizeof(struct tc358764), GFP_KERNEL); 349 if (!ctx) 350 return -ENOMEM; 351 352 mipi_dsi_set_drvdata(dsi, ctx); 353 354 ctx->dev = dev; 355 356 dsi->lanes = 4; 357 dsi->format = MIPI_DSI_FMT_RGB888; 358 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST 359 | MIPI_DSI_MODE_VIDEO_AUTO_VERT | MIPI_DSI_MODE_LPM; 360 361 ret = tc358764_parse_dt(ctx); 362 if (ret < 0) 363 return ret; 364 365 ret = tc358764_configure_regulators(ctx); 366 if (ret < 0) 367 return ret; 368 369 ctx->bridge.funcs = &tc358764_bridge_funcs; 370 ctx->bridge.of_node = dev->of_node; 371 372 drm_bridge_add(&ctx->bridge); 373 374 ret = mipi_dsi_attach(dsi); 375 if (ret < 0) { 376 drm_bridge_remove(&ctx->bridge); 377 dev_err(dev, "failed to attach dsi\n"); 378 } 379 380 return ret; 381 } 382 383 static int tc358764_remove(struct mipi_dsi_device *dsi) 384 { 385 struct tc358764 *ctx = mipi_dsi_get_drvdata(dsi); 386 387 mipi_dsi_detach(dsi); 388 drm_bridge_remove(&ctx->bridge); 389 390 return 0; 391 } 392 393 static const struct of_device_id tc358764_of_match[] = { 394 { .compatible = "toshiba,tc358764" }, 395 { } 396 }; 397 MODULE_DEVICE_TABLE(of, tc358764_of_match); 398 399 static struct mipi_dsi_driver tc358764_driver = { 400 .probe = tc358764_probe, 401 .remove = tc358764_remove, 402 .driver = { 403 .name = "tc358764", 404 .owner = THIS_MODULE, 405 .of_match_table = tc358764_of_match, 406 }, 407 }; 408 module_mipi_dsi_driver(tc358764_driver); 409 410 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); 411 MODULE_AUTHOR("Maciej Purski <m.purski@samsung.com>"); 412 MODULE_DESCRIPTION("MIPI-DSI based Driver for TC358764 DSI/LVDS Bridge"); 413 MODULE_LICENSE("GPL v2"); 414