1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd 4 * Copyright (C) STMicroelectronics SA 2017 5 * 6 * Modified by Philippe Cornu <philippe.cornu@st.com> 7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the 8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs. 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/debugfs.h> 14 #include <linux/iopoll.h> 15 #include <linux/module.h> 16 #include <linux/of_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/reset.h> 19 20 #include <video/mipi_display.h> 21 22 #include <drm/bridge/dw_mipi_dsi.h> 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_crtc.h> 26 #include <drm/drm_mipi_dsi.h> 27 #include <drm/drm_modes.h> 28 #include <drm/drm_of.h> 29 #include <drm/drm_print.h> 30 31 #define HWVER_131 0x31333100 /* IP version 1.31 */ 32 33 #define DSI_VERSION 0x00 34 #define VERSION GENMASK(31, 8) 35 36 #define DSI_PWR_UP 0x04 37 #define RESET 0 38 #define POWERUP BIT(0) 39 40 #define DSI_CLKMGR_CFG 0x08 41 #define TO_CLK_DIVISION(div) (((div) & 0xff) << 8) 42 #define TX_ESC_CLK_DIVISION(div) ((div) & 0xff) 43 44 #define DSI_DPI_VCID 0x0c 45 #define DPI_VCID(vcid) ((vcid) & 0x3) 46 47 #define DSI_DPI_COLOR_CODING 0x10 48 #define LOOSELY18_EN BIT(8) 49 #define DPI_COLOR_CODING_16BIT_1 0x0 50 #define DPI_COLOR_CODING_16BIT_2 0x1 51 #define DPI_COLOR_CODING_16BIT_3 0x2 52 #define DPI_COLOR_CODING_18BIT_1 0x3 53 #define DPI_COLOR_CODING_18BIT_2 0x4 54 #define DPI_COLOR_CODING_24BIT 0x5 55 56 #define DSI_DPI_CFG_POL 0x14 57 #define COLORM_ACTIVE_LOW BIT(4) 58 #define SHUTD_ACTIVE_LOW BIT(3) 59 #define HSYNC_ACTIVE_LOW BIT(2) 60 #define VSYNC_ACTIVE_LOW BIT(1) 61 #define DATAEN_ACTIVE_LOW BIT(0) 62 63 #define DSI_DPI_LP_CMD_TIM 0x18 64 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) 65 #define INVACT_LPCMD_TIME(p) ((p) & 0xff) 66 67 #define DSI_DBI_VCID 0x1c 68 #define DSI_DBI_CFG 0x20 69 #define DSI_DBI_PARTITIONING_EN 0x24 70 #define DSI_DBI_CMDSIZE 0x28 71 72 #define DSI_PCKHDL_CFG 0x2c 73 #define CRC_RX_EN BIT(4) 74 #define ECC_RX_EN BIT(3) 75 #define BTA_EN BIT(2) 76 #define EOTP_RX_EN BIT(1) 77 #define EOTP_TX_EN BIT(0) 78 79 #define DSI_GEN_VCID 0x30 80 81 #define DSI_MODE_CFG 0x34 82 #define ENABLE_VIDEO_MODE 0 83 #define ENABLE_CMD_MODE BIT(0) 84 85 #define DSI_VID_MODE_CFG 0x38 86 #define ENABLE_LOW_POWER (0x3f << 8) 87 #define ENABLE_LOW_POWER_MASK (0x3f << 8) 88 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0 89 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1 90 #define VID_MODE_TYPE_BURST 0x2 91 #define VID_MODE_TYPE_MASK 0x3 92 #define ENABLE_LOW_POWER_CMD BIT(15) 93 #define VID_MODE_VPG_ENABLE BIT(16) 94 #define VID_MODE_VPG_MODE BIT(20) 95 #define VID_MODE_VPG_HORIZONTAL BIT(24) 96 97 #define DSI_VID_PKT_SIZE 0x3c 98 #define VID_PKT_SIZE(p) ((p) & 0x3fff) 99 100 #define DSI_VID_NUM_CHUNKS 0x40 101 #define VID_NUM_CHUNKS(c) ((c) & 0x1fff) 102 103 #define DSI_VID_NULL_SIZE 0x44 104 #define VID_NULL_SIZE(b) ((b) & 0x1fff) 105 106 #define DSI_VID_HSA_TIME 0x48 107 #define DSI_VID_HBP_TIME 0x4c 108 #define DSI_VID_HLINE_TIME 0x50 109 #define DSI_VID_VSA_LINES 0x54 110 #define DSI_VID_VBP_LINES 0x58 111 #define DSI_VID_VFP_LINES 0x5c 112 #define DSI_VID_VACTIVE_LINES 0x60 113 #define DSI_EDPI_CMD_SIZE 0x64 114 115 #define DSI_CMD_MODE_CFG 0x68 116 #define MAX_RD_PKT_SIZE_LP BIT(24) 117 #define DCS_LW_TX_LP BIT(19) 118 #define DCS_SR_0P_TX_LP BIT(18) 119 #define DCS_SW_1P_TX_LP BIT(17) 120 #define DCS_SW_0P_TX_LP BIT(16) 121 #define GEN_LW_TX_LP BIT(14) 122 #define GEN_SR_2P_TX_LP BIT(13) 123 #define GEN_SR_1P_TX_LP BIT(12) 124 #define GEN_SR_0P_TX_LP BIT(11) 125 #define GEN_SW_2P_TX_LP BIT(10) 126 #define GEN_SW_1P_TX_LP BIT(9) 127 #define GEN_SW_0P_TX_LP BIT(8) 128 #define ACK_RQST_EN BIT(1) 129 #define TEAR_FX_EN BIT(0) 130 131 #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \ 132 DCS_LW_TX_LP | \ 133 DCS_SR_0P_TX_LP | \ 134 DCS_SW_1P_TX_LP | \ 135 DCS_SW_0P_TX_LP | \ 136 GEN_LW_TX_LP | \ 137 GEN_SR_2P_TX_LP | \ 138 GEN_SR_1P_TX_LP | \ 139 GEN_SR_0P_TX_LP | \ 140 GEN_SW_2P_TX_LP | \ 141 GEN_SW_1P_TX_LP | \ 142 GEN_SW_0P_TX_LP) 143 144 #define DSI_GEN_HDR 0x6c 145 #define DSI_GEN_PLD_DATA 0x70 146 147 #define DSI_CMD_PKT_STATUS 0x74 148 #define GEN_RD_CMD_BUSY BIT(6) 149 #define GEN_PLD_R_FULL BIT(5) 150 #define GEN_PLD_R_EMPTY BIT(4) 151 #define GEN_PLD_W_FULL BIT(3) 152 #define GEN_PLD_W_EMPTY BIT(2) 153 #define GEN_CMD_FULL BIT(1) 154 #define GEN_CMD_EMPTY BIT(0) 155 156 #define DSI_TO_CNT_CFG 0x78 157 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16) 158 #define LPRX_TO_CNT(p) ((p) & 0xffff) 159 160 #define DSI_HS_RD_TO_CNT 0x7c 161 #define DSI_LP_RD_TO_CNT 0x80 162 #define DSI_HS_WR_TO_CNT 0x84 163 #define DSI_LP_WR_TO_CNT 0x88 164 #define DSI_BTA_TO_CNT 0x8c 165 166 #define DSI_LPCLK_CTRL 0x94 167 #define AUTO_CLKLANE_CTRL BIT(1) 168 #define PHY_TXREQUESTCLKHS BIT(0) 169 170 #define DSI_PHY_TMR_LPCLK_CFG 0x98 171 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16) 172 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff) 173 174 #define DSI_PHY_TMR_CFG 0x9c 175 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24) 176 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16) 177 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) 178 #define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16) 179 #define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff) 180 181 #define DSI_PHY_RSTZ 0xa0 182 #define PHY_DISFORCEPLL 0 183 #define PHY_ENFORCEPLL BIT(3) 184 #define PHY_DISABLECLK 0 185 #define PHY_ENABLECLK BIT(2) 186 #define PHY_RSTZ 0 187 #define PHY_UNRSTZ BIT(1) 188 #define PHY_SHUTDOWNZ 0 189 #define PHY_UNSHUTDOWNZ BIT(0) 190 191 #define DSI_PHY_IF_CFG 0xa4 192 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 193 #define N_LANES(n) (((n) - 1) & 0x3) 194 195 #define DSI_PHY_ULPS_CTRL 0xa8 196 #define DSI_PHY_TX_TRIGGERS 0xac 197 198 #define DSI_PHY_STATUS 0xb0 199 #define PHY_STOP_STATE_CLK_LANE BIT(2) 200 #define PHY_LOCK BIT(0) 201 202 #define DSI_PHY_TST_CTRL0 0xb4 203 #define PHY_TESTCLK BIT(1) 204 #define PHY_UNTESTCLK 0 205 #define PHY_TESTCLR BIT(0) 206 #define PHY_UNTESTCLR 0 207 208 #define DSI_PHY_TST_CTRL1 0xb8 209 #define PHY_TESTEN BIT(16) 210 #define PHY_UNTESTEN 0 211 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 212 #define PHY_TESTDIN(n) ((n) & 0xff) 213 214 #define DSI_INT_ST0 0xbc 215 #define DSI_INT_ST1 0xc0 216 #define DSI_INT_MSK0 0xc4 217 #define DSI_INT_MSK1 0xc8 218 219 #define DSI_PHY_TMR_RD_CFG 0xf4 220 #define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff) 221 222 #define PHY_STATUS_TIMEOUT_US 10000 223 #define CMD_PKT_STATUS_TIMEOUT_US 20000 224 225 #ifdef CONFIG_DEBUG_FS 226 #define VPG_DEFS(name, dsi) \ 227 ((void __force *)&((*dsi).vpg_defs.name)) 228 229 #define REGISTER(name, mask, dsi) \ 230 { #name, VPG_DEFS(name, dsi), mask, dsi } 231 232 struct debugfs_entries { 233 const char *name; 234 bool *reg; 235 u32 mask; 236 struct dw_mipi_dsi *dsi; 237 }; 238 #endif /* CONFIG_DEBUG_FS */ 239 240 struct dw_mipi_dsi { 241 struct drm_bridge bridge; 242 struct mipi_dsi_host dsi_host; 243 struct drm_bridge *panel_bridge; 244 struct device *dev; 245 void __iomem *base; 246 247 struct clk *pclk; 248 249 unsigned int lane_mbps; /* per lane */ 250 u32 channel; 251 u32 lanes; 252 u32 format; 253 unsigned long mode_flags; 254 255 #ifdef CONFIG_DEBUG_FS 256 struct dentry *debugfs; 257 struct debugfs_entries *debugfs_vpg; 258 struct { 259 bool vpg; 260 bool vpg_horizontal; 261 bool vpg_ber_pattern; 262 } vpg_defs; 263 #endif /* CONFIG_DEBUG_FS */ 264 265 struct dw_mipi_dsi *master; /* dual-dsi master ptr */ 266 struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */ 267 268 const struct dw_mipi_dsi_plat_data *plat_data; 269 }; 270 271 /* 272 * Check if either a link to a master or slave is present 273 */ 274 static inline bool dw_mipi_is_dual_mode(struct dw_mipi_dsi *dsi) 275 { 276 return dsi->slave || dsi->master; 277 } 278 279 /* 280 * The controller should generate 2 frames before 281 * preparing the peripheral. 282 */ 283 static void dw_mipi_dsi_wait_for_two_frames(const struct drm_display_mode *mode) 284 { 285 int refresh, two_frames; 286 287 refresh = drm_mode_vrefresh(mode); 288 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2; 289 msleep(two_frames); 290 } 291 292 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host) 293 { 294 return container_of(host, struct dw_mipi_dsi, dsi_host); 295 } 296 297 static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge) 298 { 299 return container_of(bridge, struct dw_mipi_dsi, bridge); 300 } 301 302 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) 303 { 304 writel(val, dsi->base + reg); 305 } 306 307 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) 308 { 309 return readl(dsi->base + reg); 310 } 311 312 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 313 struct mipi_dsi_device *device) 314 { 315 struct dw_mipi_dsi *dsi = host_to_dsi(host); 316 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 317 struct drm_bridge *bridge; 318 int ret; 319 320 if (device->lanes > dsi->plat_data->max_data_lanes) { 321 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n", 322 device->lanes); 323 return -EINVAL; 324 } 325 326 dsi->lanes = device->lanes; 327 dsi->channel = device->channel; 328 dsi->format = device->format; 329 dsi->mode_flags = device->mode_flags; 330 331 bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node, 1, 0); 332 if (IS_ERR(bridge)) 333 return PTR_ERR(bridge); 334 335 dsi->panel_bridge = bridge; 336 337 drm_bridge_add(&dsi->bridge); 338 339 if (pdata->host_ops && pdata->host_ops->attach) { 340 ret = pdata->host_ops->attach(pdata->priv_data, device); 341 if (ret < 0) 342 return ret; 343 } 344 345 return 0; 346 } 347 348 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, 349 struct mipi_dsi_device *device) 350 { 351 struct dw_mipi_dsi *dsi = host_to_dsi(host); 352 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 353 int ret; 354 355 if (pdata->host_ops && pdata->host_ops->detach) { 356 ret = pdata->host_ops->detach(pdata->priv_data, device); 357 if (ret < 0) 358 return ret; 359 } 360 361 drm_of_panel_bridge_remove(host->dev->of_node, 1, 0); 362 363 drm_bridge_remove(&dsi->bridge); 364 365 return 0; 366 } 367 368 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, 369 const struct mipi_dsi_msg *msg) 370 { 371 bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM; 372 u32 val = 0; 373 374 /* 375 * TODO dw drv improvements 376 * largest packet sizes during hfp or during vsa/vpb/vfp 377 * should be computed according to byte lane, lane number and only 378 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS) 379 */ 380 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(16) 381 | INVACT_LPCMD_TIME(4)); 382 383 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) 384 val |= ACK_RQST_EN; 385 if (lpm) 386 val |= CMD_MODE_ALL_LP; 387 388 dsi_write(dsi, DSI_CMD_MODE_CFG, val); 389 390 val = dsi_read(dsi, DSI_VID_MODE_CFG); 391 if (lpm) 392 val |= ENABLE_LOW_POWER_CMD; 393 else 394 val &= ~ENABLE_LOW_POWER_CMD; 395 dsi_write(dsi, DSI_VID_MODE_CFG, val); 396 } 397 398 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) 399 { 400 int ret; 401 u32 val, mask; 402 403 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 404 val, !(val & GEN_CMD_FULL), 1000, 405 CMD_PKT_STATUS_TIMEOUT_US); 406 if (ret) { 407 dev_err(dsi->dev, "failed to get available command FIFO\n"); 408 return ret; 409 } 410 411 dsi_write(dsi, DSI_GEN_HDR, hdr_val); 412 413 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 414 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 415 val, (val & mask) == mask, 416 1000, CMD_PKT_STATUS_TIMEOUT_US); 417 if (ret) { 418 dev_err(dsi->dev, "failed to write command FIFO\n"); 419 return ret; 420 } 421 422 return 0; 423 } 424 425 static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi, 426 const struct mipi_dsi_packet *packet) 427 { 428 const u8 *tx_buf = packet->payload; 429 int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret; 430 __le32 word; 431 u32 val; 432 433 while (len) { 434 if (len < pld_data_bytes) { 435 word = 0; 436 memcpy(&word, tx_buf, len); 437 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word)); 438 len = 0; 439 } else { 440 memcpy(&word, tx_buf, pld_data_bytes); 441 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word)); 442 tx_buf += pld_data_bytes; 443 len -= pld_data_bytes; 444 } 445 446 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 447 val, !(val & GEN_PLD_W_FULL), 1000, 448 CMD_PKT_STATUS_TIMEOUT_US); 449 if (ret) { 450 dev_err(dsi->dev, 451 "failed to get available write payload FIFO\n"); 452 return ret; 453 } 454 } 455 456 word = 0; 457 memcpy(&word, packet->header, sizeof(packet->header)); 458 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word)); 459 } 460 461 static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi, 462 const struct mipi_dsi_msg *msg) 463 { 464 int i, j, ret, len = msg->rx_len; 465 u8 *buf = msg->rx_buf; 466 u32 val; 467 468 /* Wait end of the read operation */ 469 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 470 val, !(val & GEN_RD_CMD_BUSY), 471 1000, CMD_PKT_STATUS_TIMEOUT_US); 472 if (ret) { 473 dev_err(dsi->dev, "Timeout during read operation\n"); 474 return ret; 475 } 476 477 for (i = 0; i < len; i += 4) { 478 /* Read fifo must not be empty before all bytes are read */ 479 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 480 val, !(val & GEN_PLD_R_EMPTY), 481 1000, CMD_PKT_STATUS_TIMEOUT_US); 482 if (ret) { 483 dev_err(dsi->dev, "Read payload FIFO is empty\n"); 484 return ret; 485 } 486 487 val = dsi_read(dsi, DSI_GEN_PLD_DATA); 488 for (j = 0; j < 4 && j + i < len; j++) 489 buf[i + j] = val >> (8 * j); 490 } 491 492 return ret; 493 } 494 495 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, 496 const struct mipi_dsi_msg *msg) 497 { 498 struct dw_mipi_dsi *dsi = host_to_dsi(host); 499 struct mipi_dsi_packet packet; 500 int ret, nb_bytes; 501 502 ret = mipi_dsi_create_packet(&packet, msg); 503 if (ret) { 504 dev_err(dsi->dev, "failed to create packet: %d\n", ret); 505 return ret; 506 } 507 508 dw_mipi_message_config(dsi, msg); 509 if (dsi->slave) 510 dw_mipi_message_config(dsi->slave, msg); 511 512 ret = dw_mipi_dsi_write(dsi, &packet); 513 if (ret) 514 return ret; 515 if (dsi->slave) { 516 ret = dw_mipi_dsi_write(dsi->slave, &packet); 517 if (ret) 518 return ret; 519 } 520 521 if (msg->rx_buf && msg->rx_len) { 522 ret = dw_mipi_dsi_read(dsi, msg); 523 if (ret) 524 return ret; 525 nb_bytes = msg->rx_len; 526 } else { 527 nb_bytes = packet.size; 528 } 529 530 return nb_bytes; 531 } 532 533 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = { 534 .attach = dw_mipi_dsi_host_attach, 535 .detach = dw_mipi_dsi_host_detach, 536 .transfer = dw_mipi_dsi_host_transfer, 537 }; 538 539 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) 540 { 541 u32 val; 542 543 /* 544 * TODO dw drv improvements 545 * enabling low power is panel-dependent, we should use the 546 * panel configuration here... 547 */ 548 val = ENABLE_LOW_POWER; 549 550 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 551 val |= VID_MODE_TYPE_BURST; 552 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 553 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 554 else 555 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 556 557 #ifdef CONFIG_DEBUG_FS 558 if (dsi->vpg_defs.vpg) { 559 val |= VID_MODE_VPG_ENABLE; 560 val |= dsi->vpg_defs.vpg_horizontal ? 561 VID_MODE_VPG_HORIZONTAL : 0; 562 val |= dsi->vpg_defs.vpg_ber_pattern ? VID_MODE_VPG_MODE : 0; 563 } 564 #endif /* CONFIG_DEBUG_FS */ 565 566 dsi_write(dsi, DSI_VID_MODE_CFG, val); 567 } 568 569 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, 570 unsigned long mode_flags) 571 { 572 u32 val; 573 574 dsi_write(dsi, DSI_PWR_UP, RESET); 575 576 if (mode_flags & MIPI_DSI_MODE_VIDEO) { 577 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE); 578 dw_mipi_dsi_video_mode_config(dsi); 579 } else { 580 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 581 } 582 583 val = PHY_TXREQUESTCLKHS; 584 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 585 val |= AUTO_CLKLANE_CTRL; 586 dsi_write(dsi, DSI_LPCLK_CTRL, val); 587 588 dsi_write(dsi, DSI_PWR_UP, POWERUP); 589 } 590 591 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) 592 { 593 dsi_write(dsi, DSI_PWR_UP, RESET); 594 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ); 595 } 596 597 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) 598 { 599 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 600 unsigned int esc_rate; /* in MHz */ 601 u32 esc_clk_division; 602 int ret; 603 604 /* 605 * The maximum permitted escape clock is 20MHz and it is derived from 606 * lanebyteclk, which is running at "lane_mbps / 8". 607 */ 608 if (phy_ops->get_esc_clk_rate) { 609 ret = phy_ops->get_esc_clk_rate(dsi->plat_data->priv_data, 610 &esc_rate); 611 if (ret) 612 DRM_DEBUG_DRIVER("Phy get_esc_clk_rate() failed\n"); 613 } else 614 esc_rate = 20; /* Default to 20MHz */ 615 616 /* 617 * We want : 618 * (lane_mbps >> 3) / esc_clk_division < X 619 * which is: 620 * (lane_mbps >> 3) / X > esc_clk_division 621 */ 622 esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1; 623 624 dsi_write(dsi, DSI_PWR_UP, RESET); 625 626 /* 627 * TODO dw drv improvements 628 * timeout clock division should be computed with the 629 * high speed transmission counter timeout and byte lane... 630 */ 631 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) | 632 TX_ESC_CLK_DIVISION(esc_clk_division)); 633 } 634 635 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, 636 const struct drm_display_mode *mode) 637 { 638 u32 val = 0, color = 0; 639 640 switch (dsi->format) { 641 case MIPI_DSI_FMT_RGB888: 642 color = DPI_COLOR_CODING_24BIT; 643 break; 644 case MIPI_DSI_FMT_RGB666: 645 color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN; 646 break; 647 case MIPI_DSI_FMT_RGB666_PACKED: 648 color = DPI_COLOR_CODING_18BIT_1; 649 break; 650 case MIPI_DSI_FMT_RGB565: 651 color = DPI_COLOR_CODING_16BIT_1; 652 break; 653 } 654 655 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 656 val |= VSYNC_ACTIVE_LOW; 657 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 658 val |= HSYNC_ACTIVE_LOW; 659 660 dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel)); 661 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); 662 dsi_write(dsi, DSI_DPI_CFG_POL, val); 663 } 664 665 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) 666 { 667 dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN); 668 } 669 670 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, 671 const struct drm_display_mode *mode) 672 { 673 /* 674 * TODO dw drv improvements 675 * only burst mode is supported here. For non-burst video modes, 676 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC & 677 * DSI_VNPCR.NPSIZE... especially because this driver supports 678 * non-burst video modes, see dw_mipi_dsi_video_mode_config()... 679 */ 680 681 dsi_write(dsi, DSI_VID_PKT_SIZE, 682 dw_mipi_is_dual_mode(dsi) ? 683 VID_PKT_SIZE(mode->hdisplay / 2) : 684 VID_PKT_SIZE(mode->hdisplay)); 685 } 686 687 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) 688 { 689 /* 690 * TODO dw drv improvements 691 * compute high speed transmission counter timeout according 692 * to the timeout clock division (TO_CLK_DIVISION) and byte lane... 693 */ 694 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); 695 /* 696 * TODO dw drv improvements 697 * the Bus-Turn-Around Timeout Counter should be computed 698 * according to byte lane... 699 */ 700 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); 701 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 702 } 703 704 /* Get lane byte clock cycles. */ 705 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, 706 const struct drm_display_mode *mode, 707 u32 hcomponent) 708 { 709 u32 frac, lbcc; 710 711 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8; 712 713 frac = lbcc % mode->clock; 714 lbcc = lbcc / mode->clock; 715 if (frac) 716 lbcc++; 717 718 return lbcc; 719 } 720 721 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi, 722 const struct drm_display_mode *mode) 723 { 724 u32 htotal, hsa, hbp, lbcc; 725 726 htotal = mode->htotal; 727 hsa = mode->hsync_end - mode->hsync_start; 728 hbp = mode->htotal - mode->hsync_end; 729 730 /* 731 * TODO dw drv improvements 732 * computations below may be improved... 733 */ 734 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal); 735 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); 736 737 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa); 738 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); 739 740 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp); 741 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); 742 } 743 744 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi, 745 const struct drm_display_mode *mode) 746 { 747 u32 vactive, vsa, vfp, vbp; 748 749 vactive = mode->vdisplay; 750 vsa = mode->vsync_end - mode->vsync_start; 751 vfp = mode->vsync_start - mode->vdisplay; 752 vbp = mode->vtotal - mode->vsync_end; 753 754 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); 755 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); 756 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); 757 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); 758 } 759 760 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) 761 { 762 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 763 struct dw_mipi_dsi_dphy_timing timing; 764 u32 hw_version; 765 int ret; 766 767 ret = phy_ops->get_timing(dsi->plat_data->priv_data, 768 dsi->lane_mbps, &timing); 769 if (ret) 770 DRM_DEV_ERROR(dsi->dev, "Retrieving phy timings failed\n"); 771 772 /* 773 * TODO dw drv improvements 774 * data & clock lane timers should be computed according to panel 775 * blankings and to the automatic clock lane control mode... 776 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with 777 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP) 778 */ 779 780 hw_version = dsi_read(dsi, DSI_VERSION) & VERSION; 781 782 if (hw_version >= HWVER_131) { 783 dsi_write(dsi, DSI_PHY_TMR_CFG, 784 PHY_HS2LP_TIME_V131(timing.data_hs2lp) | 785 PHY_LP2HS_TIME_V131(timing.data_lp2hs)); 786 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000)); 787 } else { 788 dsi_write(dsi, DSI_PHY_TMR_CFG, 789 PHY_HS2LP_TIME(timing.data_hs2lp) | 790 PHY_LP2HS_TIME(timing.data_lp2hs) | 791 MAX_RD_TIME(10000)); 792 } 793 794 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, 795 PHY_CLKHS2LP_TIME(timing.clk_hs2lp) | 796 PHY_CLKLP2HS_TIME(timing.clk_lp2hs)); 797 } 798 799 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) 800 { 801 /* 802 * TODO dw drv improvements 803 * stop wait time should be the maximum between host dsi 804 * and panel stop wait times 805 */ 806 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | 807 N_LANES(dsi->lanes)); 808 } 809 810 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi) 811 { 812 /* Clear PHY state */ 813 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK 814 | PHY_RSTZ | PHY_SHUTDOWNZ); 815 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 816 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR); 817 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 818 } 819 820 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi) 821 { 822 u32 val; 823 int ret; 824 825 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | 826 PHY_UNRSTZ | PHY_UNSHUTDOWNZ); 827 828 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val, 829 val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US); 830 if (ret) 831 DRM_DEBUG_DRIVER("failed to wait phy lock state\n"); 832 833 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 834 val, val & PHY_STOP_STATE_CLK_LANE, 1000, 835 PHY_STATUS_TIMEOUT_US); 836 if (ret) 837 DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n"); 838 } 839 840 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) 841 { 842 dsi_read(dsi, DSI_INT_ST0); 843 dsi_read(dsi, DSI_INT_ST1); 844 dsi_write(dsi, DSI_INT_MSK0, 0); 845 dsi_write(dsi, DSI_INT_MSK1, 0); 846 } 847 848 static void dw_mipi_dsi_bridge_post_atomic_disable(struct drm_bridge *bridge, 849 struct drm_bridge_state *old_bridge_state) 850 { 851 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 852 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 853 854 /* 855 * Switch to command mode before panel-bridge post_disable & 856 * panel unprepare. 857 * Note: panel-bridge disable & panel disable has been called 858 * before by the drm framework. 859 */ 860 dw_mipi_dsi_set_mode(dsi, 0); 861 862 /* 863 * TODO Only way found to call panel-bridge post_disable & 864 * panel unprepare before the dsi "final" disable... 865 * This needs to be fixed in the drm_bridge framework and the API 866 * needs to be updated to manage our own call chains... 867 */ 868 if (dsi->panel_bridge->funcs->post_disable) 869 dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge); 870 871 if (phy_ops->power_off) 872 phy_ops->power_off(dsi->plat_data->priv_data); 873 874 if (dsi->slave) { 875 dw_mipi_dsi_disable(dsi->slave); 876 clk_disable_unprepare(dsi->slave->pclk); 877 pm_runtime_put(dsi->slave->dev); 878 } 879 dw_mipi_dsi_disable(dsi); 880 881 clk_disable_unprepare(dsi->pclk); 882 pm_runtime_put(dsi->dev); 883 } 884 885 static unsigned int dw_mipi_dsi_get_lanes(struct dw_mipi_dsi *dsi) 886 { 887 /* this instance is the slave, so add the master's lanes */ 888 if (dsi->master) 889 return dsi->master->lanes + dsi->lanes; 890 891 /* this instance is the master, so add the slave's lanes */ 892 if (dsi->slave) 893 return dsi->lanes + dsi->slave->lanes; 894 895 /* single-dsi, so no other instance to consider */ 896 return dsi->lanes; 897 } 898 899 static void dw_mipi_dsi_mode_set(struct dw_mipi_dsi *dsi, 900 const struct drm_display_mode *adjusted_mode) 901 { 902 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 903 void *priv_data = dsi->plat_data->priv_data; 904 int ret; 905 u32 lanes = dw_mipi_dsi_get_lanes(dsi); 906 907 clk_prepare_enable(dsi->pclk); 908 909 ret = phy_ops->get_lane_mbps(priv_data, adjusted_mode, dsi->mode_flags, 910 lanes, dsi->format, &dsi->lane_mbps); 911 if (ret) 912 DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n"); 913 914 pm_runtime_get_sync(dsi->dev); 915 dw_mipi_dsi_init(dsi); 916 dw_mipi_dsi_dpi_config(dsi, adjusted_mode); 917 dw_mipi_dsi_packet_handler_config(dsi); 918 dw_mipi_dsi_video_mode_config(dsi); 919 dw_mipi_dsi_video_packet_config(dsi, adjusted_mode); 920 dw_mipi_dsi_command_mode_config(dsi); 921 dw_mipi_dsi_line_timer_config(dsi, adjusted_mode); 922 dw_mipi_dsi_vertical_timing_config(dsi, adjusted_mode); 923 924 dw_mipi_dsi_dphy_init(dsi); 925 dw_mipi_dsi_dphy_timing_config(dsi); 926 dw_mipi_dsi_dphy_interface_config(dsi); 927 928 dw_mipi_dsi_clear_err(dsi); 929 930 ret = phy_ops->init(priv_data); 931 if (ret) 932 DRM_DEBUG_DRIVER("Phy init() failed\n"); 933 934 dw_mipi_dsi_dphy_enable(dsi); 935 936 dw_mipi_dsi_wait_for_two_frames(adjusted_mode); 937 938 /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */ 939 dw_mipi_dsi_set_mode(dsi, 0); 940 941 if (phy_ops->power_on) 942 phy_ops->power_on(dsi->plat_data->priv_data); 943 } 944 945 static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge, 946 const struct drm_display_mode *mode, 947 const struct drm_display_mode *adjusted_mode) 948 { 949 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 950 951 dw_mipi_dsi_mode_set(dsi, adjusted_mode); 952 if (dsi->slave) 953 dw_mipi_dsi_mode_set(dsi->slave, adjusted_mode); 954 } 955 956 static void dw_mipi_dsi_bridge_atomic_enable(struct drm_bridge *bridge, 957 struct drm_bridge_state *old_bridge_state) 958 { 959 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 960 961 /* Switch to video mode for panel-bridge enable & panel enable */ 962 dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO); 963 if (dsi->slave) 964 dw_mipi_dsi_set_mode(dsi->slave, MIPI_DSI_MODE_VIDEO); 965 } 966 967 static enum drm_mode_status 968 dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge, 969 const struct drm_display_info *info, 970 const struct drm_display_mode *mode) 971 { 972 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 973 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 974 enum drm_mode_status mode_status = MODE_OK; 975 976 if (pdata->mode_valid) 977 mode_status = pdata->mode_valid(pdata->priv_data, mode, 978 dsi->mode_flags, 979 dw_mipi_dsi_get_lanes(dsi), 980 dsi->format); 981 982 return mode_status; 983 } 984 985 static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge, 986 enum drm_bridge_attach_flags flags) 987 { 988 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 989 990 if (!bridge->encoder) { 991 DRM_ERROR("Parent encoder object not found\n"); 992 return -ENODEV; 993 } 994 995 /* Set the encoder type as caller does not know it */ 996 bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI; 997 998 /* Attach the panel-bridge to the dsi bridge */ 999 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge, 1000 flags); 1001 } 1002 1003 static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = { 1004 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1005 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1006 .atomic_reset = drm_atomic_helper_bridge_reset, 1007 .atomic_enable = dw_mipi_dsi_bridge_atomic_enable, 1008 .atomic_post_disable = dw_mipi_dsi_bridge_post_atomic_disable, 1009 .mode_set = dw_mipi_dsi_bridge_mode_set, 1010 .mode_valid = dw_mipi_dsi_bridge_mode_valid, 1011 .attach = dw_mipi_dsi_bridge_attach, 1012 }; 1013 1014 #ifdef CONFIG_DEBUG_FS 1015 1016 static int dw_mipi_dsi_debugfs_write(void *data, u64 val) 1017 { 1018 struct debugfs_entries *vpg = data; 1019 struct dw_mipi_dsi *dsi; 1020 u32 mode_cfg; 1021 1022 if (!vpg) 1023 return -ENODEV; 1024 1025 dsi = vpg->dsi; 1026 1027 *vpg->reg = (bool)val; 1028 1029 mode_cfg = dsi_read(dsi, DSI_VID_MODE_CFG); 1030 1031 if (*vpg->reg) 1032 mode_cfg |= vpg->mask; 1033 else 1034 mode_cfg &= ~vpg->mask; 1035 1036 dsi_write(dsi, DSI_VID_MODE_CFG, mode_cfg); 1037 1038 return 0; 1039 } 1040 1041 static int dw_mipi_dsi_debugfs_show(void *data, u64 *val) 1042 { 1043 struct debugfs_entries *vpg = data; 1044 1045 if (!vpg) 1046 return -ENODEV; 1047 1048 *val = *vpg->reg; 1049 1050 return 0; 1051 } 1052 1053 DEFINE_DEBUGFS_ATTRIBUTE(fops_x32, dw_mipi_dsi_debugfs_show, 1054 dw_mipi_dsi_debugfs_write, "%llu\n"); 1055 1056 static void debugfs_create_files(void *data) 1057 { 1058 struct dw_mipi_dsi *dsi = data; 1059 struct debugfs_entries debugfs[] = { 1060 REGISTER(vpg, VID_MODE_VPG_ENABLE, dsi), 1061 REGISTER(vpg_horizontal, VID_MODE_VPG_HORIZONTAL, dsi), 1062 REGISTER(vpg_ber_pattern, VID_MODE_VPG_MODE, dsi), 1063 }; 1064 int i; 1065 1066 dsi->debugfs_vpg = kmemdup(debugfs, sizeof(debugfs), GFP_KERNEL); 1067 if (!dsi->debugfs_vpg) 1068 return; 1069 1070 for (i = 0; i < ARRAY_SIZE(debugfs); i++) 1071 debugfs_create_file(dsi->debugfs_vpg[i].name, 0644, 1072 dsi->debugfs, &dsi->debugfs_vpg[i], 1073 &fops_x32); 1074 } 1075 1076 static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) 1077 { 1078 dsi->debugfs = debugfs_create_dir(dev_name(dsi->dev), NULL); 1079 if (IS_ERR(dsi->debugfs)) { 1080 dev_err(dsi->dev, "failed to create debugfs root\n"); 1081 return; 1082 } 1083 1084 debugfs_create_files(dsi); 1085 } 1086 1087 static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) 1088 { 1089 debugfs_remove_recursive(dsi->debugfs); 1090 kfree(dsi->debugfs_vpg); 1091 } 1092 1093 #else 1094 1095 static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) { } 1096 static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { } 1097 1098 #endif /* CONFIG_DEBUG_FS */ 1099 1100 static struct dw_mipi_dsi * 1101 __dw_mipi_dsi_probe(struct platform_device *pdev, 1102 const struct dw_mipi_dsi_plat_data *plat_data) 1103 { 1104 struct device *dev = &pdev->dev; 1105 struct reset_control *apb_rst; 1106 struct dw_mipi_dsi *dsi; 1107 int ret; 1108 1109 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1110 if (!dsi) 1111 return ERR_PTR(-ENOMEM); 1112 1113 dsi->dev = dev; 1114 dsi->plat_data = plat_data; 1115 1116 if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps || 1117 !plat_data->phy_ops->get_timing) { 1118 DRM_ERROR("Phy not properly configured\n"); 1119 return ERR_PTR(-ENODEV); 1120 } 1121 1122 if (!plat_data->base) { 1123 dsi->base = devm_platform_ioremap_resource(pdev, 0); 1124 if (IS_ERR(dsi->base)) 1125 return ERR_PTR(-ENODEV); 1126 1127 } else { 1128 dsi->base = plat_data->base; 1129 } 1130 1131 dsi->pclk = devm_clk_get(dev, "pclk"); 1132 if (IS_ERR(dsi->pclk)) { 1133 ret = PTR_ERR(dsi->pclk); 1134 dev_err(dev, "Unable to get pclk: %d\n", ret); 1135 return ERR_PTR(ret); 1136 } 1137 1138 /* 1139 * Note that the reset was not defined in the initial device tree, so 1140 * we have to be prepared for it not being found. 1141 */ 1142 apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb"); 1143 if (IS_ERR(apb_rst)) { 1144 ret = PTR_ERR(apb_rst); 1145 1146 if (ret != -EPROBE_DEFER) 1147 dev_err(dev, "Unable to get reset control: %d\n", ret); 1148 1149 return ERR_PTR(ret); 1150 } 1151 1152 if (apb_rst) { 1153 ret = clk_prepare_enable(dsi->pclk); 1154 if (ret) { 1155 dev_err(dev, "%s: Failed to enable pclk\n", __func__); 1156 return ERR_PTR(ret); 1157 } 1158 1159 reset_control_assert(apb_rst); 1160 usleep_range(10, 20); 1161 reset_control_deassert(apb_rst); 1162 1163 clk_disable_unprepare(dsi->pclk); 1164 } 1165 1166 dw_mipi_dsi_debugfs_init(dsi); 1167 pm_runtime_enable(dev); 1168 1169 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops; 1170 dsi->dsi_host.dev = dev; 1171 ret = mipi_dsi_host_register(&dsi->dsi_host); 1172 if (ret) { 1173 dev_err(dev, "Failed to register MIPI host: %d\n", ret); 1174 pm_runtime_disable(dev); 1175 dw_mipi_dsi_debugfs_remove(dsi); 1176 return ERR_PTR(ret); 1177 } 1178 1179 dsi->bridge.driver_private = dsi; 1180 dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs; 1181 #ifdef CONFIG_OF 1182 dsi->bridge.of_node = pdev->dev.of_node; 1183 #endif 1184 1185 return dsi; 1186 } 1187 1188 static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi) 1189 { 1190 mipi_dsi_host_unregister(&dsi->dsi_host); 1191 1192 pm_runtime_disable(dsi->dev); 1193 dw_mipi_dsi_debugfs_remove(dsi); 1194 } 1195 1196 void dw_mipi_dsi_set_slave(struct dw_mipi_dsi *dsi, struct dw_mipi_dsi *slave) 1197 { 1198 /* introduce controllers to each other */ 1199 dsi->slave = slave; 1200 dsi->slave->master = dsi; 1201 1202 /* migrate settings for already attached displays */ 1203 dsi->slave->lanes = dsi->lanes; 1204 dsi->slave->channel = dsi->channel; 1205 dsi->slave->format = dsi->format; 1206 dsi->slave->mode_flags = dsi->mode_flags; 1207 } 1208 EXPORT_SYMBOL_GPL(dw_mipi_dsi_set_slave); 1209 1210 /* 1211 * Probe/remove API, used from platforms based on the DRM bridge API. 1212 */ 1213 struct dw_mipi_dsi * 1214 dw_mipi_dsi_probe(struct platform_device *pdev, 1215 const struct dw_mipi_dsi_plat_data *plat_data) 1216 { 1217 return __dw_mipi_dsi_probe(pdev, plat_data); 1218 } 1219 EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe); 1220 1221 void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi) 1222 { 1223 __dw_mipi_dsi_remove(dsi); 1224 } 1225 EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove); 1226 1227 /* 1228 * Bind/unbind API, used from platforms based on the component framework. 1229 */ 1230 int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder) 1231 { 1232 return drm_bridge_attach(encoder, &dsi->bridge, NULL, 0); 1233 } 1234 EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind); 1235 1236 void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi) 1237 { 1238 } 1239 EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind); 1240 1241 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>"); 1242 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1243 MODULE_DESCRIPTION("DW MIPI DSI host controller driver"); 1244 MODULE_LICENSE("GPL"); 1245 MODULE_ALIAS("platform:dw-mipi-dsi"); 1246