1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd 4 * Copyright (C) STMicroelectronics SA 2017 5 * 6 * Modified by Philippe Cornu <philippe.cornu@st.com> 7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the 8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs. 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/iopoll.h> 14 #include <linux/module.h> 15 #include <linux/of_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 #include <drm/drmP.h> 19 #include <drm/drm_atomic_helper.h> 20 #include <drm/drm_bridge.h> 21 #include <drm/drm_crtc.h> 22 #include <drm/drm_crtc_helper.h> 23 #include <drm/drm_mipi_dsi.h> 24 #include <drm/drm_of.h> 25 #include <drm/bridge/dw_mipi_dsi.h> 26 #include <video/mipi_display.h> 27 28 #define HWVER_131 0x31333100 /* IP version 1.31 */ 29 30 #define DSI_VERSION 0x00 31 #define VERSION GENMASK(31, 8) 32 33 #define DSI_PWR_UP 0x04 34 #define RESET 0 35 #define POWERUP BIT(0) 36 37 #define DSI_CLKMGR_CFG 0x08 38 #define TO_CLK_DIVISION(div) (((div) & 0xff) << 8) 39 #define TX_ESC_CLK_DIVISION(div) ((div) & 0xff) 40 41 #define DSI_DPI_VCID 0x0c 42 #define DPI_VCID(vcid) ((vcid) & 0x3) 43 44 #define DSI_DPI_COLOR_CODING 0x10 45 #define LOOSELY18_EN BIT(8) 46 #define DPI_COLOR_CODING_16BIT_1 0x0 47 #define DPI_COLOR_CODING_16BIT_2 0x1 48 #define DPI_COLOR_CODING_16BIT_3 0x2 49 #define DPI_COLOR_CODING_18BIT_1 0x3 50 #define DPI_COLOR_CODING_18BIT_2 0x4 51 #define DPI_COLOR_CODING_24BIT 0x5 52 53 #define DSI_DPI_CFG_POL 0x14 54 #define COLORM_ACTIVE_LOW BIT(4) 55 #define SHUTD_ACTIVE_LOW BIT(3) 56 #define HSYNC_ACTIVE_LOW BIT(2) 57 #define VSYNC_ACTIVE_LOW BIT(1) 58 #define DATAEN_ACTIVE_LOW BIT(0) 59 60 #define DSI_DPI_LP_CMD_TIM 0x18 61 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) 62 #define INVACT_LPCMD_TIME(p) ((p) & 0xff) 63 64 #define DSI_DBI_VCID 0x1c 65 #define DSI_DBI_CFG 0x20 66 #define DSI_DBI_PARTITIONING_EN 0x24 67 #define DSI_DBI_CMDSIZE 0x28 68 69 #define DSI_PCKHDL_CFG 0x2c 70 #define CRC_RX_EN BIT(4) 71 #define ECC_RX_EN BIT(3) 72 #define BTA_EN BIT(2) 73 #define EOTP_RX_EN BIT(1) 74 #define EOTP_TX_EN BIT(0) 75 76 #define DSI_GEN_VCID 0x30 77 78 #define DSI_MODE_CFG 0x34 79 #define ENABLE_VIDEO_MODE 0 80 #define ENABLE_CMD_MODE BIT(0) 81 82 #define DSI_VID_MODE_CFG 0x38 83 #define ENABLE_LOW_POWER (0x3f << 8) 84 #define ENABLE_LOW_POWER_MASK (0x3f << 8) 85 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0 86 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1 87 #define VID_MODE_TYPE_BURST 0x2 88 #define VID_MODE_TYPE_MASK 0x3 89 90 #define DSI_VID_PKT_SIZE 0x3c 91 #define VID_PKT_SIZE(p) ((p) & 0x3fff) 92 93 #define DSI_VID_NUM_CHUNKS 0x40 94 #define VID_NUM_CHUNKS(c) ((c) & 0x1fff) 95 96 #define DSI_VID_NULL_SIZE 0x44 97 #define VID_NULL_SIZE(b) ((b) & 0x1fff) 98 99 #define DSI_VID_HSA_TIME 0x48 100 #define DSI_VID_HBP_TIME 0x4c 101 #define DSI_VID_HLINE_TIME 0x50 102 #define DSI_VID_VSA_LINES 0x54 103 #define DSI_VID_VBP_LINES 0x58 104 #define DSI_VID_VFP_LINES 0x5c 105 #define DSI_VID_VACTIVE_LINES 0x60 106 #define DSI_EDPI_CMD_SIZE 0x64 107 108 #define DSI_CMD_MODE_CFG 0x68 109 #define MAX_RD_PKT_SIZE_LP BIT(24) 110 #define DCS_LW_TX_LP BIT(19) 111 #define DCS_SR_0P_TX_LP BIT(18) 112 #define DCS_SW_1P_TX_LP BIT(17) 113 #define DCS_SW_0P_TX_LP BIT(16) 114 #define GEN_LW_TX_LP BIT(14) 115 #define GEN_SR_2P_TX_LP BIT(13) 116 #define GEN_SR_1P_TX_LP BIT(12) 117 #define GEN_SR_0P_TX_LP BIT(11) 118 #define GEN_SW_2P_TX_LP BIT(10) 119 #define GEN_SW_1P_TX_LP BIT(9) 120 #define GEN_SW_0P_TX_LP BIT(8) 121 #define ACK_RQST_EN BIT(1) 122 #define TEAR_FX_EN BIT(0) 123 124 #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \ 125 DCS_LW_TX_LP | \ 126 DCS_SR_0P_TX_LP | \ 127 DCS_SW_1P_TX_LP | \ 128 DCS_SW_0P_TX_LP | \ 129 GEN_LW_TX_LP | \ 130 GEN_SR_2P_TX_LP | \ 131 GEN_SR_1P_TX_LP | \ 132 GEN_SR_0P_TX_LP | \ 133 GEN_SW_2P_TX_LP | \ 134 GEN_SW_1P_TX_LP | \ 135 GEN_SW_0P_TX_LP) 136 137 #define DSI_GEN_HDR 0x6c 138 #define DSI_GEN_PLD_DATA 0x70 139 140 #define DSI_CMD_PKT_STATUS 0x74 141 #define GEN_RD_CMD_BUSY BIT(6) 142 #define GEN_PLD_R_FULL BIT(5) 143 #define GEN_PLD_R_EMPTY BIT(4) 144 #define GEN_PLD_W_FULL BIT(3) 145 #define GEN_PLD_W_EMPTY BIT(2) 146 #define GEN_CMD_FULL BIT(1) 147 #define GEN_CMD_EMPTY BIT(0) 148 149 #define DSI_TO_CNT_CFG 0x78 150 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16) 151 #define LPRX_TO_CNT(p) ((p) & 0xffff) 152 153 #define DSI_HS_RD_TO_CNT 0x7c 154 #define DSI_LP_RD_TO_CNT 0x80 155 #define DSI_HS_WR_TO_CNT 0x84 156 #define DSI_LP_WR_TO_CNT 0x88 157 #define DSI_BTA_TO_CNT 0x8c 158 159 #define DSI_LPCLK_CTRL 0x94 160 #define AUTO_CLKLANE_CTRL BIT(1) 161 #define PHY_TXREQUESTCLKHS BIT(0) 162 163 #define DSI_PHY_TMR_LPCLK_CFG 0x98 164 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16) 165 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff) 166 167 #define DSI_PHY_TMR_CFG 0x9c 168 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24) 169 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16) 170 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) 171 #define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16) 172 #define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff) 173 174 #define DSI_PHY_RSTZ 0xa0 175 #define PHY_DISFORCEPLL 0 176 #define PHY_ENFORCEPLL BIT(3) 177 #define PHY_DISABLECLK 0 178 #define PHY_ENABLECLK BIT(2) 179 #define PHY_RSTZ 0 180 #define PHY_UNRSTZ BIT(1) 181 #define PHY_SHUTDOWNZ 0 182 #define PHY_UNSHUTDOWNZ BIT(0) 183 184 #define DSI_PHY_IF_CFG 0xa4 185 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 186 #define N_LANES(n) (((n) - 1) & 0x3) 187 188 #define DSI_PHY_ULPS_CTRL 0xa8 189 #define DSI_PHY_TX_TRIGGERS 0xac 190 191 #define DSI_PHY_STATUS 0xb0 192 #define PHY_STOP_STATE_CLK_LANE BIT(2) 193 #define PHY_LOCK BIT(0) 194 195 #define DSI_PHY_TST_CTRL0 0xb4 196 #define PHY_TESTCLK BIT(1) 197 #define PHY_UNTESTCLK 0 198 #define PHY_TESTCLR BIT(0) 199 #define PHY_UNTESTCLR 0 200 201 #define DSI_PHY_TST_CTRL1 0xb8 202 #define PHY_TESTEN BIT(16) 203 #define PHY_UNTESTEN 0 204 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 205 #define PHY_TESTDIN(n) ((n) & 0xff) 206 207 #define DSI_INT_ST0 0xbc 208 #define DSI_INT_ST1 0xc0 209 #define DSI_INT_MSK0 0xc4 210 #define DSI_INT_MSK1 0xc8 211 212 #define DSI_PHY_TMR_RD_CFG 0xf4 213 #define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff) 214 215 #define PHY_STATUS_TIMEOUT_US 10000 216 #define CMD_PKT_STATUS_TIMEOUT_US 20000 217 218 struct dw_mipi_dsi { 219 struct drm_bridge bridge; 220 struct mipi_dsi_host dsi_host; 221 struct drm_bridge *panel_bridge; 222 struct device *dev; 223 void __iomem *base; 224 225 struct clk *pclk; 226 227 unsigned int lane_mbps; /* per lane */ 228 u32 channel; 229 u32 lanes; 230 u32 format; 231 unsigned long mode_flags; 232 233 struct dw_mipi_dsi *master; /* dual-dsi master ptr */ 234 struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */ 235 236 const struct dw_mipi_dsi_plat_data *plat_data; 237 }; 238 239 /* 240 * Check if either a link to a master or slave is present 241 */ 242 static inline bool dw_mipi_is_dual_mode(struct dw_mipi_dsi *dsi) 243 { 244 return dsi->slave || dsi->master; 245 } 246 247 /* 248 * The controller should generate 2 frames before 249 * preparing the peripheral. 250 */ 251 static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode *mode) 252 { 253 int refresh, two_frames; 254 255 refresh = drm_mode_vrefresh(mode); 256 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2; 257 msleep(two_frames); 258 } 259 260 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host) 261 { 262 return container_of(host, struct dw_mipi_dsi, dsi_host); 263 } 264 265 static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge) 266 { 267 return container_of(bridge, struct dw_mipi_dsi, bridge); 268 } 269 270 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) 271 { 272 writel(val, dsi->base + reg); 273 } 274 275 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) 276 { 277 return readl(dsi->base + reg); 278 } 279 280 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 281 struct mipi_dsi_device *device) 282 { 283 struct dw_mipi_dsi *dsi = host_to_dsi(host); 284 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 285 struct drm_bridge *bridge; 286 struct drm_panel *panel; 287 int ret; 288 289 if (device->lanes > dsi->plat_data->max_data_lanes) { 290 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n", 291 device->lanes); 292 return -EINVAL; 293 } 294 295 dsi->lanes = device->lanes; 296 dsi->channel = device->channel; 297 dsi->format = device->format; 298 dsi->mode_flags = device->mode_flags; 299 300 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, 301 &panel, &bridge); 302 if (ret) 303 return ret; 304 305 if (panel) { 306 bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DSI); 307 if (IS_ERR(bridge)) 308 return PTR_ERR(bridge); 309 } 310 311 dsi->panel_bridge = bridge; 312 313 drm_bridge_add(&dsi->bridge); 314 315 if (pdata->host_ops && pdata->host_ops->attach) { 316 ret = pdata->host_ops->attach(pdata->priv_data, device); 317 if (ret < 0) 318 return ret; 319 } 320 321 return 0; 322 } 323 324 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, 325 struct mipi_dsi_device *device) 326 { 327 struct dw_mipi_dsi *dsi = host_to_dsi(host); 328 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 329 int ret; 330 331 if (pdata->host_ops && pdata->host_ops->detach) { 332 ret = pdata->host_ops->detach(pdata->priv_data, device); 333 if (ret < 0) 334 return ret; 335 } 336 337 drm_of_panel_bridge_remove(host->dev->of_node, 1, 0); 338 339 drm_bridge_remove(&dsi->bridge); 340 341 return 0; 342 } 343 344 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, 345 const struct mipi_dsi_msg *msg) 346 { 347 bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM; 348 u32 val = 0; 349 350 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) 351 val |= ACK_RQST_EN; 352 if (lpm) 353 val |= CMD_MODE_ALL_LP; 354 355 dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS); 356 dsi_write(dsi, DSI_CMD_MODE_CFG, val); 357 } 358 359 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) 360 { 361 int ret; 362 u32 val, mask; 363 364 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 365 val, !(val & GEN_CMD_FULL), 1000, 366 CMD_PKT_STATUS_TIMEOUT_US); 367 if (ret) { 368 dev_err(dsi->dev, "failed to get available command FIFO\n"); 369 return ret; 370 } 371 372 dsi_write(dsi, DSI_GEN_HDR, hdr_val); 373 374 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 375 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 376 val, (val & mask) == mask, 377 1000, CMD_PKT_STATUS_TIMEOUT_US); 378 if (ret) { 379 dev_err(dsi->dev, "failed to write command FIFO\n"); 380 return ret; 381 } 382 383 return 0; 384 } 385 386 static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi, 387 const struct mipi_dsi_packet *packet) 388 { 389 const u8 *tx_buf = packet->payload; 390 int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret; 391 __le32 word; 392 u32 val; 393 394 while (len) { 395 if (len < pld_data_bytes) { 396 word = 0; 397 memcpy(&word, tx_buf, len); 398 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word)); 399 len = 0; 400 } else { 401 memcpy(&word, tx_buf, pld_data_bytes); 402 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word)); 403 tx_buf += pld_data_bytes; 404 len -= pld_data_bytes; 405 } 406 407 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 408 val, !(val & GEN_PLD_W_FULL), 1000, 409 CMD_PKT_STATUS_TIMEOUT_US); 410 if (ret) { 411 dev_err(dsi->dev, 412 "failed to get available write payload FIFO\n"); 413 return ret; 414 } 415 } 416 417 word = 0; 418 memcpy(&word, packet->header, sizeof(packet->header)); 419 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word)); 420 } 421 422 static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi, 423 const struct mipi_dsi_msg *msg) 424 { 425 int i, j, ret, len = msg->rx_len; 426 u8 *buf = msg->rx_buf; 427 u32 val; 428 429 /* Wait end of the read operation */ 430 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 431 val, !(val & GEN_RD_CMD_BUSY), 432 1000, CMD_PKT_STATUS_TIMEOUT_US); 433 if (ret) { 434 dev_err(dsi->dev, "Timeout during read operation\n"); 435 return ret; 436 } 437 438 for (i = 0; i < len; i += 4) { 439 /* Read fifo must not be empty before all bytes are read */ 440 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 441 val, !(val & GEN_PLD_R_EMPTY), 442 1000, CMD_PKT_STATUS_TIMEOUT_US); 443 if (ret) { 444 dev_err(dsi->dev, "Read payload FIFO is empty\n"); 445 return ret; 446 } 447 448 val = dsi_read(dsi, DSI_GEN_PLD_DATA); 449 for (j = 0; j < 4 && j + i < len; j++) 450 buf[i + j] = val >> (8 * j); 451 } 452 453 return ret; 454 } 455 456 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, 457 const struct mipi_dsi_msg *msg) 458 { 459 struct dw_mipi_dsi *dsi = host_to_dsi(host); 460 struct mipi_dsi_packet packet; 461 int ret, nb_bytes; 462 463 ret = mipi_dsi_create_packet(&packet, msg); 464 if (ret) { 465 dev_err(dsi->dev, "failed to create packet: %d\n", ret); 466 return ret; 467 } 468 469 dw_mipi_message_config(dsi, msg); 470 if (dsi->slave) 471 dw_mipi_message_config(dsi->slave, msg); 472 473 ret = dw_mipi_dsi_write(dsi, &packet); 474 if (ret) 475 return ret; 476 if (dsi->slave) { 477 ret = dw_mipi_dsi_write(dsi->slave, &packet); 478 if (ret) 479 return ret; 480 } 481 482 if (msg->rx_buf && msg->rx_len) { 483 ret = dw_mipi_dsi_read(dsi, msg); 484 if (ret) 485 return ret; 486 nb_bytes = msg->rx_len; 487 } else { 488 nb_bytes = packet.size; 489 } 490 491 return nb_bytes; 492 } 493 494 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = { 495 .attach = dw_mipi_dsi_host_attach, 496 .detach = dw_mipi_dsi_host_detach, 497 .transfer = dw_mipi_dsi_host_transfer, 498 }; 499 500 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) 501 { 502 u32 val; 503 504 /* 505 * TODO dw drv improvements 506 * enabling low power is panel-dependent, we should use the 507 * panel configuration here... 508 */ 509 val = ENABLE_LOW_POWER; 510 511 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 512 val |= VID_MODE_TYPE_BURST; 513 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 514 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 515 else 516 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 517 518 dsi_write(dsi, DSI_VID_MODE_CFG, val); 519 } 520 521 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, 522 unsigned long mode_flags) 523 { 524 dsi_write(dsi, DSI_PWR_UP, RESET); 525 526 if (mode_flags & MIPI_DSI_MODE_VIDEO) { 527 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE); 528 dw_mipi_dsi_video_mode_config(dsi); 529 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); 530 } else { 531 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 532 } 533 534 dsi_write(dsi, DSI_PWR_UP, POWERUP); 535 } 536 537 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) 538 { 539 dsi_write(dsi, DSI_PWR_UP, RESET); 540 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ); 541 } 542 543 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) 544 { 545 /* 546 * The maximum permitted escape clock is 20MHz and it is derived from 547 * lanebyteclk, which is running at "lane_mbps / 8". Thus we want: 548 * 549 * (lane_mbps >> 3) / esc_clk_division < 20 550 * which is: 551 * (lane_mbps >> 3) / 20 > esc_clk_division 552 */ 553 u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1; 554 555 dsi_write(dsi, DSI_PWR_UP, RESET); 556 557 /* 558 * TODO dw drv improvements 559 * timeout clock division should be computed with the 560 * high speed transmission counter timeout and byte lane... 561 */ 562 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) | 563 TX_ESC_CLK_DIVISION(esc_clk_division)); 564 } 565 566 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, 567 struct drm_display_mode *mode) 568 { 569 u32 val = 0, color = 0; 570 571 switch (dsi->format) { 572 case MIPI_DSI_FMT_RGB888: 573 color = DPI_COLOR_CODING_24BIT; 574 break; 575 case MIPI_DSI_FMT_RGB666: 576 color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN; 577 break; 578 case MIPI_DSI_FMT_RGB666_PACKED: 579 color = DPI_COLOR_CODING_18BIT_1; 580 break; 581 case MIPI_DSI_FMT_RGB565: 582 color = DPI_COLOR_CODING_16BIT_1; 583 break; 584 } 585 586 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 587 val |= VSYNC_ACTIVE_LOW; 588 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 589 val |= HSYNC_ACTIVE_LOW; 590 591 dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel)); 592 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); 593 dsi_write(dsi, DSI_DPI_CFG_POL, val); 594 /* 595 * TODO dw drv improvements 596 * largest packet sizes during hfp or during vsa/vpb/vfp 597 * should be computed according to byte lane, lane number and only 598 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS) 599 */ 600 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4) 601 | INVACT_LPCMD_TIME(4)); 602 } 603 604 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) 605 { 606 dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN); 607 } 608 609 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, 610 struct drm_display_mode *mode) 611 { 612 /* 613 * TODO dw drv improvements 614 * only burst mode is supported here. For non-burst video modes, 615 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC & 616 * DSI_VNPCR.NPSIZE... especially because this driver supports 617 * non-burst video modes, see dw_mipi_dsi_video_mode_config()... 618 */ 619 620 dsi_write(dsi, DSI_VID_PKT_SIZE, 621 dw_mipi_is_dual_mode(dsi) ? 622 VID_PKT_SIZE(mode->hdisplay / 2) : 623 VID_PKT_SIZE(mode->hdisplay)); 624 } 625 626 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) 627 { 628 /* 629 * TODO dw drv improvements 630 * compute high speed transmission counter timeout according 631 * to the timeout clock division (TO_CLK_DIVISION) and byte lane... 632 */ 633 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); 634 /* 635 * TODO dw drv improvements 636 * the Bus-Turn-Around Timeout Counter should be computed 637 * according to byte lane... 638 */ 639 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); 640 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 641 } 642 643 /* Get lane byte clock cycles. */ 644 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, 645 struct drm_display_mode *mode, 646 u32 hcomponent) 647 { 648 u32 frac, lbcc; 649 650 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8; 651 652 frac = lbcc % mode->clock; 653 lbcc = lbcc / mode->clock; 654 if (frac) 655 lbcc++; 656 657 return lbcc; 658 } 659 660 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi, 661 struct drm_display_mode *mode) 662 { 663 u32 htotal, hsa, hbp, lbcc; 664 665 htotal = mode->htotal; 666 hsa = mode->hsync_end - mode->hsync_start; 667 hbp = mode->htotal - mode->hsync_end; 668 669 /* 670 * TODO dw drv improvements 671 * computations below may be improved... 672 */ 673 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal); 674 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); 675 676 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa); 677 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); 678 679 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp); 680 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); 681 } 682 683 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi, 684 struct drm_display_mode *mode) 685 { 686 u32 vactive, vsa, vfp, vbp; 687 688 vactive = mode->vdisplay; 689 vsa = mode->vsync_end - mode->vsync_start; 690 vfp = mode->vsync_start - mode->vdisplay; 691 vbp = mode->vtotal - mode->vsync_end; 692 693 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); 694 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); 695 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); 696 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); 697 } 698 699 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) 700 { 701 u32 hw_version; 702 703 /* 704 * TODO dw drv improvements 705 * data & clock lane timers should be computed according to panel 706 * blankings and to the automatic clock lane control mode... 707 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with 708 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP) 709 */ 710 711 hw_version = dsi_read(dsi, DSI_VERSION) & VERSION; 712 713 if (hw_version >= HWVER_131) { 714 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(0x40) | 715 PHY_LP2HS_TIME_V131(0x40)); 716 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000)); 717 } else { 718 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) | 719 PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000)); 720 } 721 722 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40) 723 | PHY_CLKLP2HS_TIME(0x40)); 724 } 725 726 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) 727 { 728 /* 729 * TODO dw drv improvements 730 * stop wait time should be the maximum between host dsi 731 * and panel stop wait times 732 */ 733 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | 734 N_LANES(dsi->lanes)); 735 } 736 737 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi) 738 { 739 /* Clear PHY state */ 740 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK 741 | PHY_RSTZ | PHY_SHUTDOWNZ); 742 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 743 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR); 744 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 745 } 746 747 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi) 748 { 749 u32 val; 750 int ret; 751 752 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | 753 PHY_UNRSTZ | PHY_UNSHUTDOWNZ); 754 755 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val, 756 val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US); 757 if (ret) 758 DRM_DEBUG_DRIVER("failed to wait phy lock state\n"); 759 760 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 761 val, val & PHY_STOP_STATE_CLK_LANE, 1000, 762 PHY_STATUS_TIMEOUT_US); 763 if (ret) 764 DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n"); 765 } 766 767 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) 768 { 769 dsi_read(dsi, DSI_INT_ST0); 770 dsi_read(dsi, DSI_INT_ST1); 771 dsi_write(dsi, DSI_INT_MSK0, 0); 772 dsi_write(dsi, DSI_INT_MSK1, 0); 773 } 774 775 static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge) 776 { 777 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 778 779 /* 780 * Switch to command mode before panel-bridge post_disable & 781 * panel unprepare. 782 * Note: panel-bridge disable & panel disable has been called 783 * before by the drm framework. 784 */ 785 dw_mipi_dsi_set_mode(dsi, 0); 786 787 /* 788 * TODO Only way found to call panel-bridge post_disable & 789 * panel unprepare before the dsi "final" disable... 790 * This needs to be fixed in the drm_bridge framework and the API 791 * needs to be updated to manage our own call chains... 792 */ 793 dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge); 794 795 if (dsi->slave) { 796 dw_mipi_dsi_disable(dsi->slave); 797 clk_disable_unprepare(dsi->slave->pclk); 798 pm_runtime_put(dsi->slave->dev); 799 } 800 dw_mipi_dsi_disable(dsi); 801 802 clk_disable_unprepare(dsi->pclk); 803 pm_runtime_put(dsi->dev); 804 } 805 806 static unsigned int dw_mipi_dsi_get_lanes(struct dw_mipi_dsi *dsi) 807 { 808 /* this instance is the slave, so add the master's lanes */ 809 if (dsi->master) 810 return dsi->master->lanes + dsi->lanes; 811 812 /* this instance is the master, so add the slave's lanes */ 813 if (dsi->slave) 814 return dsi->lanes + dsi->slave->lanes; 815 816 /* single-dsi, so no other instance to consider */ 817 return dsi->lanes; 818 } 819 820 static void dw_mipi_dsi_mode_set(struct dw_mipi_dsi *dsi, 821 struct drm_display_mode *adjusted_mode) 822 { 823 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 824 void *priv_data = dsi->plat_data->priv_data; 825 int ret; 826 u32 lanes = dw_mipi_dsi_get_lanes(dsi); 827 828 clk_prepare_enable(dsi->pclk); 829 830 ret = phy_ops->get_lane_mbps(priv_data, adjusted_mode, dsi->mode_flags, 831 lanes, dsi->format, &dsi->lane_mbps); 832 if (ret) 833 DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n"); 834 835 pm_runtime_get_sync(dsi->dev); 836 dw_mipi_dsi_init(dsi); 837 dw_mipi_dsi_dpi_config(dsi, adjusted_mode); 838 dw_mipi_dsi_packet_handler_config(dsi); 839 dw_mipi_dsi_video_mode_config(dsi); 840 dw_mipi_dsi_video_packet_config(dsi, adjusted_mode); 841 dw_mipi_dsi_command_mode_config(dsi); 842 dw_mipi_dsi_line_timer_config(dsi, adjusted_mode); 843 dw_mipi_dsi_vertical_timing_config(dsi, adjusted_mode); 844 845 dw_mipi_dsi_dphy_init(dsi); 846 dw_mipi_dsi_dphy_timing_config(dsi); 847 dw_mipi_dsi_dphy_interface_config(dsi); 848 849 dw_mipi_dsi_clear_err(dsi); 850 851 ret = phy_ops->init(priv_data); 852 if (ret) 853 DRM_DEBUG_DRIVER("Phy init() failed\n"); 854 855 dw_mipi_dsi_dphy_enable(dsi); 856 857 dw_mipi_dsi_wait_for_two_frames(adjusted_mode); 858 859 /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */ 860 dw_mipi_dsi_set_mode(dsi, 0); 861 } 862 863 static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge, 864 struct drm_display_mode *mode, 865 struct drm_display_mode *adjusted_mode) 866 { 867 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 868 869 dw_mipi_dsi_mode_set(dsi, adjusted_mode); 870 if (dsi->slave) 871 dw_mipi_dsi_mode_set(dsi->slave, adjusted_mode); 872 } 873 874 static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge) 875 { 876 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 877 878 /* Switch to video mode for panel-bridge enable & panel enable */ 879 dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO); 880 if (dsi->slave) 881 dw_mipi_dsi_set_mode(dsi->slave, MIPI_DSI_MODE_VIDEO); 882 } 883 884 static enum drm_mode_status 885 dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge, 886 const struct drm_display_mode *mode) 887 { 888 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 889 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 890 enum drm_mode_status mode_status = MODE_OK; 891 892 if (pdata->mode_valid) 893 mode_status = pdata->mode_valid(pdata->priv_data, mode); 894 895 return mode_status; 896 } 897 898 static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge) 899 { 900 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 901 902 if (!bridge->encoder) { 903 DRM_ERROR("Parent encoder object not found\n"); 904 return -ENODEV; 905 } 906 907 /* Set the encoder type as caller does not know it */ 908 bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI; 909 910 /* Attach the panel-bridge to the dsi bridge */ 911 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge); 912 } 913 914 static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = { 915 .mode_set = dw_mipi_dsi_bridge_mode_set, 916 .enable = dw_mipi_dsi_bridge_enable, 917 .post_disable = dw_mipi_dsi_bridge_post_disable, 918 .mode_valid = dw_mipi_dsi_bridge_mode_valid, 919 .attach = dw_mipi_dsi_bridge_attach, 920 }; 921 922 static struct dw_mipi_dsi * 923 __dw_mipi_dsi_probe(struct platform_device *pdev, 924 const struct dw_mipi_dsi_plat_data *plat_data) 925 { 926 struct device *dev = &pdev->dev; 927 struct reset_control *apb_rst; 928 struct dw_mipi_dsi *dsi; 929 struct resource *res; 930 int ret; 931 932 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 933 if (!dsi) 934 return ERR_PTR(-ENOMEM); 935 936 dsi->dev = dev; 937 dsi->plat_data = plat_data; 938 939 if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps) { 940 DRM_ERROR("Phy not properly configured\n"); 941 return ERR_PTR(-ENODEV); 942 } 943 944 if (!plat_data->base) { 945 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 946 if (!res) 947 return ERR_PTR(-ENODEV); 948 949 dsi->base = devm_ioremap_resource(dev, res); 950 if (IS_ERR(dsi->base)) 951 return ERR_PTR(-ENODEV); 952 953 } else { 954 dsi->base = plat_data->base; 955 } 956 957 dsi->pclk = devm_clk_get(dev, "pclk"); 958 if (IS_ERR(dsi->pclk)) { 959 ret = PTR_ERR(dsi->pclk); 960 dev_err(dev, "Unable to get pclk: %d\n", ret); 961 return ERR_PTR(ret); 962 } 963 964 /* 965 * Note that the reset was not defined in the initial device tree, so 966 * we have to be prepared for it not being found. 967 */ 968 apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb"); 969 if (IS_ERR(apb_rst)) { 970 ret = PTR_ERR(apb_rst); 971 972 if (ret != -EPROBE_DEFER) 973 dev_err(dev, "Unable to get reset control: %d\n", ret); 974 975 return ERR_PTR(ret); 976 } 977 978 if (apb_rst) { 979 ret = clk_prepare_enable(dsi->pclk); 980 if (ret) { 981 dev_err(dev, "%s: Failed to enable pclk\n", __func__); 982 return ERR_PTR(ret); 983 } 984 985 reset_control_assert(apb_rst); 986 usleep_range(10, 20); 987 reset_control_deassert(apb_rst); 988 989 clk_disable_unprepare(dsi->pclk); 990 } 991 992 pm_runtime_enable(dev); 993 994 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops; 995 dsi->dsi_host.dev = dev; 996 ret = mipi_dsi_host_register(&dsi->dsi_host); 997 if (ret) { 998 dev_err(dev, "Failed to register MIPI host: %d\n", ret); 999 return ERR_PTR(ret); 1000 } 1001 1002 dsi->bridge.driver_private = dsi; 1003 dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs; 1004 #ifdef CONFIG_OF 1005 dsi->bridge.of_node = pdev->dev.of_node; 1006 #endif 1007 1008 return dsi; 1009 } 1010 1011 static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi) 1012 { 1013 mipi_dsi_host_unregister(&dsi->dsi_host); 1014 1015 pm_runtime_disable(dsi->dev); 1016 } 1017 1018 void dw_mipi_dsi_set_slave(struct dw_mipi_dsi *dsi, struct dw_mipi_dsi *slave) 1019 { 1020 /* introduce controllers to each other */ 1021 dsi->slave = slave; 1022 dsi->slave->master = dsi; 1023 1024 /* migrate settings for already attached displays */ 1025 dsi->slave->lanes = dsi->lanes; 1026 dsi->slave->channel = dsi->channel; 1027 dsi->slave->format = dsi->format; 1028 dsi->slave->mode_flags = dsi->mode_flags; 1029 } 1030 EXPORT_SYMBOL_GPL(dw_mipi_dsi_set_slave); 1031 1032 /* 1033 * Probe/remove API, used from platforms based on the DRM bridge API. 1034 */ 1035 struct dw_mipi_dsi * 1036 dw_mipi_dsi_probe(struct platform_device *pdev, 1037 const struct dw_mipi_dsi_plat_data *plat_data) 1038 { 1039 return __dw_mipi_dsi_probe(pdev, plat_data); 1040 } 1041 EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe); 1042 1043 void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi) 1044 { 1045 __dw_mipi_dsi_remove(dsi); 1046 } 1047 EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove); 1048 1049 /* 1050 * Bind/unbind API, used from platforms based on the component framework. 1051 */ 1052 int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder) 1053 { 1054 int ret; 1055 1056 ret = drm_bridge_attach(encoder, &dsi->bridge, NULL); 1057 if (ret) { 1058 DRM_ERROR("Failed to initialize bridge with drm\n"); 1059 return ret; 1060 } 1061 1062 return ret; 1063 } 1064 EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind); 1065 1066 void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi) 1067 { 1068 } 1069 EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind); 1070 1071 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>"); 1072 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1073 MODULE_DESCRIPTION("DW MIPI DSI host controller driver"); 1074 MODULE_LICENSE("GPL"); 1075 MODULE_ALIAS("platform:dw-mipi-dsi"); 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