1 /* 2 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * Modified by Philippe Cornu <philippe.cornu@st.com> 11 * This generic Synopsys DesignWare MIPI DSI host driver is based on the 12 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/component.h> 17 #include <linux/iopoll.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/reset.h> 22 #include <drm/drmP.h> 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_crtc.h> 26 #include <drm/drm_crtc_helper.h> 27 #include <drm/drm_mipi_dsi.h> 28 #include <drm/drm_of.h> 29 #include <drm/bridge/dw_mipi_dsi.h> 30 #include <video/mipi_display.h> 31 32 #define HWVER_131 0x31333100 /* IP version 1.31 */ 33 34 #define DSI_VERSION 0x00 35 #define VERSION GENMASK(31, 8) 36 37 #define DSI_PWR_UP 0x04 38 #define RESET 0 39 #define POWERUP BIT(0) 40 41 #define DSI_CLKMGR_CFG 0x08 42 #define TO_CLK_DIVISION(div) (((div) & 0xff) << 8) 43 #define TX_ESC_CLK_DIVISION(div) ((div) & 0xff) 44 45 #define DSI_DPI_VCID 0x0c 46 #define DPI_VCID(vcid) ((vcid) & 0x3) 47 48 #define DSI_DPI_COLOR_CODING 0x10 49 #define LOOSELY18_EN BIT(8) 50 #define DPI_COLOR_CODING_16BIT_1 0x0 51 #define DPI_COLOR_CODING_16BIT_2 0x1 52 #define DPI_COLOR_CODING_16BIT_3 0x2 53 #define DPI_COLOR_CODING_18BIT_1 0x3 54 #define DPI_COLOR_CODING_18BIT_2 0x4 55 #define DPI_COLOR_CODING_24BIT 0x5 56 57 #define DSI_DPI_CFG_POL 0x14 58 #define COLORM_ACTIVE_LOW BIT(4) 59 #define SHUTD_ACTIVE_LOW BIT(3) 60 #define HSYNC_ACTIVE_LOW BIT(2) 61 #define VSYNC_ACTIVE_LOW BIT(1) 62 #define DATAEN_ACTIVE_LOW BIT(0) 63 64 #define DSI_DPI_LP_CMD_TIM 0x18 65 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) 66 #define INVACT_LPCMD_TIME(p) ((p) & 0xff) 67 68 #define DSI_DBI_VCID 0x1c 69 #define DSI_DBI_CFG 0x20 70 #define DSI_DBI_PARTITIONING_EN 0x24 71 #define DSI_DBI_CMDSIZE 0x28 72 73 #define DSI_PCKHDL_CFG 0x2c 74 #define CRC_RX_EN BIT(4) 75 #define ECC_RX_EN BIT(3) 76 #define BTA_EN BIT(2) 77 #define EOTP_RX_EN BIT(1) 78 #define EOTP_TX_EN BIT(0) 79 80 #define DSI_GEN_VCID 0x30 81 82 #define DSI_MODE_CFG 0x34 83 #define ENABLE_VIDEO_MODE 0 84 #define ENABLE_CMD_MODE BIT(0) 85 86 #define DSI_VID_MODE_CFG 0x38 87 #define ENABLE_LOW_POWER (0x3f << 8) 88 #define ENABLE_LOW_POWER_MASK (0x3f << 8) 89 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0 90 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1 91 #define VID_MODE_TYPE_BURST 0x2 92 #define VID_MODE_TYPE_MASK 0x3 93 94 #define DSI_VID_PKT_SIZE 0x3c 95 #define VID_PKT_SIZE(p) ((p) & 0x3fff) 96 97 #define DSI_VID_NUM_CHUNKS 0x40 98 #define VID_NUM_CHUNKS(c) ((c) & 0x1fff) 99 100 #define DSI_VID_NULL_SIZE 0x44 101 #define VID_NULL_SIZE(b) ((b) & 0x1fff) 102 103 #define DSI_VID_HSA_TIME 0x48 104 #define DSI_VID_HBP_TIME 0x4c 105 #define DSI_VID_HLINE_TIME 0x50 106 #define DSI_VID_VSA_LINES 0x54 107 #define DSI_VID_VBP_LINES 0x58 108 #define DSI_VID_VFP_LINES 0x5c 109 #define DSI_VID_VACTIVE_LINES 0x60 110 #define DSI_EDPI_CMD_SIZE 0x64 111 112 #define DSI_CMD_MODE_CFG 0x68 113 #define MAX_RD_PKT_SIZE_LP BIT(24) 114 #define DCS_LW_TX_LP BIT(19) 115 #define DCS_SR_0P_TX_LP BIT(18) 116 #define DCS_SW_1P_TX_LP BIT(17) 117 #define DCS_SW_0P_TX_LP BIT(16) 118 #define GEN_LW_TX_LP BIT(14) 119 #define GEN_SR_2P_TX_LP BIT(13) 120 #define GEN_SR_1P_TX_LP BIT(12) 121 #define GEN_SR_0P_TX_LP BIT(11) 122 #define GEN_SW_2P_TX_LP BIT(10) 123 #define GEN_SW_1P_TX_LP BIT(9) 124 #define GEN_SW_0P_TX_LP BIT(8) 125 #define ACK_RQST_EN BIT(1) 126 #define TEAR_FX_EN BIT(0) 127 128 #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \ 129 DCS_LW_TX_LP | \ 130 DCS_SR_0P_TX_LP | \ 131 DCS_SW_1P_TX_LP | \ 132 DCS_SW_0P_TX_LP | \ 133 GEN_LW_TX_LP | \ 134 GEN_SR_2P_TX_LP | \ 135 GEN_SR_1P_TX_LP | \ 136 GEN_SR_0P_TX_LP | \ 137 GEN_SW_2P_TX_LP | \ 138 GEN_SW_1P_TX_LP | \ 139 GEN_SW_0P_TX_LP) 140 141 #define DSI_GEN_HDR 0x6c 142 #define DSI_GEN_PLD_DATA 0x70 143 144 #define DSI_CMD_PKT_STATUS 0x74 145 #define GEN_RD_CMD_BUSY BIT(6) 146 #define GEN_PLD_R_FULL BIT(5) 147 #define GEN_PLD_R_EMPTY BIT(4) 148 #define GEN_PLD_W_FULL BIT(3) 149 #define GEN_PLD_W_EMPTY BIT(2) 150 #define GEN_CMD_FULL BIT(1) 151 #define GEN_CMD_EMPTY BIT(0) 152 153 #define DSI_TO_CNT_CFG 0x78 154 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16) 155 #define LPRX_TO_CNT(p) ((p) & 0xffff) 156 157 #define DSI_HS_RD_TO_CNT 0x7c 158 #define DSI_LP_RD_TO_CNT 0x80 159 #define DSI_HS_WR_TO_CNT 0x84 160 #define DSI_LP_WR_TO_CNT 0x88 161 #define DSI_BTA_TO_CNT 0x8c 162 163 #define DSI_LPCLK_CTRL 0x94 164 #define AUTO_CLKLANE_CTRL BIT(1) 165 #define PHY_TXREQUESTCLKHS BIT(0) 166 167 #define DSI_PHY_TMR_LPCLK_CFG 0x98 168 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16) 169 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff) 170 171 #define DSI_PHY_TMR_CFG 0x9c 172 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24) 173 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16) 174 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) 175 #define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16) 176 #define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff) 177 178 #define DSI_PHY_RSTZ 0xa0 179 #define PHY_DISFORCEPLL 0 180 #define PHY_ENFORCEPLL BIT(3) 181 #define PHY_DISABLECLK 0 182 #define PHY_ENABLECLK BIT(2) 183 #define PHY_RSTZ 0 184 #define PHY_UNRSTZ BIT(1) 185 #define PHY_SHUTDOWNZ 0 186 #define PHY_UNSHUTDOWNZ BIT(0) 187 188 #define DSI_PHY_IF_CFG 0xa4 189 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 190 #define N_LANES(n) (((n) - 1) & 0x3) 191 192 #define DSI_PHY_ULPS_CTRL 0xa8 193 #define DSI_PHY_TX_TRIGGERS 0xac 194 195 #define DSI_PHY_STATUS 0xb0 196 #define PHY_STOP_STATE_CLK_LANE BIT(2) 197 #define PHY_LOCK BIT(0) 198 199 #define DSI_PHY_TST_CTRL0 0xb4 200 #define PHY_TESTCLK BIT(1) 201 #define PHY_UNTESTCLK 0 202 #define PHY_TESTCLR BIT(0) 203 #define PHY_UNTESTCLR 0 204 205 #define DSI_PHY_TST_CTRL1 0xb8 206 #define PHY_TESTEN BIT(16) 207 #define PHY_UNTESTEN 0 208 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 209 #define PHY_TESTDIN(n) ((n) & 0xff) 210 211 #define DSI_INT_ST0 0xbc 212 #define DSI_INT_ST1 0xc0 213 #define DSI_INT_MSK0 0xc4 214 #define DSI_INT_MSK1 0xc8 215 216 #define DSI_PHY_TMR_RD_CFG 0xf4 217 #define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff) 218 219 #define PHY_STATUS_TIMEOUT_US 10000 220 #define CMD_PKT_STATUS_TIMEOUT_US 20000 221 222 struct dw_mipi_dsi { 223 struct drm_bridge bridge; 224 struct mipi_dsi_host dsi_host; 225 struct drm_bridge *panel_bridge; 226 struct device *dev; 227 void __iomem *base; 228 229 struct clk *pclk; 230 231 unsigned int lane_mbps; /* per lane */ 232 u32 channel; 233 u32 lanes; 234 u32 format; 235 unsigned long mode_flags; 236 237 const struct dw_mipi_dsi_plat_data *plat_data; 238 }; 239 240 /* 241 * The controller should generate 2 frames before 242 * preparing the peripheral. 243 */ 244 static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode *mode) 245 { 246 int refresh, two_frames; 247 248 refresh = drm_mode_vrefresh(mode); 249 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2; 250 msleep(two_frames); 251 } 252 253 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host) 254 { 255 return container_of(host, struct dw_mipi_dsi, dsi_host); 256 } 257 258 static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge) 259 { 260 return container_of(bridge, struct dw_mipi_dsi, bridge); 261 } 262 263 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) 264 { 265 writel(val, dsi->base + reg); 266 } 267 268 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) 269 { 270 return readl(dsi->base + reg); 271 } 272 273 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 274 struct mipi_dsi_device *device) 275 { 276 struct dw_mipi_dsi *dsi = host_to_dsi(host); 277 struct drm_bridge *bridge; 278 struct drm_panel *panel; 279 int ret; 280 281 if (device->lanes > dsi->plat_data->max_data_lanes) { 282 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n", 283 device->lanes); 284 return -EINVAL; 285 } 286 287 dsi->lanes = device->lanes; 288 dsi->channel = device->channel; 289 dsi->format = device->format; 290 dsi->mode_flags = device->mode_flags; 291 292 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, 293 &panel, &bridge); 294 if (ret) 295 return ret; 296 297 if (panel) { 298 bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DSI); 299 if (IS_ERR(bridge)) 300 return PTR_ERR(bridge); 301 } 302 303 dsi->panel_bridge = bridge; 304 305 drm_bridge_add(&dsi->bridge); 306 307 return 0; 308 } 309 310 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, 311 struct mipi_dsi_device *device) 312 { 313 struct dw_mipi_dsi *dsi = host_to_dsi(host); 314 315 drm_of_panel_bridge_remove(host->dev->of_node, 1, 0); 316 317 drm_bridge_remove(&dsi->bridge); 318 319 return 0; 320 } 321 322 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, 323 const struct mipi_dsi_msg *msg) 324 { 325 bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM; 326 u32 val = 0; 327 328 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) 329 val |= ACK_RQST_EN; 330 if (lpm) 331 val |= CMD_MODE_ALL_LP; 332 333 dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS); 334 dsi_write(dsi, DSI_CMD_MODE_CFG, val); 335 } 336 337 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) 338 { 339 int ret; 340 u32 val, mask; 341 342 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 343 val, !(val & GEN_CMD_FULL), 1000, 344 CMD_PKT_STATUS_TIMEOUT_US); 345 if (ret) { 346 dev_err(dsi->dev, "failed to get available command FIFO\n"); 347 return ret; 348 } 349 350 dsi_write(dsi, DSI_GEN_HDR, hdr_val); 351 352 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 353 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 354 val, (val & mask) == mask, 355 1000, CMD_PKT_STATUS_TIMEOUT_US); 356 if (ret) { 357 dev_err(dsi->dev, "failed to write command FIFO\n"); 358 return ret; 359 } 360 361 return 0; 362 } 363 364 static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi, 365 const struct mipi_dsi_packet *packet) 366 { 367 const u8 *tx_buf = packet->payload; 368 int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret; 369 __le32 word; 370 u32 val; 371 372 while (len) { 373 if (len < pld_data_bytes) { 374 word = 0; 375 memcpy(&word, tx_buf, len); 376 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word)); 377 len = 0; 378 } else { 379 memcpy(&word, tx_buf, pld_data_bytes); 380 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word)); 381 tx_buf += pld_data_bytes; 382 len -= pld_data_bytes; 383 } 384 385 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 386 val, !(val & GEN_PLD_W_FULL), 1000, 387 CMD_PKT_STATUS_TIMEOUT_US); 388 if (ret) { 389 dev_err(dsi->dev, 390 "failed to get available write payload FIFO\n"); 391 return ret; 392 } 393 } 394 395 word = 0; 396 memcpy(&word, packet->header, sizeof(packet->header)); 397 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word)); 398 } 399 400 static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi, 401 const struct mipi_dsi_msg *msg) 402 { 403 int i, j, ret, len = msg->rx_len; 404 u8 *buf = msg->rx_buf; 405 u32 val; 406 407 /* Wait end of the read operation */ 408 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 409 val, !(val & GEN_RD_CMD_BUSY), 410 1000, CMD_PKT_STATUS_TIMEOUT_US); 411 if (ret) { 412 dev_err(dsi->dev, "Timeout during read operation\n"); 413 return ret; 414 } 415 416 for (i = 0; i < len; i += 4) { 417 /* Read fifo must not be empty before all bytes are read */ 418 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 419 val, !(val & GEN_PLD_R_EMPTY), 420 1000, CMD_PKT_STATUS_TIMEOUT_US); 421 if (ret) { 422 dev_err(dsi->dev, "Read payload FIFO is empty\n"); 423 return ret; 424 } 425 426 val = dsi_read(dsi, DSI_GEN_PLD_DATA); 427 for (j = 0; j < 4 && j + i < len; j++) 428 buf[i + j] = val >> (8 * j); 429 } 430 431 return ret; 432 } 433 434 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, 435 const struct mipi_dsi_msg *msg) 436 { 437 struct dw_mipi_dsi *dsi = host_to_dsi(host); 438 struct mipi_dsi_packet packet; 439 int ret, nb_bytes; 440 441 ret = mipi_dsi_create_packet(&packet, msg); 442 if (ret) { 443 dev_err(dsi->dev, "failed to create packet: %d\n", ret); 444 return ret; 445 } 446 447 dw_mipi_message_config(dsi, msg); 448 449 ret = dw_mipi_dsi_write(dsi, &packet); 450 if (ret) 451 return ret; 452 453 if (msg->rx_buf && msg->rx_len) { 454 ret = dw_mipi_dsi_read(dsi, msg); 455 if (ret) 456 return ret; 457 nb_bytes = msg->rx_len; 458 } else { 459 nb_bytes = packet.size; 460 } 461 462 return nb_bytes; 463 } 464 465 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = { 466 .attach = dw_mipi_dsi_host_attach, 467 .detach = dw_mipi_dsi_host_detach, 468 .transfer = dw_mipi_dsi_host_transfer, 469 }; 470 471 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) 472 { 473 u32 val; 474 475 /* 476 * TODO dw drv improvements 477 * enabling low power is panel-dependent, we should use the 478 * panel configuration here... 479 */ 480 val = ENABLE_LOW_POWER; 481 482 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 483 val |= VID_MODE_TYPE_BURST; 484 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 485 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 486 else 487 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 488 489 dsi_write(dsi, DSI_VID_MODE_CFG, val); 490 } 491 492 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, 493 unsigned long mode_flags) 494 { 495 dsi_write(dsi, DSI_PWR_UP, RESET); 496 497 if (mode_flags & MIPI_DSI_MODE_VIDEO) { 498 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE); 499 dw_mipi_dsi_video_mode_config(dsi); 500 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); 501 } else { 502 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 503 } 504 505 dsi_write(dsi, DSI_PWR_UP, POWERUP); 506 } 507 508 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) 509 { 510 dsi_write(dsi, DSI_PWR_UP, RESET); 511 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ); 512 } 513 514 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) 515 { 516 /* 517 * The maximum permitted escape clock is 20MHz and it is derived from 518 * lanebyteclk, which is running at "lane_mbps / 8". Thus we want: 519 * 520 * (lane_mbps >> 3) / esc_clk_division < 20 521 * which is: 522 * (lane_mbps >> 3) / 20 > esc_clk_division 523 */ 524 u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1; 525 526 dsi_write(dsi, DSI_PWR_UP, RESET); 527 528 /* 529 * TODO dw drv improvements 530 * timeout clock division should be computed with the 531 * high speed transmission counter timeout and byte lane... 532 */ 533 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) | 534 TX_ESC_CLK_DIVISION(esc_clk_division)); 535 } 536 537 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, 538 struct drm_display_mode *mode) 539 { 540 u32 val = 0, color = 0; 541 542 switch (dsi->format) { 543 case MIPI_DSI_FMT_RGB888: 544 color = DPI_COLOR_CODING_24BIT; 545 break; 546 case MIPI_DSI_FMT_RGB666: 547 color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN; 548 break; 549 case MIPI_DSI_FMT_RGB666_PACKED: 550 color = DPI_COLOR_CODING_18BIT_1; 551 break; 552 case MIPI_DSI_FMT_RGB565: 553 color = DPI_COLOR_CODING_16BIT_1; 554 break; 555 } 556 557 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 558 val |= VSYNC_ACTIVE_LOW; 559 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 560 val |= HSYNC_ACTIVE_LOW; 561 562 dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel)); 563 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); 564 dsi_write(dsi, DSI_DPI_CFG_POL, val); 565 /* 566 * TODO dw drv improvements 567 * largest packet sizes during hfp or during vsa/vpb/vfp 568 * should be computed according to byte lane, lane number and only 569 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS) 570 */ 571 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4) 572 | INVACT_LPCMD_TIME(4)); 573 } 574 575 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) 576 { 577 dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN); 578 } 579 580 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, 581 struct drm_display_mode *mode) 582 { 583 /* 584 * TODO dw drv improvements 585 * only burst mode is supported here. For non-burst video modes, 586 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC & 587 * DSI_VNPCR.NPSIZE... especially because this driver supports 588 * non-burst video modes, see dw_mipi_dsi_video_mode_config()... 589 */ 590 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay)); 591 } 592 593 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) 594 { 595 /* 596 * TODO dw drv improvements 597 * compute high speed transmission counter timeout according 598 * to the timeout clock division (TO_CLK_DIVISION) and byte lane... 599 */ 600 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); 601 /* 602 * TODO dw drv improvements 603 * the Bus-Turn-Around Timeout Counter should be computed 604 * according to byte lane... 605 */ 606 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); 607 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 608 } 609 610 /* Get lane byte clock cycles. */ 611 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, 612 struct drm_display_mode *mode, 613 u32 hcomponent) 614 { 615 u32 frac, lbcc; 616 617 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8; 618 619 frac = lbcc % mode->clock; 620 lbcc = lbcc / mode->clock; 621 if (frac) 622 lbcc++; 623 624 return lbcc; 625 } 626 627 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi, 628 struct drm_display_mode *mode) 629 { 630 u32 htotal, hsa, hbp, lbcc; 631 632 htotal = mode->htotal; 633 hsa = mode->hsync_end - mode->hsync_start; 634 hbp = mode->htotal - mode->hsync_end; 635 636 /* 637 * TODO dw drv improvements 638 * computations below may be improved... 639 */ 640 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal); 641 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); 642 643 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa); 644 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); 645 646 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp); 647 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); 648 } 649 650 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi, 651 struct drm_display_mode *mode) 652 { 653 u32 vactive, vsa, vfp, vbp; 654 655 vactive = mode->vdisplay; 656 vsa = mode->vsync_end - mode->vsync_start; 657 vfp = mode->vsync_start - mode->vdisplay; 658 vbp = mode->vtotal - mode->vsync_end; 659 660 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); 661 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); 662 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); 663 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); 664 } 665 666 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) 667 { 668 u32 hw_version; 669 670 /* 671 * TODO dw drv improvements 672 * data & clock lane timers should be computed according to panel 673 * blankings and to the automatic clock lane control mode... 674 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with 675 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP) 676 */ 677 678 hw_version = dsi_read(dsi, DSI_VERSION) & VERSION; 679 680 if (hw_version >= HWVER_131) { 681 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(0x40) | 682 PHY_LP2HS_TIME_V131(0x40)); 683 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000)); 684 } else { 685 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) | 686 PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000)); 687 } 688 689 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40) 690 | PHY_CLKLP2HS_TIME(0x40)); 691 } 692 693 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) 694 { 695 /* 696 * TODO dw drv improvements 697 * stop wait time should be the maximum between host dsi 698 * and panel stop wait times 699 */ 700 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | 701 N_LANES(dsi->lanes)); 702 } 703 704 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi) 705 { 706 /* Clear PHY state */ 707 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK 708 | PHY_RSTZ | PHY_SHUTDOWNZ); 709 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 710 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR); 711 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 712 } 713 714 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi) 715 { 716 u32 val; 717 int ret; 718 719 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | 720 PHY_UNRSTZ | PHY_UNSHUTDOWNZ); 721 722 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val, 723 val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US); 724 if (ret) 725 DRM_DEBUG_DRIVER("failed to wait phy lock state\n"); 726 727 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 728 val, val & PHY_STOP_STATE_CLK_LANE, 1000, 729 PHY_STATUS_TIMEOUT_US); 730 if (ret) 731 DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n"); 732 } 733 734 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) 735 { 736 dsi_read(dsi, DSI_INT_ST0); 737 dsi_read(dsi, DSI_INT_ST1); 738 dsi_write(dsi, DSI_INT_MSK0, 0); 739 dsi_write(dsi, DSI_INT_MSK1, 0); 740 } 741 742 static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge) 743 { 744 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 745 746 /* 747 * Switch to command mode before panel-bridge post_disable & 748 * panel unprepare. 749 * Note: panel-bridge disable & panel disable has been called 750 * before by the drm framework. 751 */ 752 dw_mipi_dsi_set_mode(dsi, 0); 753 754 /* 755 * TODO Only way found to call panel-bridge post_disable & 756 * panel unprepare before the dsi "final" disable... 757 * This needs to be fixed in the drm_bridge framework and the API 758 * needs to be updated to manage our own call chains... 759 */ 760 dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge); 761 762 dw_mipi_dsi_disable(dsi); 763 clk_disable_unprepare(dsi->pclk); 764 pm_runtime_put(dsi->dev); 765 } 766 767 static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge, 768 struct drm_display_mode *mode, 769 struct drm_display_mode *adjusted_mode) 770 { 771 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 772 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 773 void *priv_data = dsi->plat_data->priv_data; 774 int ret; 775 776 clk_prepare_enable(dsi->pclk); 777 778 ret = phy_ops->get_lane_mbps(priv_data, mode, dsi->mode_flags, 779 dsi->lanes, dsi->format, &dsi->lane_mbps); 780 if (ret) 781 DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n"); 782 783 pm_runtime_get_sync(dsi->dev); 784 dw_mipi_dsi_init(dsi); 785 dw_mipi_dsi_dpi_config(dsi, mode); 786 dw_mipi_dsi_packet_handler_config(dsi); 787 dw_mipi_dsi_video_mode_config(dsi); 788 dw_mipi_dsi_video_packet_config(dsi, mode); 789 dw_mipi_dsi_command_mode_config(dsi); 790 dw_mipi_dsi_line_timer_config(dsi, mode); 791 dw_mipi_dsi_vertical_timing_config(dsi, mode); 792 793 dw_mipi_dsi_dphy_init(dsi); 794 dw_mipi_dsi_dphy_timing_config(dsi); 795 dw_mipi_dsi_dphy_interface_config(dsi); 796 797 dw_mipi_dsi_clear_err(dsi); 798 799 ret = phy_ops->init(priv_data); 800 if (ret) 801 DRM_DEBUG_DRIVER("Phy init() failed\n"); 802 803 dw_mipi_dsi_dphy_enable(dsi); 804 805 dw_mipi_dsi_wait_for_two_frames(mode); 806 807 /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */ 808 dw_mipi_dsi_set_mode(dsi, 0); 809 } 810 811 static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge) 812 { 813 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 814 815 /* Switch to video mode for panel-bridge enable & panel enable */ 816 dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO); 817 } 818 819 static enum drm_mode_status 820 dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge, 821 const struct drm_display_mode *mode) 822 { 823 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 824 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 825 enum drm_mode_status mode_status = MODE_OK; 826 827 if (pdata->mode_valid) 828 mode_status = pdata->mode_valid(pdata->priv_data, mode); 829 830 return mode_status; 831 } 832 833 static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge) 834 { 835 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 836 837 if (!bridge->encoder) { 838 DRM_ERROR("Parent encoder object not found\n"); 839 return -ENODEV; 840 } 841 842 /* Set the encoder type as caller does not know it */ 843 bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI; 844 845 /* Attach the panel-bridge to the dsi bridge */ 846 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge); 847 } 848 849 static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = { 850 .mode_set = dw_mipi_dsi_bridge_mode_set, 851 .enable = dw_mipi_dsi_bridge_enable, 852 .post_disable = dw_mipi_dsi_bridge_post_disable, 853 .mode_valid = dw_mipi_dsi_bridge_mode_valid, 854 .attach = dw_mipi_dsi_bridge_attach, 855 }; 856 857 static struct dw_mipi_dsi * 858 __dw_mipi_dsi_probe(struct platform_device *pdev, 859 const struct dw_mipi_dsi_plat_data *plat_data) 860 { 861 struct device *dev = &pdev->dev; 862 struct reset_control *apb_rst; 863 struct dw_mipi_dsi *dsi; 864 struct resource *res; 865 int ret; 866 867 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 868 if (!dsi) 869 return ERR_PTR(-ENOMEM); 870 871 dsi->dev = dev; 872 dsi->plat_data = plat_data; 873 874 if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps) { 875 DRM_ERROR("Phy not properly configured\n"); 876 return ERR_PTR(-ENODEV); 877 } 878 879 if (!plat_data->base) { 880 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 881 if (!res) 882 return ERR_PTR(-ENODEV); 883 884 dsi->base = devm_ioremap_resource(dev, res); 885 if (IS_ERR(dsi->base)) 886 return ERR_PTR(-ENODEV); 887 888 } else { 889 dsi->base = plat_data->base; 890 } 891 892 dsi->pclk = devm_clk_get(dev, "pclk"); 893 if (IS_ERR(dsi->pclk)) { 894 ret = PTR_ERR(dsi->pclk); 895 dev_err(dev, "Unable to get pclk: %d\n", ret); 896 return ERR_PTR(ret); 897 } 898 899 /* 900 * Note that the reset was not defined in the initial device tree, so 901 * we have to be prepared for it not being found. 902 */ 903 apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb"); 904 if (IS_ERR(apb_rst)) { 905 ret = PTR_ERR(apb_rst); 906 907 if (ret != -EPROBE_DEFER) 908 dev_err(dev, "Unable to get reset control: %d\n", ret); 909 910 return ERR_PTR(ret); 911 } 912 913 if (apb_rst) { 914 ret = clk_prepare_enable(dsi->pclk); 915 if (ret) { 916 dev_err(dev, "%s: Failed to enable pclk\n", __func__); 917 return ERR_PTR(ret); 918 } 919 920 reset_control_assert(apb_rst); 921 usleep_range(10, 20); 922 reset_control_deassert(apb_rst); 923 924 clk_disable_unprepare(dsi->pclk); 925 } 926 927 pm_runtime_enable(dev); 928 929 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops; 930 dsi->dsi_host.dev = dev; 931 ret = mipi_dsi_host_register(&dsi->dsi_host); 932 if (ret) { 933 dev_err(dev, "Failed to register MIPI host: %d\n", ret); 934 return ERR_PTR(ret); 935 } 936 937 dsi->bridge.driver_private = dsi; 938 dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs; 939 #ifdef CONFIG_OF 940 dsi->bridge.of_node = pdev->dev.of_node; 941 #endif 942 943 return dsi; 944 } 945 946 static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi) 947 { 948 pm_runtime_disable(dsi->dev); 949 } 950 951 /* 952 * Probe/remove API, used from platforms based on the DRM bridge API. 953 */ 954 struct dw_mipi_dsi * 955 dw_mipi_dsi_probe(struct platform_device *pdev, 956 const struct dw_mipi_dsi_plat_data *plat_data) 957 { 958 return __dw_mipi_dsi_probe(pdev, plat_data); 959 } 960 EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe); 961 962 void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi) 963 { 964 mipi_dsi_host_unregister(&dsi->dsi_host); 965 966 __dw_mipi_dsi_remove(dsi); 967 } 968 EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove); 969 970 /* 971 * Bind/unbind API, used from platforms based on the component framework. 972 */ 973 struct dw_mipi_dsi * 974 dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder, 975 const struct dw_mipi_dsi_plat_data *plat_data) 976 { 977 struct dw_mipi_dsi *dsi; 978 int ret; 979 980 dsi = __dw_mipi_dsi_probe(pdev, plat_data); 981 if (IS_ERR(dsi)) 982 return dsi; 983 984 ret = drm_bridge_attach(encoder, &dsi->bridge, NULL); 985 if (ret) { 986 dw_mipi_dsi_remove(dsi); 987 DRM_ERROR("Failed to initialize bridge with drm\n"); 988 return ERR_PTR(ret); 989 } 990 991 return dsi; 992 } 993 EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind); 994 995 void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi) 996 { 997 __dw_mipi_dsi_remove(dsi); 998 } 999 EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind); 1000 1001 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>"); 1002 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1003 MODULE_DESCRIPTION("DW MIPI DSI host controller driver"); 1004 MODULE_LICENSE("GPL"); 1005 MODULE_ALIAS("platform:dw-mipi-dsi"); 1006