1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd 4 * Copyright (C) STMicroelectronics SA 2017 5 * 6 * Modified by Philippe Cornu <philippe.cornu@st.com> 7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the 8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs. 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/debugfs.h> 14 #include <linux/iopoll.h> 15 #include <linux/module.h> 16 #include <linux/of_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/reset.h> 19 20 #include <video/mipi_display.h> 21 22 #include <drm/bridge/dw_mipi_dsi.h> 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_crtc.h> 26 #include <drm/drm_mipi_dsi.h> 27 #include <drm/drm_modes.h> 28 #include <drm/drm_of.h> 29 #include <drm/drm_print.h> 30 31 #define HWVER_131 0x31333100 /* IP version 1.31 */ 32 33 #define DSI_VERSION 0x00 34 #define VERSION GENMASK(31, 8) 35 36 #define DSI_PWR_UP 0x04 37 #define RESET 0 38 #define POWERUP BIT(0) 39 40 #define DSI_CLKMGR_CFG 0x08 41 #define TO_CLK_DIVISION(div) (((div) & 0xff) << 8) 42 #define TX_ESC_CLK_DIVISION(div) ((div) & 0xff) 43 44 #define DSI_DPI_VCID 0x0c 45 #define DPI_VCID(vcid) ((vcid) & 0x3) 46 47 #define DSI_DPI_COLOR_CODING 0x10 48 #define LOOSELY18_EN BIT(8) 49 #define DPI_COLOR_CODING_16BIT_1 0x0 50 #define DPI_COLOR_CODING_16BIT_2 0x1 51 #define DPI_COLOR_CODING_16BIT_3 0x2 52 #define DPI_COLOR_CODING_18BIT_1 0x3 53 #define DPI_COLOR_CODING_18BIT_2 0x4 54 #define DPI_COLOR_CODING_24BIT 0x5 55 56 #define DSI_DPI_CFG_POL 0x14 57 #define COLORM_ACTIVE_LOW BIT(4) 58 #define SHUTD_ACTIVE_LOW BIT(3) 59 #define HSYNC_ACTIVE_LOW BIT(2) 60 #define VSYNC_ACTIVE_LOW BIT(1) 61 #define DATAEN_ACTIVE_LOW BIT(0) 62 63 #define DSI_DPI_LP_CMD_TIM 0x18 64 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) 65 #define INVACT_LPCMD_TIME(p) ((p) & 0xff) 66 67 #define DSI_DBI_VCID 0x1c 68 #define DSI_DBI_CFG 0x20 69 #define DSI_DBI_PARTITIONING_EN 0x24 70 #define DSI_DBI_CMDSIZE 0x28 71 72 #define DSI_PCKHDL_CFG 0x2c 73 #define CRC_RX_EN BIT(4) 74 #define ECC_RX_EN BIT(3) 75 #define BTA_EN BIT(2) 76 #define EOTP_RX_EN BIT(1) 77 #define EOTP_TX_EN BIT(0) 78 79 #define DSI_GEN_VCID 0x30 80 81 #define DSI_MODE_CFG 0x34 82 #define ENABLE_VIDEO_MODE 0 83 #define ENABLE_CMD_MODE BIT(0) 84 85 #define DSI_VID_MODE_CFG 0x38 86 #define ENABLE_LOW_POWER (0x3f << 8) 87 #define ENABLE_LOW_POWER_MASK (0x3f << 8) 88 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0 89 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1 90 #define VID_MODE_TYPE_BURST 0x2 91 #define VID_MODE_TYPE_MASK 0x3 92 #define ENABLE_LOW_POWER_CMD BIT(15) 93 #define VID_MODE_VPG_ENABLE BIT(16) 94 #define VID_MODE_VPG_MODE BIT(20) 95 #define VID_MODE_VPG_HORIZONTAL BIT(24) 96 97 #define DSI_VID_PKT_SIZE 0x3c 98 #define VID_PKT_SIZE(p) ((p) & 0x3fff) 99 100 #define DSI_VID_NUM_CHUNKS 0x40 101 #define VID_NUM_CHUNKS(c) ((c) & 0x1fff) 102 103 #define DSI_VID_NULL_SIZE 0x44 104 #define VID_NULL_SIZE(b) ((b) & 0x1fff) 105 106 #define DSI_VID_HSA_TIME 0x48 107 #define DSI_VID_HBP_TIME 0x4c 108 #define DSI_VID_HLINE_TIME 0x50 109 #define DSI_VID_VSA_LINES 0x54 110 #define DSI_VID_VBP_LINES 0x58 111 #define DSI_VID_VFP_LINES 0x5c 112 #define DSI_VID_VACTIVE_LINES 0x60 113 #define DSI_EDPI_CMD_SIZE 0x64 114 115 #define DSI_CMD_MODE_CFG 0x68 116 #define MAX_RD_PKT_SIZE_LP BIT(24) 117 #define DCS_LW_TX_LP BIT(19) 118 #define DCS_SR_0P_TX_LP BIT(18) 119 #define DCS_SW_1P_TX_LP BIT(17) 120 #define DCS_SW_0P_TX_LP BIT(16) 121 #define GEN_LW_TX_LP BIT(14) 122 #define GEN_SR_2P_TX_LP BIT(13) 123 #define GEN_SR_1P_TX_LP BIT(12) 124 #define GEN_SR_0P_TX_LP BIT(11) 125 #define GEN_SW_2P_TX_LP BIT(10) 126 #define GEN_SW_1P_TX_LP BIT(9) 127 #define GEN_SW_0P_TX_LP BIT(8) 128 #define ACK_RQST_EN BIT(1) 129 #define TEAR_FX_EN BIT(0) 130 131 #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \ 132 DCS_LW_TX_LP | \ 133 DCS_SR_0P_TX_LP | \ 134 DCS_SW_1P_TX_LP | \ 135 DCS_SW_0P_TX_LP | \ 136 GEN_LW_TX_LP | \ 137 GEN_SR_2P_TX_LP | \ 138 GEN_SR_1P_TX_LP | \ 139 GEN_SR_0P_TX_LP | \ 140 GEN_SW_2P_TX_LP | \ 141 GEN_SW_1P_TX_LP | \ 142 GEN_SW_0P_TX_LP) 143 144 #define DSI_GEN_HDR 0x6c 145 #define DSI_GEN_PLD_DATA 0x70 146 147 #define DSI_CMD_PKT_STATUS 0x74 148 #define GEN_RD_CMD_BUSY BIT(6) 149 #define GEN_PLD_R_FULL BIT(5) 150 #define GEN_PLD_R_EMPTY BIT(4) 151 #define GEN_PLD_W_FULL BIT(3) 152 #define GEN_PLD_W_EMPTY BIT(2) 153 #define GEN_CMD_FULL BIT(1) 154 #define GEN_CMD_EMPTY BIT(0) 155 156 #define DSI_TO_CNT_CFG 0x78 157 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16) 158 #define LPRX_TO_CNT(p) ((p) & 0xffff) 159 160 #define DSI_HS_RD_TO_CNT 0x7c 161 #define DSI_LP_RD_TO_CNT 0x80 162 #define DSI_HS_WR_TO_CNT 0x84 163 #define DSI_LP_WR_TO_CNT 0x88 164 #define DSI_BTA_TO_CNT 0x8c 165 166 #define DSI_LPCLK_CTRL 0x94 167 #define AUTO_CLKLANE_CTRL BIT(1) 168 #define PHY_TXREQUESTCLKHS BIT(0) 169 170 #define DSI_PHY_TMR_LPCLK_CFG 0x98 171 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16) 172 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff) 173 174 #define DSI_PHY_TMR_CFG 0x9c 175 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24) 176 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16) 177 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) 178 #define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16) 179 #define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff) 180 181 #define DSI_PHY_RSTZ 0xa0 182 #define PHY_DISFORCEPLL 0 183 #define PHY_ENFORCEPLL BIT(3) 184 #define PHY_DISABLECLK 0 185 #define PHY_ENABLECLK BIT(2) 186 #define PHY_RSTZ 0 187 #define PHY_UNRSTZ BIT(1) 188 #define PHY_SHUTDOWNZ 0 189 #define PHY_UNSHUTDOWNZ BIT(0) 190 191 #define DSI_PHY_IF_CFG 0xa4 192 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 193 #define N_LANES(n) (((n) - 1) & 0x3) 194 195 #define DSI_PHY_ULPS_CTRL 0xa8 196 #define DSI_PHY_TX_TRIGGERS 0xac 197 198 #define DSI_PHY_STATUS 0xb0 199 #define PHY_STOP_STATE_CLK_LANE BIT(2) 200 #define PHY_LOCK BIT(0) 201 202 #define DSI_PHY_TST_CTRL0 0xb4 203 #define PHY_TESTCLK BIT(1) 204 #define PHY_UNTESTCLK 0 205 #define PHY_TESTCLR BIT(0) 206 #define PHY_UNTESTCLR 0 207 208 #define DSI_PHY_TST_CTRL1 0xb8 209 #define PHY_TESTEN BIT(16) 210 #define PHY_UNTESTEN 0 211 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 212 #define PHY_TESTDIN(n) ((n) & 0xff) 213 214 #define DSI_INT_ST0 0xbc 215 #define DSI_INT_ST1 0xc0 216 #define DSI_INT_MSK0 0xc4 217 #define DSI_INT_MSK1 0xc8 218 219 #define DSI_PHY_TMR_RD_CFG 0xf4 220 #define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff) 221 222 #define PHY_STATUS_TIMEOUT_US 10000 223 #define CMD_PKT_STATUS_TIMEOUT_US 20000 224 225 #ifdef CONFIG_DEBUG_FS 226 #define VPG_DEFS(name, dsi) \ 227 ((void __force *)&((*dsi).vpg_defs.name)) 228 229 #define REGISTER(name, mask, dsi) \ 230 { #name, VPG_DEFS(name, dsi), mask, dsi } 231 232 struct debugfs_entries { 233 const char *name; 234 bool *reg; 235 u32 mask; 236 struct dw_mipi_dsi *dsi; 237 }; 238 #endif /* CONFIG_DEBUG_FS */ 239 240 struct dw_mipi_dsi { 241 struct drm_bridge bridge; 242 struct mipi_dsi_host dsi_host; 243 struct drm_bridge *panel_bridge; 244 struct device *dev; 245 void __iomem *base; 246 247 struct clk *pclk; 248 249 bool device_found; 250 unsigned int lane_mbps; /* per lane */ 251 u32 channel; 252 u32 lanes; 253 u32 format; 254 unsigned long mode_flags; 255 256 #ifdef CONFIG_DEBUG_FS 257 struct dentry *debugfs; 258 struct debugfs_entries *debugfs_vpg; 259 struct { 260 bool vpg; 261 bool vpg_horizontal; 262 bool vpg_ber_pattern; 263 } vpg_defs; 264 #endif /* CONFIG_DEBUG_FS */ 265 266 struct dw_mipi_dsi *master; /* dual-dsi master ptr */ 267 struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */ 268 269 const struct dw_mipi_dsi_plat_data *plat_data; 270 }; 271 272 /* 273 * Check if either a link to a master or slave is present 274 */ 275 static inline bool dw_mipi_is_dual_mode(struct dw_mipi_dsi *dsi) 276 { 277 return dsi->slave || dsi->master; 278 } 279 280 /* 281 * The controller should generate 2 frames before 282 * preparing the peripheral. 283 */ 284 static void dw_mipi_dsi_wait_for_two_frames(const struct drm_display_mode *mode) 285 { 286 int refresh, two_frames; 287 288 refresh = drm_mode_vrefresh(mode); 289 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2; 290 msleep(two_frames); 291 } 292 293 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host) 294 { 295 return container_of(host, struct dw_mipi_dsi, dsi_host); 296 } 297 298 static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge) 299 { 300 return container_of(bridge, struct dw_mipi_dsi, bridge); 301 } 302 303 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) 304 { 305 writel(val, dsi->base + reg); 306 } 307 308 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) 309 { 310 return readl(dsi->base + reg); 311 } 312 313 static int dw_mipi_dsi_panel_or_bridge(struct dw_mipi_dsi *dsi, 314 struct device_node *node) 315 { 316 struct drm_bridge *bridge; 317 struct drm_panel *panel; 318 int ret; 319 320 ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge); 321 if (ret) 322 return ret; 323 324 if (panel) { 325 bridge = drm_panel_bridge_add_typed(panel, 326 DRM_MODE_CONNECTOR_DSI); 327 if (IS_ERR(bridge)) 328 return PTR_ERR(bridge); 329 } 330 331 dsi->panel_bridge = bridge; 332 333 if (!dsi->panel_bridge) 334 return -EPROBE_DEFER; 335 336 return 0; 337 } 338 339 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 340 struct mipi_dsi_device *device) 341 { 342 struct dw_mipi_dsi *dsi = host_to_dsi(host); 343 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 344 int ret; 345 346 if (device->lanes > dsi->plat_data->max_data_lanes) { 347 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n", 348 device->lanes); 349 return -EINVAL; 350 } 351 352 dsi->lanes = device->lanes; 353 dsi->channel = device->channel; 354 dsi->format = device->format; 355 dsi->mode_flags = device->mode_flags; 356 357 if (!dsi->device_found) { 358 ret = dw_mipi_dsi_panel_or_bridge(dsi, host->dev->of_node); 359 if (ret) 360 return ret; 361 362 dsi->device_found = true; 363 } 364 365 if (pdata->host_ops && pdata->host_ops->attach) { 366 ret = pdata->host_ops->attach(pdata->priv_data, device); 367 if (ret < 0) 368 return ret; 369 } 370 371 return 0; 372 } 373 374 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, 375 struct mipi_dsi_device *device) 376 { 377 struct dw_mipi_dsi *dsi = host_to_dsi(host); 378 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 379 int ret; 380 381 if (pdata->host_ops && pdata->host_ops->detach) { 382 ret = pdata->host_ops->detach(pdata->priv_data, device); 383 if (ret < 0) 384 return ret; 385 } 386 387 drm_of_panel_bridge_remove(host->dev->of_node, 1, 0); 388 389 drm_bridge_remove(&dsi->bridge); 390 391 return 0; 392 } 393 394 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, 395 const struct mipi_dsi_msg *msg) 396 { 397 bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM; 398 u32 val = 0; 399 400 /* 401 * TODO dw drv improvements 402 * largest packet sizes during hfp or during vsa/vpb/vfp 403 * should be computed according to byte lane, lane number and only 404 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS) 405 */ 406 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(16) 407 | INVACT_LPCMD_TIME(4)); 408 409 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) 410 val |= ACK_RQST_EN; 411 if (lpm) 412 val |= CMD_MODE_ALL_LP; 413 414 dsi_write(dsi, DSI_CMD_MODE_CFG, val); 415 416 val = dsi_read(dsi, DSI_VID_MODE_CFG); 417 if (lpm) 418 val |= ENABLE_LOW_POWER_CMD; 419 else 420 val &= ~ENABLE_LOW_POWER_CMD; 421 dsi_write(dsi, DSI_VID_MODE_CFG, val); 422 } 423 424 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) 425 { 426 int ret; 427 u32 val, mask; 428 429 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 430 val, !(val & GEN_CMD_FULL), 1000, 431 CMD_PKT_STATUS_TIMEOUT_US); 432 if (ret) { 433 dev_err(dsi->dev, "failed to get available command FIFO\n"); 434 return ret; 435 } 436 437 dsi_write(dsi, DSI_GEN_HDR, hdr_val); 438 439 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 440 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 441 val, (val & mask) == mask, 442 1000, CMD_PKT_STATUS_TIMEOUT_US); 443 if (ret) { 444 dev_err(dsi->dev, "failed to write command FIFO\n"); 445 return ret; 446 } 447 448 return 0; 449 } 450 451 static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi, 452 const struct mipi_dsi_packet *packet) 453 { 454 const u8 *tx_buf = packet->payload; 455 int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret; 456 __le32 word; 457 u32 val; 458 459 while (len) { 460 if (len < pld_data_bytes) { 461 word = 0; 462 memcpy(&word, tx_buf, len); 463 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word)); 464 len = 0; 465 } else { 466 memcpy(&word, tx_buf, pld_data_bytes); 467 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word)); 468 tx_buf += pld_data_bytes; 469 len -= pld_data_bytes; 470 } 471 472 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 473 val, !(val & GEN_PLD_W_FULL), 1000, 474 CMD_PKT_STATUS_TIMEOUT_US); 475 if (ret) { 476 dev_err(dsi->dev, 477 "failed to get available write payload FIFO\n"); 478 return ret; 479 } 480 } 481 482 word = 0; 483 memcpy(&word, packet->header, sizeof(packet->header)); 484 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word)); 485 } 486 487 static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi, 488 const struct mipi_dsi_msg *msg) 489 { 490 int i, j, ret, len = msg->rx_len; 491 u8 *buf = msg->rx_buf; 492 u32 val; 493 494 /* Wait end of the read operation */ 495 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 496 val, !(val & GEN_RD_CMD_BUSY), 497 1000, CMD_PKT_STATUS_TIMEOUT_US); 498 if (ret) { 499 dev_err(dsi->dev, "Timeout during read operation\n"); 500 return ret; 501 } 502 503 for (i = 0; i < len; i += 4) { 504 /* Read fifo must not be empty before all bytes are read */ 505 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 506 val, !(val & GEN_PLD_R_EMPTY), 507 1000, CMD_PKT_STATUS_TIMEOUT_US); 508 if (ret) { 509 dev_err(dsi->dev, "Read payload FIFO is empty\n"); 510 return ret; 511 } 512 513 val = dsi_read(dsi, DSI_GEN_PLD_DATA); 514 for (j = 0; j < 4 && j + i < len; j++) 515 buf[i + j] = val >> (8 * j); 516 } 517 518 return ret; 519 } 520 521 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, 522 const struct mipi_dsi_msg *msg) 523 { 524 struct dw_mipi_dsi *dsi = host_to_dsi(host); 525 struct mipi_dsi_packet packet; 526 int ret, nb_bytes; 527 528 ret = mipi_dsi_create_packet(&packet, msg); 529 if (ret) { 530 dev_err(dsi->dev, "failed to create packet: %d\n", ret); 531 return ret; 532 } 533 534 dw_mipi_message_config(dsi, msg); 535 if (dsi->slave) 536 dw_mipi_message_config(dsi->slave, msg); 537 538 ret = dw_mipi_dsi_write(dsi, &packet); 539 if (ret) 540 return ret; 541 if (dsi->slave) { 542 ret = dw_mipi_dsi_write(dsi->slave, &packet); 543 if (ret) 544 return ret; 545 } 546 547 if (msg->rx_buf && msg->rx_len) { 548 ret = dw_mipi_dsi_read(dsi, msg); 549 if (ret) 550 return ret; 551 nb_bytes = msg->rx_len; 552 } else { 553 nb_bytes = packet.size; 554 } 555 556 return nb_bytes; 557 } 558 559 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = { 560 .attach = dw_mipi_dsi_host_attach, 561 .detach = dw_mipi_dsi_host_detach, 562 .transfer = dw_mipi_dsi_host_transfer, 563 }; 564 565 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) 566 { 567 u32 val; 568 569 /* 570 * TODO dw drv improvements 571 * enabling low power is panel-dependent, we should use the 572 * panel configuration here... 573 */ 574 val = ENABLE_LOW_POWER; 575 576 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 577 val |= VID_MODE_TYPE_BURST; 578 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 579 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 580 else 581 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 582 583 #ifdef CONFIG_DEBUG_FS 584 if (dsi->vpg_defs.vpg) { 585 val |= VID_MODE_VPG_ENABLE; 586 val |= dsi->vpg_defs.vpg_horizontal ? 587 VID_MODE_VPG_HORIZONTAL : 0; 588 val |= dsi->vpg_defs.vpg_ber_pattern ? VID_MODE_VPG_MODE : 0; 589 } 590 #endif /* CONFIG_DEBUG_FS */ 591 592 dsi_write(dsi, DSI_VID_MODE_CFG, val); 593 } 594 595 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, 596 unsigned long mode_flags) 597 { 598 u32 val; 599 600 dsi_write(dsi, DSI_PWR_UP, RESET); 601 602 if (mode_flags & MIPI_DSI_MODE_VIDEO) { 603 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE); 604 dw_mipi_dsi_video_mode_config(dsi); 605 } else { 606 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 607 } 608 609 val = PHY_TXREQUESTCLKHS; 610 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 611 val |= AUTO_CLKLANE_CTRL; 612 dsi_write(dsi, DSI_LPCLK_CTRL, val); 613 614 dsi_write(dsi, DSI_PWR_UP, POWERUP); 615 } 616 617 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) 618 { 619 dsi_write(dsi, DSI_PWR_UP, RESET); 620 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ); 621 } 622 623 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) 624 { 625 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 626 unsigned int esc_rate; /* in MHz */ 627 u32 esc_clk_division; 628 int ret; 629 630 /* 631 * The maximum permitted escape clock is 20MHz and it is derived from 632 * lanebyteclk, which is running at "lane_mbps / 8". 633 */ 634 if (phy_ops->get_esc_clk_rate) { 635 ret = phy_ops->get_esc_clk_rate(dsi->plat_data->priv_data, 636 &esc_rate); 637 if (ret) 638 DRM_DEBUG_DRIVER("Phy get_esc_clk_rate() failed\n"); 639 } else 640 esc_rate = 20; /* Default to 20MHz */ 641 642 /* 643 * We want : 644 * (lane_mbps >> 3) / esc_clk_division < X 645 * which is: 646 * (lane_mbps >> 3) / X > esc_clk_division 647 */ 648 esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1; 649 650 dsi_write(dsi, DSI_PWR_UP, RESET); 651 652 /* 653 * TODO dw drv improvements 654 * timeout clock division should be computed with the 655 * high speed transmission counter timeout and byte lane... 656 */ 657 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) | 658 TX_ESC_CLK_DIVISION(esc_clk_division)); 659 } 660 661 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, 662 const struct drm_display_mode *mode) 663 { 664 u32 val = 0, color = 0; 665 666 switch (dsi->format) { 667 case MIPI_DSI_FMT_RGB888: 668 color = DPI_COLOR_CODING_24BIT; 669 break; 670 case MIPI_DSI_FMT_RGB666: 671 color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN; 672 break; 673 case MIPI_DSI_FMT_RGB666_PACKED: 674 color = DPI_COLOR_CODING_18BIT_1; 675 break; 676 case MIPI_DSI_FMT_RGB565: 677 color = DPI_COLOR_CODING_16BIT_1; 678 break; 679 } 680 681 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 682 val |= VSYNC_ACTIVE_LOW; 683 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 684 val |= HSYNC_ACTIVE_LOW; 685 686 dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel)); 687 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); 688 dsi_write(dsi, DSI_DPI_CFG_POL, val); 689 } 690 691 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) 692 { 693 dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN); 694 } 695 696 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, 697 const struct drm_display_mode *mode) 698 { 699 /* 700 * TODO dw drv improvements 701 * only burst mode is supported here. For non-burst video modes, 702 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC & 703 * DSI_VNPCR.NPSIZE... especially because this driver supports 704 * non-burst video modes, see dw_mipi_dsi_video_mode_config()... 705 */ 706 707 dsi_write(dsi, DSI_VID_PKT_SIZE, 708 dw_mipi_is_dual_mode(dsi) ? 709 VID_PKT_SIZE(mode->hdisplay / 2) : 710 VID_PKT_SIZE(mode->hdisplay)); 711 } 712 713 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) 714 { 715 /* 716 * TODO dw drv improvements 717 * compute high speed transmission counter timeout according 718 * to the timeout clock division (TO_CLK_DIVISION) and byte lane... 719 */ 720 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); 721 /* 722 * TODO dw drv improvements 723 * the Bus-Turn-Around Timeout Counter should be computed 724 * according to byte lane... 725 */ 726 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); 727 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 728 } 729 730 /* Get lane byte clock cycles. */ 731 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, 732 const struct drm_display_mode *mode, 733 u32 hcomponent) 734 { 735 u32 frac, lbcc; 736 737 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8; 738 739 frac = lbcc % mode->clock; 740 lbcc = lbcc / mode->clock; 741 if (frac) 742 lbcc++; 743 744 return lbcc; 745 } 746 747 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi, 748 const struct drm_display_mode *mode) 749 { 750 u32 htotal, hsa, hbp, lbcc; 751 752 htotal = mode->htotal; 753 hsa = mode->hsync_end - mode->hsync_start; 754 hbp = mode->htotal - mode->hsync_end; 755 756 /* 757 * TODO dw drv improvements 758 * computations below may be improved... 759 */ 760 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal); 761 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); 762 763 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa); 764 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); 765 766 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp); 767 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); 768 } 769 770 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi, 771 const struct drm_display_mode *mode) 772 { 773 u32 vactive, vsa, vfp, vbp; 774 775 vactive = mode->vdisplay; 776 vsa = mode->vsync_end - mode->vsync_start; 777 vfp = mode->vsync_start - mode->vdisplay; 778 vbp = mode->vtotal - mode->vsync_end; 779 780 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); 781 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); 782 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); 783 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); 784 } 785 786 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) 787 { 788 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 789 struct dw_mipi_dsi_dphy_timing timing; 790 u32 hw_version; 791 int ret; 792 793 ret = phy_ops->get_timing(dsi->plat_data->priv_data, 794 dsi->lane_mbps, &timing); 795 if (ret) 796 DRM_DEV_ERROR(dsi->dev, "Retrieving phy timings failed\n"); 797 798 /* 799 * TODO dw drv improvements 800 * data & clock lane timers should be computed according to panel 801 * blankings and to the automatic clock lane control mode... 802 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with 803 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP) 804 */ 805 806 hw_version = dsi_read(dsi, DSI_VERSION) & VERSION; 807 808 if (hw_version >= HWVER_131) { 809 dsi_write(dsi, DSI_PHY_TMR_CFG, 810 PHY_HS2LP_TIME_V131(timing.data_hs2lp) | 811 PHY_LP2HS_TIME_V131(timing.data_lp2hs)); 812 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000)); 813 } else { 814 dsi_write(dsi, DSI_PHY_TMR_CFG, 815 PHY_HS2LP_TIME(timing.data_hs2lp) | 816 PHY_LP2HS_TIME(timing.data_lp2hs) | 817 MAX_RD_TIME(10000)); 818 } 819 820 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, 821 PHY_CLKHS2LP_TIME(timing.clk_hs2lp) | 822 PHY_CLKLP2HS_TIME(timing.clk_lp2hs)); 823 } 824 825 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) 826 { 827 /* 828 * TODO dw drv improvements 829 * stop wait time should be the maximum between host dsi 830 * and panel stop wait times 831 */ 832 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | 833 N_LANES(dsi->lanes)); 834 } 835 836 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi) 837 { 838 /* Clear PHY state */ 839 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK 840 | PHY_RSTZ | PHY_SHUTDOWNZ); 841 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 842 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR); 843 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 844 } 845 846 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi) 847 { 848 u32 val; 849 int ret; 850 851 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | 852 PHY_UNRSTZ | PHY_UNSHUTDOWNZ); 853 854 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val, 855 val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US); 856 if (ret) 857 DRM_DEBUG_DRIVER("failed to wait phy lock state\n"); 858 859 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 860 val, val & PHY_STOP_STATE_CLK_LANE, 1000, 861 PHY_STATUS_TIMEOUT_US); 862 if (ret) 863 DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n"); 864 } 865 866 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) 867 { 868 dsi_read(dsi, DSI_INT_ST0); 869 dsi_read(dsi, DSI_INT_ST1); 870 dsi_write(dsi, DSI_INT_MSK0, 0); 871 dsi_write(dsi, DSI_INT_MSK1, 0); 872 } 873 874 static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge) 875 { 876 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 877 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 878 879 /* 880 * Switch to command mode before panel-bridge post_disable & 881 * panel unprepare. 882 * Note: panel-bridge disable & panel disable has been called 883 * before by the drm framework. 884 */ 885 dw_mipi_dsi_set_mode(dsi, 0); 886 887 /* 888 * TODO Only way found to call panel-bridge post_disable & 889 * panel unprepare before the dsi "final" disable... 890 * This needs to be fixed in the drm_bridge framework and the API 891 * needs to be updated to manage our own call chains... 892 */ 893 if (dsi->panel_bridge->funcs->post_disable) 894 dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge); 895 896 if (phy_ops->power_off) 897 phy_ops->power_off(dsi->plat_data->priv_data); 898 899 if (dsi->slave) { 900 dw_mipi_dsi_disable(dsi->slave); 901 clk_disable_unprepare(dsi->slave->pclk); 902 pm_runtime_put(dsi->slave->dev); 903 } 904 dw_mipi_dsi_disable(dsi); 905 906 clk_disable_unprepare(dsi->pclk); 907 pm_runtime_put(dsi->dev); 908 } 909 910 static unsigned int dw_mipi_dsi_get_lanes(struct dw_mipi_dsi *dsi) 911 { 912 /* this instance is the slave, so add the master's lanes */ 913 if (dsi->master) 914 return dsi->master->lanes + dsi->lanes; 915 916 /* this instance is the master, so add the slave's lanes */ 917 if (dsi->slave) 918 return dsi->lanes + dsi->slave->lanes; 919 920 /* single-dsi, so no other instance to consider */ 921 return dsi->lanes; 922 } 923 924 static void dw_mipi_dsi_mode_set(struct dw_mipi_dsi *dsi, 925 const struct drm_display_mode *adjusted_mode) 926 { 927 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 928 void *priv_data = dsi->plat_data->priv_data; 929 int ret; 930 u32 lanes = dw_mipi_dsi_get_lanes(dsi); 931 932 clk_prepare_enable(dsi->pclk); 933 934 ret = phy_ops->get_lane_mbps(priv_data, adjusted_mode, dsi->mode_flags, 935 lanes, dsi->format, &dsi->lane_mbps); 936 if (ret) 937 DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n"); 938 939 pm_runtime_get_sync(dsi->dev); 940 dw_mipi_dsi_init(dsi); 941 dw_mipi_dsi_dpi_config(dsi, adjusted_mode); 942 dw_mipi_dsi_packet_handler_config(dsi); 943 dw_mipi_dsi_video_mode_config(dsi); 944 dw_mipi_dsi_video_packet_config(dsi, adjusted_mode); 945 dw_mipi_dsi_command_mode_config(dsi); 946 dw_mipi_dsi_line_timer_config(dsi, adjusted_mode); 947 dw_mipi_dsi_vertical_timing_config(dsi, adjusted_mode); 948 949 dw_mipi_dsi_dphy_init(dsi); 950 dw_mipi_dsi_dphy_timing_config(dsi); 951 dw_mipi_dsi_dphy_interface_config(dsi); 952 953 dw_mipi_dsi_clear_err(dsi); 954 955 ret = phy_ops->init(priv_data); 956 if (ret) 957 DRM_DEBUG_DRIVER("Phy init() failed\n"); 958 959 dw_mipi_dsi_dphy_enable(dsi); 960 961 dw_mipi_dsi_wait_for_two_frames(adjusted_mode); 962 963 /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */ 964 dw_mipi_dsi_set_mode(dsi, 0); 965 966 if (phy_ops->power_on) 967 phy_ops->power_on(dsi->plat_data->priv_data); 968 } 969 970 static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge, 971 const struct drm_display_mode *mode, 972 const struct drm_display_mode *adjusted_mode) 973 { 974 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 975 976 dw_mipi_dsi_mode_set(dsi, adjusted_mode); 977 if (dsi->slave) 978 dw_mipi_dsi_mode_set(dsi->slave, adjusted_mode); 979 } 980 981 static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge) 982 { 983 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 984 985 /* Switch to video mode for panel-bridge enable & panel enable */ 986 dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO); 987 if (dsi->slave) 988 dw_mipi_dsi_set_mode(dsi->slave, MIPI_DSI_MODE_VIDEO); 989 } 990 991 static enum drm_mode_status 992 dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge, 993 const struct drm_display_info *info, 994 const struct drm_display_mode *mode) 995 { 996 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 997 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 998 enum drm_mode_status mode_status = MODE_OK; 999 1000 if (pdata->mode_valid) 1001 mode_status = pdata->mode_valid(pdata->priv_data, mode); 1002 1003 return mode_status; 1004 } 1005 1006 static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge, 1007 enum drm_bridge_attach_flags flags) 1008 { 1009 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 1010 1011 if (!bridge->encoder) { 1012 DRM_ERROR("Parent encoder object not found\n"); 1013 return -ENODEV; 1014 } 1015 1016 /* Set the encoder type as caller does not know it */ 1017 bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI; 1018 1019 if (!dsi->device_found) { 1020 int ret; 1021 1022 ret = dw_mipi_dsi_panel_or_bridge(dsi, dsi->dev->of_node); 1023 if (ret) 1024 return ret; 1025 1026 dsi->device_found = true; 1027 } 1028 1029 /* Attach the panel-bridge to the dsi bridge */ 1030 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge, 1031 flags); 1032 } 1033 1034 static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = { 1035 .mode_set = dw_mipi_dsi_bridge_mode_set, 1036 .enable = dw_mipi_dsi_bridge_enable, 1037 .post_disable = dw_mipi_dsi_bridge_post_disable, 1038 .mode_valid = dw_mipi_dsi_bridge_mode_valid, 1039 .attach = dw_mipi_dsi_bridge_attach, 1040 }; 1041 1042 #ifdef CONFIG_DEBUG_FS 1043 1044 static int dw_mipi_dsi_debugfs_write(void *data, u64 val) 1045 { 1046 struct debugfs_entries *vpg = data; 1047 struct dw_mipi_dsi *dsi; 1048 u32 mode_cfg; 1049 1050 if (!vpg) 1051 return -ENODEV; 1052 1053 dsi = vpg->dsi; 1054 1055 *vpg->reg = (bool)val; 1056 1057 mode_cfg = dsi_read(dsi, DSI_VID_MODE_CFG); 1058 1059 if (*vpg->reg) 1060 mode_cfg |= vpg->mask; 1061 else 1062 mode_cfg &= ~vpg->mask; 1063 1064 dsi_write(dsi, DSI_VID_MODE_CFG, mode_cfg); 1065 1066 return 0; 1067 } 1068 1069 static int dw_mipi_dsi_debugfs_show(void *data, u64 *val) 1070 { 1071 struct debugfs_entries *vpg = data; 1072 1073 if (!vpg) 1074 return -ENODEV; 1075 1076 *val = *vpg->reg; 1077 1078 return 0; 1079 } 1080 1081 DEFINE_DEBUGFS_ATTRIBUTE(fops_x32, dw_mipi_dsi_debugfs_show, 1082 dw_mipi_dsi_debugfs_write, "%llu\n"); 1083 1084 static void debugfs_create_files(void *data) 1085 { 1086 struct dw_mipi_dsi *dsi = data; 1087 struct debugfs_entries debugfs[] = { 1088 REGISTER(vpg, VID_MODE_VPG_ENABLE, dsi), 1089 REGISTER(vpg_horizontal, VID_MODE_VPG_HORIZONTAL, dsi), 1090 REGISTER(vpg_ber_pattern, VID_MODE_VPG_MODE, dsi), 1091 }; 1092 int i; 1093 1094 dsi->debugfs_vpg = kmemdup(debugfs, sizeof(debugfs), GFP_KERNEL); 1095 if (!dsi->debugfs_vpg) 1096 return; 1097 1098 for (i = 0; i < ARRAY_SIZE(debugfs); i++) 1099 debugfs_create_file(dsi->debugfs_vpg[i].name, 0644, 1100 dsi->debugfs, &dsi->debugfs_vpg[i], 1101 &fops_x32); 1102 } 1103 1104 static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) 1105 { 1106 dsi->debugfs = debugfs_create_dir(dev_name(dsi->dev), NULL); 1107 if (IS_ERR(dsi->debugfs)) { 1108 dev_err(dsi->dev, "failed to create debugfs root\n"); 1109 return; 1110 } 1111 1112 debugfs_create_files(dsi); 1113 } 1114 1115 static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) 1116 { 1117 debugfs_remove_recursive(dsi->debugfs); 1118 kfree(dsi->debugfs_vpg); 1119 } 1120 1121 #else 1122 1123 static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) { } 1124 static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { } 1125 1126 #endif /* CONFIG_DEBUG_FS */ 1127 1128 static struct dw_mipi_dsi * 1129 __dw_mipi_dsi_probe(struct platform_device *pdev, 1130 const struct dw_mipi_dsi_plat_data *plat_data) 1131 { 1132 struct device *dev = &pdev->dev; 1133 struct reset_control *apb_rst; 1134 struct dw_mipi_dsi *dsi; 1135 int ret; 1136 1137 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1138 if (!dsi) 1139 return ERR_PTR(-ENOMEM); 1140 1141 dsi->dev = dev; 1142 dsi->plat_data = plat_data; 1143 1144 if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps || 1145 !plat_data->phy_ops->get_timing) { 1146 DRM_ERROR("Phy not properly configured\n"); 1147 return ERR_PTR(-ENODEV); 1148 } 1149 1150 if (!plat_data->base) { 1151 dsi->base = devm_platform_ioremap_resource(pdev, 0); 1152 if (IS_ERR(dsi->base)) 1153 return ERR_PTR(-ENODEV); 1154 1155 } else { 1156 dsi->base = plat_data->base; 1157 } 1158 1159 dsi->pclk = devm_clk_get(dev, "pclk"); 1160 if (IS_ERR(dsi->pclk)) { 1161 ret = PTR_ERR(dsi->pclk); 1162 dev_err(dev, "Unable to get pclk: %d\n", ret); 1163 return ERR_PTR(ret); 1164 } 1165 1166 /* 1167 * Note that the reset was not defined in the initial device tree, so 1168 * we have to be prepared for it not being found. 1169 */ 1170 apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb"); 1171 if (IS_ERR(apb_rst)) { 1172 ret = PTR_ERR(apb_rst); 1173 1174 if (ret != -EPROBE_DEFER) 1175 dev_err(dev, "Unable to get reset control: %d\n", ret); 1176 1177 return ERR_PTR(ret); 1178 } 1179 1180 if (apb_rst) { 1181 ret = clk_prepare_enable(dsi->pclk); 1182 if (ret) { 1183 dev_err(dev, "%s: Failed to enable pclk\n", __func__); 1184 return ERR_PTR(ret); 1185 } 1186 1187 reset_control_assert(apb_rst); 1188 usleep_range(10, 20); 1189 reset_control_deassert(apb_rst); 1190 1191 clk_disable_unprepare(dsi->pclk); 1192 } 1193 1194 dw_mipi_dsi_debugfs_init(dsi); 1195 pm_runtime_enable(dev); 1196 1197 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops; 1198 dsi->dsi_host.dev = dev; 1199 ret = mipi_dsi_host_register(&dsi->dsi_host); 1200 if (ret) { 1201 dev_err(dev, "Failed to register MIPI host: %d\n", ret); 1202 dw_mipi_dsi_debugfs_remove(dsi); 1203 return ERR_PTR(ret); 1204 } 1205 1206 dsi->bridge.driver_private = dsi; 1207 dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs; 1208 #ifdef CONFIG_OF 1209 dsi->bridge.of_node = pdev->dev.of_node; 1210 #endif 1211 drm_bridge_add(&dsi->bridge); 1212 1213 return dsi; 1214 } 1215 1216 static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi) 1217 { 1218 mipi_dsi_host_unregister(&dsi->dsi_host); 1219 1220 pm_runtime_disable(dsi->dev); 1221 dw_mipi_dsi_debugfs_remove(dsi); 1222 } 1223 1224 void dw_mipi_dsi_set_slave(struct dw_mipi_dsi *dsi, struct dw_mipi_dsi *slave) 1225 { 1226 /* introduce controllers to each other */ 1227 dsi->slave = slave; 1228 dsi->slave->master = dsi; 1229 1230 /* migrate settings for already attached displays */ 1231 dsi->slave->lanes = dsi->lanes; 1232 dsi->slave->channel = dsi->channel; 1233 dsi->slave->format = dsi->format; 1234 dsi->slave->mode_flags = dsi->mode_flags; 1235 } 1236 EXPORT_SYMBOL_GPL(dw_mipi_dsi_set_slave); 1237 1238 /* 1239 * Probe/remove API, used from platforms based on the DRM bridge API. 1240 */ 1241 struct dw_mipi_dsi * 1242 dw_mipi_dsi_probe(struct platform_device *pdev, 1243 const struct dw_mipi_dsi_plat_data *plat_data) 1244 { 1245 return __dw_mipi_dsi_probe(pdev, plat_data); 1246 } 1247 EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe); 1248 1249 void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi) 1250 { 1251 __dw_mipi_dsi_remove(dsi); 1252 } 1253 EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove); 1254 1255 /* 1256 * Bind/unbind API, used from platforms based on the component framework. 1257 */ 1258 int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder) 1259 { 1260 return drm_bridge_attach(encoder, &dsi->bridge, NULL, 0); 1261 } 1262 EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind); 1263 1264 void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi) 1265 { 1266 } 1267 EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind); 1268 1269 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>"); 1270 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1271 MODULE_DESCRIPTION("DW MIPI DSI host controller driver"); 1272 MODULE_LICENSE("GPL"); 1273 MODULE_ALIAS("platform:dw-mipi-dsi"); 1274