1 /* 2 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * Modified by Philippe Cornu <philippe.cornu@st.com> 11 * This generic Synopsys DesignWare MIPI DSI host driver is based on the 12 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/component.h> 17 #include <linux/iopoll.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/reset.h> 22 #include <drm/drmP.h> 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_crtc.h> 26 #include <drm/drm_crtc_helper.h> 27 #include <drm/drm_mipi_dsi.h> 28 #include <drm/drm_of.h> 29 #include <drm/bridge/dw_mipi_dsi.h> 30 #include <video/mipi_display.h> 31 32 #define DSI_VERSION 0x00 33 #define DSI_PWR_UP 0x04 34 #define RESET 0 35 #define POWERUP BIT(0) 36 37 #define DSI_CLKMGR_CFG 0x08 38 #define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) 39 #define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) 40 41 #define DSI_DPI_VCID 0x0c 42 #define DPI_VID(vid) (((vid) & 0x3) << 0) 43 44 #define DSI_DPI_COLOR_CODING 0x10 45 #define EN18_LOOSELY BIT(8) 46 #define DPI_COLOR_CODING_16BIT_1 0x0 47 #define DPI_COLOR_CODING_16BIT_2 0x1 48 #define DPI_COLOR_CODING_16BIT_3 0x2 49 #define DPI_COLOR_CODING_18BIT_1 0x3 50 #define DPI_COLOR_CODING_18BIT_2 0x4 51 #define DPI_COLOR_CODING_24BIT 0x5 52 53 #define DSI_DPI_CFG_POL 0x14 54 #define COLORM_ACTIVE_LOW BIT(4) 55 #define SHUTD_ACTIVE_LOW BIT(3) 56 #define HSYNC_ACTIVE_LOW BIT(2) 57 #define VSYNC_ACTIVE_LOW BIT(1) 58 #define DATAEN_ACTIVE_LOW BIT(0) 59 60 #define DSI_DPI_LP_CMD_TIM 0x18 61 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) 62 #define INVACT_LPCMD_TIME(p) ((p) & 0xff) 63 64 #define DSI_DBI_CFG 0x20 65 #define DSI_DBI_CMDSIZE 0x28 66 67 #define DSI_PCKHDL_CFG 0x2c 68 #define EN_CRC_RX BIT(4) 69 #define EN_ECC_RX BIT(3) 70 #define EN_BTA BIT(2) 71 #define EN_EOTP_RX BIT(1) 72 #define EN_EOTP_TX BIT(0) 73 74 #define DSI_MODE_CFG 0x34 75 #define ENABLE_VIDEO_MODE 0 76 #define ENABLE_CMD_MODE BIT(0) 77 78 #define DSI_VID_MODE_CFG 0x38 79 #define FRAME_BTA_ACK BIT(14) 80 #define ENABLE_LOW_POWER (0x3f << 8) 81 #define ENABLE_LOW_POWER_MASK (0x3f << 8) 82 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0 83 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1 84 #define VID_MODE_TYPE_BURST 0x2 85 #define VID_MODE_TYPE_MASK 0x3 86 87 #define DSI_VID_PKT_SIZE 0x3c 88 #define VID_PKT_SIZE(p) (((p) & 0x3fff) << 0) 89 #define VID_PKT_MAX_SIZE 0x3fff 90 91 #define DSI_VID_HSA_TIME 0x48 92 #define DSI_VID_HBP_TIME 0x4c 93 #define DSI_VID_HLINE_TIME 0x50 94 #define DSI_VID_VSA_LINES 0x54 95 #define DSI_VID_VBP_LINES 0x58 96 #define DSI_VID_VFP_LINES 0x5c 97 #define DSI_VID_VACTIVE_LINES 0x60 98 #define DSI_CMD_MODE_CFG 0x68 99 #define MAX_RD_PKT_SIZE_LP BIT(24) 100 #define DCS_LW_TX_LP BIT(19) 101 #define DCS_SR_0P_TX_LP BIT(18) 102 #define DCS_SW_1P_TX_LP BIT(17) 103 #define DCS_SW_0P_TX_LP BIT(16) 104 #define GEN_LW_TX_LP BIT(14) 105 #define GEN_SR_2P_TX_LP BIT(13) 106 #define GEN_SR_1P_TX_LP BIT(12) 107 #define GEN_SR_0P_TX_LP BIT(11) 108 #define GEN_SW_2P_TX_LP BIT(10) 109 #define GEN_SW_1P_TX_LP BIT(9) 110 #define GEN_SW_0P_TX_LP BIT(8) 111 #define EN_ACK_RQST BIT(1) 112 #define EN_TEAR_FX BIT(0) 113 114 #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \ 115 DCS_LW_TX_LP | \ 116 DCS_SR_0P_TX_LP | \ 117 DCS_SW_1P_TX_LP | \ 118 DCS_SW_0P_TX_LP | \ 119 GEN_LW_TX_LP | \ 120 GEN_SR_2P_TX_LP | \ 121 GEN_SR_1P_TX_LP | \ 122 GEN_SR_0P_TX_LP | \ 123 GEN_SW_2P_TX_LP | \ 124 GEN_SW_1P_TX_LP | \ 125 GEN_SW_0P_TX_LP) 126 127 #define DSI_GEN_HDR 0x6c 128 #define GEN_HDATA(data) (((data) & 0xffff) << 8) 129 #define GEN_HDATA_MASK (0xffff << 8) 130 #define GEN_HTYPE(type) (((type) & 0xff) << 0) 131 #define GEN_HTYPE_MASK 0xff 132 133 #define DSI_GEN_PLD_DATA 0x70 134 135 #define DSI_CMD_PKT_STATUS 0x74 136 #define GEN_CMD_EMPTY BIT(0) 137 #define GEN_CMD_FULL BIT(1) 138 #define GEN_PLD_W_EMPTY BIT(2) 139 #define GEN_PLD_W_FULL BIT(3) 140 #define GEN_PLD_R_EMPTY BIT(4) 141 #define GEN_PLD_R_FULL BIT(5) 142 #define GEN_RD_CMD_BUSY BIT(6) 143 144 #define DSI_TO_CNT_CFG 0x78 145 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16) 146 #define LPRX_TO_CNT(p) ((p) & 0xffff) 147 148 #define DSI_BTA_TO_CNT 0x8c 149 #define DSI_LPCLK_CTRL 0x94 150 #define AUTO_CLKLANE_CTRL BIT(1) 151 #define PHY_TXREQUESTCLKHS BIT(0) 152 153 #define DSI_PHY_TMR_LPCLK_CFG 0x98 154 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16) 155 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff) 156 157 #define DSI_PHY_TMR_CFG 0x9c 158 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24) 159 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16) 160 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) 161 162 #define DSI_PHY_RSTZ 0xa0 163 #define PHY_DISFORCEPLL 0 164 #define PHY_ENFORCEPLL BIT(3) 165 #define PHY_DISABLECLK 0 166 #define PHY_ENABLECLK BIT(2) 167 #define PHY_RSTZ 0 168 #define PHY_UNRSTZ BIT(1) 169 #define PHY_SHUTDOWNZ 0 170 #define PHY_UNSHUTDOWNZ BIT(0) 171 172 #define DSI_PHY_IF_CFG 0xa4 173 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 174 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 175 176 #define DSI_PHY_STATUS 0xb0 177 #define LOCK BIT(0) 178 #define STOP_STATE_CLK_LANE BIT(2) 179 180 #define DSI_PHY_TST_CTRL0 0xb4 181 #define PHY_TESTCLK BIT(1) 182 #define PHY_UNTESTCLK 0 183 #define PHY_TESTCLR BIT(0) 184 #define PHY_UNTESTCLR 0 185 186 #define DSI_PHY_TST_CTRL1 0xb8 187 #define PHY_TESTEN BIT(16) 188 #define PHY_UNTESTEN 0 189 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 190 #define PHY_TESTDIN(n) (((n) & 0xff) << 0) 191 192 #define DSI_INT_ST0 0xbc 193 #define DSI_INT_ST1 0xc0 194 #define DSI_INT_MSK0 0xc4 195 #define DSI_INT_MSK1 0xc8 196 197 #define PHY_STATUS_TIMEOUT_US 10000 198 #define CMD_PKT_STATUS_TIMEOUT_US 20000 199 200 struct dw_mipi_dsi { 201 struct drm_bridge bridge; 202 struct mipi_dsi_host dsi_host; 203 struct drm_bridge *panel_bridge; 204 bool is_panel_bridge; 205 struct device *dev; 206 void __iomem *base; 207 208 struct clk *pclk; 209 210 unsigned int lane_mbps; /* per lane */ 211 u32 channel; 212 u32 lanes; 213 u32 format; 214 unsigned long mode_flags; 215 216 const struct dw_mipi_dsi_plat_data *plat_data; 217 }; 218 219 /* 220 * The controller should generate 2 frames before 221 * preparing the peripheral. 222 */ 223 static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode *mode) 224 { 225 int refresh, two_frames; 226 227 refresh = drm_mode_vrefresh(mode); 228 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2; 229 msleep(two_frames); 230 } 231 232 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host) 233 { 234 return container_of(host, struct dw_mipi_dsi, dsi_host); 235 } 236 237 static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge) 238 { 239 return container_of(bridge, struct dw_mipi_dsi, bridge); 240 } 241 242 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) 243 { 244 writel(val, dsi->base + reg); 245 } 246 247 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) 248 { 249 return readl(dsi->base + reg); 250 } 251 252 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 253 struct mipi_dsi_device *device) 254 { 255 struct dw_mipi_dsi *dsi = host_to_dsi(host); 256 struct drm_bridge *bridge; 257 struct drm_panel *panel; 258 int ret; 259 260 if (device->lanes > dsi->plat_data->max_data_lanes) { 261 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n", 262 device->lanes); 263 return -EINVAL; 264 } 265 266 dsi->lanes = device->lanes; 267 dsi->channel = device->channel; 268 dsi->format = device->format; 269 dsi->mode_flags = device->mode_flags; 270 271 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, 272 &panel, &bridge); 273 if (ret) 274 return ret; 275 276 if (panel) { 277 bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DSI); 278 if (IS_ERR(bridge)) 279 return PTR_ERR(bridge); 280 dsi->is_panel_bridge = true; 281 } 282 283 dsi->panel_bridge = bridge; 284 285 drm_bridge_add(&dsi->bridge); 286 287 return 0; 288 } 289 290 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, 291 struct mipi_dsi_device *device) 292 { 293 struct dw_mipi_dsi *dsi = host_to_dsi(host); 294 295 if (dsi->is_panel_bridge) 296 drm_panel_bridge_remove(dsi->panel_bridge); 297 298 drm_bridge_remove(&dsi->bridge); 299 300 return 0; 301 } 302 303 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, 304 const struct mipi_dsi_msg *msg) 305 { 306 bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM; 307 u32 val = 0; 308 309 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) 310 val |= EN_ACK_RQST; 311 if (lpm) 312 val |= CMD_MODE_ALL_LP; 313 314 dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS); 315 dsi_write(dsi, DSI_CMD_MODE_CFG, val); 316 } 317 318 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) 319 { 320 int ret; 321 u32 val, mask; 322 323 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 324 val, !(val & GEN_CMD_FULL), 1000, 325 CMD_PKT_STATUS_TIMEOUT_US); 326 if (ret < 0) { 327 dev_err(dsi->dev, "failed to get available command FIFO\n"); 328 return ret; 329 } 330 331 dsi_write(dsi, DSI_GEN_HDR, hdr_val); 332 333 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 334 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 335 val, (val & mask) == mask, 336 1000, CMD_PKT_STATUS_TIMEOUT_US); 337 if (ret < 0) { 338 dev_err(dsi->dev, "failed to write command FIFO\n"); 339 return ret; 340 } 341 342 return 0; 343 } 344 345 static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi, 346 const struct mipi_dsi_msg *msg) 347 { 348 const u8 *tx_buf = msg->tx_buf; 349 u16 data = 0; 350 u32 val; 351 352 if (msg->tx_len > 0) 353 data |= tx_buf[0]; 354 if (msg->tx_len > 1) 355 data |= tx_buf[1] << 8; 356 357 if (msg->tx_len > 2) { 358 dev_err(dsi->dev, "too long tx buf length %zu for short write\n", 359 msg->tx_len); 360 return -EINVAL; 361 } 362 363 val = GEN_HDATA(data) | GEN_HTYPE(msg->type); 364 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val); 365 } 366 367 static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi, 368 const struct mipi_dsi_msg *msg) 369 { 370 const u8 *tx_buf = msg->tx_buf; 371 int len = msg->tx_len, pld_data_bytes = sizeof(u32), ret; 372 u32 hdr_val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type); 373 u32 remainder; 374 u32 val; 375 376 if (msg->tx_len < 3) { 377 dev_err(dsi->dev, "wrong tx buf length %zu for long write\n", 378 msg->tx_len); 379 return -EINVAL; 380 } 381 382 while (DIV_ROUND_UP(len, pld_data_bytes)) { 383 if (len < pld_data_bytes) { 384 remainder = 0; 385 memcpy(&remainder, tx_buf, len); 386 dsi_write(dsi, DSI_GEN_PLD_DATA, remainder); 387 len = 0; 388 } else { 389 memcpy(&remainder, tx_buf, pld_data_bytes); 390 dsi_write(dsi, DSI_GEN_PLD_DATA, remainder); 391 tx_buf += pld_data_bytes; 392 len -= pld_data_bytes; 393 } 394 395 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 396 val, !(val & GEN_PLD_W_FULL), 1000, 397 CMD_PKT_STATUS_TIMEOUT_US); 398 if (ret < 0) { 399 dev_err(dsi->dev, 400 "failed to get available write payload FIFO\n"); 401 return ret; 402 } 403 } 404 405 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, hdr_val); 406 } 407 408 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, 409 const struct mipi_dsi_msg *msg) 410 { 411 struct dw_mipi_dsi *dsi = host_to_dsi(host); 412 int ret; 413 414 /* 415 * TODO dw drv improvements 416 * use mipi_dsi_create_packet() instead of all following 417 * functions and code (no switch cases, no 418 * dw_mipi_dsi_dcs_short_write(), only the loop in long_write...) 419 * and use packet.header... 420 */ 421 dw_mipi_message_config(dsi, msg); 422 423 switch (msg->type) { 424 case MIPI_DSI_DCS_SHORT_WRITE: 425 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 426 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: 427 ret = dw_mipi_dsi_dcs_short_write(dsi, msg); 428 break; 429 case MIPI_DSI_DCS_LONG_WRITE: 430 ret = dw_mipi_dsi_dcs_long_write(dsi, msg); 431 break; 432 default: 433 dev_err(dsi->dev, "unsupported message type 0x%02x\n", 434 msg->type); 435 ret = -EINVAL; 436 } 437 438 return ret; 439 } 440 441 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = { 442 .attach = dw_mipi_dsi_host_attach, 443 .detach = dw_mipi_dsi_host_detach, 444 .transfer = dw_mipi_dsi_host_transfer, 445 }; 446 447 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) 448 { 449 u32 val; 450 451 /* 452 * TODO dw drv improvements 453 * enabling low power is panel-dependent, we should use the 454 * panel configuration here... 455 */ 456 val = ENABLE_LOW_POWER; 457 458 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 459 val |= VID_MODE_TYPE_BURST; 460 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 461 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 462 else 463 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 464 465 dsi_write(dsi, DSI_VID_MODE_CFG, val); 466 } 467 468 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, 469 unsigned long mode_flags) 470 { 471 dsi_write(dsi, DSI_PWR_UP, RESET); 472 473 if (mode_flags & MIPI_DSI_MODE_VIDEO) { 474 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE); 475 dw_mipi_dsi_video_mode_config(dsi); 476 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); 477 } else { 478 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 479 } 480 481 dsi_write(dsi, DSI_PWR_UP, POWERUP); 482 } 483 484 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) 485 { 486 dsi_write(dsi, DSI_PWR_UP, RESET); 487 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ); 488 } 489 490 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) 491 { 492 /* 493 * The maximum permitted escape clock is 20MHz and it is derived from 494 * lanebyteclk, which is running at "lane_mbps / 8". Thus we want: 495 * 496 * (lane_mbps >> 3) / esc_clk_division < 20 497 * which is: 498 * (lane_mbps >> 3) / 20 > esc_clk_division 499 */ 500 u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1; 501 502 dsi_write(dsi, DSI_PWR_UP, RESET); 503 504 /* 505 * TODO dw drv improvements 506 * timeout clock division should be computed with the 507 * high speed transmission counter timeout and byte lane... 508 */ 509 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) | 510 TX_ESC_CLK_DIVIDSION(esc_clk_division)); 511 } 512 513 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, 514 struct drm_display_mode *mode) 515 { 516 u32 val = 0, color = 0; 517 518 switch (dsi->format) { 519 case MIPI_DSI_FMT_RGB888: 520 color = DPI_COLOR_CODING_24BIT; 521 break; 522 case MIPI_DSI_FMT_RGB666: 523 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY; 524 break; 525 case MIPI_DSI_FMT_RGB666_PACKED: 526 color = DPI_COLOR_CODING_18BIT_1; 527 break; 528 case MIPI_DSI_FMT_RGB565: 529 color = DPI_COLOR_CODING_16BIT_1; 530 break; 531 } 532 533 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 534 val |= VSYNC_ACTIVE_LOW; 535 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 536 val |= HSYNC_ACTIVE_LOW; 537 538 dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel)); 539 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); 540 dsi_write(dsi, DSI_DPI_CFG_POL, val); 541 /* 542 * TODO dw drv improvements 543 * largest packet sizes during hfp or during vsa/vpb/vfp 544 * should be computed according to byte lane, lane number and only 545 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS) 546 */ 547 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4) 548 | INVACT_LPCMD_TIME(4)); 549 } 550 551 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) 552 { 553 dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA); 554 } 555 556 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, 557 struct drm_display_mode *mode) 558 { 559 /* 560 * TODO dw drv improvements 561 * only burst mode is supported here. For non-burst video modes, 562 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC & 563 * DSI_VNPCR.NPSIZE... especially because this driver supports 564 * non-burst video modes, see dw_mipi_dsi_video_mode_config()... 565 */ 566 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay)); 567 } 568 569 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) 570 { 571 /* 572 * TODO dw drv improvements 573 * compute high speed transmission counter timeout according 574 * to the timeout clock division (TO_CLK_DIVIDSION) and byte lane... 575 */ 576 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); 577 /* 578 * TODO dw drv improvements 579 * the Bus-Turn-Around Timeout Counter should be computed 580 * according to byte lane... 581 */ 582 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); 583 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 584 } 585 586 /* Get lane byte clock cycles. */ 587 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, 588 struct drm_display_mode *mode, 589 u32 hcomponent) 590 { 591 u32 frac, lbcc; 592 593 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8; 594 595 frac = lbcc % mode->clock; 596 lbcc = lbcc / mode->clock; 597 if (frac) 598 lbcc++; 599 600 return lbcc; 601 } 602 603 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi, 604 struct drm_display_mode *mode) 605 { 606 u32 htotal, hsa, hbp, lbcc; 607 608 htotal = mode->htotal; 609 hsa = mode->hsync_end - mode->hsync_start; 610 hbp = mode->htotal - mode->hsync_end; 611 612 /* 613 * TODO dw drv improvements 614 * computations below may be improved... 615 */ 616 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal); 617 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); 618 619 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa); 620 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); 621 622 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp); 623 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); 624 } 625 626 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi, 627 struct drm_display_mode *mode) 628 { 629 u32 vactive, vsa, vfp, vbp; 630 631 vactive = mode->vdisplay; 632 vsa = mode->vsync_end - mode->vsync_start; 633 vfp = mode->vsync_start - mode->vdisplay; 634 vbp = mode->vtotal - mode->vsync_end; 635 636 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); 637 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); 638 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); 639 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); 640 } 641 642 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) 643 { 644 /* 645 * TODO dw drv improvements 646 * data & clock lane timers should be computed according to panel 647 * blankings and to the automatic clock lane control mode... 648 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with 649 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP) 650 */ 651 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) 652 | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000)); 653 654 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40) 655 | PHY_CLKLP2HS_TIME(0x40)); 656 } 657 658 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) 659 { 660 /* 661 * TODO dw drv improvements 662 * stop wait time should be the maximum between host dsi 663 * and panel stop wait times 664 */ 665 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | 666 N_LANES(dsi->lanes)); 667 } 668 669 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi) 670 { 671 /* Clear PHY state */ 672 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK 673 | PHY_RSTZ | PHY_SHUTDOWNZ); 674 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 675 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR); 676 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 677 } 678 679 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi) 680 { 681 u32 val; 682 int ret; 683 684 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | 685 PHY_UNRSTZ | PHY_UNSHUTDOWNZ); 686 687 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 688 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US); 689 if (ret < 0) 690 DRM_DEBUG_DRIVER("failed to wait phy lock state\n"); 691 692 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 693 val, val & STOP_STATE_CLK_LANE, 1000, 694 PHY_STATUS_TIMEOUT_US); 695 if (ret < 0) 696 DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n"); 697 } 698 699 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) 700 { 701 dsi_read(dsi, DSI_INT_ST0); 702 dsi_read(dsi, DSI_INT_ST1); 703 dsi_write(dsi, DSI_INT_MSK0, 0); 704 dsi_write(dsi, DSI_INT_MSK1, 0); 705 } 706 707 static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge) 708 { 709 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 710 711 /* 712 * Switch to command mode before panel-bridge post_disable & 713 * panel unprepare. 714 * Note: panel-bridge disable & panel disable has been called 715 * before by the drm framework. 716 */ 717 dw_mipi_dsi_set_mode(dsi, 0); 718 719 /* 720 * TODO Only way found to call panel-bridge post_disable & 721 * panel unprepare before the dsi "final" disable... 722 * This needs to be fixed in the drm_bridge framework and the API 723 * needs to be updated to manage our own call chains... 724 */ 725 dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge); 726 727 dw_mipi_dsi_disable(dsi); 728 clk_disable_unprepare(dsi->pclk); 729 pm_runtime_put(dsi->dev); 730 } 731 732 void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge, 733 struct drm_display_mode *mode, 734 struct drm_display_mode *adjusted_mode) 735 { 736 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 737 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 738 void *priv_data = dsi->plat_data->priv_data; 739 int ret; 740 741 clk_prepare_enable(dsi->pclk); 742 743 ret = phy_ops->get_lane_mbps(priv_data, mode, dsi->mode_flags, 744 dsi->lanes, dsi->format, &dsi->lane_mbps); 745 if (ret) 746 DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n"); 747 748 pm_runtime_get_sync(dsi->dev); 749 dw_mipi_dsi_init(dsi); 750 dw_mipi_dsi_dpi_config(dsi, mode); 751 dw_mipi_dsi_packet_handler_config(dsi); 752 dw_mipi_dsi_video_mode_config(dsi); 753 dw_mipi_dsi_video_packet_config(dsi, mode); 754 dw_mipi_dsi_command_mode_config(dsi); 755 dw_mipi_dsi_line_timer_config(dsi, mode); 756 dw_mipi_dsi_vertical_timing_config(dsi, mode); 757 758 dw_mipi_dsi_dphy_init(dsi); 759 dw_mipi_dsi_dphy_timing_config(dsi); 760 dw_mipi_dsi_dphy_interface_config(dsi); 761 762 dw_mipi_dsi_clear_err(dsi); 763 764 ret = phy_ops->init(priv_data); 765 if (ret) 766 DRM_DEBUG_DRIVER("Phy init() failed\n"); 767 768 dw_mipi_dsi_dphy_enable(dsi); 769 770 dw_mipi_dsi_wait_for_two_frames(mode); 771 772 /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */ 773 dw_mipi_dsi_set_mode(dsi, 0); 774 } 775 776 static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge) 777 { 778 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 779 780 /* Switch to video mode for panel-bridge enable & panel enable */ 781 dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO); 782 } 783 784 static enum drm_mode_status 785 dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge, 786 const struct drm_display_mode *mode) 787 { 788 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 789 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 790 enum drm_mode_status mode_status = MODE_OK; 791 792 if (pdata->mode_valid) 793 mode_status = pdata->mode_valid(pdata->priv_data, mode); 794 795 return mode_status; 796 } 797 798 static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge) 799 { 800 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 801 802 if (!bridge->encoder) { 803 DRM_ERROR("Parent encoder object not found\n"); 804 return -ENODEV; 805 } 806 807 /* Set the encoder type as caller does not know it */ 808 bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI; 809 810 /* Attach the panel-bridge to the dsi bridge */ 811 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge); 812 } 813 814 static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = { 815 .mode_set = dw_mipi_dsi_bridge_mode_set, 816 .enable = dw_mipi_dsi_bridge_enable, 817 .post_disable = dw_mipi_dsi_bridge_post_disable, 818 .mode_valid = dw_mipi_dsi_bridge_mode_valid, 819 .attach = dw_mipi_dsi_bridge_attach, 820 }; 821 822 static struct dw_mipi_dsi * 823 __dw_mipi_dsi_probe(struct platform_device *pdev, 824 const struct dw_mipi_dsi_plat_data *plat_data) 825 { 826 struct device *dev = &pdev->dev; 827 struct reset_control *apb_rst; 828 struct dw_mipi_dsi *dsi; 829 struct resource *res; 830 int ret; 831 832 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 833 if (!dsi) 834 return ERR_PTR(-ENOMEM); 835 836 dsi->dev = dev; 837 dsi->plat_data = plat_data; 838 839 if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps) { 840 DRM_ERROR("Phy not properly configured\n"); 841 return ERR_PTR(-ENODEV); 842 } 843 844 if (!plat_data->base) { 845 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 846 if (!res) 847 return ERR_PTR(-ENODEV); 848 849 dsi->base = devm_ioremap_resource(dev, res); 850 if (IS_ERR(dsi->base)) 851 return ERR_PTR(-ENODEV); 852 853 } else { 854 dsi->base = plat_data->base; 855 } 856 857 dsi->pclk = devm_clk_get(dev, "pclk"); 858 if (IS_ERR(dsi->pclk)) { 859 ret = PTR_ERR(dsi->pclk); 860 dev_err(dev, "Unable to get pclk: %d\n", ret); 861 return ERR_PTR(ret); 862 } 863 864 /* 865 * Note that the reset was not defined in the initial device tree, so 866 * we have to be prepared for it not being found. 867 */ 868 apb_rst = devm_reset_control_get(dev, "apb"); 869 if (IS_ERR(apb_rst)) { 870 ret = PTR_ERR(apb_rst); 871 if (ret == -ENOENT) { 872 apb_rst = NULL; 873 } else { 874 dev_err(dev, "Unable to get reset control: %d\n", ret); 875 return ERR_PTR(ret); 876 } 877 } 878 879 if (apb_rst) { 880 ret = clk_prepare_enable(dsi->pclk); 881 if (ret) { 882 dev_err(dev, "%s: Failed to enable pclk\n", __func__); 883 return ERR_PTR(ret); 884 } 885 886 reset_control_assert(apb_rst); 887 usleep_range(10, 20); 888 reset_control_deassert(apb_rst); 889 890 clk_disable_unprepare(dsi->pclk); 891 } 892 893 pm_runtime_enable(dev); 894 895 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops; 896 dsi->dsi_host.dev = dev; 897 ret = mipi_dsi_host_register(&dsi->dsi_host); 898 if (ret) { 899 dev_err(dev, "Failed to register MIPI host: %d\n", ret); 900 return ERR_PTR(ret); 901 } 902 903 dsi->bridge.driver_private = dsi; 904 dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs; 905 #ifdef CONFIG_OF 906 dsi->bridge.of_node = pdev->dev.of_node; 907 #endif 908 909 dev_set_drvdata(dev, dsi); 910 911 return dsi; 912 } 913 914 static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi) 915 { 916 pm_runtime_disable(dsi->dev); 917 } 918 919 /* 920 * Probe/remove API, used from platforms based on the DRM bridge API. 921 */ 922 int dw_mipi_dsi_probe(struct platform_device *pdev, 923 const struct dw_mipi_dsi_plat_data *plat_data) 924 { 925 struct dw_mipi_dsi *dsi; 926 927 dsi = __dw_mipi_dsi_probe(pdev, plat_data); 928 if (IS_ERR(dsi)) 929 return PTR_ERR(dsi); 930 931 return 0; 932 } 933 EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe); 934 935 void dw_mipi_dsi_remove(struct platform_device *pdev) 936 { 937 struct dw_mipi_dsi *dsi = platform_get_drvdata(pdev); 938 939 mipi_dsi_host_unregister(&dsi->dsi_host); 940 941 __dw_mipi_dsi_remove(dsi); 942 } 943 EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove); 944 945 /* 946 * Bind/unbind API, used from platforms based on the component framework. 947 */ 948 int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder, 949 const struct dw_mipi_dsi_plat_data *plat_data) 950 { 951 struct dw_mipi_dsi *dsi; 952 int ret; 953 954 dsi = __dw_mipi_dsi_probe(pdev, plat_data); 955 if (IS_ERR(dsi)) 956 return PTR_ERR(dsi); 957 958 ret = drm_bridge_attach(encoder, &dsi->bridge, NULL); 959 if (ret) { 960 dw_mipi_dsi_remove(pdev); 961 DRM_ERROR("Failed to initialize bridge with drm\n"); 962 return ret; 963 } 964 965 return 0; 966 } 967 EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind); 968 969 void dw_mipi_dsi_unbind(struct device *dev) 970 { 971 struct dw_mipi_dsi *dsi = dev_get_drvdata(dev); 972 973 __dw_mipi_dsi_remove(dsi); 974 } 975 EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind); 976 977 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>"); 978 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 979 MODULE_DESCRIPTION("DW MIPI DSI host controller driver"); 980 MODULE_LICENSE("GPL"); 981 MODULE_ALIAS("platform:dw-mipi-dsi"); 982