1 /* 2 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * Modified by Philippe Cornu <philippe.cornu@st.com> 11 * This generic Synopsys DesignWare MIPI DSI host driver is based on the 12 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/component.h> 17 #include <linux/iopoll.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/reset.h> 22 #include <drm/drmP.h> 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_crtc.h> 26 #include <drm/drm_crtc_helper.h> 27 #include <drm/drm_mipi_dsi.h> 28 #include <drm/drm_of.h> 29 #include <drm/bridge/dw_mipi_dsi.h> 30 #include <video/mipi_display.h> 31 32 #define DSI_VERSION 0x00 33 34 #define DSI_PWR_UP 0x04 35 #define RESET 0 36 #define POWERUP BIT(0) 37 38 #define DSI_CLKMGR_CFG 0x08 39 #define TO_CLK_DIVISION(div) (((div) & 0xff) << 8) 40 #define TX_ESC_CLK_DIVISION(div) ((div) & 0xff) 41 42 #define DSI_DPI_VCID 0x0c 43 #define DPI_VCID(vcid) ((vcid) & 0x3) 44 45 #define DSI_DPI_COLOR_CODING 0x10 46 #define LOOSELY18_EN BIT(8) 47 #define DPI_COLOR_CODING_16BIT_1 0x0 48 #define DPI_COLOR_CODING_16BIT_2 0x1 49 #define DPI_COLOR_CODING_16BIT_3 0x2 50 #define DPI_COLOR_CODING_18BIT_1 0x3 51 #define DPI_COLOR_CODING_18BIT_2 0x4 52 #define DPI_COLOR_CODING_24BIT 0x5 53 54 #define DSI_DPI_CFG_POL 0x14 55 #define COLORM_ACTIVE_LOW BIT(4) 56 #define SHUTD_ACTIVE_LOW BIT(3) 57 #define HSYNC_ACTIVE_LOW BIT(2) 58 #define VSYNC_ACTIVE_LOW BIT(1) 59 #define DATAEN_ACTIVE_LOW BIT(0) 60 61 #define DSI_DPI_LP_CMD_TIM 0x18 62 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) 63 #define INVACT_LPCMD_TIME(p) ((p) & 0xff) 64 65 #define DSI_DBI_VCID 0x1c 66 #define DSI_DBI_CFG 0x20 67 #define DSI_DBI_PARTITIONING_EN 0x24 68 #define DSI_DBI_CMDSIZE 0x28 69 70 #define DSI_PCKHDL_CFG 0x2c 71 #define CRC_RX_EN BIT(4) 72 #define ECC_RX_EN BIT(3) 73 #define BTA_EN BIT(2) 74 #define EOTP_RX_EN BIT(1) 75 #define EOTP_TX_EN BIT(0) 76 77 #define DSI_GEN_VCID 0x30 78 79 #define DSI_MODE_CFG 0x34 80 #define ENABLE_VIDEO_MODE 0 81 #define ENABLE_CMD_MODE BIT(0) 82 83 #define DSI_VID_MODE_CFG 0x38 84 #define ENABLE_LOW_POWER (0x3f << 8) 85 #define ENABLE_LOW_POWER_MASK (0x3f << 8) 86 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0 87 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1 88 #define VID_MODE_TYPE_BURST 0x2 89 #define VID_MODE_TYPE_MASK 0x3 90 91 #define DSI_VID_PKT_SIZE 0x3c 92 #define VID_PKT_SIZE(p) ((p) & 0x3fff) 93 94 #define DSI_VID_NUM_CHUNKS 0x40 95 #define VID_NUM_CHUNKS(c) ((c) & 0x1fff) 96 97 #define DSI_VID_NULL_SIZE 0x44 98 #define VID_NULL_SIZE(b) ((b) & 0x1fff) 99 100 #define DSI_VID_HSA_TIME 0x48 101 #define DSI_VID_HBP_TIME 0x4c 102 #define DSI_VID_HLINE_TIME 0x50 103 #define DSI_VID_VSA_LINES 0x54 104 #define DSI_VID_VBP_LINES 0x58 105 #define DSI_VID_VFP_LINES 0x5c 106 #define DSI_VID_VACTIVE_LINES 0x60 107 #define DSI_EDPI_CMD_SIZE 0x64 108 109 #define DSI_CMD_MODE_CFG 0x68 110 #define MAX_RD_PKT_SIZE_LP BIT(24) 111 #define DCS_LW_TX_LP BIT(19) 112 #define DCS_SR_0P_TX_LP BIT(18) 113 #define DCS_SW_1P_TX_LP BIT(17) 114 #define DCS_SW_0P_TX_LP BIT(16) 115 #define GEN_LW_TX_LP BIT(14) 116 #define GEN_SR_2P_TX_LP BIT(13) 117 #define GEN_SR_1P_TX_LP BIT(12) 118 #define GEN_SR_0P_TX_LP BIT(11) 119 #define GEN_SW_2P_TX_LP BIT(10) 120 #define GEN_SW_1P_TX_LP BIT(9) 121 #define GEN_SW_0P_TX_LP BIT(8) 122 #define ACK_RQST_EN BIT(1) 123 #define TEAR_FX_EN BIT(0) 124 125 #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \ 126 DCS_LW_TX_LP | \ 127 DCS_SR_0P_TX_LP | \ 128 DCS_SW_1P_TX_LP | \ 129 DCS_SW_0P_TX_LP | \ 130 GEN_LW_TX_LP | \ 131 GEN_SR_2P_TX_LP | \ 132 GEN_SR_1P_TX_LP | \ 133 GEN_SR_0P_TX_LP | \ 134 GEN_SW_2P_TX_LP | \ 135 GEN_SW_1P_TX_LP | \ 136 GEN_SW_0P_TX_LP) 137 138 #define DSI_GEN_HDR 0x6c 139 /* TODO These 2 defines will be reworked thanks to mipi_dsi_create_packet() */ 140 #define GEN_HDATA(data) (((data) & 0xffff) << 8) 141 #define GEN_HTYPE(type) (((type) & 0xff) << 0) 142 143 #define DSI_GEN_PLD_DATA 0x70 144 145 #define DSI_CMD_PKT_STATUS 0x74 146 #define GEN_RD_CMD_BUSY BIT(6) 147 #define GEN_PLD_R_FULL BIT(5) 148 #define GEN_PLD_R_EMPTY BIT(4) 149 #define GEN_PLD_W_FULL BIT(3) 150 #define GEN_PLD_W_EMPTY BIT(2) 151 #define GEN_CMD_FULL BIT(1) 152 #define GEN_CMD_EMPTY BIT(0) 153 154 #define DSI_TO_CNT_CFG 0x78 155 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16) 156 #define LPRX_TO_CNT(p) ((p) & 0xffff) 157 158 #define DSI_HS_RD_TO_CNT 0x7c 159 #define DSI_LP_RD_TO_CNT 0x80 160 #define DSI_HS_WR_TO_CNT 0x84 161 #define DSI_LP_WR_TO_CNT 0x88 162 #define DSI_BTA_TO_CNT 0x8c 163 164 #define DSI_LPCLK_CTRL 0x94 165 #define AUTO_CLKLANE_CTRL BIT(1) 166 #define PHY_TXREQUESTCLKHS BIT(0) 167 168 #define DSI_PHY_TMR_LPCLK_CFG 0x98 169 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16) 170 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff) 171 172 /* TODO Next register is slightly different between 1.30 & 1.31 IP version */ 173 #define DSI_PHY_TMR_CFG 0x9c 174 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24) 175 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16) 176 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) 177 178 #define DSI_PHY_RSTZ 0xa0 179 #define PHY_DISFORCEPLL 0 180 #define PHY_ENFORCEPLL BIT(3) 181 #define PHY_DISABLECLK 0 182 #define PHY_ENABLECLK BIT(2) 183 #define PHY_RSTZ 0 184 #define PHY_UNRSTZ BIT(1) 185 #define PHY_SHUTDOWNZ 0 186 #define PHY_UNSHUTDOWNZ BIT(0) 187 188 #define DSI_PHY_IF_CFG 0xa4 189 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 190 #define N_LANES(n) (((n) - 1) & 0x3) 191 192 #define DSI_PHY_ULPS_CTRL 0xa8 193 #define DSI_PHY_TX_TRIGGERS 0xac 194 195 #define DSI_PHY_STATUS 0xb0 196 #define PHY_STOP_STATE_CLK_LANE BIT(2) 197 #define PHY_LOCK BIT(0) 198 199 #define DSI_PHY_TST_CTRL0 0xb4 200 #define PHY_TESTCLK BIT(1) 201 #define PHY_UNTESTCLK 0 202 #define PHY_TESTCLR BIT(0) 203 #define PHY_UNTESTCLR 0 204 205 #define DSI_PHY_TST_CTRL1 0xb8 206 #define PHY_TESTEN BIT(16) 207 #define PHY_UNTESTEN 0 208 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 209 #define PHY_TESTDIN(n) ((n) & 0xff) 210 211 #define DSI_INT_ST0 0xbc 212 #define DSI_INT_ST1 0xc0 213 #define DSI_INT_MSK0 0xc4 214 #define DSI_INT_MSK1 0xc8 215 #define DSI_PHY_TMR_RD_CFG 0xf4 216 217 #define PHY_STATUS_TIMEOUT_US 10000 218 #define CMD_PKT_STATUS_TIMEOUT_US 20000 219 220 struct dw_mipi_dsi { 221 struct drm_bridge bridge; 222 struct mipi_dsi_host dsi_host; 223 struct drm_bridge *panel_bridge; 224 struct device *dev; 225 void __iomem *base; 226 227 struct clk *pclk; 228 229 unsigned int lane_mbps; /* per lane */ 230 u32 channel; 231 u32 lanes; 232 u32 format; 233 unsigned long mode_flags; 234 235 const struct dw_mipi_dsi_plat_data *plat_data; 236 }; 237 238 /* 239 * The controller should generate 2 frames before 240 * preparing the peripheral. 241 */ 242 static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode *mode) 243 { 244 int refresh, two_frames; 245 246 refresh = drm_mode_vrefresh(mode); 247 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2; 248 msleep(two_frames); 249 } 250 251 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host) 252 { 253 return container_of(host, struct dw_mipi_dsi, dsi_host); 254 } 255 256 static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge) 257 { 258 return container_of(bridge, struct dw_mipi_dsi, bridge); 259 } 260 261 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) 262 { 263 writel(val, dsi->base + reg); 264 } 265 266 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) 267 { 268 return readl(dsi->base + reg); 269 } 270 271 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 272 struct mipi_dsi_device *device) 273 { 274 struct dw_mipi_dsi *dsi = host_to_dsi(host); 275 struct drm_bridge *bridge; 276 struct drm_panel *panel; 277 int ret; 278 279 if (device->lanes > dsi->plat_data->max_data_lanes) { 280 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n", 281 device->lanes); 282 return -EINVAL; 283 } 284 285 dsi->lanes = device->lanes; 286 dsi->channel = device->channel; 287 dsi->format = device->format; 288 dsi->mode_flags = device->mode_flags; 289 290 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, 291 &panel, &bridge); 292 if (ret) 293 return ret; 294 295 if (panel) { 296 bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DSI); 297 if (IS_ERR(bridge)) 298 return PTR_ERR(bridge); 299 } 300 301 dsi->panel_bridge = bridge; 302 303 drm_bridge_add(&dsi->bridge); 304 305 return 0; 306 } 307 308 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, 309 struct mipi_dsi_device *device) 310 { 311 struct dw_mipi_dsi *dsi = host_to_dsi(host); 312 313 drm_of_panel_bridge_remove(host->dev->of_node, 1, 0); 314 315 drm_bridge_remove(&dsi->bridge); 316 317 return 0; 318 } 319 320 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, 321 const struct mipi_dsi_msg *msg) 322 { 323 bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM; 324 u32 val = 0; 325 326 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) 327 val |= ACK_RQST_EN; 328 if (lpm) 329 val |= CMD_MODE_ALL_LP; 330 331 dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS); 332 dsi_write(dsi, DSI_CMD_MODE_CFG, val); 333 } 334 335 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) 336 { 337 int ret; 338 u32 val, mask; 339 340 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 341 val, !(val & GEN_CMD_FULL), 1000, 342 CMD_PKT_STATUS_TIMEOUT_US); 343 if (ret < 0) { 344 dev_err(dsi->dev, "failed to get available command FIFO\n"); 345 return ret; 346 } 347 348 dsi_write(dsi, DSI_GEN_HDR, hdr_val); 349 350 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 351 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 352 val, (val & mask) == mask, 353 1000, CMD_PKT_STATUS_TIMEOUT_US); 354 if (ret < 0) { 355 dev_err(dsi->dev, "failed to write command FIFO\n"); 356 return ret; 357 } 358 359 return 0; 360 } 361 362 static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi, 363 const struct mipi_dsi_msg *msg) 364 { 365 const u8 *tx_buf = msg->tx_buf; 366 u16 data = 0; 367 u32 val; 368 369 if (msg->tx_len > 0) 370 data |= tx_buf[0]; 371 if (msg->tx_len > 1) 372 data |= tx_buf[1] << 8; 373 374 if (msg->tx_len > 2) { 375 dev_err(dsi->dev, "too long tx buf length %zu for short write\n", 376 msg->tx_len); 377 return -EINVAL; 378 } 379 380 val = GEN_HDATA(data) | GEN_HTYPE(msg->type); 381 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val); 382 } 383 384 static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi, 385 const struct mipi_dsi_msg *msg) 386 { 387 const u8 *tx_buf = msg->tx_buf; 388 int len = msg->tx_len, pld_data_bytes = sizeof(u32), ret; 389 u32 hdr_val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type); 390 u32 remainder; 391 u32 val; 392 393 if (msg->tx_len < 3) { 394 dev_err(dsi->dev, "wrong tx buf length %zu for long write\n", 395 msg->tx_len); 396 return -EINVAL; 397 } 398 399 while (DIV_ROUND_UP(len, pld_data_bytes)) { 400 if (len < pld_data_bytes) { 401 remainder = 0; 402 memcpy(&remainder, tx_buf, len); 403 dsi_write(dsi, DSI_GEN_PLD_DATA, remainder); 404 len = 0; 405 } else { 406 memcpy(&remainder, tx_buf, pld_data_bytes); 407 dsi_write(dsi, DSI_GEN_PLD_DATA, remainder); 408 tx_buf += pld_data_bytes; 409 len -= pld_data_bytes; 410 } 411 412 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 413 val, !(val & GEN_PLD_W_FULL), 1000, 414 CMD_PKT_STATUS_TIMEOUT_US); 415 if (ret < 0) { 416 dev_err(dsi->dev, 417 "failed to get available write payload FIFO\n"); 418 return ret; 419 } 420 } 421 422 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, hdr_val); 423 } 424 425 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, 426 const struct mipi_dsi_msg *msg) 427 { 428 struct dw_mipi_dsi *dsi = host_to_dsi(host); 429 int ret; 430 431 /* 432 * TODO dw drv improvements 433 * use mipi_dsi_create_packet() instead of all following 434 * functions and code (no switch cases, no 435 * dw_mipi_dsi_dcs_short_write(), only the loop in long_write...) 436 * and use packet.header... 437 */ 438 dw_mipi_message_config(dsi, msg); 439 440 switch (msg->type) { 441 case MIPI_DSI_DCS_SHORT_WRITE: 442 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 443 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: 444 ret = dw_mipi_dsi_dcs_short_write(dsi, msg); 445 break; 446 case MIPI_DSI_DCS_LONG_WRITE: 447 ret = dw_mipi_dsi_dcs_long_write(dsi, msg); 448 break; 449 default: 450 dev_err(dsi->dev, "unsupported message type 0x%02x\n", 451 msg->type); 452 ret = -EINVAL; 453 } 454 455 return ret; 456 } 457 458 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = { 459 .attach = dw_mipi_dsi_host_attach, 460 .detach = dw_mipi_dsi_host_detach, 461 .transfer = dw_mipi_dsi_host_transfer, 462 }; 463 464 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) 465 { 466 u32 val; 467 468 /* 469 * TODO dw drv improvements 470 * enabling low power is panel-dependent, we should use the 471 * panel configuration here... 472 */ 473 val = ENABLE_LOW_POWER; 474 475 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 476 val |= VID_MODE_TYPE_BURST; 477 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 478 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 479 else 480 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 481 482 dsi_write(dsi, DSI_VID_MODE_CFG, val); 483 } 484 485 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, 486 unsigned long mode_flags) 487 { 488 dsi_write(dsi, DSI_PWR_UP, RESET); 489 490 if (mode_flags & MIPI_DSI_MODE_VIDEO) { 491 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE); 492 dw_mipi_dsi_video_mode_config(dsi); 493 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); 494 } else { 495 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 496 } 497 498 dsi_write(dsi, DSI_PWR_UP, POWERUP); 499 } 500 501 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) 502 { 503 dsi_write(dsi, DSI_PWR_UP, RESET); 504 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ); 505 } 506 507 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) 508 { 509 /* 510 * The maximum permitted escape clock is 20MHz and it is derived from 511 * lanebyteclk, which is running at "lane_mbps / 8". Thus we want: 512 * 513 * (lane_mbps >> 3) / esc_clk_division < 20 514 * which is: 515 * (lane_mbps >> 3) / 20 > esc_clk_division 516 */ 517 u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1; 518 519 dsi_write(dsi, DSI_PWR_UP, RESET); 520 521 /* 522 * TODO dw drv improvements 523 * timeout clock division should be computed with the 524 * high speed transmission counter timeout and byte lane... 525 */ 526 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) | 527 TX_ESC_CLK_DIVISION(esc_clk_division)); 528 } 529 530 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, 531 struct drm_display_mode *mode) 532 { 533 u32 val = 0, color = 0; 534 535 switch (dsi->format) { 536 case MIPI_DSI_FMT_RGB888: 537 color = DPI_COLOR_CODING_24BIT; 538 break; 539 case MIPI_DSI_FMT_RGB666: 540 color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN; 541 break; 542 case MIPI_DSI_FMT_RGB666_PACKED: 543 color = DPI_COLOR_CODING_18BIT_1; 544 break; 545 case MIPI_DSI_FMT_RGB565: 546 color = DPI_COLOR_CODING_16BIT_1; 547 break; 548 } 549 550 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 551 val |= VSYNC_ACTIVE_LOW; 552 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 553 val |= HSYNC_ACTIVE_LOW; 554 555 dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel)); 556 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); 557 dsi_write(dsi, DSI_DPI_CFG_POL, val); 558 /* 559 * TODO dw drv improvements 560 * largest packet sizes during hfp or during vsa/vpb/vfp 561 * should be computed according to byte lane, lane number and only 562 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS) 563 */ 564 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4) 565 | INVACT_LPCMD_TIME(4)); 566 } 567 568 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) 569 { 570 dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN); 571 } 572 573 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, 574 struct drm_display_mode *mode) 575 { 576 /* 577 * TODO dw drv improvements 578 * only burst mode is supported here. For non-burst video modes, 579 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC & 580 * DSI_VNPCR.NPSIZE... especially because this driver supports 581 * non-burst video modes, see dw_mipi_dsi_video_mode_config()... 582 */ 583 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay)); 584 } 585 586 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) 587 { 588 /* 589 * TODO dw drv improvements 590 * compute high speed transmission counter timeout according 591 * to the timeout clock division (TO_CLK_DIVISION) and byte lane... 592 */ 593 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); 594 /* 595 * TODO dw drv improvements 596 * the Bus-Turn-Around Timeout Counter should be computed 597 * according to byte lane... 598 */ 599 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); 600 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 601 } 602 603 /* Get lane byte clock cycles. */ 604 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, 605 struct drm_display_mode *mode, 606 u32 hcomponent) 607 { 608 u32 frac, lbcc; 609 610 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8; 611 612 frac = lbcc % mode->clock; 613 lbcc = lbcc / mode->clock; 614 if (frac) 615 lbcc++; 616 617 return lbcc; 618 } 619 620 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi, 621 struct drm_display_mode *mode) 622 { 623 u32 htotal, hsa, hbp, lbcc; 624 625 htotal = mode->htotal; 626 hsa = mode->hsync_end - mode->hsync_start; 627 hbp = mode->htotal - mode->hsync_end; 628 629 /* 630 * TODO dw drv improvements 631 * computations below may be improved... 632 */ 633 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal); 634 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); 635 636 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa); 637 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); 638 639 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp); 640 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); 641 } 642 643 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi, 644 struct drm_display_mode *mode) 645 { 646 u32 vactive, vsa, vfp, vbp; 647 648 vactive = mode->vdisplay; 649 vsa = mode->vsync_end - mode->vsync_start; 650 vfp = mode->vsync_start - mode->vdisplay; 651 vbp = mode->vtotal - mode->vsync_end; 652 653 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); 654 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); 655 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); 656 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); 657 } 658 659 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) 660 { 661 /* 662 * TODO dw drv improvements 663 * data & clock lane timers should be computed according to panel 664 * blankings and to the automatic clock lane control mode... 665 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with 666 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP) 667 */ 668 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) 669 | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000)); 670 671 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40) 672 | PHY_CLKLP2HS_TIME(0x40)); 673 } 674 675 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) 676 { 677 /* 678 * TODO dw drv improvements 679 * stop wait time should be the maximum between host dsi 680 * and panel stop wait times 681 */ 682 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | 683 N_LANES(dsi->lanes)); 684 } 685 686 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi) 687 { 688 /* Clear PHY state */ 689 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK 690 | PHY_RSTZ | PHY_SHUTDOWNZ); 691 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 692 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR); 693 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 694 } 695 696 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi) 697 { 698 u32 val; 699 int ret; 700 701 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | 702 PHY_UNRSTZ | PHY_UNSHUTDOWNZ); 703 704 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val, 705 val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US); 706 if (ret < 0) 707 DRM_DEBUG_DRIVER("failed to wait phy lock state\n"); 708 709 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 710 val, val & PHY_STOP_STATE_CLK_LANE, 1000, 711 PHY_STATUS_TIMEOUT_US); 712 if (ret < 0) 713 DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n"); 714 } 715 716 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) 717 { 718 dsi_read(dsi, DSI_INT_ST0); 719 dsi_read(dsi, DSI_INT_ST1); 720 dsi_write(dsi, DSI_INT_MSK0, 0); 721 dsi_write(dsi, DSI_INT_MSK1, 0); 722 } 723 724 static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge) 725 { 726 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 727 728 /* 729 * Switch to command mode before panel-bridge post_disable & 730 * panel unprepare. 731 * Note: panel-bridge disable & panel disable has been called 732 * before by the drm framework. 733 */ 734 dw_mipi_dsi_set_mode(dsi, 0); 735 736 /* 737 * TODO Only way found to call panel-bridge post_disable & 738 * panel unprepare before the dsi "final" disable... 739 * This needs to be fixed in the drm_bridge framework and the API 740 * needs to be updated to manage our own call chains... 741 */ 742 dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge); 743 744 dw_mipi_dsi_disable(dsi); 745 clk_disable_unprepare(dsi->pclk); 746 pm_runtime_put(dsi->dev); 747 } 748 749 void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge, 750 struct drm_display_mode *mode, 751 struct drm_display_mode *adjusted_mode) 752 { 753 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 754 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 755 void *priv_data = dsi->plat_data->priv_data; 756 int ret; 757 758 clk_prepare_enable(dsi->pclk); 759 760 ret = phy_ops->get_lane_mbps(priv_data, mode, dsi->mode_flags, 761 dsi->lanes, dsi->format, &dsi->lane_mbps); 762 if (ret) 763 DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n"); 764 765 pm_runtime_get_sync(dsi->dev); 766 dw_mipi_dsi_init(dsi); 767 dw_mipi_dsi_dpi_config(dsi, mode); 768 dw_mipi_dsi_packet_handler_config(dsi); 769 dw_mipi_dsi_video_mode_config(dsi); 770 dw_mipi_dsi_video_packet_config(dsi, mode); 771 dw_mipi_dsi_command_mode_config(dsi); 772 dw_mipi_dsi_line_timer_config(dsi, mode); 773 dw_mipi_dsi_vertical_timing_config(dsi, mode); 774 775 dw_mipi_dsi_dphy_init(dsi); 776 dw_mipi_dsi_dphy_timing_config(dsi); 777 dw_mipi_dsi_dphy_interface_config(dsi); 778 779 dw_mipi_dsi_clear_err(dsi); 780 781 ret = phy_ops->init(priv_data); 782 if (ret) 783 DRM_DEBUG_DRIVER("Phy init() failed\n"); 784 785 dw_mipi_dsi_dphy_enable(dsi); 786 787 dw_mipi_dsi_wait_for_two_frames(mode); 788 789 /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */ 790 dw_mipi_dsi_set_mode(dsi, 0); 791 } 792 793 static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge) 794 { 795 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 796 797 /* Switch to video mode for panel-bridge enable & panel enable */ 798 dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO); 799 } 800 801 static enum drm_mode_status 802 dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge, 803 const struct drm_display_mode *mode) 804 { 805 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 806 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 807 enum drm_mode_status mode_status = MODE_OK; 808 809 if (pdata->mode_valid) 810 mode_status = pdata->mode_valid(pdata->priv_data, mode); 811 812 return mode_status; 813 } 814 815 static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge) 816 { 817 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 818 819 if (!bridge->encoder) { 820 DRM_ERROR("Parent encoder object not found\n"); 821 return -ENODEV; 822 } 823 824 /* Set the encoder type as caller does not know it */ 825 bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI; 826 827 /* Attach the panel-bridge to the dsi bridge */ 828 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge); 829 } 830 831 static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = { 832 .mode_set = dw_mipi_dsi_bridge_mode_set, 833 .enable = dw_mipi_dsi_bridge_enable, 834 .post_disable = dw_mipi_dsi_bridge_post_disable, 835 .mode_valid = dw_mipi_dsi_bridge_mode_valid, 836 .attach = dw_mipi_dsi_bridge_attach, 837 }; 838 839 static struct dw_mipi_dsi * 840 __dw_mipi_dsi_probe(struct platform_device *pdev, 841 const struct dw_mipi_dsi_plat_data *plat_data) 842 { 843 struct device *dev = &pdev->dev; 844 struct reset_control *apb_rst; 845 struct dw_mipi_dsi *dsi; 846 struct resource *res; 847 int ret; 848 849 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 850 if (!dsi) 851 return ERR_PTR(-ENOMEM); 852 853 dsi->dev = dev; 854 dsi->plat_data = plat_data; 855 856 if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps) { 857 DRM_ERROR("Phy not properly configured\n"); 858 return ERR_PTR(-ENODEV); 859 } 860 861 if (!plat_data->base) { 862 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 863 if (!res) 864 return ERR_PTR(-ENODEV); 865 866 dsi->base = devm_ioremap_resource(dev, res); 867 if (IS_ERR(dsi->base)) 868 return ERR_PTR(-ENODEV); 869 870 } else { 871 dsi->base = plat_data->base; 872 } 873 874 dsi->pclk = devm_clk_get(dev, "pclk"); 875 if (IS_ERR(dsi->pclk)) { 876 ret = PTR_ERR(dsi->pclk); 877 dev_err(dev, "Unable to get pclk: %d\n", ret); 878 return ERR_PTR(ret); 879 } 880 881 /* 882 * Note that the reset was not defined in the initial device tree, so 883 * we have to be prepared for it not being found. 884 */ 885 apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb"); 886 if (IS_ERR(apb_rst)) { 887 ret = PTR_ERR(apb_rst); 888 889 if (ret != -EPROBE_DEFER) 890 dev_err(dev, "Unable to get reset control: %d\n", ret); 891 892 return ERR_PTR(ret); 893 } 894 895 if (apb_rst) { 896 ret = clk_prepare_enable(dsi->pclk); 897 if (ret) { 898 dev_err(dev, "%s: Failed to enable pclk\n", __func__); 899 return ERR_PTR(ret); 900 } 901 902 reset_control_assert(apb_rst); 903 usleep_range(10, 20); 904 reset_control_deassert(apb_rst); 905 906 clk_disable_unprepare(dsi->pclk); 907 } 908 909 pm_runtime_enable(dev); 910 911 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops; 912 dsi->dsi_host.dev = dev; 913 ret = mipi_dsi_host_register(&dsi->dsi_host); 914 if (ret) { 915 dev_err(dev, "Failed to register MIPI host: %d\n", ret); 916 return ERR_PTR(ret); 917 } 918 919 dsi->bridge.driver_private = dsi; 920 dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs; 921 #ifdef CONFIG_OF 922 dsi->bridge.of_node = pdev->dev.of_node; 923 #endif 924 925 dev_set_drvdata(dev, dsi); 926 927 return dsi; 928 } 929 930 static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi) 931 { 932 pm_runtime_disable(dsi->dev); 933 } 934 935 /* 936 * Probe/remove API, used from platforms based on the DRM bridge API. 937 */ 938 int dw_mipi_dsi_probe(struct platform_device *pdev, 939 const struct dw_mipi_dsi_plat_data *plat_data) 940 { 941 struct dw_mipi_dsi *dsi; 942 943 dsi = __dw_mipi_dsi_probe(pdev, plat_data); 944 if (IS_ERR(dsi)) 945 return PTR_ERR(dsi); 946 947 return 0; 948 } 949 EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe); 950 951 void dw_mipi_dsi_remove(struct platform_device *pdev) 952 { 953 struct dw_mipi_dsi *dsi = platform_get_drvdata(pdev); 954 955 mipi_dsi_host_unregister(&dsi->dsi_host); 956 957 __dw_mipi_dsi_remove(dsi); 958 } 959 EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove); 960 961 /* 962 * Bind/unbind API, used from platforms based on the component framework. 963 */ 964 int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder, 965 const struct dw_mipi_dsi_plat_data *plat_data) 966 { 967 struct dw_mipi_dsi *dsi; 968 int ret; 969 970 dsi = __dw_mipi_dsi_probe(pdev, plat_data); 971 if (IS_ERR(dsi)) 972 return PTR_ERR(dsi); 973 974 ret = drm_bridge_attach(encoder, &dsi->bridge, NULL); 975 if (ret) { 976 dw_mipi_dsi_remove(pdev); 977 DRM_ERROR("Failed to initialize bridge with drm\n"); 978 return ret; 979 } 980 981 return 0; 982 } 983 EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind); 984 985 void dw_mipi_dsi_unbind(struct device *dev) 986 { 987 struct dw_mipi_dsi *dsi = dev_get_drvdata(dev); 988 989 __dw_mipi_dsi_remove(dsi); 990 } 991 EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind); 992 993 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>"); 994 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 995 MODULE_DESCRIPTION("DW MIPI DSI host controller driver"); 996 MODULE_LICENSE("GPL"); 997 MODULE_ALIAS("platform:dw-mipi-dsi"); 998