1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd 4 * Copyright (C) STMicroelectronics SA 2017 5 * 6 * Modified by Philippe Cornu <philippe.cornu@st.com> 7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the 8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs. 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/iopoll.h> 14 #include <linux/module.h> 15 #include <linux/of_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 19 #include <video/mipi_display.h> 20 21 #include <drm/bridge/dw_mipi_dsi.h> 22 #include <drm/drm_atomic_helper.h> 23 #include <drm/drm_bridge.h> 24 #include <drm/drm_crtc.h> 25 #include <drm/drm_mipi_dsi.h> 26 #include <drm/drm_modes.h> 27 #include <drm/drm_of.h> 28 #include <drm/drm_print.h> 29 #include <drm/drm_probe_helper.h> 30 31 #define HWVER_131 0x31333100 /* IP version 1.31 */ 32 33 #define DSI_VERSION 0x00 34 #define VERSION GENMASK(31, 8) 35 36 #define DSI_PWR_UP 0x04 37 #define RESET 0 38 #define POWERUP BIT(0) 39 40 #define DSI_CLKMGR_CFG 0x08 41 #define TO_CLK_DIVISION(div) (((div) & 0xff) << 8) 42 #define TX_ESC_CLK_DIVISION(div) ((div) & 0xff) 43 44 #define DSI_DPI_VCID 0x0c 45 #define DPI_VCID(vcid) ((vcid) & 0x3) 46 47 #define DSI_DPI_COLOR_CODING 0x10 48 #define LOOSELY18_EN BIT(8) 49 #define DPI_COLOR_CODING_16BIT_1 0x0 50 #define DPI_COLOR_CODING_16BIT_2 0x1 51 #define DPI_COLOR_CODING_16BIT_3 0x2 52 #define DPI_COLOR_CODING_18BIT_1 0x3 53 #define DPI_COLOR_CODING_18BIT_2 0x4 54 #define DPI_COLOR_CODING_24BIT 0x5 55 56 #define DSI_DPI_CFG_POL 0x14 57 #define COLORM_ACTIVE_LOW BIT(4) 58 #define SHUTD_ACTIVE_LOW BIT(3) 59 #define HSYNC_ACTIVE_LOW BIT(2) 60 #define VSYNC_ACTIVE_LOW BIT(1) 61 #define DATAEN_ACTIVE_LOW BIT(0) 62 63 #define DSI_DPI_LP_CMD_TIM 0x18 64 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) 65 #define INVACT_LPCMD_TIME(p) ((p) & 0xff) 66 67 #define DSI_DBI_VCID 0x1c 68 #define DSI_DBI_CFG 0x20 69 #define DSI_DBI_PARTITIONING_EN 0x24 70 #define DSI_DBI_CMDSIZE 0x28 71 72 #define DSI_PCKHDL_CFG 0x2c 73 #define CRC_RX_EN BIT(4) 74 #define ECC_RX_EN BIT(3) 75 #define BTA_EN BIT(2) 76 #define EOTP_RX_EN BIT(1) 77 #define EOTP_TX_EN BIT(0) 78 79 #define DSI_GEN_VCID 0x30 80 81 #define DSI_MODE_CFG 0x34 82 #define ENABLE_VIDEO_MODE 0 83 #define ENABLE_CMD_MODE BIT(0) 84 85 #define DSI_VID_MODE_CFG 0x38 86 #define ENABLE_LOW_POWER (0x3f << 8) 87 #define ENABLE_LOW_POWER_MASK (0x3f << 8) 88 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0 89 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1 90 #define VID_MODE_TYPE_BURST 0x2 91 #define VID_MODE_TYPE_MASK 0x3 92 93 #define DSI_VID_PKT_SIZE 0x3c 94 #define VID_PKT_SIZE(p) ((p) & 0x3fff) 95 96 #define DSI_VID_NUM_CHUNKS 0x40 97 #define VID_NUM_CHUNKS(c) ((c) & 0x1fff) 98 99 #define DSI_VID_NULL_SIZE 0x44 100 #define VID_NULL_SIZE(b) ((b) & 0x1fff) 101 102 #define DSI_VID_HSA_TIME 0x48 103 #define DSI_VID_HBP_TIME 0x4c 104 #define DSI_VID_HLINE_TIME 0x50 105 #define DSI_VID_VSA_LINES 0x54 106 #define DSI_VID_VBP_LINES 0x58 107 #define DSI_VID_VFP_LINES 0x5c 108 #define DSI_VID_VACTIVE_LINES 0x60 109 #define DSI_EDPI_CMD_SIZE 0x64 110 111 #define DSI_CMD_MODE_CFG 0x68 112 #define MAX_RD_PKT_SIZE_LP BIT(24) 113 #define DCS_LW_TX_LP BIT(19) 114 #define DCS_SR_0P_TX_LP BIT(18) 115 #define DCS_SW_1P_TX_LP BIT(17) 116 #define DCS_SW_0P_TX_LP BIT(16) 117 #define GEN_LW_TX_LP BIT(14) 118 #define GEN_SR_2P_TX_LP BIT(13) 119 #define GEN_SR_1P_TX_LP BIT(12) 120 #define GEN_SR_0P_TX_LP BIT(11) 121 #define GEN_SW_2P_TX_LP BIT(10) 122 #define GEN_SW_1P_TX_LP BIT(9) 123 #define GEN_SW_0P_TX_LP BIT(8) 124 #define ACK_RQST_EN BIT(1) 125 #define TEAR_FX_EN BIT(0) 126 127 #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \ 128 DCS_LW_TX_LP | \ 129 DCS_SR_0P_TX_LP | \ 130 DCS_SW_1P_TX_LP | \ 131 DCS_SW_0P_TX_LP | \ 132 GEN_LW_TX_LP | \ 133 GEN_SR_2P_TX_LP | \ 134 GEN_SR_1P_TX_LP | \ 135 GEN_SR_0P_TX_LP | \ 136 GEN_SW_2P_TX_LP | \ 137 GEN_SW_1P_TX_LP | \ 138 GEN_SW_0P_TX_LP) 139 140 #define DSI_GEN_HDR 0x6c 141 #define DSI_GEN_PLD_DATA 0x70 142 143 #define DSI_CMD_PKT_STATUS 0x74 144 #define GEN_RD_CMD_BUSY BIT(6) 145 #define GEN_PLD_R_FULL BIT(5) 146 #define GEN_PLD_R_EMPTY BIT(4) 147 #define GEN_PLD_W_FULL BIT(3) 148 #define GEN_PLD_W_EMPTY BIT(2) 149 #define GEN_CMD_FULL BIT(1) 150 #define GEN_CMD_EMPTY BIT(0) 151 152 #define DSI_TO_CNT_CFG 0x78 153 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16) 154 #define LPRX_TO_CNT(p) ((p) & 0xffff) 155 156 #define DSI_HS_RD_TO_CNT 0x7c 157 #define DSI_LP_RD_TO_CNT 0x80 158 #define DSI_HS_WR_TO_CNT 0x84 159 #define DSI_LP_WR_TO_CNT 0x88 160 #define DSI_BTA_TO_CNT 0x8c 161 162 #define DSI_LPCLK_CTRL 0x94 163 #define AUTO_CLKLANE_CTRL BIT(1) 164 #define PHY_TXREQUESTCLKHS BIT(0) 165 166 #define DSI_PHY_TMR_LPCLK_CFG 0x98 167 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16) 168 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff) 169 170 #define DSI_PHY_TMR_CFG 0x9c 171 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24) 172 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16) 173 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) 174 #define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16) 175 #define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff) 176 177 #define DSI_PHY_RSTZ 0xa0 178 #define PHY_DISFORCEPLL 0 179 #define PHY_ENFORCEPLL BIT(3) 180 #define PHY_DISABLECLK 0 181 #define PHY_ENABLECLK BIT(2) 182 #define PHY_RSTZ 0 183 #define PHY_UNRSTZ BIT(1) 184 #define PHY_SHUTDOWNZ 0 185 #define PHY_UNSHUTDOWNZ BIT(0) 186 187 #define DSI_PHY_IF_CFG 0xa4 188 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 189 #define N_LANES(n) (((n) - 1) & 0x3) 190 191 #define DSI_PHY_ULPS_CTRL 0xa8 192 #define DSI_PHY_TX_TRIGGERS 0xac 193 194 #define DSI_PHY_STATUS 0xb0 195 #define PHY_STOP_STATE_CLK_LANE BIT(2) 196 #define PHY_LOCK BIT(0) 197 198 #define DSI_PHY_TST_CTRL0 0xb4 199 #define PHY_TESTCLK BIT(1) 200 #define PHY_UNTESTCLK 0 201 #define PHY_TESTCLR BIT(0) 202 #define PHY_UNTESTCLR 0 203 204 #define DSI_PHY_TST_CTRL1 0xb8 205 #define PHY_TESTEN BIT(16) 206 #define PHY_UNTESTEN 0 207 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 208 #define PHY_TESTDIN(n) ((n) & 0xff) 209 210 #define DSI_INT_ST0 0xbc 211 #define DSI_INT_ST1 0xc0 212 #define DSI_INT_MSK0 0xc4 213 #define DSI_INT_MSK1 0xc8 214 215 #define DSI_PHY_TMR_RD_CFG 0xf4 216 #define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff) 217 218 #define PHY_STATUS_TIMEOUT_US 10000 219 #define CMD_PKT_STATUS_TIMEOUT_US 20000 220 221 struct dw_mipi_dsi { 222 struct drm_bridge bridge; 223 struct mipi_dsi_host dsi_host; 224 struct drm_bridge *panel_bridge; 225 struct device *dev; 226 void __iomem *base; 227 228 struct clk *pclk; 229 230 unsigned int lane_mbps; /* per lane */ 231 u32 channel; 232 u32 lanes; 233 u32 format; 234 unsigned long mode_flags; 235 236 struct dw_mipi_dsi *master; /* dual-dsi master ptr */ 237 struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */ 238 239 const struct dw_mipi_dsi_plat_data *plat_data; 240 }; 241 242 /* 243 * Check if either a link to a master or slave is present 244 */ 245 static inline bool dw_mipi_is_dual_mode(struct dw_mipi_dsi *dsi) 246 { 247 return dsi->slave || dsi->master; 248 } 249 250 /* 251 * The controller should generate 2 frames before 252 * preparing the peripheral. 253 */ 254 static void dw_mipi_dsi_wait_for_two_frames(const struct drm_display_mode *mode) 255 { 256 int refresh, two_frames; 257 258 refresh = drm_mode_vrefresh(mode); 259 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2; 260 msleep(two_frames); 261 } 262 263 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host) 264 { 265 return container_of(host, struct dw_mipi_dsi, dsi_host); 266 } 267 268 static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge) 269 { 270 return container_of(bridge, struct dw_mipi_dsi, bridge); 271 } 272 273 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) 274 { 275 writel(val, dsi->base + reg); 276 } 277 278 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) 279 { 280 return readl(dsi->base + reg); 281 } 282 283 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 284 struct mipi_dsi_device *device) 285 { 286 struct dw_mipi_dsi *dsi = host_to_dsi(host); 287 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 288 struct drm_bridge *bridge; 289 struct drm_panel *panel; 290 int ret; 291 292 if (device->lanes > dsi->plat_data->max_data_lanes) { 293 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n", 294 device->lanes); 295 return -EINVAL; 296 } 297 298 dsi->lanes = device->lanes; 299 dsi->channel = device->channel; 300 dsi->format = device->format; 301 dsi->mode_flags = device->mode_flags; 302 303 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, 304 &panel, &bridge); 305 if (ret) 306 return ret; 307 308 if (panel) { 309 bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DSI); 310 if (IS_ERR(bridge)) 311 return PTR_ERR(bridge); 312 } 313 314 dsi->panel_bridge = bridge; 315 316 drm_bridge_add(&dsi->bridge); 317 318 if (pdata->host_ops && pdata->host_ops->attach) { 319 ret = pdata->host_ops->attach(pdata->priv_data, device); 320 if (ret < 0) 321 return ret; 322 } 323 324 return 0; 325 } 326 327 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, 328 struct mipi_dsi_device *device) 329 { 330 struct dw_mipi_dsi *dsi = host_to_dsi(host); 331 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 332 int ret; 333 334 if (pdata->host_ops && pdata->host_ops->detach) { 335 ret = pdata->host_ops->detach(pdata->priv_data, device); 336 if (ret < 0) 337 return ret; 338 } 339 340 drm_of_panel_bridge_remove(host->dev->of_node, 1, 0); 341 342 drm_bridge_remove(&dsi->bridge); 343 344 return 0; 345 } 346 347 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, 348 const struct mipi_dsi_msg *msg) 349 { 350 bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM; 351 u32 val = 0; 352 353 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) 354 val |= ACK_RQST_EN; 355 if (lpm) 356 val |= CMD_MODE_ALL_LP; 357 358 dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS); 359 dsi_write(dsi, DSI_CMD_MODE_CFG, val); 360 } 361 362 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) 363 { 364 int ret; 365 u32 val, mask; 366 367 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 368 val, !(val & GEN_CMD_FULL), 1000, 369 CMD_PKT_STATUS_TIMEOUT_US); 370 if (ret) { 371 dev_err(dsi->dev, "failed to get available command FIFO\n"); 372 return ret; 373 } 374 375 dsi_write(dsi, DSI_GEN_HDR, hdr_val); 376 377 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 378 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 379 val, (val & mask) == mask, 380 1000, CMD_PKT_STATUS_TIMEOUT_US); 381 if (ret) { 382 dev_err(dsi->dev, "failed to write command FIFO\n"); 383 return ret; 384 } 385 386 return 0; 387 } 388 389 static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi, 390 const struct mipi_dsi_packet *packet) 391 { 392 const u8 *tx_buf = packet->payload; 393 int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret; 394 __le32 word; 395 u32 val; 396 397 while (len) { 398 if (len < pld_data_bytes) { 399 word = 0; 400 memcpy(&word, tx_buf, len); 401 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word)); 402 len = 0; 403 } else { 404 memcpy(&word, tx_buf, pld_data_bytes); 405 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word)); 406 tx_buf += pld_data_bytes; 407 len -= pld_data_bytes; 408 } 409 410 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 411 val, !(val & GEN_PLD_W_FULL), 1000, 412 CMD_PKT_STATUS_TIMEOUT_US); 413 if (ret) { 414 dev_err(dsi->dev, 415 "failed to get available write payload FIFO\n"); 416 return ret; 417 } 418 } 419 420 word = 0; 421 memcpy(&word, packet->header, sizeof(packet->header)); 422 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word)); 423 } 424 425 static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi, 426 const struct mipi_dsi_msg *msg) 427 { 428 int i, j, ret, len = msg->rx_len; 429 u8 *buf = msg->rx_buf; 430 u32 val; 431 432 /* Wait end of the read operation */ 433 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 434 val, !(val & GEN_RD_CMD_BUSY), 435 1000, CMD_PKT_STATUS_TIMEOUT_US); 436 if (ret) { 437 dev_err(dsi->dev, "Timeout during read operation\n"); 438 return ret; 439 } 440 441 for (i = 0; i < len; i += 4) { 442 /* Read fifo must not be empty before all bytes are read */ 443 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 444 val, !(val & GEN_PLD_R_EMPTY), 445 1000, CMD_PKT_STATUS_TIMEOUT_US); 446 if (ret) { 447 dev_err(dsi->dev, "Read payload FIFO is empty\n"); 448 return ret; 449 } 450 451 val = dsi_read(dsi, DSI_GEN_PLD_DATA); 452 for (j = 0; j < 4 && j + i < len; j++) 453 buf[i + j] = val >> (8 * j); 454 } 455 456 return ret; 457 } 458 459 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, 460 const struct mipi_dsi_msg *msg) 461 { 462 struct dw_mipi_dsi *dsi = host_to_dsi(host); 463 struct mipi_dsi_packet packet; 464 int ret, nb_bytes; 465 466 ret = mipi_dsi_create_packet(&packet, msg); 467 if (ret) { 468 dev_err(dsi->dev, "failed to create packet: %d\n", ret); 469 return ret; 470 } 471 472 dw_mipi_message_config(dsi, msg); 473 if (dsi->slave) 474 dw_mipi_message_config(dsi->slave, msg); 475 476 ret = dw_mipi_dsi_write(dsi, &packet); 477 if (ret) 478 return ret; 479 if (dsi->slave) { 480 ret = dw_mipi_dsi_write(dsi->slave, &packet); 481 if (ret) 482 return ret; 483 } 484 485 if (msg->rx_buf && msg->rx_len) { 486 ret = dw_mipi_dsi_read(dsi, msg); 487 if (ret) 488 return ret; 489 nb_bytes = msg->rx_len; 490 } else { 491 nb_bytes = packet.size; 492 } 493 494 return nb_bytes; 495 } 496 497 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = { 498 .attach = dw_mipi_dsi_host_attach, 499 .detach = dw_mipi_dsi_host_detach, 500 .transfer = dw_mipi_dsi_host_transfer, 501 }; 502 503 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) 504 { 505 u32 val; 506 507 /* 508 * TODO dw drv improvements 509 * enabling low power is panel-dependent, we should use the 510 * panel configuration here... 511 */ 512 val = ENABLE_LOW_POWER; 513 514 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 515 val |= VID_MODE_TYPE_BURST; 516 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 517 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 518 else 519 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 520 521 dsi_write(dsi, DSI_VID_MODE_CFG, val); 522 } 523 524 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, 525 unsigned long mode_flags) 526 { 527 dsi_write(dsi, DSI_PWR_UP, RESET); 528 529 if (mode_flags & MIPI_DSI_MODE_VIDEO) { 530 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE); 531 dw_mipi_dsi_video_mode_config(dsi); 532 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); 533 } else { 534 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 535 } 536 537 dsi_write(dsi, DSI_PWR_UP, POWERUP); 538 } 539 540 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) 541 { 542 dsi_write(dsi, DSI_PWR_UP, RESET); 543 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ); 544 } 545 546 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) 547 { 548 /* 549 * The maximum permitted escape clock is 20MHz and it is derived from 550 * lanebyteclk, which is running at "lane_mbps / 8". Thus we want: 551 * 552 * (lane_mbps >> 3) / esc_clk_division < 20 553 * which is: 554 * (lane_mbps >> 3) / 20 > esc_clk_division 555 */ 556 u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1; 557 558 dsi_write(dsi, DSI_PWR_UP, RESET); 559 560 /* 561 * TODO dw drv improvements 562 * timeout clock division should be computed with the 563 * high speed transmission counter timeout and byte lane... 564 */ 565 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) | 566 TX_ESC_CLK_DIVISION(esc_clk_division)); 567 } 568 569 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, 570 const struct drm_display_mode *mode) 571 { 572 u32 val = 0, color = 0; 573 574 switch (dsi->format) { 575 case MIPI_DSI_FMT_RGB888: 576 color = DPI_COLOR_CODING_24BIT; 577 break; 578 case MIPI_DSI_FMT_RGB666: 579 color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN; 580 break; 581 case MIPI_DSI_FMT_RGB666_PACKED: 582 color = DPI_COLOR_CODING_18BIT_1; 583 break; 584 case MIPI_DSI_FMT_RGB565: 585 color = DPI_COLOR_CODING_16BIT_1; 586 break; 587 } 588 589 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 590 val |= VSYNC_ACTIVE_LOW; 591 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 592 val |= HSYNC_ACTIVE_LOW; 593 594 dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel)); 595 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); 596 dsi_write(dsi, DSI_DPI_CFG_POL, val); 597 /* 598 * TODO dw drv improvements 599 * largest packet sizes during hfp or during vsa/vpb/vfp 600 * should be computed according to byte lane, lane number and only 601 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS) 602 */ 603 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4) 604 | INVACT_LPCMD_TIME(4)); 605 } 606 607 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) 608 { 609 dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN); 610 } 611 612 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, 613 const struct drm_display_mode *mode) 614 { 615 /* 616 * TODO dw drv improvements 617 * only burst mode is supported here. For non-burst video modes, 618 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC & 619 * DSI_VNPCR.NPSIZE... especially because this driver supports 620 * non-burst video modes, see dw_mipi_dsi_video_mode_config()... 621 */ 622 623 dsi_write(dsi, DSI_VID_PKT_SIZE, 624 dw_mipi_is_dual_mode(dsi) ? 625 VID_PKT_SIZE(mode->hdisplay / 2) : 626 VID_PKT_SIZE(mode->hdisplay)); 627 } 628 629 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) 630 { 631 /* 632 * TODO dw drv improvements 633 * compute high speed transmission counter timeout according 634 * to the timeout clock division (TO_CLK_DIVISION) and byte lane... 635 */ 636 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); 637 /* 638 * TODO dw drv improvements 639 * the Bus-Turn-Around Timeout Counter should be computed 640 * according to byte lane... 641 */ 642 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); 643 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 644 } 645 646 /* Get lane byte clock cycles. */ 647 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, 648 const struct drm_display_mode *mode, 649 u32 hcomponent) 650 { 651 u32 frac, lbcc; 652 653 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8; 654 655 frac = lbcc % mode->clock; 656 lbcc = lbcc / mode->clock; 657 if (frac) 658 lbcc++; 659 660 return lbcc; 661 } 662 663 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi, 664 const struct drm_display_mode *mode) 665 { 666 u32 htotal, hsa, hbp, lbcc; 667 668 htotal = mode->htotal; 669 hsa = mode->hsync_end - mode->hsync_start; 670 hbp = mode->htotal - mode->hsync_end; 671 672 /* 673 * TODO dw drv improvements 674 * computations below may be improved... 675 */ 676 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal); 677 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); 678 679 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa); 680 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); 681 682 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp); 683 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); 684 } 685 686 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi, 687 const struct drm_display_mode *mode) 688 { 689 u32 vactive, vsa, vfp, vbp; 690 691 vactive = mode->vdisplay; 692 vsa = mode->vsync_end - mode->vsync_start; 693 vfp = mode->vsync_start - mode->vdisplay; 694 vbp = mode->vtotal - mode->vsync_end; 695 696 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); 697 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); 698 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); 699 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); 700 } 701 702 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) 703 { 704 u32 hw_version; 705 706 /* 707 * TODO dw drv improvements 708 * data & clock lane timers should be computed according to panel 709 * blankings and to the automatic clock lane control mode... 710 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with 711 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP) 712 */ 713 714 hw_version = dsi_read(dsi, DSI_VERSION) & VERSION; 715 716 if (hw_version >= HWVER_131) { 717 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(0x40) | 718 PHY_LP2HS_TIME_V131(0x40)); 719 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000)); 720 } else { 721 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) | 722 PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000)); 723 } 724 725 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40) 726 | PHY_CLKLP2HS_TIME(0x40)); 727 } 728 729 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) 730 { 731 /* 732 * TODO dw drv improvements 733 * stop wait time should be the maximum between host dsi 734 * and panel stop wait times 735 */ 736 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | 737 N_LANES(dsi->lanes)); 738 } 739 740 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi) 741 { 742 /* Clear PHY state */ 743 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK 744 | PHY_RSTZ | PHY_SHUTDOWNZ); 745 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 746 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR); 747 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 748 } 749 750 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi) 751 { 752 u32 val; 753 int ret; 754 755 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | 756 PHY_UNRSTZ | PHY_UNSHUTDOWNZ); 757 758 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val, 759 val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US); 760 if (ret) 761 DRM_DEBUG_DRIVER("failed to wait phy lock state\n"); 762 763 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 764 val, val & PHY_STOP_STATE_CLK_LANE, 1000, 765 PHY_STATUS_TIMEOUT_US); 766 if (ret) 767 DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n"); 768 } 769 770 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) 771 { 772 dsi_read(dsi, DSI_INT_ST0); 773 dsi_read(dsi, DSI_INT_ST1); 774 dsi_write(dsi, DSI_INT_MSK0, 0); 775 dsi_write(dsi, DSI_INT_MSK1, 0); 776 } 777 778 static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge) 779 { 780 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 781 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 782 783 if (phy_ops->power_off) 784 phy_ops->power_off(dsi->plat_data->priv_data); 785 786 /* 787 * Switch to command mode before panel-bridge post_disable & 788 * panel unprepare. 789 * Note: panel-bridge disable & panel disable has been called 790 * before by the drm framework. 791 */ 792 dw_mipi_dsi_set_mode(dsi, 0); 793 794 /* 795 * TODO Only way found to call panel-bridge post_disable & 796 * panel unprepare before the dsi "final" disable... 797 * This needs to be fixed in the drm_bridge framework and the API 798 * needs to be updated to manage our own call chains... 799 */ 800 dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge); 801 802 if (dsi->slave) { 803 dw_mipi_dsi_disable(dsi->slave); 804 clk_disable_unprepare(dsi->slave->pclk); 805 pm_runtime_put(dsi->slave->dev); 806 } 807 dw_mipi_dsi_disable(dsi); 808 809 clk_disable_unprepare(dsi->pclk); 810 pm_runtime_put(dsi->dev); 811 } 812 813 static unsigned int dw_mipi_dsi_get_lanes(struct dw_mipi_dsi *dsi) 814 { 815 /* this instance is the slave, so add the master's lanes */ 816 if (dsi->master) 817 return dsi->master->lanes + dsi->lanes; 818 819 /* this instance is the master, so add the slave's lanes */ 820 if (dsi->slave) 821 return dsi->lanes + dsi->slave->lanes; 822 823 /* single-dsi, so no other instance to consider */ 824 return dsi->lanes; 825 } 826 827 static void dw_mipi_dsi_mode_set(struct dw_mipi_dsi *dsi, 828 const struct drm_display_mode *adjusted_mode) 829 { 830 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 831 void *priv_data = dsi->plat_data->priv_data; 832 int ret; 833 u32 lanes = dw_mipi_dsi_get_lanes(dsi); 834 835 clk_prepare_enable(dsi->pclk); 836 837 ret = phy_ops->get_lane_mbps(priv_data, adjusted_mode, dsi->mode_flags, 838 lanes, dsi->format, &dsi->lane_mbps); 839 if (ret) 840 DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n"); 841 842 pm_runtime_get_sync(dsi->dev); 843 dw_mipi_dsi_init(dsi); 844 dw_mipi_dsi_dpi_config(dsi, adjusted_mode); 845 dw_mipi_dsi_packet_handler_config(dsi); 846 dw_mipi_dsi_video_mode_config(dsi); 847 dw_mipi_dsi_video_packet_config(dsi, adjusted_mode); 848 dw_mipi_dsi_command_mode_config(dsi); 849 dw_mipi_dsi_line_timer_config(dsi, adjusted_mode); 850 dw_mipi_dsi_vertical_timing_config(dsi, adjusted_mode); 851 852 dw_mipi_dsi_dphy_init(dsi); 853 dw_mipi_dsi_dphy_timing_config(dsi); 854 dw_mipi_dsi_dphy_interface_config(dsi); 855 856 dw_mipi_dsi_clear_err(dsi); 857 858 ret = phy_ops->init(priv_data); 859 if (ret) 860 DRM_DEBUG_DRIVER("Phy init() failed\n"); 861 862 dw_mipi_dsi_dphy_enable(dsi); 863 864 dw_mipi_dsi_wait_for_two_frames(adjusted_mode); 865 866 /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */ 867 dw_mipi_dsi_set_mode(dsi, 0); 868 } 869 870 static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge, 871 const struct drm_display_mode *mode, 872 const struct drm_display_mode *adjusted_mode) 873 { 874 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 875 876 dw_mipi_dsi_mode_set(dsi, adjusted_mode); 877 if (dsi->slave) 878 dw_mipi_dsi_mode_set(dsi->slave, adjusted_mode); 879 } 880 881 static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge) 882 { 883 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 884 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 885 886 /* Switch to video mode for panel-bridge enable & panel enable */ 887 dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO); 888 if (dsi->slave) 889 dw_mipi_dsi_set_mode(dsi->slave, MIPI_DSI_MODE_VIDEO); 890 891 if (phy_ops->power_on) 892 phy_ops->power_on(dsi->plat_data->priv_data); 893 } 894 895 static enum drm_mode_status 896 dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge, 897 const struct drm_display_mode *mode) 898 { 899 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 900 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 901 enum drm_mode_status mode_status = MODE_OK; 902 903 if (pdata->mode_valid) 904 mode_status = pdata->mode_valid(pdata->priv_data, mode); 905 906 return mode_status; 907 } 908 909 static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge) 910 { 911 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 912 913 if (!bridge->encoder) { 914 DRM_ERROR("Parent encoder object not found\n"); 915 return -ENODEV; 916 } 917 918 /* Set the encoder type as caller does not know it */ 919 bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI; 920 921 /* Attach the panel-bridge to the dsi bridge */ 922 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge); 923 } 924 925 static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = { 926 .mode_set = dw_mipi_dsi_bridge_mode_set, 927 .enable = dw_mipi_dsi_bridge_enable, 928 .post_disable = dw_mipi_dsi_bridge_post_disable, 929 .mode_valid = dw_mipi_dsi_bridge_mode_valid, 930 .attach = dw_mipi_dsi_bridge_attach, 931 }; 932 933 static struct dw_mipi_dsi * 934 __dw_mipi_dsi_probe(struct platform_device *pdev, 935 const struct dw_mipi_dsi_plat_data *plat_data) 936 { 937 struct device *dev = &pdev->dev; 938 struct reset_control *apb_rst; 939 struct dw_mipi_dsi *dsi; 940 struct resource *res; 941 int ret; 942 943 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 944 if (!dsi) 945 return ERR_PTR(-ENOMEM); 946 947 dsi->dev = dev; 948 dsi->plat_data = plat_data; 949 950 if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps) { 951 DRM_ERROR("Phy not properly configured\n"); 952 return ERR_PTR(-ENODEV); 953 } 954 955 if (!plat_data->base) { 956 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 957 if (!res) 958 return ERR_PTR(-ENODEV); 959 960 dsi->base = devm_ioremap_resource(dev, res); 961 if (IS_ERR(dsi->base)) 962 return ERR_PTR(-ENODEV); 963 964 } else { 965 dsi->base = plat_data->base; 966 } 967 968 dsi->pclk = devm_clk_get(dev, "pclk"); 969 if (IS_ERR(dsi->pclk)) { 970 ret = PTR_ERR(dsi->pclk); 971 dev_err(dev, "Unable to get pclk: %d\n", ret); 972 return ERR_PTR(ret); 973 } 974 975 /* 976 * Note that the reset was not defined in the initial device tree, so 977 * we have to be prepared for it not being found. 978 */ 979 apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb"); 980 if (IS_ERR(apb_rst)) { 981 ret = PTR_ERR(apb_rst); 982 983 if (ret != -EPROBE_DEFER) 984 dev_err(dev, "Unable to get reset control: %d\n", ret); 985 986 return ERR_PTR(ret); 987 } 988 989 if (apb_rst) { 990 ret = clk_prepare_enable(dsi->pclk); 991 if (ret) { 992 dev_err(dev, "%s: Failed to enable pclk\n", __func__); 993 return ERR_PTR(ret); 994 } 995 996 reset_control_assert(apb_rst); 997 usleep_range(10, 20); 998 reset_control_deassert(apb_rst); 999 1000 clk_disable_unprepare(dsi->pclk); 1001 } 1002 1003 pm_runtime_enable(dev); 1004 1005 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops; 1006 dsi->dsi_host.dev = dev; 1007 ret = mipi_dsi_host_register(&dsi->dsi_host); 1008 if (ret) { 1009 dev_err(dev, "Failed to register MIPI host: %d\n", ret); 1010 return ERR_PTR(ret); 1011 } 1012 1013 dsi->bridge.driver_private = dsi; 1014 dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs; 1015 #ifdef CONFIG_OF 1016 dsi->bridge.of_node = pdev->dev.of_node; 1017 #endif 1018 1019 return dsi; 1020 } 1021 1022 static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi) 1023 { 1024 mipi_dsi_host_unregister(&dsi->dsi_host); 1025 1026 pm_runtime_disable(dsi->dev); 1027 } 1028 1029 void dw_mipi_dsi_set_slave(struct dw_mipi_dsi *dsi, struct dw_mipi_dsi *slave) 1030 { 1031 /* introduce controllers to each other */ 1032 dsi->slave = slave; 1033 dsi->slave->master = dsi; 1034 1035 /* migrate settings for already attached displays */ 1036 dsi->slave->lanes = dsi->lanes; 1037 dsi->slave->channel = dsi->channel; 1038 dsi->slave->format = dsi->format; 1039 dsi->slave->mode_flags = dsi->mode_flags; 1040 } 1041 EXPORT_SYMBOL_GPL(dw_mipi_dsi_set_slave); 1042 1043 /* 1044 * Probe/remove API, used from platforms based on the DRM bridge API. 1045 */ 1046 struct dw_mipi_dsi * 1047 dw_mipi_dsi_probe(struct platform_device *pdev, 1048 const struct dw_mipi_dsi_plat_data *plat_data) 1049 { 1050 return __dw_mipi_dsi_probe(pdev, plat_data); 1051 } 1052 EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe); 1053 1054 void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi) 1055 { 1056 __dw_mipi_dsi_remove(dsi); 1057 } 1058 EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove); 1059 1060 /* 1061 * Bind/unbind API, used from platforms based on the component framework. 1062 */ 1063 int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder) 1064 { 1065 int ret; 1066 1067 ret = drm_bridge_attach(encoder, &dsi->bridge, NULL); 1068 if (ret) { 1069 DRM_ERROR("Failed to initialize bridge with drm\n"); 1070 return ret; 1071 } 1072 1073 return ret; 1074 } 1075 EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind); 1076 1077 void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi) 1078 { 1079 } 1080 EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind); 1081 1082 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>"); 1083 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1084 MODULE_DESCRIPTION("DW MIPI DSI host controller driver"); 1085 MODULE_LICENSE("GPL"); 1086 MODULE_ALIAS("platform:dw-mipi-dsi"); 1087