1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd 4 * Copyright (C) STMicroelectronics SA 2017 5 * 6 * Modified by Philippe Cornu <philippe.cornu@st.com> 7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the 8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs. 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/iopoll.h> 14 #include <linux/module.h> 15 #include <linux/of_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 #include <drm/drmP.h> 19 #include <drm/drm_atomic_helper.h> 20 #include <drm/drm_bridge.h> 21 #include <drm/drm_crtc.h> 22 #include <drm/drm_crtc_helper.h> 23 #include <drm/drm_mipi_dsi.h> 24 #include <drm/drm_of.h> 25 #include <drm/bridge/dw_mipi_dsi.h> 26 #include <video/mipi_display.h> 27 28 #define HWVER_131 0x31333100 /* IP version 1.31 */ 29 30 #define DSI_VERSION 0x00 31 #define VERSION GENMASK(31, 8) 32 33 #define DSI_PWR_UP 0x04 34 #define RESET 0 35 #define POWERUP BIT(0) 36 37 #define DSI_CLKMGR_CFG 0x08 38 #define TO_CLK_DIVISION(div) (((div) & 0xff) << 8) 39 #define TX_ESC_CLK_DIVISION(div) ((div) & 0xff) 40 41 #define DSI_DPI_VCID 0x0c 42 #define DPI_VCID(vcid) ((vcid) & 0x3) 43 44 #define DSI_DPI_COLOR_CODING 0x10 45 #define LOOSELY18_EN BIT(8) 46 #define DPI_COLOR_CODING_16BIT_1 0x0 47 #define DPI_COLOR_CODING_16BIT_2 0x1 48 #define DPI_COLOR_CODING_16BIT_3 0x2 49 #define DPI_COLOR_CODING_18BIT_1 0x3 50 #define DPI_COLOR_CODING_18BIT_2 0x4 51 #define DPI_COLOR_CODING_24BIT 0x5 52 53 #define DSI_DPI_CFG_POL 0x14 54 #define COLORM_ACTIVE_LOW BIT(4) 55 #define SHUTD_ACTIVE_LOW BIT(3) 56 #define HSYNC_ACTIVE_LOW BIT(2) 57 #define VSYNC_ACTIVE_LOW BIT(1) 58 #define DATAEN_ACTIVE_LOW BIT(0) 59 60 #define DSI_DPI_LP_CMD_TIM 0x18 61 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) 62 #define INVACT_LPCMD_TIME(p) ((p) & 0xff) 63 64 #define DSI_DBI_VCID 0x1c 65 #define DSI_DBI_CFG 0x20 66 #define DSI_DBI_PARTITIONING_EN 0x24 67 #define DSI_DBI_CMDSIZE 0x28 68 69 #define DSI_PCKHDL_CFG 0x2c 70 #define CRC_RX_EN BIT(4) 71 #define ECC_RX_EN BIT(3) 72 #define BTA_EN BIT(2) 73 #define EOTP_RX_EN BIT(1) 74 #define EOTP_TX_EN BIT(0) 75 76 #define DSI_GEN_VCID 0x30 77 78 #define DSI_MODE_CFG 0x34 79 #define ENABLE_VIDEO_MODE 0 80 #define ENABLE_CMD_MODE BIT(0) 81 82 #define DSI_VID_MODE_CFG 0x38 83 #define ENABLE_LOW_POWER (0x3f << 8) 84 #define ENABLE_LOW_POWER_MASK (0x3f << 8) 85 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0 86 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1 87 #define VID_MODE_TYPE_BURST 0x2 88 #define VID_MODE_TYPE_MASK 0x3 89 90 #define DSI_VID_PKT_SIZE 0x3c 91 #define VID_PKT_SIZE(p) ((p) & 0x3fff) 92 93 #define DSI_VID_NUM_CHUNKS 0x40 94 #define VID_NUM_CHUNKS(c) ((c) & 0x1fff) 95 96 #define DSI_VID_NULL_SIZE 0x44 97 #define VID_NULL_SIZE(b) ((b) & 0x1fff) 98 99 #define DSI_VID_HSA_TIME 0x48 100 #define DSI_VID_HBP_TIME 0x4c 101 #define DSI_VID_HLINE_TIME 0x50 102 #define DSI_VID_VSA_LINES 0x54 103 #define DSI_VID_VBP_LINES 0x58 104 #define DSI_VID_VFP_LINES 0x5c 105 #define DSI_VID_VACTIVE_LINES 0x60 106 #define DSI_EDPI_CMD_SIZE 0x64 107 108 #define DSI_CMD_MODE_CFG 0x68 109 #define MAX_RD_PKT_SIZE_LP BIT(24) 110 #define DCS_LW_TX_LP BIT(19) 111 #define DCS_SR_0P_TX_LP BIT(18) 112 #define DCS_SW_1P_TX_LP BIT(17) 113 #define DCS_SW_0P_TX_LP BIT(16) 114 #define GEN_LW_TX_LP BIT(14) 115 #define GEN_SR_2P_TX_LP BIT(13) 116 #define GEN_SR_1P_TX_LP BIT(12) 117 #define GEN_SR_0P_TX_LP BIT(11) 118 #define GEN_SW_2P_TX_LP BIT(10) 119 #define GEN_SW_1P_TX_LP BIT(9) 120 #define GEN_SW_0P_TX_LP BIT(8) 121 #define ACK_RQST_EN BIT(1) 122 #define TEAR_FX_EN BIT(0) 123 124 #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \ 125 DCS_LW_TX_LP | \ 126 DCS_SR_0P_TX_LP | \ 127 DCS_SW_1P_TX_LP | \ 128 DCS_SW_0P_TX_LP | \ 129 GEN_LW_TX_LP | \ 130 GEN_SR_2P_TX_LP | \ 131 GEN_SR_1P_TX_LP | \ 132 GEN_SR_0P_TX_LP | \ 133 GEN_SW_2P_TX_LP | \ 134 GEN_SW_1P_TX_LP | \ 135 GEN_SW_0P_TX_LP) 136 137 #define DSI_GEN_HDR 0x6c 138 #define DSI_GEN_PLD_DATA 0x70 139 140 #define DSI_CMD_PKT_STATUS 0x74 141 #define GEN_RD_CMD_BUSY BIT(6) 142 #define GEN_PLD_R_FULL BIT(5) 143 #define GEN_PLD_R_EMPTY BIT(4) 144 #define GEN_PLD_W_FULL BIT(3) 145 #define GEN_PLD_W_EMPTY BIT(2) 146 #define GEN_CMD_FULL BIT(1) 147 #define GEN_CMD_EMPTY BIT(0) 148 149 #define DSI_TO_CNT_CFG 0x78 150 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16) 151 #define LPRX_TO_CNT(p) ((p) & 0xffff) 152 153 #define DSI_HS_RD_TO_CNT 0x7c 154 #define DSI_LP_RD_TO_CNT 0x80 155 #define DSI_HS_WR_TO_CNT 0x84 156 #define DSI_LP_WR_TO_CNT 0x88 157 #define DSI_BTA_TO_CNT 0x8c 158 159 #define DSI_LPCLK_CTRL 0x94 160 #define AUTO_CLKLANE_CTRL BIT(1) 161 #define PHY_TXREQUESTCLKHS BIT(0) 162 163 #define DSI_PHY_TMR_LPCLK_CFG 0x98 164 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16) 165 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff) 166 167 #define DSI_PHY_TMR_CFG 0x9c 168 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24) 169 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16) 170 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) 171 #define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16) 172 #define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff) 173 174 #define DSI_PHY_RSTZ 0xa0 175 #define PHY_DISFORCEPLL 0 176 #define PHY_ENFORCEPLL BIT(3) 177 #define PHY_DISABLECLK 0 178 #define PHY_ENABLECLK BIT(2) 179 #define PHY_RSTZ 0 180 #define PHY_UNRSTZ BIT(1) 181 #define PHY_SHUTDOWNZ 0 182 #define PHY_UNSHUTDOWNZ BIT(0) 183 184 #define DSI_PHY_IF_CFG 0xa4 185 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 186 #define N_LANES(n) (((n) - 1) & 0x3) 187 188 #define DSI_PHY_ULPS_CTRL 0xa8 189 #define DSI_PHY_TX_TRIGGERS 0xac 190 191 #define DSI_PHY_STATUS 0xb0 192 #define PHY_STOP_STATE_CLK_LANE BIT(2) 193 #define PHY_LOCK BIT(0) 194 195 #define DSI_PHY_TST_CTRL0 0xb4 196 #define PHY_TESTCLK BIT(1) 197 #define PHY_UNTESTCLK 0 198 #define PHY_TESTCLR BIT(0) 199 #define PHY_UNTESTCLR 0 200 201 #define DSI_PHY_TST_CTRL1 0xb8 202 #define PHY_TESTEN BIT(16) 203 #define PHY_UNTESTEN 0 204 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 205 #define PHY_TESTDIN(n) ((n) & 0xff) 206 207 #define DSI_INT_ST0 0xbc 208 #define DSI_INT_ST1 0xc0 209 #define DSI_INT_MSK0 0xc4 210 #define DSI_INT_MSK1 0xc8 211 212 #define DSI_PHY_TMR_RD_CFG 0xf4 213 #define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff) 214 215 #define PHY_STATUS_TIMEOUT_US 10000 216 #define CMD_PKT_STATUS_TIMEOUT_US 20000 217 218 struct dw_mipi_dsi { 219 struct drm_bridge bridge; 220 struct mipi_dsi_host dsi_host; 221 struct drm_bridge *panel_bridge; 222 struct device *dev; 223 void __iomem *base; 224 225 struct clk *pclk; 226 227 unsigned int lane_mbps; /* per lane */ 228 u32 channel; 229 u32 lanes; 230 u32 format; 231 unsigned long mode_flags; 232 233 const struct dw_mipi_dsi_plat_data *plat_data; 234 }; 235 236 /* 237 * The controller should generate 2 frames before 238 * preparing the peripheral. 239 */ 240 static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode *mode) 241 { 242 int refresh, two_frames; 243 244 refresh = drm_mode_vrefresh(mode); 245 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2; 246 msleep(two_frames); 247 } 248 249 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host) 250 { 251 return container_of(host, struct dw_mipi_dsi, dsi_host); 252 } 253 254 static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge) 255 { 256 return container_of(bridge, struct dw_mipi_dsi, bridge); 257 } 258 259 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) 260 { 261 writel(val, dsi->base + reg); 262 } 263 264 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) 265 { 266 return readl(dsi->base + reg); 267 } 268 269 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 270 struct mipi_dsi_device *device) 271 { 272 struct dw_mipi_dsi *dsi = host_to_dsi(host); 273 struct drm_bridge *bridge; 274 struct drm_panel *panel; 275 int ret; 276 277 if (device->lanes > dsi->plat_data->max_data_lanes) { 278 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n", 279 device->lanes); 280 return -EINVAL; 281 } 282 283 dsi->lanes = device->lanes; 284 dsi->channel = device->channel; 285 dsi->format = device->format; 286 dsi->mode_flags = device->mode_flags; 287 288 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, 289 &panel, &bridge); 290 if (ret) 291 return ret; 292 293 if (panel) { 294 bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DSI); 295 if (IS_ERR(bridge)) 296 return PTR_ERR(bridge); 297 } 298 299 dsi->panel_bridge = bridge; 300 301 drm_bridge_add(&dsi->bridge); 302 303 return 0; 304 } 305 306 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, 307 struct mipi_dsi_device *device) 308 { 309 struct dw_mipi_dsi *dsi = host_to_dsi(host); 310 311 drm_of_panel_bridge_remove(host->dev->of_node, 1, 0); 312 313 drm_bridge_remove(&dsi->bridge); 314 315 return 0; 316 } 317 318 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, 319 const struct mipi_dsi_msg *msg) 320 { 321 bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM; 322 u32 val = 0; 323 324 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) 325 val |= ACK_RQST_EN; 326 if (lpm) 327 val |= CMD_MODE_ALL_LP; 328 329 dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS); 330 dsi_write(dsi, DSI_CMD_MODE_CFG, val); 331 } 332 333 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) 334 { 335 int ret; 336 u32 val, mask; 337 338 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 339 val, !(val & GEN_CMD_FULL), 1000, 340 CMD_PKT_STATUS_TIMEOUT_US); 341 if (ret) { 342 dev_err(dsi->dev, "failed to get available command FIFO\n"); 343 return ret; 344 } 345 346 dsi_write(dsi, DSI_GEN_HDR, hdr_val); 347 348 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 349 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 350 val, (val & mask) == mask, 351 1000, CMD_PKT_STATUS_TIMEOUT_US); 352 if (ret) { 353 dev_err(dsi->dev, "failed to write command FIFO\n"); 354 return ret; 355 } 356 357 return 0; 358 } 359 360 static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi, 361 const struct mipi_dsi_packet *packet) 362 { 363 const u8 *tx_buf = packet->payload; 364 int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret; 365 __le32 word; 366 u32 val; 367 368 while (len) { 369 if (len < pld_data_bytes) { 370 word = 0; 371 memcpy(&word, tx_buf, len); 372 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word)); 373 len = 0; 374 } else { 375 memcpy(&word, tx_buf, pld_data_bytes); 376 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word)); 377 tx_buf += pld_data_bytes; 378 len -= pld_data_bytes; 379 } 380 381 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 382 val, !(val & GEN_PLD_W_FULL), 1000, 383 CMD_PKT_STATUS_TIMEOUT_US); 384 if (ret) { 385 dev_err(dsi->dev, 386 "failed to get available write payload FIFO\n"); 387 return ret; 388 } 389 } 390 391 word = 0; 392 memcpy(&word, packet->header, sizeof(packet->header)); 393 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word)); 394 } 395 396 static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi, 397 const struct mipi_dsi_msg *msg) 398 { 399 int i, j, ret, len = msg->rx_len; 400 u8 *buf = msg->rx_buf; 401 u32 val; 402 403 /* Wait end of the read operation */ 404 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 405 val, !(val & GEN_RD_CMD_BUSY), 406 1000, CMD_PKT_STATUS_TIMEOUT_US); 407 if (ret) { 408 dev_err(dsi->dev, "Timeout during read operation\n"); 409 return ret; 410 } 411 412 for (i = 0; i < len; i += 4) { 413 /* Read fifo must not be empty before all bytes are read */ 414 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 415 val, !(val & GEN_PLD_R_EMPTY), 416 1000, CMD_PKT_STATUS_TIMEOUT_US); 417 if (ret) { 418 dev_err(dsi->dev, "Read payload FIFO is empty\n"); 419 return ret; 420 } 421 422 val = dsi_read(dsi, DSI_GEN_PLD_DATA); 423 for (j = 0; j < 4 && j + i < len; j++) 424 buf[i + j] = val >> (8 * j); 425 } 426 427 return ret; 428 } 429 430 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, 431 const struct mipi_dsi_msg *msg) 432 { 433 struct dw_mipi_dsi *dsi = host_to_dsi(host); 434 struct mipi_dsi_packet packet; 435 int ret, nb_bytes; 436 437 ret = mipi_dsi_create_packet(&packet, msg); 438 if (ret) { 439 dev_err(dsi->dev, "failed to create packet: %d\n", ret); 440 return ret; 441 } 442 443 dw_mipi_message_config(dsi, msg); 444 445 ret = dw_mipi_dsi_write(dsi, &packet); 446 if (ret) 447 return ret; 448 449 if (msg->rx_buf && msg->rx_len) { 450 ret = dw_mipi_dsi_read(dsi, msg); 451 if (ret) 452 return ret; 453 nb_bytes = msg->rx_len; 454 } else { 455 nb_bytes = packet.size; 456 } 457 458 return nb_bytes; 459 } 460 461 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = { 462 .attach = dw_mipi_dsi_host_attach, 463 .detach = dw_mipi_dsi_host_detach, 464 .transfer = dw_mipi_dsi_host_transfer, 465 }; 466 467 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) 468 { 469 u32 val; 470 471 /* 472 * TODO dw drv improvements 473 * enabling low power is panel-dependent, we should use the 474 * panel configuration here... 475 */ 476 val = ENABLE_LOW_POWER; 477 478 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 479 val |= VID_MODE_TYPE_BURST; 480 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 481 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 482 else 483 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 484 485 dsi_write(dsi, DSI_VID_MODE_CFG, val); 486 } 487 488 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, 489 unsigned long mode_flags) 490 { 491 dsi_write(dsi, DSI_PWR_UP, RESET); 492 493 if (mode_flags & MIPI_DSI_MODE_VIDEO) { 494 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE); 495 dw_mipi_dsi_video_mode_config(dsi); 496 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); 497 } else { 498 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 499 } 500 501 dsi_write(dsi, DSI_PWR_UP, POWERUP); 502 } 503 504 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) 505 { 506 dsi_write(dsi, DSI_PWR_UP, RESET); 507 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ); 508 } 509 510 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) 511 { 512 /* 513 * The maximum permitted escape clock is 20MHz and it is derived from 514 * lanebyteclk, which is running at "lane_mbps / 8". Thus we want: 515 * 516 * (lane_mbps >> 3) / esc_clk_division < 20 517 * which is: 518 * (lane_mbps >> 3) / 20 > esc_clk_division 519 */ 520 u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1; 521 522 dsi_write(dsi, DSI_PWR_UP, RESET); 523 524 /* 525 * TODO dw drv improvements 526 * timeout clock division should be computed with the 527 * high speed transmission counter timeout and byte lane... 528 */ 529 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) | 530 TX_ESC_CLK_DIVISION(esc_clk_division)); 531 } 532 533 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, 534 struct drm_display_mode *mode) 535 { 536 u32 val = 0, color = 0; 537 538 switch (dsi->format) { 539 case MIPI_DSI_FMT_RGB888: 540 color = DPI_COLOR_CODING_24BIT; 541 break; 542 case MIPI_DSI_FMT_RGB666: 543 color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN; 544 break; 545 case MIPI_DSI_FMT_RGB666_PACKED: 546 color = DPI_COLOR_CODING_18BIT_1; 547 break; 548 case MIPI_DSI_FMT_RGB565: 549 color = DPI_COLOR_CODING_16BIT_1; 550 break; 551 } 552 553 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 554 val |= VSYNC_ACTIVE_LOW; 555 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 556 val |= HSYNC_ACTIVE_LOW; 557 558 dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel)); 559 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); 560 dsi_write(dsi, DSI_DPI_CFG_POL, val); 561 /* 562 * TODO dw drv improvements 563 * largest packet sizes during hfp or during vsa/vpb/vfp 564 * should be computed according to byte lane, lane number and only 565 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS) 566 */ 567 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4) 568 | INVACT_LPCMD_TIME(4)); 569 } 570 571 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) 572 { 573 dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN); 574 } 575 576 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, 577 struct drm_display_mode *mode) 578 { 579 /* 580 * TODO dw drv improvements 581 * only burst mode is supported here. For non-burst video modes, 582 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC & 583 * DSI_VNPCR.NPSIZE... especially because this driver supports 584 * non-burst video modes, see dw_mipi_dsi_video_mode_config()... 585 */ 586 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay)); 587 } 588 589 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) 590 { 591 /* 592 * TODO dw drv improvements 593 * compute high speed transmission counter timeout according 594 * to the timeout clock division (TO_CLK_DIVISION) and byte lane... 595 */ 596 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); 597 /* 598 * TODO dw drv improvements 599 * the Bus-Turn-Around Timeout Counter should be computed 600 * according to byte lane... 601 */ 602 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); 603 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 604 } 605 606 /* Get lane byte clock cycles. */ 607 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, 608 struct drm_display_mode *mode, 609 u32 hcomponent) 610 { 611 u32 frac, lbcc; 612 613 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8; 614 615 frac = lbcc % mode->clock; 616 lbcc = lbcc / mode->clock; 617 if (frac) 618 lbcc++; 619 620 return lbcc; 621 } 622 623 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi, 624 struct drm_display_mode *mode) 625 { 626 u32 htotal, hsa, hbp, lbcc; 627 628 htotal = mode->htotal; 629 hsa = mode->hsync_end - mode->hsync_start; 630 hbp = mode->htotal - mode->hsync_end; 631 632 /* 633 * TODO dw drv improvements 634 * computations below may be improved... 635 */ 636 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal); 637 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); 638 639 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa); 640 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); 641 642 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp); 643 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); 644 } 645 646 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi, 647 struct drm_display_mode *mode) 648 { 649 u32 vactive, vsa, vfp, vbp; 650 651 vactive = mode->vdisplay; 652 vsa = mode->vsync_end - mode->vsync_start; 653 vfp = mode->vsync_start - mode->vdisplay; 654 vbp = mode->vtotal - mode->vsync_end; 655 656 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); 657 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); 658 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); 659 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); 660 } 661 662 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) 663 { 664 u32 hw_version; 665 666 /* 667 * TODO dw drv improvements 668 * data & clock lane timers should be computed according to panel 669 * blankings and to the automatic clock lane control mode... 670 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with 671 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP) 672 */ 673 674 hw_version = dsi_read(dsi, DSI_VERSION) & VERSION; 675 676 if (hw_version >= HWVER_131) { 677 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(0x40) | 678 PHY_LP2HS_TIME_V131(0x40)); 679 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000)); 680 } else { 681 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) | 682 PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000)); 683 } 684 685 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40) 686 | PHY_CLKLP2HS_TIME(0x40)); 687 } 688 689 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) 690 { 691 /* 692 * TODO dw drv improvements 693 * stop wait time should be the maximum between host dsi 694 * and panel stop wait times 695 */ 696 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | 697 N_LANES(dsi->lanes)); 698 } 699 700 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi) 701 { 702 /* Clear PHY state */ 703 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK 704 | PHY_RSTZ | PHY_SHUTDOWNZ); 705 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 706 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR); 707 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 708 } 709 710 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi) 711 { 712 u32 val; 713 int ret; 714 715 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | 716 PHY_UNRSTZ | PHY_UNSHUTDOWNZ); 717 718 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val, 719 val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US); 720 if (ret) 721 DRM_DEBUG_DRIVER("failed to wait phy lock state\n"); 722 723 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 724 val, val & PHY_STOP_STATE_CLK_LANE, 1000, 725 PHY_STATUS_TIMEOUT_US); 726 if (ret) 727 DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n"); 728 } 729 730 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) 731 { 732 dsi_read(dsi, DSI_INT_ST0); 733 dsi_read(dsi, DSI_INT_ST1); 734 dsi_write(dsi, DSI_INT_MSK0, 0); 735 dsi_write(dsi, DSI_INT_MSK1, 0); 736 } 737 738 static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge) 739 { 740 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 741 742 /* 743 * Switch to command mode before panel-bridge post_disable & 744 * panel unprepare. 745 * Note: panel-bridge disable & panel disable has been called 746 * before by the drm framework. 747 */ 748 dw_mipi_dsi_set_mode(dsi, 0); 749 750 /* 751 * TODO Only way found to call panel-bridge post_disable & 752 * panel unprepare before the dsi "final" disable... 753 * This needs to be fixed in the drm_bridge framework and the API 754 * needs to be updated to manage our own call chains... 755 */ 756 dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge); 757 758 dw_mipi_dsi_disable(dsi); 759 clk_disable_unprepare(dsi->pclk); 760 pm_runtime_put(dsi->dev); 761 } 762 763 static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge, 764 struct drm_display_mode *mode, 765 struct drm_display_mode *adjusted_mode) 766 { 767 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 768 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 769 void *priv_data = dsi->plat_data->priv_data; 770 int ret; 771 772 clk_prepare_enable(dsi->pclk); 773 774 ret = phy_ops->get_lane_mbps(priv_data, adjusted_mode, dsi->mode_flags, 775 dsi->lanes, dsi->format, &dsi->lane_mbps); 776 if (ret) 777 DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n"); 778 779 pm_runtime_get_sync(dsi->dev); 780 dw_mipi_dsi_init(dsi); 781 dw_mipi_dsi_dpi_config(dsi, adjusted_mode); 782 dw_mipi_dsi_packet_handler_config(dsi); 783 dw_mipi_dsi_video_mode_config(dsi); 784 dw_mipi_dsi_video_packet_config(dsi, adjusted_mode); 785 dw_mipi_dsi_command_mode_config(dsi); 786 dw_mipi_dsi_line_timer_config(dsi, adjusted_mode); 787 dw_mipi_dsi_vertical_timing_config(dsi, adjusted_mode); 788 789 dw_mipi_dsi_dphy_init(dsi); 790 dw_mipi_dsi_dphy_timing_config(dsi); 791 dw_mipi_dsi_dphy_interface_config(dsi); 792 793 dw_mipi_dsi_clear_err(dsi); 794 795 ret = phy_ops->init(priv_data); 796 if (ret) 797 DRM_DEBUG_DRIVER("Phy init() failed\n"); 798 799 dw_mipi_dsi_dphy_enable(dsi); 800 801 dw_mipi_dsi_wait_for_two_frames(adjusted_mode); 802 803 /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */ 804 dw_mipi_dsi_set_mode(dsi, 0); 805 } 806 807 static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge) 808 { 809 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 810 811 /* Switch to video mode for panel-bridge enable & panel enable */ 812 dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO); 813 } 814 815 static enum drm_mode_status 816 dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge, 817 const struct drm_display_mode *mode) 818 { 819 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 820 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 821 enum drm_mode_status mode_status = MODE_OK; 822 823 if (pdata->mode_valid) 824 mode_status = pdata->mode_valid(pdata->priv_data, mode); 825 826 return mode_status; 827 } 828 829 static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge) 830 { 831 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 832 833 if (!bridge->encoder) { 834 DRM_ERROR("Parent encoder object not found\n"); 835 return -ENODEV; 836 } 837 838 /* Set the encoder type as caller does not know it */ 839 bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI; 840 841 /* Attach the panel-bridge to the dsi bridge */ 842 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge); 843 } 844 845 static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = { 846 .mode_set = dw_mipi_dsi_bridge_mode_set, 847 .enable = dw_mipi_dsi_bridge_enable, 848 .post_disable = dw_mipi_dsi_bridge_post_disable, 849 .mode_valid = dw_mipi_dsi_bridge_mode_valid, 850 .attach = dw_mipi_dsi_bridge_attach, 851 }; 852 853 static struct dw_mipi_dsi * 854 __dw_mipi_dsi_probe(struct platform_device *pdev, 855 const struct dw_mipi_dsi_plat_data *plat_data) 856 { 857 struct device *dev = &pdev->dev; 858 struct reset_control *apb_rst; 859 struct dw_mipi_dsi *dsi; 860 struct resource *res; 861 int ret; 862 863 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 864 if (!dsi) 865 return ERR_PTR(-ENOMEM); 866 867 dsi->dev = dev; 868 dsi->plat_data = plat_data; 869 870 if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps) { 871 DRM_ERROR("Phy not properly configured\n"); 872 return ERR_PTR(-ENODEV); 873 } 874 875 if (!plat_data->base) { 876 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 877 if (!res) 878 return ERR_PTR(-ENODEV); 879 880 dsi->base = devm_ioremap_resource(dev, res); 881 if (IS_ERR(dsi->base)) 882 return ERR_PTR(-ENODEV); 883 884 } else { 885 dsi->base = plat_data->base; 886 } 887 888 dsi->pclk = devm_clk_get(dev, "pclk"); 889 if (IS_ERR(dsi->pclk)) { 890 ret = PTR_ERR(dsi->pclk); 891 dev_err(dev, "Unable to get pclk: %d\n", ret); 892 return ERR_PTR(ret); 893 } 894 895 /* 896 * Note that the reset was not defined in the initial device tree, so 897 * we have to be prepared for it not being found. 898 */ 899 apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb"); 900 if (IS_ERR(apb_rst)) { 901 ret = PTR_ERR(apb_rst); 902 903 if (ret != -EPROBE_DEFER) 904 dev_err(dev, "Unable to get reset control: %d\n", ret); 905 906 return ERR_PTR(ret); 907 } 908 909 if (apb_rst) { 910 ret = clk_prepare_enable(dsi->pclk); 911 if (ret) { 912 dev_err(dev, "%s: Failed to enable pclk\n", __func__); 913 return ERR_PTR(ret); 914 } 915 916 reset_control_assert(apb_rst); 917 usleep_range(10, 20); 918 reset_control_deassert(apb_rst); 919 920 clk_disable_unprepare(dsi->pclk); 921 } 922 923 pm_runtime_enable(dev); 924 925 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops; 926 dsi->dsi_host.dev = dev; 927 ret = mipi_dsi_host_register(&dsi->dsi_host); 928 if (ret) { 929 dev_err(dev, "Failed to register MIPI host: %d\n", ret); 930 return ERR_PTR(ret); 931 } 932 933 dsi->bridge.driver_private = dsi; 934 dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs; 935 #ifdef CONFIG_OF 936 dsi->bridge.of_node = pdev->dev.of_node; 937 #endif 938 939 return dsi; 940 } 941 942 static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi) 943 { 944 pm_runtime_disable(dsi->dev); 945 } 946 947 /* 948 * Probe/remove API, used from platforms based on the DRM bridge API. 949 */ 950 struct dw_mipi_dsi * 951 dw_mipi_dsi_probe(struct platform_device *pdev, 952 const struct dw_mipi_dsi_plat_data *plat_data) 953 { 954 return __dw_mipi_dsi_probe(pdev, plat_data); 955 } 956 EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe); 957 958 void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi) 959 { 960 mipi_dsi_host_unregister(&dsi->dsi_host); 961 962 __dw_mipi_dsi_remove(dsi); 963 } 964 EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove); 965 966 /* 967 * Bind/unbind API, used from platforms based on the component framework. 968 */ 969 struct dw_mipi_dsi * 970 dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder, 971 const struct dw_mipi_dsi_plat_data *plat_data) 972 { 973 struct dw_mipi_dsi *dsi; 974 int ret; 975 976 dsi = __dw_mipi_dsi_probe(pdev, plat_data); 977 if (IS_ERR(dsi)) 978 return dsi; 979 980 ret = drm_bridge_attach(encoder, &dsi->bridge, NULL); 981 if (ret) { 982 dw_mipi_dsi_remove(dsi); 983 DRM_ERROR("Failed to initialize bridge with drm\n"); 984 return ERR_PTR(ret); 985 } 986 987 return dsi; 988 } 989 EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind); 990 991 void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi) 992 { 993 __dw_mipi_dsi_remove(dsi); 994 } 995 EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind); 996 997 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>"); 998 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 999 MODULE_DESCRIPTION("DW MIPI DSI host controller driver"); 1000 MODULE_LICENSE("GPL"); 1001 MODULE_ALIAS("platform:dw-mipi-dsi"); 1002