1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd 4 * Copyright (C) STMicroelectronics SA 2017 5 * 6 * Modified by Philippe Cornu <philippe.cornu@st.com> 7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the 8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs. 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/debugfs.h> 14 #include <linux/iopoll.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/reset.h> 19 20 #include <video/mipi_display.h> 21 22 #include <drm/bridge/dw_mipi_dsi.h> 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_crtc.h> 26 #include <drm/drm_mipi_dsi.h> 27 #include <drm/drm_modes.h> 28 #include <drm/drm_of.h> 29 #include <drm/drm_print.h> 30 31 #define HWVER_131 0x31333100 /* IP version 1.31 */ 32 33 #define DSI_VERSION 0x00 34 #define VERSION GENMASK(31, 8) 35 36 #define DSI_PWR_UP 0x04 37 #define RESET 0 38 #define POWERUP BIT(0) 39 40 #define DSI_CLKMGR_CFG 0x08 41 #define TO_CLK_DIVISION(div) (((div) & 0xff) << 8) 42 #define TX_ESC_CLK_DIVISION(div) ((div) & 0xff) 43 44 #define DSI_DPI_VCID 0x0c 45 #define DPI_VCID(vcid) ((vcid) & 0x3) 46 47 #define DSI_DPI_COLOR_CODING 0x10 48 #define LOOSELY18_EN BIT(8) 49 #define DPI_COLOR_CODING_16BIT_1 0x0 50 #define DPI_COLOR_CODING_16BIT_2 0x1 51 #define DPI_COLOR_CODING_16BIT_3 0x2 52 #define DPI_COLOR_CODING_18BIT_1 0x3 53 #define DPI_COLOR_CODING_18BIT_2 0x4 54 #define DPI_COLOR_CODING_24BIT 0x5 55 56 #define DSI_DPI_CFG_POL 0x14 57 #define COLORM_ACTIVE_LOW BIT(4) 58 #define SHUTD_ACTIVE_LOW BIT(3) 59 #define HSYNC_ACTIVE_LOW BIT(2) 60 #define VSYNC_ACTIVE_LOW BIT(1) 61 #define DATAEN_ACTIVE_LOW BIT(0) 62 63 #define DSI_DPI_LP_CMD_TIM 0x18 64 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) 65 #define INVACT_LPCMD_TIME(p) ((p) & 0xff) 66 67 #define DSI_DBI_VCID 0x1c 68 #define DSI_DBI_CFG 0x20 69 #define DSI_DBI_PARTITIONING_EN 0x24 70 #define DSI_DBI_CMDSIZE 0x28 71 72 #define DSI_PCKHDL_CFG 0x2c 73 #define CRC_RX_EN BIT(4) 74 #define ECC_RX_EN BIT(3) 75 #define BTA_EN BIT(2) 76 #define EOTP_RX_EN BIT(1) 77 #define EOTP_TX_EN BIT(0) 78 79 #define DSI_GEN_VCID 0x30 80 81 #define DSI_MODE_CFG 0x34 82 #define ENABLE_VIDEO_MODE 0 83 #define ENABLE_CMD_MODE BIT(0) 84 85 #define DSI_VID_MODE_CFG 0x38 86 #define ENABLE_LOW_POWER (0x3f << 8) 87 #define ENABLE_LOW_POWER_MASK (0x3f << 8) 88 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0 89 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1 90 #define VID_MODE_TYPE_BURST 0x2 91 #define VID_MODE_TYPE_MASK 0x3 92 #define ENABLE_LOW_POWER_CMD BIT(15) 93 #define VID_MODE_VPG_ENABLE BIT(16) 94 #define VID_MODE_VPG_MODE BIT(20) 95 #define VID_MODE_VPG_HORIZONTAL BIT(24) 96 97 #define DSI_VID_PKT_SIZE 0x3c 98 #define VID_PKT_SIZE(p) ((p) & 0x3fff) 99 100 #define DSI_VID_NUM_CHUNKS 0x40 101 #define VID_NUM_CHUNKS(c) ((c) & 0x1fff) 102 103 #define DSI_VID_NULL_SIZE 0x44 104 #define VID_NULL_SIZE(b) ((b) & 0x1fff) 105 106 #define DSI_VID_HSA_TIME 0x48 107 #define DSI_VID_HBP_TIME 0x4c 108 #define DSI_VID_HLINE_TIME 0x50 109 #define DSI_VID_VSA_LINES 0x54 110 #define DSI_VID_VBP_LINES 0x58 111 #define DSI_VID_VFP_LINES 0x5c 112 #define DSI_VID_VACTIVE_LINES 0x60 113 #define DSI_EDPI_CMD_SIZE 0x64 114 115 #define DSI_CMD_MODE_CFG 0x68 116 #define MAX_RD_PKT_SIZE_LP BIT(24) 117 #define DCS_LW_TX_LP BIT(19) 118 #define DCS_SR_0P_TX_LP BIT(18) 119 #define DCS_SW_1P_TX_LP BIT(17) 120 #define DCS_SW_0P_TX_LP BIT(16) 121 #define GEN_LW_TX_LP BIT(14) 122 #define GEN_SR_2P_TX_LP BIT(13) 123 #define GEN_SR_1P_TX_LP BIT(12) 124 #define GEN_SR_0P_TX_LP BIT(11) 125 #define GEN_SW_2P_TX_LP BIT(10) 126 #define GEN_SW_1P_TX_LP BIT(9) 127 #define GEN_SW_0P_TX_LP BIT(8) 128 #define ACK_RQST_EN BIT(1) 129 #define TEAR_FX_EN BIT(0) 130 131 #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \ 132 DCS_LW_TX_LP | \ 133 DCS_SR_0P_TX_LP | \ 134 DCS_SW_1P_TX_LP | \ 135 DCS_SW_0P_TX_LP | \ 136 GEN_LW_TX_LP | \ 137 GEN_SR_2P_TX_LP | \ 138 GEN_SR_1P_TX_LP | \ 139 GEN_SR_0P_TX_LP | \ 140 GEN_SW_2P_TX_LP | \ 141 GEN_SW_1P_TX_LP | \ 142 GEN_SW_0P_TX_LP) 143 144 #define DSI_GEN_HDR 0x6c 145 #define DSI_GEN_PLD_DATA 0x70 146 147 #define DSI_CMD_PKT_STATUS 0x74 148 #define GEN_RD_CMD_BUSY BIT(6) 149 #define GEN_PLD_R_FULL BIT(5) 150 #define GEN_PLD_R_EMPTY BIT(4) 151 #define GEN_PLD_W_FULL BIT(3) 152 #define GEN_PLD_W_EMPTY BIT(2) 153 #define GEN_CMD_FULL BIT(1) 154 #define GEN_CMD_EMPTY BIT(0) 155 156 #define DSI_TO_CNT_CFG 0x78 157 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16) 158 #define LPRX_TO_CNT(p) ((p) & 0xffff) 159 160 #define DSI_HS_RD_TO_CNT 0x7c 161 #define DSI_LP_RD_TO_CNT 0x80 162 #define DSI_HS_WR_TO_CNT 0x84 163 #define DSI_LP_WR_TO_CNT 0x88 164 #define DSI_BTA_TO_CNT 0x8c 165 166 #define DSI_LPCLK_CTRL 0x94 167 #define AUTO_CLKLANE_CTRL BIT(1) 168 #define PHY_TXREQUESTCLKHS BIT(0) 169 170 #define DSI_PHY_TMR_LPCLK_CFG 0x98 171 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16) 172 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff) 173 174 #define DSI_PHY_TMR_CFG 0x9c 175 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24) 176 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16) 177 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) 178 #define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16) 179 #define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff) 180 181 #define DSI_PHY_RSTZ 0xa0 182 #define PHY_DISFORCEPLL 0 183 #define PHY_ENFORCEPLL BIT(3) 184 #define PHY_DISABLECLK 0 185 #define PHY_ENABLECLK BIT(2) 186 #define PHY_RSTZ 0 187 #define PHY_UNRSTZ BIT(1) 188 #define PHY_SHUTDOWNZ 0 189 #define PHY_UNSHUTDOWNZ BIT(0) 190 191 #define DSI_PHY_IF_CFG 0xa4 192 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 193 #define N_LANES(n) (((n) - 1) & 0x3) 194 195 #define DSI_PHY_ULPS_CTRL 0xa8 196 #define DSI_PHY_TX_TRIGGERS 0xac 197 198 #define DSI_PHY_STATUS 0xb0 199 #define PHY_STOP_STATE_CLK_LANE BIT(2) 200 #define PHY_LOCK BIT(0) 201 202 #define DSI_PHY_TST_CTRL0 0xb4 203 #define PHY_TESTCLK BIT(1) 204 #define PHY_UNTESTCLK 0 205 #define PHY_TESTCLR BIT(0) 206 #define PHY_UNTESTCLR 0 207 208 #define DSI_PHY_TST_CTRL1 0xb8 209 #define PHY_TESTEN BIT(16) 210 #define PHY_UNTESTEN 0 211 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 212 #define PHY_TESTDIN(n) ((n) & 0xff) 213 214 #define DSI_INT_ST0 0xbc 215 #define DSI_INT_ST1 0xc0 216 #define DSI_INT_MSK0 0xc4 217 #define DSI_INT_MSK1 0xc8 218 219 #define DSI_PHY_TMR_RD_CFG 0xf4 220 #define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff) 221 222 #define PHY_STATUS_TIMEOUT_US 10000 223 #define CMD_PKT_STATUS_TIMEOUT_US 20000 224 225 #ifdef CONFIG_DEBUG_FS 226 #define VPG_DEFS(name, dsi) \ 227 ((void __force *)&((*dsi).vpg_defs.name)) 228 229 #define REGISTER(name, mask, dsi) \ 230 { #name, VPG_DEFS(name, dsi), mask, dsi } 231 232 struct debugfs_entries { 233 const char *name; 234 bool *reg; 235 u32 mask; 236 struct dw_mipi_dsi *dsi; 237 }; 238 #endif /* CONFIG_DEBUG_FS */ 239 240 struct dw_mipi_dsi { 241 struct drm_bridge bridge; 242 struct mipi_dsi_host dsi_host; 243 struct drm_bridge *panel_bridge; 244 struct device *dev; 245 void __iomem *base; 246 247 struct clk *pclk; 248 249 unsigned int lane_mbps; /* per lane */ 250 u32 channel; 251 u32 lanes; 252 u32 format; 253 unsigned long mode_flags; 254 255 #ifdef CONFIG_DEBUG_FS 256 struct dentry *debugfs; 257 struct debugfs_entries *debugfs_vpg; 258 struct { 259 bool vpg; 260 bool vpg_horizontal; 261 bool vpg_ber_pattern; 262 } vpg_defs; 263 #endif /* CONFIG_DEBUG_FS */ 264 265 struct dw_mipi_dsi *master; /* dual-dsi master ptr */ 266 struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */ 267 268 struct drm_display_mode mode; 269 const struct dw_mipi_dsi_plat_data *plat_data; 270 }; 271 272 /* 273 * Check if either a link to a master or slave is present 274 */ 275 static inline bool dw_mipi_is_dual_mode(struct dw_mipi_dsi *dsi) 276 { 277 return dsi->slave || dsi->master; 278 } 279 280 /* 281 * The controller should generate 2 frames before 282 * preparing the peripheral. 283 */ 284 static void dw_mipi_dsi_wait_for_two_frames(const struct drm_display_mode *mode) 285 { 286 int refresh, two_frames; 287 288 refresh = drm_mode_vrefresh(mode); 289 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2; 290 msleep(two_frames); 291 } 292 293 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host) 294 { 295 return container_of(host, struct dw_mipi_dsi, dsi_host); 296 } 297 298 static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge) 299 { 300 return container_of(bridge, struct dw_mipi_dsi, bridge); 301 } 302 303 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) 304 { 305 writel(val, dsi->base + reg); 306 } 307 308 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) 309 { 310 return readl(dsi->base + reg); 311 } 312 313 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 314 struct mipi_dsi_device *device) 315 { 316 struct dw_mipi_dsi *dsi = host_to_dsi(host); 317 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 318 struct drm_bridge *bridge; 319 int ret; 320 321 if (device->lanes > dsi->plat_data->max_data_lanes) { 322 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n", 323 device->lanes); 324 return -EINVAL; 325 } 326 327 dsi->lanes = device->lanes; 328 dsi->channel = device->channel; 329 dsi->format = device->format; 330 dsi->mode_flags = device->mode_flags; 331 332 bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node, 1, 0); 333 if (IS_ERR(bridge)) 334 return PTR_ERR(bridge); 335 336 bridge->pre_enable_prev_first = true; 337 dsi->panel_bridge = bridge; 338 339 drm_bridge_add(&dsi->bridge); 340 341 if (pdata->host_ops && pdata->host_ops->attach) { 342 ret = pdata->host_ops->attach(pdata->priv_data, device); 343 if (ret < 0) 344 return ret; 345 } 346 347 return 0; 348 } 349 350 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, 351 struct mipi_dsi_device *device) 352 { 353 struct dw_mipi_dsi *dsi = host_to_dsi(host); 354 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 355 int ret; 356 357 if (pdata->host_ops && pdata->host_ops->detach) { 358 ret = pdata->host_ops->detach(pdata->priv_data, device); 359 if (ret < 0) 360 return ret; 361 } 362 363 drm_of_panel_bridge_remove(host->dev->of_node, 1, 0); 364 365 drm_bridge_remove(&dsi->bridge); 366 367 return 0; 368 } 369 370 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, 371 const struct mipi_dsi_msg *msg) 372 { 373 bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM; 374 u32 val = 0; 375 376 /* 377 * TODO dw drv improvements 378 * largest packet sizes during hfp or during vsa/vpb/vfp 379 * should be computed according to byte lane, lane number and only 380 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS) 381 */ 382 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(16) 383 | INVACT_LPCMD_TIME(4)); 384 385 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) 386 val |= ACK_RQST_EN; 387 if (lpm) 388 val |= CMD_MODE_ALL_LP; 389 390 dsi_write(dsi, DSI_CMD_MODE_CFG, val); 391 392 val = dsi_read(dsi, DSI_VID_MODE_CFG); 393 if (lpm) 394 val |= ENABLE_LOW_POWER_CMD; 395 else 396 val &= ~ENABLE_LOW_POWER_CMD; 397 dsi_write(dsi, DSI_VID_MODE_CFG, val); 398 } 399 400 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) 401 { 402 int ret; 403 u32 val, mask; 404 405 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 406 val, !(val & GEN_CMD_FULL), 1000, 407 CMD_PKT_STATUS_TIMEOUT_US); 408 if (ret) { 409 dev_err(dsi->dev, "failed to get available command FIFO\n"); 410 return ret; 411 } 412 413 dsi_write(dsi, DSI_GEN_HDR, hdr_val); 414 415 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 416 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 417 val, (val & mask) == mask, 418 1000, CMD_PKT_STATUS_TIMEOUT_US); 419 if (ret) { 420 dev_err(dsi->dev, "failed to write command FIFO\n"); 421 return ret; 422 } 423 424 return 0; 425 } 426 427 static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi, 428 const struct mipi_dsi_packet *packet) 429 { 430 const u8 *tx_buf = packet->payload; 431 int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret; 432 __le32 word; 433 u32 val; 434 435 while (len) { 436 if (len < pld_data_bytes) { 437 word = 0; 438 memcpy(&word, tx_buf, len); 439 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word)); 440 len = 0; 441 } else { 442 memcpy(&word, tx_buf, pld_data_bytes); 443 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word)); 444 tx_buf += pld_data_bytes; 445 len -= pld_data_bytes; 446 } 447 448 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 449 val, !(val & GEN_PLD_W_FULL), 1000, 450 CMD_PKT_STATUS_TIMEOUT_US); 451 if (ret) { 452 dev_err(dsi->dev, 453 "failed to get available write payload FIFO\n"); 454 return ret; 455 } 456 } 457 458 word = 0; 459 memcpy(&word, packet->header, sizeof(packet->header)); 460 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word)); 461 } 462 463 static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi, 464 const struct mipi_dsi_msg *msg) 465 { 466 int i, j, ret, len = msg->rx_len; 467 u8 *buf = msg->rx_buf; 468 u32 val; 469 470 /* Wait end of the read operation */ 471 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 472 val, !(val & GEN_RD_CMD_BUSY), 473 1000, CMD_PKT_STATUS_TIMEOUT_US); 474 if (ret) { 475 dev_err(dsi->dev, "Timeout during read operation\n"); 476 return ret; 477 } 478 479 for (i = 0; i < len; i += 4) { 480 /* Read fifo must not be empty before all bytes are read */ 481 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 482 val, !(val & GEN_PLD_R_EMPTY), 483 1000, CMD_PKT_STATUS_TIMEOUT_US); 484 if (ret) { 485 dev_err(dsi->dev, "Read payload FIFO is empty\n"); 486 return ret; 487 } 488 489 val = dsi_read(dsi, DSI_GEN_PLD_DATA); 490 for (j = 0; j < 4 && j + i < len; j++) 491 buf[i + j] = val >> (8 * j); 492 } 493 494 return ret; 495 } 496 497 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, 498 const struct mipi_dsi_msg *msg) 499 { 500 struct dw_mipi_dsi *dsi = host_to_dsi(host); 501 struct mipi_dsi_packet packet; 502 int ret, nb_bytes; 503 504 ret = mipi_dsi_create_packet(&packet, msg); 505 if (ret) { 506 dev_err(dsi->dev, "failed to create packet: %d\n", ret); 507 return ret; 508 } 509 510 dw_mipi_message_config(dsi, msg); 511 if (dsi->slave) 512 dw_mipi_message_config(dsi->slave, msg); 513 514 ret = dw_mipi_dsi_write(dsi, &packet); 515 if (ret) 516 return ret; 517 if (dsi->slave) { 518 ret = dw_mipi_dsi_write(dsi->slave, &packet); 519 if (ret) 520 return ret; 521 } 522 523 if (msg->rx_buf && msg->rx_len) { 524 ret = dw_mipi_dsi_read(dsi, msg); 525 if (ret) 526 return ret; 527 nb_bytes = msg->rx_len; 528 } else { 529 nb_bytes = packet.size; 530 } 531 532 return nb_bytes; 533 } 534 535 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = { 536 .attach = dw_mipi_dsi_host_attach, 537 .detach = dw_mipi_dsi_host_detach, 538 .transfer = dw_mipi_dsi_host_transfer, 539 }; 540 541 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) 542 { 543 u32 val; 544 545 /* 546 * TODO dw drv improvements 547 * enabling low power is panel-dependent, we should use the 548 * panel configuration here... 549 */ 550 val = ENABLE_LOW_POWER; 551 552 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 553 val |= VID_MODE_TYPE_BURST; 554 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 555 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 556 else 557 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 558 559 #ifdef CONFIG_DEBUG_FS 560 if (dsi->vpg_defs.vpg) { 561 val |= VID_MODE_VPG_ENABLE; 562 val |= dsi->vpg_defs.vpg_horizontal ? 563 VID_MODE_VPG_HORIZONTAL : 0; 564 val |= dsi->vpg_defs.vpg_ber_pattern ? VID_MODE_VPG_MODE : 0; 565 } 566 #endif /* CONFIG_DEBUG_FS */ 567 568 dsi_write(dsi, DSI_VID_MODE_CFG, val); 569 } 570 571 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, 572 unsigned long mode_flags) 573 { 574 u32 val; 575 576 dsi_write(dsi, DSI_PWR_UP, RESET); 577 578 if (mode_flags & MIPI_DSI_MODE_VIDEO) { 579 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE); 580 dw_mipi_dsi_video_mode_config(dsi); 581 } else { 582 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 583 } 584 585 val = PHY_TXREQUESTCLKHS; 586 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 587 val |= AUTO_CLKLANE_CTRL; 588 dsi_write(dsi, DSI_LPCLK_CTRL, val); 589 590 dsi_write(dsi, DSI_PWR_UP, POWERUP); 591 } 592 593 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) 594 { 595 dsi_write(dsi, DSI_PWR_UP, RESET); 596 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ); 597 } 598 599 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) 600 { 601 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 602 unsigned int esc_rate; /* in MHz */ 603 u32 esc_clk_division; 604 int ret; 605 606 /* 607 * The maximum permitted escape clock is 20MHz and it is derived from 608 * lanebyteclk, which is running at "lane_mbps / 8". 609 */ 610 if (phy_ops->get_esc_clk_rate) { 611 ret = phy_ops->get_esc_clk_rate(dsi->plat_data->priv_data, 612 &esc_rate); 613 if (ret) 614 DRM_DEBUG_DRIVER("Phy get_esc_clk_rate() failed\n"); 615 } else 616 esc_rate = 20; /* Default to 20MHz */ 617 618 /* 619 * We want : 620 * (lane_mbps >> 3) / esc_clk_division < X 621 * which is: 622 * (lane_mbps >> 3) / X > esc_clk_division 623 */ 624 esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1; 625 626 dsi_write(dsi, DSI_PWR_UP, RESET); 627 628 /* 629 * TODO dw drv improvements 630 * timeout clock division should be computed with the 631 * high speed transmission counter timeout and byte lane... 632 */ 633 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) | 634 TX_ESC_CLK_DIVISION(esc_clk_division)); 635 } 636 637 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, 638 const struct drm_display_mode *mode) 639 { 640 u32 val = 0, color = 0; 641 642 switch (dsi->format) { 643 case MIPI_DSI_FMT_RGB888: 644 color = DPI_COLOR_CODING_24BIT; 645 break; 646 case MIPI_DSI_FMT_RGB666: 647 color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN; 648 break; 649 case MIPI_DSI_FMT_RGB666_PACKED: 650 color = DPI_COLOR_CODING_18BIT_1; 651 break; 652 case MIPI_DSI_FMT_RGB565: 653 color = DPI_COLOR_CODING_16BIT_1; 654 break; 655 } 656 657 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 658 val |= VSYNC_ACTIVE_LOW; 659 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 660 val |= HSYNC_ACTIVE_LOW; 661 662 dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel)); 663 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); 664 dsi_write(dsi, DSI_DPI_CFG_POL, val); 665 } 666 667 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) 668 { 669 dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN); 670 } 671 672 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, 673 const struct drm_display_mode *mode) 674 { 675 /* 676 * TODO dw drv improvements 677 * only burst mode is supported here. For non-burst video modes, 678 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC & 679 * DSI_VNPCR.NPSIZE... especially because this driver supports 680 * non-burst video modes, see dw_mipi_dsi_video_mode_config()... 681 */ 682 683 dsi_write(dsi, DSI_VID_PKT_SIZE, 684 dw_mipi_is_dual_mode(dsi) ? 685 VID_PKT_SIZE(mode->hdisplay / 2) : 686 VID_PKT_SIZE(mode->hdisplay)); 687 } 688 689 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) 690 { 691 /* 692 * TODO dw drv improvements 693 * compute high speed transmission counter timeout according 694 * to the timeout clock division (TO_CLK_DIVISION) and byte lane... 695 */ 696 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); 697 /* 698 * TODO dw drv improvements 699 * the Bus-Turn-Around Timeout Counter should be computed 700 * according to byte lane... 701 */ 702 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); 703 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 704 } 705 706 /* Get lane byte clock cycles. */ 707 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, 708 const struct drm_display_mode *mode, 709 u32 hcomponent) 710 { 711 u32 frac, lbcc; 712 713 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8; 714 715 frac = lbcc % mode->clock; 716 lbcc = lbcc / mode->clock; 717 if (frac) 718 lbcc++; 719 720 return lbcc; 721 } 722 723 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi, 724 const struct drm_display_mode *mode) 725 { 726 u32 htotal, hsa, hbp, lbcc; 727 728 htotal = mode->htotal; 729 hsa = mode->hsync_end - mode->hsync_start; 730 hbp = mode->htotal - mode->hsync_end; 731 732 /* 733 * TODO dw drv improvements 734 * computations below may be improved... 735 */ 736 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal); 737 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); 738 739 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa); 740 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); 741 742 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp); 743 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); 744 } 745 746 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi, 747 const struct drm_display_mode *mode) 748 { 749 u32 vactive, vsa, vfp, vbp; 750 751 vactive = mode->vdisplay; 752 vsa = mode->vsync_end - mode->vsync_start; 753 vfp = mode->vsync_start - mode->vdisplay; 754 vbp = mode->vtotal - mode->vsync_end; 755 756 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); 757 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); 758 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); 759 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); 760 } 761 762 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) 763 { 764 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 765 struct dw_mipi_dsi_dphy_timing timing; 766 u32 hw_version; 767 int ret; 768 769 ret = phy_ops->get_timing(dsi->plat_data->priv_data, 770 dsi->lane_mbps, &timing); 771 if (ret) 772 DRM_DEV_ERROR(dsi->dev, "Retrieving phy timings failed\n"); 773 774 /* 775 * TODO dw drv improvements 776 * data & clock lane timers should be computed according to panel 777 * blankings and to the automatic clock lane control mode... 778 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with 779 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP) 780 */ 781 782 hw_version = dsi_read(dsi, DSI_VERSION) & VERSION; 783 784 if (hw_version >= HWVER_131) { 785 dsi_write(dsi, DSI_PHY_TMR_CFG, 786 PHY_HS2LP_TIME_V131(timing.data_hs2lp) | 787 PHY_LP2HS_TIME_V131(timing.data_lp2hs)); 788 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000)); 789 } else { 790 dsi_write(dsi, DSI_PHY_TMR_CFG, 791 PHY_HS2LP_TIME(timing.data_hs2lp) | 792 PHY_LP2HS_TIME(timing.data_lp2hs) | 793 MAX_RD_TIME(10000)); 794 } 795 796 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, 797 PHY_CLKHS2LP_TIME(timing.clk_hs2lp) | 798 PHY_CLKLP2HS_TIME(timing.clk_lp2hs)); 799 } 800 801 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) 802 { 803 /* 804 * TODO dw drv improvements 805 * stop wait time should be the maximum between host dsi 806 * and panel stop wait times 807 */ 808 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | 809 N_LANES(dsi->lanes)); 810 } 811 812 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi) 813 { 814 /* Clear PHY state */ 815 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK 816 | PHY_RSTZ | PHY_SHUTDOWNZ); 817 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 818 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR); 819 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 820 } 821 822 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi) 823 { 824 u32 val; 825 int ret; 826 827 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | 828 PHY_UNRSTZ | PHY_UNSHUTDOWNZ); 829 830 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val, 831 val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US); 832 if (ret) 833 DRM_DEBUG_DRIVER("failed to wait phy lock state\n"); 834 835 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 836 val, val & PHY_STOP_STATE_CLK_LANE, 1000, 837 PHY_STATUS_TIMEOUT_US); 838 if (ret) 839 DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n"); 840 } 841 842 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) 843 { 844 dsi_read(dsi, DSI_INT_ST0); 845 dsi_read(dsi, DSI_INT_ST1); 846 dsi_write(dsi, DSI_INT_MSK0, 0); 847 dsi_write(dsi, DSI_INT_MSK1, 0); 848 } 849 850 static void dw_mipi_dsi_bridge_post_atomic_disable(struct drm_bridge *bridge, 851 struct drm_bridge_state *old_bridge_state) 852 { 853 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 854 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 855 856 /* 857 * Switch to command mode before panel-bridge post_disable & 858 * panel unprepare. 859 * Note: panel-bridge disable & panel disable has been called 860 * before by the drm framework. 861 */ 862 dw_mipi_dsi_set_mode(dsi, 0); 863 864 if (phy_ops->power_off) 865 phy_ops->power_off(dsi->plat_data->priv_data); 866 867 if (dsi->slave) { 868 dw_mipi_dsi_disable(dsi->slave); 869 clk_disable_unprepare(dsi->slave->pclk); 870 pm_runtime_put(dsi->slave->dev); 871 } 872 dw_mipi_dsi_disable(dsi); 873 874 clk_disable_unprepare(dsi->pclk); 875 pm_runtime_put(dsi->dev); 876 } 877 878 static unsigned int dw_mipi_dsi_get_lanes(struct dw_mipi_dsi *dsi) 879 { 880 /* this instance is the slave, so add the master's lanes */ 881 if (dsi->master) 882 return dsi->master->lanes + dsi->lanes; 883 884 /* this instance is the master, so add the slave's lanes */ 885 if (dsi->slave) 886 return dsi->lanes + dsi->slave->lanes; 887 888 /* single-dsi, so no other instance to consider */ 889 return dsi->lanes; 890 } 891 892 static void dw_mipi_dsi_mode_set(struct dw_mipi_dsi *dsi, 893 const struct drm_display_mode *adjusted_mode) 894 { 895 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 896 void *priv_data = dsi->plat_data->priv_data; 897 int ret; 898 u32 lanes = dw_mipi_dsi_get_lanes(dsi); 899 900 clk_prepare_enable(dsi->pclk); 901 902 ret = phy_ops->get_lane_mbps(priv_data, adjusted_mode, dsi->mode_flags, 903 lanes, dsi->format, &dsi->lane_mbps); 904 if (ret) 905 DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n"); 906 907 pm_runtime_get_sync(dsi->dev); 908 dw_mipi_dsi_init(dsi); 909 dw_mipi_dsi_dpi_config(dsi, adjusted_mode); 910 dw_mipi_dsi_packet_handler_config(dsi); 911 dw_mipi_dsi_video_mode_config(dsi); 912 dw_mipi_dsi_video_packet_config(dsi, adjusted_mode); 913 dw_mipi_dsi_command_mode_config(dsi); 914 dw_mipi_dsi_line_timer_config(dsi, adjusted_mode); 915 dw_mipi_dsi_vertical_timing_config(dsi, adjusted_mode); 916 917 dw_mipi_dsi_dphy_init(dsi); 918 dw_mipi_dsi_dphy_timing_config(dsi); 919 dw_mipi_dsi_dphy_interface_config(dsi); 920 921 dw_mipi_dsi_clear_err(dsi); 922 923 ret = phy_ops->init(priv_data); 924 if (ret) 925 DRM_DEBUG_DRIVER("Phy init() failed\n"); 926 927 dw_mipi_dsi_dphy_enable(dsi); 928 929 dw_mipi_dsi_wait_for_two_frames(adjusted_mode); 930 931 /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */ 932 dw_mipi_dsi_set_mode(dsi, 0); 933 934 if (phy_ops->power_on) 935 phy_ops->power_on(dsi->plat_data->priv_data); 936 } 937 938 static void dw_mipi_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge, 939 struct drm_bridge_state *old_bridge_state) 940 { 941 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 942 943 /* Power up the dsi ctl into a command mode */ 944 dw_mipi_dsi_mode_set(dsi, &dsi->mode); 945 if (dsi->slave) 946 dw_mipi_dsi_mode_set(dsi->slave, &dsi->mode); 947 } 948 949 static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge, 950 const struct drm_display_mode *mode, 951 const struct drm_display_mode *adjusted_mode) 952 { 953 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 954 955 /* Store the display mode for later use in pre_enable callback */ 956 drm_mode_copy(&dsi->mode, adjusted_mode); 957 } 958 959 static void dw_mipi_dsi_bridge_atomic_enable(struct drm_bridge *bridge, 960 struct drm_bridge_state *old_bridge_state) 961 { 962 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 963 964 /* Switch to video mode for panel-bridge enable & panel enable */ 965 dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO); 966 if (dsi->slave) 967 dw_mipi_dsi_set_mode(dsi->slave, MIPI_DSI_MODE_VIDEO); 968 } 969 970 static enum drm_mode_status 971 dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge, 972 const struct drm_display_info *info, 973 const struct drm_display_mode *mode) 974 { 975 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 976 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 977 enum drm_mode_status mode_status = MODE_OK; 978 979 if (pdata->mode_valid) 980 mode_status = pdata->mode_valid(pdata->priv_data, mode, 981 dsi->mode_flags, 982 dw_mipi_dsi_get_lanes(dsi), 983 dsi->format); 984 985 return mode_status; 986 } 987 988 static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge, 989 enum drm_bridge_attach_flags flags) 990 { 991 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 992 993 if (!bridge->encoder) { 994 DRM_ERROR("Parent encoder object not found\n"); 995 return -ENODEV; 996 } 997 998 /* Set the encoder type as caller does not know it */ 999 bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI; 1000 1001 /* Attach the panel-bridge to the dsi bridge */ 1002 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge, 1003 flags); 1004 } 1005 1006 static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = { 1007 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1008 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1009 .atomic_reset = drm_atomic_helper_bridge_reset, 1010 .atomic_pre_enable = dw_mipi_dsi_bridge_atomic_pre_enable, 1011 .atomic_enable = dw_mipi_dsi_bridge_atomic_enable, 1012 .atomic_post_disable = dw_mipi_dsi_bridge_post_atomic_disable, 1013 .mode_set = dw_mipi_dsi_bridge_mode_set, 1014 .mode_valid = dw_mipi_dsi_bridge_mode_valid, 1015 .attach = dw_mipi_dsi_bridge_attach, 1016 }; 1017 1018 #ifdef CONFIG_DEBUG_FS 1019 1020 static int dw_mipi_dsi_debugfs_write(void *data, u64 val) 1021 { 1022 struct debugfs_entries *vpg = data; 1023 struct dw_mipi_dsi *dsi; 1024 u32 mode_cfg; 1025 1026 if (!vpg) 1027 return -ENODEV; 1028 1029 dsi = vpg->dsi; 1030 1031 *vpg->reg = (bool)val; 1032 1033 mode_cfg = dsi_read(dsi, DSI_VID_MODE_CFG); 1034 1035 if (*vpg->reg) 1036 mode_cfg |= vpg->mask; 1037 else 1038 mode_cfg &= ~vpg->mask; 1039 1040 dsi_write(dsi, DSI_VID_MODE_CFG, mode_cfg); 1041 1042 return 0; 1043 } 1044 1045 static int dw_mipi_dsi_debugfs_show(void *data, u64 *val) 1046 { 1047 struct debugfs_entries *vpg = data; 1048 1049 if (!vpg) 1050 return -ENODEV; 1051 1052 *val = *vpg->reg; 1053 1054 return 0; 1055 } 1056 1057 DEFINE_DEBUGFS_ATTRIBUTE(fops_x32, dw_mipi_dsi_debugfs_show, 1058 dw_mipi_dsi_debugfs_write, "%llu\n"); 1059 1060 static void debugfs_create_files(void *data) 1061 { 1062 struct dw_mipi_dsi *dsi = data; 1063 struct debugfs_entries debugfs[] = { 1064 REGISTER(vpg, VID_MODE_VPG_ENABLE, dsi), 1065 REGISTER(vpg_horizontal, VID_MODE_VPG_HORIZONTAL, dsi), 1066 REGISTER(vpg_ber_pattern, VID_MODE_VPG_MODE, dsi), 1067 }; 1068 int i; 1069 1070 dsi->debugfs_vpg = kmemdup(debugfs, sizeof(debugfs), GFP_KERNEL); 1071 if (!dsi->debugfs_vpg) 1072 return; 1073 1074 for (i = 0; i < ARRAY_SIZE(debugfs); i++) 1075 debugfs_create_file(dsi->debugfs_vpg[i].name, 0644, 1076 dsi->debugfs, &dsi->debugfs_vpg[i], 1077 &fops_x32); 1078 } 1079 1080 static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) 1081 { 1082 dsi->debugfs = debugfs_create_dir(dev_name(dsi->dev), NULL); 1083 if (IS_ERR(dsi->debugfs)) { 1084 dev_err(dsi->dev, "failed to create debugfs root\n"); 1085 return; 1086 } 1087 1088 debugfs_create_files(dsi); 1089 } 1090 1091 static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) 1092 { 1093 debugfs_remove_recursive(dsi->debugfs); 1094 kfree(dsi->debugfs_vpg); 1095 } 1096 1097 #else 1098 1099 static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) { } 1100 static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { } 1101 1102 #endif /* CONFIG_DEBUG_FS */ 1103 1104 static struct dw_mipi_dsi * 1105 __dw_mipi_dsi_probe(struct platform_device *pdev, 1106 const struct dw_mipi_dsi_plat_data *plat_data) 1107 { 1108 struct device *dev = &pdev->dev; 1109 struct reset_control *apb_rst; 1110 struct dw_mipi_dsi *dsi; 1111 int ret; 1112 1113 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1114 if (!dsi) 1115 return ERR_PTR(-ENOMEM); 1116 1117 dsi->dev = dev; 1118 dsi->plat_data = plat_data; 1119 1120 if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps || 1121 !plat_data->phy_ops->get_timing) { 1122 DRM_ERROR("Phy not properly configured\n"); 1123 return ERR_PTR(-ENODEV); 1124 } 1125 1126 if (!plat_data->base) { 1127 dsi->base = devm_platform_ioremap_resource(pdev, 0); 1128 if (IS_ERR(dsi->base)) 1129 return ERR_PTR(-ENODEV); 1130 1131 } else { 1132 dsi->base = plat_data->base; 1133 } 1134 1135 dsi->pclk = devm_clk_get(dev, "pclk"); 1136 if (IS_ERR(dsi->pclk)) { 1137 ret = PTR_ERR(dsi->pclk); 1138 dev_err(dev, "Unable to get pclk: %d\n", ret); 1139 return ERR_PTR(ret); 1140 } 1141 1142 /* 1143 * Note that the reset was not defined in the initial device tree, so 1144 * we have to be prepared for it not being found. 1145 */ 1146 apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb"); 1147 if (IS_ERR(apb_rst)) { 1148 ret = PTR_ERR(apb_rst); 1149 1150 if (ret != -EPROBE_DEFER) 1151 dev_err(dev, "Unable to get reset control: %d\n", ret); 1152 1153 return ERR_PTR(ret); 1154 } 1155 1156 if (apb_rst) { 1157 ret = clk_prepare_enable(dsi->pclk); 1158 if (ret) { 1159 dev_err(dev, "%s: Failed to enable pclk\n", __func__); 1160 return ERR_PTR(ret); 1161 } 1162 1163 reset_control_assert(apb_rst); 1164 usleep_range(10, 20); 1165 reset_control_deassert(apb_rst); 1166 1167 clk_disable_unprepare(dsi->pclk); 1168 } 1169 1170 dw_mipi_dsi_debugfs_init(dsi); 1171 pm_runtime_enable(dev); 1172 1173 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops; 1174 dsi->dsi_host.dev = dev; 1175 ret = mipi_dsi_host_register(&dsi->dsi_host); 1176 if (ret) { 1177 dev_err(dev, "Failed to register MIPI host: %d\n", ret); 1178 pm_runtime_disable(dev); 1179 dw_mipi_dsi_debugfs_remove(dsi); 1180 return ERR_PTR(ret); 1181 } 1182 1183 dsi->bridge.driver_private = dsi; 1184 dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs; 1185 #ifdef CONFIG_OF 1186 dsi->bridge.of_node = pdev->dev.of_node; 1187 #endif 1188 1189 return dsi; 1190 } 1191 1192 static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi) 1193 { 1194 mipi_dsi_host_unregister(&dsi->dsi_host); 1195 1196 pm_runtime_disable(dsi->dev); 1197 dw_mipi_dsi_debugfs_remove(dsi); 1198 } 1199 1200 void dw_mipi_dsi_set_slave(struct dw_mipi_dsi *dsi, struct dw_mipi_dsi *slave) 1201 { 1202 /* introduce controllers to each other */ 1203 dsi->slave = slave; 1204 dsi->slave->master = dsi; 1205 1206 /* migrate settings for already attached displays */ 1207 dsi->slave->lanes = dsi->lanes; 1208 dsi->slave->channel = dsi->channel; 1209 dsi->slave->format = dsi->format; 1210 dsi->slave->mode_flags = dsi->mode_flags; 1211 } 1212 EXPORT_SYMBOL_GPL(dw_mipi_dsi_set_slave); 1213 1214 /* 1215 * Probe/remove API, used from platforms based on the DRM bridge API. 1216 */ 1217 struct dw_mipi_dsi * 1218 dw_mipi_dsi_probe(struct platform_device *pdev, 1219 const struct dw_mipi_dsi_plat_data *plat_data) 1220 { 1221 return __dw_mipi_dsi_probe(pdev, plat_data); 1222 } 1223 EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe); 1224 1225 void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi) 1226 { 1227 __dw_mipi_dsi_remove(dsi); 1228 } 1229 EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove); 1230 1231 /* 1232 * Bind/unbind API, used from platforms based on the component framework. 1233 */ 1234 int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder) 1235 { 1236 return drm_bridge_attach(encoder, &dsi->bridge, NULL, 0); 1237 } 1238 EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind); 1239 1240 void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi) 1241 { 1242 } 1243 EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind); 1244 1245 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>"); 1246 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1247 MODULE_DESCRIPTION("DW MIPI DSI host controller driver"); 1248 MODULE_LICENSE("GPL"); 1249 MODULE_ALIAS("platform:dw-mipi-dsi"); 1250