1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DesignWare High-Definition Multimedia Interface (HDMI) driver 4 * 5 * Copyright (C) 2013-2015 Mentor Graphics Inc. 6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 8 */ 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/hdmi.h> 13 #include <linux/i2c.h> 14 #include <linux/irq.h> 15 #include <linux/module.h> 16 #include <linux/mutex.h> 17 #include <linux/of_device.h> 18 #include <linux/pinctrl/consumer.h> 19 #include <linux/regmap.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/spinlock.h> 22 23 #include <media/cec-notifier.h> 24 25 #include <uapi/linux/media-bus-format.h> 26 #include <uapi/linux/videodev2.h> 27 28 #include <drm/bridge/dw_hdmi.h> 29 #include <drm/display/drm_hdmi_helper.h> 30 #include <drm/display/drm_scdc_helper.h> 31 #include <drm/drm_atomic.h> 32 #include <drm/drm_atomic_helper.h> 33 #include <drm/drm_bridge.h> 34 #include <drm/drm_of.h> 35 #include <drm/drm_print.h> 36 #include <drm/drm_probe_helper.h> 37 38 #include "dw-hdmi-audio.h" 39 #include "dw-hdmi-cec.h" 40 #include "dw-hdmi.h" 41 42 #define DDC_CI_ADDR 0x37 43 #define DDC_SEGMENT_ADDR 0x30 44 45 #define HDMI_EDID_LEN 512 46 47 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ 48 #define SCDC_MIN_SOURCE_VERSION 0x1 49 50 #define HDMI14_MAX_TMDSCLK 340000000 51 52 enum hdmi_datamap { 53 RGB444_8B = 0x01, 54 RGB444_10B = 0x03, 55 RGB444_12B = 0x05, 56 RGB444_16B = 0x07, 57 YCbCr444_8B = 0x09, 58 YCbCr444_10B = 0x0B, 59 YCbCr444_12B = 0x0D, 60 YCbCr444_16B = 0x0F, 61 YCbCr422_8B = 0x16, 62 YCbCr422_10B = 0x14, 63 YCbCr422_12B = 0x12, 64 }; 65 66 static const u16 csc_coeff_default[3][4] = { 67 { 0x2000, 0x0000, 0x0000, 0x0000 }, 68 { 0x0000, 0x2000, 0x0000, 0x0000 }, 69 { 0x0000, 0x0000, 0x2000, 0x0000 } 70 }; 71 72 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 73 { 0x2000, 0x6926, 0x74fd, 0x010e }, 74 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 75 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 76 }; 77 78 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 79 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 80 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 81 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 82 }; 83 84 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 85 { 0x2591, 0x1322, 0x074b, 0x0000 }, 86 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 87 { 0x6acd, 0x7534, 0x2000, 0x0200 } 88 }; 89 90 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 91 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 92 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 93 { 0x6756, 0x78ab, 0x2000, 0x0200 } 94 }; 95 96 static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = { 97 { 0x1b7c, 0x0000, 0x0000, 0x0020 }, 98 { 0x0000, 0x1b7c, 0x0000, 0x0020 }, 99 { 0x0000, 0x0000, 0x1b7c, 0x0020 } 100 }; 101 102 struct hdmi_vmode { 103 bool mdataenablepolarity; 104 105 unsigned int mpixelclock; 106 unsigned int mpixelrepetitioninput; 107 unsigned int mpixelrepetitionoutput; 108 unsigned int mtmdsclock; 109 }; 110 111 struct hdmi_data_info { 112 unsigned int enc_in_bus_format; 113 unsigned int enc_out_bus_format; 114 unsigned int enc_in_encoding; 115 unsigned int enc_out_encoding; 116 unsigned int pix_repet_factor; 117 unsigned int hdcp_enable; 118 struct hdmi_vmode video_mode; 119 bool rgb_limited_range; 120 }; 121 122 struct dw_hdmi_i2c { 123 struct i2c_adapter adap; 124 125 struct mutex lock; /* used to serialize data transfers */ 126 struct completion cmp; 127 u8 stat; 128 129 u8 slave_reg; 130 bool is_regaddr; 131 bool is_segment; 132 }; 133 134 struct dw_hdmi_phy_data { 135 enum dw_hdmi_phy_type type; 136 const char *name; 137 unsigned int gen; 138 bool has_svsret; 139 int (*configure)(struct dw_hdmi *hdmi, 140 const struct dw_hdmi_plat_data *pdata, 141 unsigned long mpixelclock); 142 }; 143 144 struct dw_hdmi { 145 struct drm_connector connector; 146 struct drm_bridge bridge; 147 struct drm_bridge *next_bridge; 148 149 unsigned int version; 150 151 struct platform_device *audio; 152 struct platform_device *cec; 153 struct device *dev; 154 struct clk *isfr_clk; 155 struct clk *iahb_clk; 156 struct clk *cec_clk; 157 struct dw_hdmi_i2c *i2c; 158 159 struct hdmi_data_info hdmi_data; 160 const struct dw_hdmi_plat_data *plat_data; 161 162 int vic; 163 164 u8 edid[HDMI_EDID_LEN]; 165 166 struct { 167 const struct dw_hdmi_phy_ops *ops; 168 const char *name; 169 void *data; 170 bool enabled; 171 } phy; 172 173 struct drm_display_mode previous_mode; 174 175 struct i2c_adapter *ddc; 176 void __iomem *regs; 177 bool sink_is_hdmi; 178 bool sink_has_audio; 179 180 struct pinctrl *pinctrl; 181 struct pinctrl_state *default_state; 182 struct pinctrl_state *unwedge_state; 183 184 struct mutex mutex; /* for state below and previous_mode */ 185 enum drm_connector_force force; /* mutex-protected force state */ 186 struct drm_connector *curr_conn;/* current connector (only valid when !disabled) */ 187 bool disabled; /* DRM has disabled our bridge */ 188 bool bridge_is_on; /* indicates the bridge is on */ 189 bool rxsense; /* rxsense state */ 190 u8 phy_mask; /* desired phy int mask settings */ 191 u8 mc_clkdis; /* clock disable register */ 192 193 spinlock_t audio_lock; 194 struct mutex audio_mutex; 195 unsigned int sample_non_pcm; 196 unsigned int sample_width; 197 unsigned int sample_rate; 198 unsigned int channels; 199 unsigned int audio_cts; 200 unsigned int audio_n; 201 bool audio_enable; 202 203 unsigned int reg_shift; 204 struct regmap *regm; 205 void (*enable_audio)(struct dw_hdmi *hdmi); 206 void (*disable_audio)(struct dw_hdmi *hdmi); 207 208 struct mutex cec_notifier_mutex; 209 struct cec_notifier *cec_notifier; 210 211 hdmi_codec_plugged_cb plugged_cb; 212 struct device *codec_dev; 213 enum drm_connector_status last_connector_result; 214 }; 215 216 #define HDMI_IH_PHY_STAT0_RX_SENSE \ 217 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ 218 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) 219 220 #define HDMI_PHY_RX_SENSE \ 221 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ 222 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) 223 224 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 225 { 226 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); 227 } 228 229 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 230 { 231 unsigned int val = 0; 232 233 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); 234 235 return val; 236 } 237 238 static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged) 239 { 240 if (hdmi->plugged_cb && hdmi->codec_dev) 241 hdmi->plugged_cb(hdmi->codec_dev, plugged); 242 } 243 244 int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn, 245 struct device *codec_dev) 246 { 247 bool plugged; 248 249 mutex_lock(&hdmi->mutex); 250 hdmi->plugged_cb = fn; 251 hdmi->codec_dev = codec_dev; 252 plugged = hdmi->last_connector_result == connector_status_connected; 253 handle_plugged_change(hdmi, plugged); 254 mutex_unlock(&hdmi->mutex); 255 256 return 0; 257 } 258 EXPORT_SYMBOL_GPL(dw_hdmi_set_plugged_cb); 259 260 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 261 { 262 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); 263 } 264 265 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 266 u8 shift, u8 mask) 267 { 268 hdmi_modb(hdmi, data << shift, mask, reg); 269 } 270 271 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 272 { 273 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, 274 HDMI_PHY_I2CM_INT_ADDR); 275 276 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | 277 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, 278 HDMI_PHY_I2CM_CTLINT_ADDR); 279 280 /* Software reset */ 281 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 282 283 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ 284 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); 285 286 /* Set done, not acknowledged and arbitration interrupt polarities */ 287 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 288 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 289 HDMI_I2CM_CTLINT); 290 291 /* Clear DONE and ERROR interrupts */ 292 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 293 HDMI_IH_I2CM_STAT0); 294 295 /* Mute DONE and ERROR interrupts */ 296 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 297 HDMI_IH_MUTE_I2CM_STAT0); 298 } 299 300 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi) 301 { 302 /* If no unwedge state then give up */ 303 if (!hdmi->unwedge_state) 304 return false; 305 306 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n"); 307 308 /* 309 * This is a huge hack to workaround a problem where the dw_hdmi i2c 310 * bus could sometimes get wedged. Once wedged there doesn't appear 311 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ) 312 * other than pulsing the SDA line. 313 * 314 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi) 315 * by: 316 * 1. Remux the pin as a GPIO output, driven low. 317 * 2. Wait a little while. 1 ms seems to work, but we'll do 10. 318 * 3. Immediately jump to remux the pin as dw_hdmi i2c again. 319 * 320 * At the moment of remuxing, the line will still be low due to its 321 * recent stint as an output, but then it will be pulled high by the 322 * (presumed) external pullup. dw_hdmi seems to see this as a rising 323 * edge and that seems to get it out of its jam. 324 * 325 * This wedging was only ever seen on one TV, and only on one of 326 * its HDMI ports. It happened when the TV was powered on while the 327 * device was plugged in. A scope trace shows the TV bringing both SDA 328 * and SCL low, then bringing them both back up at roughly the same 329 * time. Presumably this confuses dw_hdmi because it saw activity but 330 * no real STOP (maybe it thinks there's another master on the bus?). 331 * Giving it a clean rising edge of SDA while SCL is already high 332 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out 333 * of its stupor. 334 * 335 * Note that after coming back alive, transfers seem to immediately 336 * resume, so if we unwedge due to a timeout we should wait a little 337 * longer for our transfer to finish, since it might have just started 338 * now. 339 */ 340 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state); 341 msleep(10); 342 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state); 343 344 return true; 345 } 346 347 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi) 348 { 349 struct dw_hdmi_i2c *i2c = hdmi->i2c; 350 int stat; 351 352 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 353 if (!stat) { 354 /* If we can't unwedge, return timeout */ 355 if (!dw_hdmi_i2c_unwedge(hdmi)) 356 return -EAGAIN; 357 358 /* We tried to unwedge; give it another chance */ 359 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 360 if (!stat) 361 return -EAGAIN; 362 } 363 364 /* Check for error condition on the bus */ 365 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 366 return -EIO; 367 368 return 0; 369 } 370 371 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 372 unsigned char *buf, unsigned int length) 373 { 374 struct dw_hdmi_i2c *i2c = hdmi->i2c; 375 int ret; 376 377 if (!i2c->is_regaddr) { 378 dev_dbg(hdmi->dev, "set read register address to 0\n"); 379 i2c->slave_reg = 0x00; 380 i2c->is_regaddr = true; 381 } 382 383 while (length--) { 384 reinit_completion(&i2c->cmp); 385 386 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 387 if (i2c->is_segment) 388 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 389 HDMI_I2CM_OPERATION); 390 else 391 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 392 HDMI_I2CM_OPERATION); 393 394 ret = dw_hdmi_i2c_wait(hdmi); 395 if (ret) 396 return ret; 397 398 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 399 } 400 i2c->is_segment = false; 401 402 return 0; 403 } 404 405 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 406 unsigned char *buf, unsigned int length) 407 { 408 struct dw_hdmi_i2c *i2c = hdmi->i2c; 409 int ret; 410 411 if (!i2c->is_regaddr) { 412 /* Use the first write byte as register address */ 413 i2c->slave_reg = buf[0]; 414 length--; 415 buf++; 416 i2c->is_regaddr = true; 417 } 418 419 while (length--) { 420 reinit_completion(&i2c->cmp); 421 422 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 423 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 424 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 425 HDMI_I2CM_OPERATION); 426 427 ret = dw_hdmi_i2c_wait(hdmi); 428 if (ret) 429 return ret; 430 } 431 432 return 0; 433 } 434 435 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, 436 struct i2c_msg *msgs, int num) 437 { 438 struct dw_hdmi *hdmi = i2c_get_adapdata(adap); 439 struct dw_hdmi_i2c *i2c = hdmi->i2c; 440 u8 addr = msgs[0].addr; 441 int i, ret = 0; 442 443 if (addr == DDC_CI_ADDR) 444 /* 445 * The internal I2C controller does not support the multi-byte 446 * read and write operations needed for DDC/CI. 447 * TOFIX: Blacklist the DDC/CI address until we filter out 448 * unsupported I2C operations. 449 */ 450 return -EOPNOTSUPP; 451 452 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); 453 454 for (i = 0; i < num; i++) { 455 if (msgs[i].len == 0) { 456 dev_dbg(hdmi->dev, 457 "unsupported transfer %d/%d, no data\n", 458 i + 1, num); 459 return -EOPNOTSUPP; 460 } 461 } 462 463 mutex_lock(&i2c->lock); 464 465 /* Unmute DONE and ERROR interrupts */ 466 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 467 468 /* Set slave device address taken from the first I2C message */ 469 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 470 471 /* Set slave device register address on transfer */ 472 i2c->is_regaddr = false; 473 474 /* Set segment pointer for I2C extended read mode operation */ 475 i2c->is_segment = false; 476 477 for (i = 0; i < num; i++) { 478 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", 479 i + 1, num, msgs[i].len, msgs[i].flags); 480 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 481 i2c->is_segment = true; 482 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 483 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 484 } else { 485 if (msgs[i].flags & I2C_M_RD) 486 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 487 msgs[i].len); 488 else 489 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 490 msgs[i].len); 491 } 492 if (ret < 0) 493 break; 494 } 495 496 if (!ret) 497 ret = num; 498 499 /* Mute DONE and ERROR interrupts */ 500 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 501 HDMI_IH_MUTE_I2CM_STAT0); 502 503 mutex_unlock(&i2c->lock); 504 505 return ret; 506 } 507 508 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) 509 { 510 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 511 } 512 513 static const struct i2c_algorithm dw_hdmi_algorithm = { 514 .master_xfer = dw_hdmi_i2c_xfer, 515 .functionality = dw_hdmi_i2c_func, 516 }; 517 518 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) 519 { 520 struct i2c_adapter *adap; 521 struct dw_hdmi_i2c *i2c; 522 int ret; 523 524 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 525 if (!i2c) 526 return ERR_PTR(-ENOMEM); 527 528 mutex_init(&i2c->lock); 529 init_completion(&i2c->cmp); 530 531 adap = &i2c->adap; 532 adap->class = I2C_CLASS_DDC; 533 adap->owner = THIS_MODULE; 534 adap->dev.parent = hdmi->dev; 535 adap->algo = &dw_hdmi_algorithm; 536 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name)); 537 i2c_set_adapdata(adap, hdmi); 538 539 ret = i2c_add_adapter(adap); 540 if (ret) { 541 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 542 devm_kfree(hdmi->dev, i2c); 543 return ERR_PTR(ret); 544 } 545 546 hdmi->i2c = i2c; 547 548 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 549 550 return adap; 551 } 552 553 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 554 unsigned int n) 555 { 556 /* Must be set/cleared first */ 557 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 558 559 /* nshift factor = 0 */ 560 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 561 562 /* Use automatic CTS generation mode when CTS is not set */ 563 if (cts) 564 hdmi_writeb(hdmi, ((cts >> 16) & 565 HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 566 HDMI_AUD_CTS3_CTS_MANUAL, 567 HDMI_AUD_CTS3); 568 else 569 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3); 570 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 571 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 572 573 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 574 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 575 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 576 } 577 578 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) 579 { 580 unsigned int n = (128 * freq) / 1000; 581 unsigned int mult = 1; 582 583 while (freq > 48000) { 584 mult *= 2; 585 freq /= 2; 586 } 587 588 switch (freq) { 589 case 32000: 590 if (pixel_clk == 25175000) 591 n = 4576; 592 else if (pixel_clk == 27027000) 593 n = 4096; 594 else if (pixel_clk == 74176000 || pixel_clk == 148352000) 595 n = 11648; 596 else if (pixel_clk == 297000000) 597 n = 3072; 598 else 599 n = 4096; 600 n *= mult; 601 break; 602 603 case 44100: 604 if (pixel_clk == 25175000) 605 n = 7007; 606 else if (pixel_clk == 74176000) 607 n = 17836; 608 else if (pixel_clk == 148352000) 609 n = 8918; 610 else if (pixel_clk == 297000000) 611 n = 4704; 612 else 613 n = 6272; 614 n *= mult; 615 break; 616 617 case 48000: 618 if (pixel_clk == 25175000) 619 n = 6864; 620 else if (pixel_clk == 27027000) 621 n = 6144; 622 else if (pixel_clk == 74176000) 623 n = 11648; 624 else if (pixel_clk == 148352000) 625 n = 5824; 626 else if (pixel_clk == 297000000) 627 n = 5120; 628 else 629 n = 6144; 630 n *= mult; 631 break; 632 633 default: 634 break; 635 } 636 637 return n; 638 } 639 640 /* 641 * When transmitting IEC60958 linear PCM audio, these registers allow to 642 * configure the channel status information of all the channel status 643 * bits in the IEC60958 frame. For the moment this configuration is only 644 * used when the I2S audio interface, General Purpose Audio (GPA), 645 * or AHB audio DMA (AHBAUDDMA) interface is active 646 * (for S/PDIF interface this information comes from the stream). 647 */ 648 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, 649 u8 *channel_status) 650 { 651 /* 652 * Set channel status register for frequency and word length. 653 * Use default values for other registers. 654 */ 655 hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7); 656 hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8); 657 } 658 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status); 659 660 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, 661 unsigned long pixel_clk, unsigned int sample_rate) 662 { 663 unsigned long ftdms = pixel_clk; 664 unsigned int n, cts; 665 u8 config3; 666 u64 tmp; 667 668 n = hdmi_compute_n(sample_rate, pixel_clk); 669 670 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 671 672 /* Compute CTS when using internal AHB audio or General Parallel audio*/ 673 if ((config3 & HDMI_CONFIG3_AHBAUDDMA) || (config3 & HDMI_CONFIG3_GPAUD)) { 674 /* 675 * Compute the CTS value from the N value. Note that CTS and N 676 * can be up to 20 bits in total, so we need 64-bit math. Also 677 * note that our TDMS clock is not fully accurate; it is 678 * accurate to kHz. This can introduce an unnecessary remainder 679 * in the calculation below, so we don't try to warn about that. 680 */ 681 tmp = (u64)ftdms * n; 682 do_div(tmp, 128 * sample_rate); 683 cts = tmp; 684 685 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", 686 __func__, sample_rate, 687 ftdms / 1000000, (ftdms / 1000) % 1000, 688 n, cts); 689 } else { 690 cts = 0; 691 } 692 693 spin_lock_irq(&hdmi->audio_lock); 694 hdmi->audio_n = n; 695 hdmi->audio_cts = cts; 696 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 697 spin_unlock_irq(&hdmi->audio_lock); 698 } 699 700 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) 701 { 702 mutex_lock(&hdmi->audio_mutex); 703 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); 704 mutex_unlock(&hdmi->audio_mutex); 705 } 706 707 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 708 { 709 mutex_lock(&hdmi->audio_mutex); 710 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 711 hdmi->sample_rate); 712 mutex_unlock(&hdmi->audio_mutex); 713 } 714 715 void dw_hdmi_set_sample_width(struct dw_hdmi *hdmi, unsigned int width) 716 { 717 mutex_lock(&hdmi->audio_mutex); 718 hdmi->sample_width = width; 719 mutex_unlock(&hdmi->audio_mutex); 720 } 721 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_width); 722 723 void dw_hdmi_set_sample_non_pcm(struct dw_hdmi *hdmi, unsigned int non_pcm) 724 { 725 mutex_lock(&hdmi->audio_mutex); 726 hdmi->sample_non_pcm = non_pcm; 727 mutex_unlock(&hdmi->audio_mutex); 728 } 729 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_non_pcm); 730 731 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 732 { 733 mutex_lock(&hdmi->audio_mutex); 734 hdmi->sample_rate = rate; 735 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 736 hdmi->sample_rate); 737 mutex_unlock(&hdmi->audio_mutex); 738 } 739 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); 740 741 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt) 742 { 743 u8 layout; 744 745 mutex_lock(&hdmi->audio_mutex); 746 hdmi->channels = cnt; 747 748 /* 749 * For >2 channel PCM audio, we need to select layout 1 750 * and set an appropriate channel map. 751 */ 752 if (cnt > 2) 753 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1; 754 else 755 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0; 756 757 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK, 758 HDMI_FC_AUDSCONF); 759 760 /* Set the audio infoframes channel count */ 761 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET, 762 HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0); 763 764 mutex_unlock(&hdmi->audio_mutex); 765 } 766 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count); 767 768 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca) 769 { 770 mutex_lock(&hdmi->audio_mutex); 771 772 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2); 773 774 mutex_unlock(&hdmi->audio_mutex); 775 } 776 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation); 777 778 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) 779 { 780 if (enable) 781 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; 782 else 783 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; 784 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 785 } 786 787 static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi) 788 { 789 if (!hdmi->curr_conn) 790 return NULL; 791 792 return hdmi->curr_conn->eld; 793 } 794 795 static void dw_hdmi_gp_audio_enable(struct dw_hdmi *hdmi) 796 { 797 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 798 int sample_freq = 0x2, org_sample_freq = 0xD; 799 int ch_mask = BIT(hdmi->channels) - 1; 800 801 switch (hdmi->sample_rate) { 802 case 32000: 803 sample_freq = 0x03; 804 org_sample_freq = 0x0C; 805 break; 806 case 44100: 807 sample_freq = 0x00; 808 org_sample_freq = 0x0F; 809 break; 810 case 48000: 811 sample_freq = 0x02; 812 org_sample_freq = 0x0D; 813 break; 814 case 88200: 815 sample_freq = 0x08; 816 org_sample_freq = 0x07; 817 break; 818 case 96000: 819 sample_freq = 0x0A; 820 org_sample_freq = 0x05; 821 break; 822 case 176400: 823 sample_freq = 0x0C; 824 org_sample_freq = 0x03; 825 break; 826 case 192000: 827 sample_freq = 0x0E; 828 org_sample_freq = 0x01; 829 break; 830 default: 831 break; 832 } 833 834 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 835 hdmi_enable_audio_clk(hdmi, true); 836 837 hdmi_writeb(hdmi, 0x1, HDMI_FC_AUDSCHNLS0); 838 hdmi_writeb(hdmi, hdmi->channels, HDMI_FC_AUDSCHNLS2); 839 hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS3); 840 hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS4); 841 hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS5); 842 hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS6); 843 hdmi_writeb(hdmi, (0x3 << 4) | sample_freq, HDMI_FC_AUDSCHNLS7); 844 hdmi_writeb(hdmi, (org_sample_freq << 4) | 0xb, HDMI_FC_AUDSCHNLS8); 845 846 hdmi_writeb(hdmi, ch_mask, HDMI_GP_CONF1); 847 hdmi_writeb(hdmi, 0x02, HDMI_GP_CONF2); 848 hdmi_writeb(hdmi, 0x01, HDMI_GP_CONF0); 849 850 hdmi_modb(hdmi, 0x3, 0x3, HDMI_FC_DATAUTO3); 851 852 /* hbr */ 853 if (hdmi->sample_rate == 192000 && hdmi->channels == 8 && 854 hdmi->sample_width == 32 && hdmi->sample_non_pcm) 855 hdmi_modb(hdmi, 0x01, 0x01, HDMI_GP_CONF2); 856 857 if (pdata->enable_audio) 858 pdata->enable_audio(hdmi, 859 hdmi->channels, 860 hdmi->sample_width, 861 hdmi->sample_rate, 862 hdmi->sample_non_pcm); 863 } 864 865 static void dw_hdmi_gp_audio_disable(struct dw_hdmi *hdmi) 866 { 867 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 868 869 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 870 871 hdmi_modb(hdmi, 0, 0x3, HDMI_FC_DATAUTO3); 872 if (pdata->disable_audio) 873 pdata->disable_audio(hdmi); 874 875 hdmi_enable_audio_clk(hdmi, false); 876 } 877 878 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi) 879 { 880 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 881 } 882 883 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi) 884 { 885 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 886 } 887 888 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi) 889 { 890 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 891 hdmi_enable_audio_clk(hdmi, true); 892 } 893 894 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi) 895 { 896 hdmi_enable_audio_clk(hdmi, false); 897 } 898 899 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 900 { 901 unsigned long flags; 902 903 spin_lock_irqsave(&hdmi->audio_lock, flags); 904 hdmi->audio_enable = true; 905 if (hdmi->enable_audio) 906 hdmi->enable_audio(hdmi); 907 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 908 } 909 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); 910 911 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 912 { 913 unsigned long flags; 914 915 spin_lock_irqsave(&hdmi->audio_lock, flags); 916 hdmi->audio_enable = false; 917 if (hdmi->disable_audio) 918 hdmi->disable_audio(hdmi); 919 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 920 } 921 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); 922 923 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 924 { 925 switch (bus_format) { 926 case MEDIA_BUS_FMT_RGB888_1X24: 927 case MEDIA_BUS_FMT_RGB101010_1X30: 928 case MEDIA_BUS_FMT_RGB121212_1X36: 929 case MEDIA_BUS_FMT_RGB161616_1X48: 930 return true; 931 932 default: 933 return false; 934 } 935 } 936 937 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 938 { 939 switch (bus_format) { 940 case MEDIA_BUS_FMT_YUV8_1X24: 941 case MEDIA_BUS_FMT_YUV10_1X30: 942 case MEDIA_BUS_FMT_YUV12_1X36: 943 case MEDIA_BUS_FMT_YUV16_1X48: 944 return true; 945 946 default: 947 return false; 948 } 949 } 950 951 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 952 { 953 switch (bus_format) { 954 case MEDIA_BUS_FMT_UYVY8_1X16: 955 case MEDIA_BUS_FMT_UYVY10_1X20: 956 case MEDIA_BUS_FMT_UYVY12_1X24: 957 return true; 958 959 default: 960 return false; 961 } 962 } 963 964 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 965 { 966 switch (bus_format) { 967 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 968 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 969 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 970 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 971 return true; 972 973 default: 974 return false; 975 } 976 } 977 978 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 979 { 980 switch (bus_format) { 981 case MEDIA_BUS_FMT_RGB888_1X24: 982 case MEDIA_BUS_FMT_YUV8_1X24: 983 case MEDIA_BUS_FMT_UYVY8_1X16: 984 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 985 return 8; 986 987 case MEDIA_BUS_FMT_RGB101010_1X30: 988 case MEDIA_BUS_FMT_YUV10_1X30: 989 case MEDIA_BUS_FMT_UYVY10_1X20: 990 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 991 return 10; 992 993 case MEDIA_BUS_FMT_RGB121212_1X36: 994 case MEDIA_BUS_FMT_YUV12_1X36: 995 case MEDIA_BUS_FMT_UYVY12_1X24: 996 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 997 return 12; 998 999 case MEDIA_BUS_FMT_RGB161616_1X48: 1000 case MEDIA_BUS_FMT_YUV16_1X48: 1001 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 1002 return 16; 1003 1004 default: 1005 return 0; 1006 } 1007 } 1008 1009 /* 1010 * this submodule is responsible for the video data synchronization. 1011 * for example, for RGB 4:4:4 input, the data map is defined as 1012 * pin{47~40} <==> R[7:0] 1013 * pin{31~24} <==> G[7:0] 1014 * pin{15~8} <==> B[7:0] 1015 */ 1016 static void hdmi_video_sample(struct dw_hdmi *hdmi) 1017 { 1018 int color_format = 0; 1019 u8 val; 1020 1021 switch (hdmi->hdmi_data.enc_in_bus_format) { 1022 case MEDIA_BUS_FMT_RGB888_1X24: 1023 color_format = 0x01; 1024 break; 1025 case MEDIA_BUS_FMT_RGB101010_1X30: 1026 color_format = 0x03; 1027 break; 1028 case MEDIA_BUS_FMT_RGB121212_1X36: 1029 color_format = 0x05; 1030 break; 1031 case MEDIA_BUS_FMT_RGB161616_1X48: 1032 color_format = 0x07; 1033 break; 1034 1035 case MEDIA_BUS_FMT_YUV8_1X24: 1036 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1037 color_format = 0x09; 1038 break; 1039 case MEDIA_BUS_FMT_YUV10_1X30: 1040 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1041 color_format = 0x0B; 1042 break; 1043 case MEDIA_BUS_FMT_YUV12_1X36: 1044 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 1045 color_format = 0x0D; 1046 break; 1047 case MEDIA_BUS_FMT_YUV16_1X48: 1048 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 1049 color_format = 0x0F; 1050 break; 1051 1052 case MEDIA_BUS_FMT_UYVY8_1X16: 1053 color_format = 0x16; 1054 break; 1055 case MEDIA_BUS_FMT_UYVY10_1X20: 1056 color_format = 0x14; 1057 break; 1058 case MEDIA_BUS_FMT_UYVY12_1X24: 1059 color_format = 0x12; 1060 break; 1061 1062 default: 1063 return; 1064 } 1065 1066 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 1067 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 1068 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 1069 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 1070 1071 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 1072 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 1073 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 1074 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 1075 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 1076 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 1077 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 1078 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 1079 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 1080 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 1081 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 1082 } 1083 1084 static int is_color_space_conversion(struct dw_hdmi *hdmi) 1085 { 1086 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1087 bool is_input_rgb, is_output_rgb; 1088 1089 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format); 1090 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format); 1091 1092 return (is_input_rgb != is_output_rgb) || 1093 (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range); 1094 } 1095 1096 static int is_color_space_decimation(struct dw_hdmi *hdmi) 1097 { 1098 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1099 return 0; 1100 1101 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 1102 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 1103 return 1; 1104 1105 return 0; 1106 } 1107 1108 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 1109 { 1110 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 1111 return 0; 1112 1113 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1114 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1115 return 1; 1116 1117 return 0; 1118 } 1119 1120 static bool is_csc_needed(struct dw_hdmi *hdmi) 1121 { 1122 return is_color_space_conversion(hdmi) || 1123 is_color_space_decimation(hdmi) || 1124 is_color_space_interpolation(hdmi); 1125 } 1126 1127 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 1128 { 1129 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 1130 bool is_input_rgb, is_output_rgb; 1131 unsigned i; 1132 u32 csc_scale = 1; 1133 1134 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format); 1135 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format); 1136 1137 if (!is_input_rgb && is_output_rgb) { 1138 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) 1139 csc_coeff = &csc_coeff_rgb_out_eitu601; 1140 else 1141 csc_coeff = &csc_coeff_rgb_out_eitu709; 1142 } else if (is_input_rgb && !is_output_rgb) { 1143 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) 1144 csc_coeff = &csc_coeff_rgb_in_eitu601; 1145 else 1146 csc_coeff = &csc_coeff_rgb_in_eitu709; 1147 csc_scale = 0; 1148 } else if (is_input_rgb && is_output_rgb && 1149 hdmi->hdmi_data.rgb_limited_range) { 1150 csc_coeff = &csc_coeff_rgb_full_to_rgb_limited; 1151 } 1152 1153 /* The CSC registers are sequential, alternating MSB then LSB */ 1154 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 1155 u16 coeff_a = (*csc_coeff)[0][i]; 1156 u16 coeff_b = (*csc_coeff)[1][i]; 1157 u16 coeff_c = (*csc_coeff)[2][i]; 1158 1159 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 1160 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 1161 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 1162 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 1163 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 1164 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 1165 } 1166 1167 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 1168 HDMI_CSC_SCALE); 1169 } 1170 1171 static void hdmi_video_csc(struct dw_hdmi *hdmi) 1172 { 1173 int color_depth = 0; 1174 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 1175 int decimation = 0; 1176 1177 /* YCC422 interpolation to 444 mode */ 1178 if (is_color_space_interpolation(hdmi)) 1179 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 1180 else if (is_color_space_decimation(hdmi)) 1181 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 1182 1183 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 1184 case 8: 1185 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 1186 break; 1187 case 10: 1188 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 1189 break; 1190 case 12: 1191 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 1192 break; 1193 case 16: 1194 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 1195 break; 1196 1197 default: 1198 return; 1199 } 1200 1201 /* Configure the CSC registers */ 1202 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 1203 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 1204 HDMI_CSC_SCALE); 1205 1206 dw_hdmi_update_csc_coeffs(hdmi); 1207 } 1208 1209 /* 1210 * HDMI video packetizer is used to packetize the data. 1211 * for example, if input is YCC422 mode or repeater is used, 1212 * data should be repacked this module can be bypassed. 1213 */ 1214 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 1215 { 1216 unsigned int color_depth = 0; 1217 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 1218 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 1219 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1220 u8 val, vp_conf; 1221 u8 clear_gcp_auto = 0; 1222 1223 1224 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1225 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 1226 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1227 switch (hdmi_bus_fmt_color_depth( 1228 hdmi->hdmi_data.enc_out_bus_format)) { 1229 case 8: 1230 color_depth = 4; 1231 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1232 clear_gcp_auto = 1; 1233 break; 1234 case 10: 1235 color_depth = 5; 1236 break; 1237 case 12: 1238 color_depth = 6; 1239 break; 1240 case 16: 1241 color_depth = 7; 1242 break; 1243 default: 1244 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1245 } 1246 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1247 switch (hdmi_bus_fmt_color_depth( 1248 hdmi->hdmi_data.enc_out_bus_format)) { 1249 case 0: 1250 case 8: 1251 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1252 clear_gcp_auto = 1; 1253 break; 1254 case 10: 1255 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1256 break; 1257 case 12: 1258 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1259 break; 1260 1261 default: 1262 return; 1263 } 1264 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1265 } else { 1266 return; 1267 } 1268 1269 /* set the packetizer registers */ 1270 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1271 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | 1272 ((hdmi_data->pix_repet_factor << 1273 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & 1274 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); 1275 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1276 1277 /* HDMI1.4b specification section 6.5.3: 1278 * Source shall only send GCPs with non-zero CD to sinks 1279 * that indicate support for Deep Color. 1280 * GCP only transmit CD and do not handle AVMUTE, PP norDefault_Phase (yet). 1281 * Disable Auto GCP when 24-bit color for sinks that not support Deep Color. 1282 */ 1283 val = hdmi_readb(hdmi, HDMI_FC_DATAUTO3); 1284 if (clear_gcp_auto == 1) 1285 val &= ~HDMI_FC_DATAUTO3_GCP_AUTO; 1286 else 1287 val |= HDMI_FC_DATAUTO3_GCP_AUTO; 1288 hdmi_writeb(hdmi, val, HDMI_FC_DATAUTO3); 1289 1290 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1291 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1292 1293 /* Data from pixel repeater block */ 1294 if (hdmi_data->pix_repet_factor > 1) { 1295 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1296 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1297 } else { /* data from packetizer block */ 1298 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1299 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1300 } 1301 1302 hdmi_modb(hdmi, vp_conf, 1303 HDMI_VP_CONF_PR_EN_MASK | 1304 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1305 1306 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 1307 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 1308 1309 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1310 1311 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1312 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1313 HDMI_VP_CONF_PP_EN_ENABLE | 1314 HDMI_VP_CONF_YCC422_EN_DISABLE; 1315 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1316 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1317 HDMI_VP_CONF_PP_EN_DISABLE | 1318 HDMI_VP_CONF_YCC422_EN_ENABLE; 1319 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1320 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1321 HDMI_VP_CONF_PP_EN_DISABLE | 1322 HDMI_VP_CONF_YCC422_EN_DISABLE; 1323 } else { 1324 return; 1325 } 1326 1327 hdmi_modb(hdmi, vp_conf, 1328 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1329 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1330 1331 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1332 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1333 HDMI_VP_STUFF_PP_STUFFING_MASK | 1334 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1335 1336 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1337 HDMI_VP_CONF); 1338 } 1339 1340 /* ----------------------------------------------------------------------------- 1341 * Synopsys PHY Handling 1342 */ 1343 1344 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 1345 unsigned char bit) 1346 { 1347 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 1348 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 1349 } 1350 1351 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 1352 { 1353 u32 val; 1354 1355 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 1356 if (msec-- == 0) 1357 return false; 1358 udelay(1000); 1359 } 1360 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 1361 1362 return true; 1363 } 1364 1365 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 1366 unsigned char addr) 1367 { 1368 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 1369 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 1370 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 1371 HDMI_PHY_I2CM_DATAO_1_ADDR); 1372 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 1373 HDMI_PHY_I2CM_DATAO_0_ADDR); 1374 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 1375 HDMI_PHY_I2CM_OPERATION_ADDR); 1376 hdmi_phy_wait_i2c_done(hdmi, 1000); 1377 } 1378 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); 1379 1380 /* Filter out invalid setups to avoid configuring SCDC and scrambling */ 1381 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi, 1382 const struct drm_display_info *display) 1383 { 1384 /* Completely disable SCDC support for older controllers */ 1385 if (hdmi->version < 0x200a) 1386 return false; 1387 1388 /* Disable if no DDC bus */ 1389 if (!hdmi->ddc) 1390 return false; 1391 1392 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */ 1393 if (!display->hdmi.scdc.supported || 1394 !display->hdmi.scdc.scrambling.supported) 1395 return false; 1396 1397 /* 1398 * Disable if display only support low TMDS rates and scrambling 1399 * for low rates is not supported either 1400 */ 1401 if (!display->hdmi.scdc.scrambling.low_rates && 1402 display->max_tmds_clock <= 340000) 1403 return false; 1404 1405 return true; 1406 } 1407 1408 /* 1409 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates: 1410 * - The Source shall suspend transmission of the TMDS clock and data 1411 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it 1412 * from a 0 to a 1 or from a 1 to a 0 1413 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from 1414 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming 1415 * transmission of TMDS clock and data 1416 * 1417 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio() 1418 * helper should called right before enabling the TMDS Clock and Data in 1419 * the PHY configuration callback. 1420 */ 1421 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi, 1422 const struct drm_display_info *display) 1423 { 1424 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1425 1426 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 1427 if (dw_hdmi_support_scdc(hdmi, display)) { 1428 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1429 drm_scdc_set_high_tmds_clock_ratio(&hdmi->connector, 1); 1430 else 1431 drm_scdc_set_high_tmds_clock_ratio(&hdmi->connector, 0); 1432 } 1433 } 1434 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio); 1435 1436 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 1437 { 1438 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 1439 HDMI_PHY_CONF0_PDZ_OFFSET, 1440 HDMI_PHY_CONF0_PDZ_MASK); 1441 } 1442 1443 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 1444 { 1445 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1446 HDMI_PHY_CONF0_ENTMDS_OFFSET, 1447 HDMI_PHY_CONF0_ENTMDS_MASK); 1448 } 1449 1450 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 1451 { 1452 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1453 HDMI_PHY_CONF0_SVSRET_OFFSET, 1454 HDMI_PHY_CONF0_SVSRET_MASK); 1455 } 1456 1457 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 1458 { 1459 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1460 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 1461 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 1462 } 1463 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq); 1464 1465 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 1466 { 1467 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1468 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 1469 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 1470 } 1471 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron); 1472 1473 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 1474 { 1475 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1476 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 1477 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 1478 } 1479 1480 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 1481 { 1482 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1483 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 1484 HDMI_PHY_CONF0_SELDIPIF_MASK); 1485 } 1486 1487 void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi) 1488 { 1489 /* PHY reset. The reset signal is active low on Gen1 PHYs. */ 1490 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1491 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1492 } 1493 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen1_reset); 1494 1495 void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi) 1496 { 1497 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 1498 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1499 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1500 } 1501 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_reset); 1502 1503 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) 1504 { 1505 hdmi_phy_test_clear(hdmi, 1); 1506 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR); 1507 hdmi_phy_test_clear(hdmi, 0); 1508 } 1509 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr); 1510 1511 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 1512 { 1513 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1514 unsigned int i; 1515 u16 val; 1516 1517 if (phy->gen == 1) { 1518 dw_hdmi_phy_enable_tmds(hdmi, 0); 1519 dw_hdmi_phy_enable_powerdown(hdmi, true); 1520 return; 1521 } 1522 1523 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 1524 1525 /* 1526 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 1527 * to low power mode. 1528 */ 1529 for (i = 0; i < 5; ++i) { 1530 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 1531 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 1532 break; 1533 1534 usleep_range(1000, 2000); 1535 } 1536 1537 if (val & HDMI_PHY_TX_PHY_LOCK) 1538 dev_warn(hdmi->dev, "PHY failed to power down\n"); 1539 else 1540 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); 1541 1542 dw_hdmi_phy_gen2_pddq(hdmi, 1); 1543 } 1544 1545 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 1546 { 1547 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1548 unsigned int i; 1549 u8 val; 1550 1551 if (phy->gen == 1) { 1552 dw_hdmi_phy_enable_powerdown(hdmi, false); 1553 1554 /* Toggle TMDS enable. */ 1555 dw_hdmi_phy_enable_tmds(hdmi, 0); 1556 dw_hdmi_phy_enable_tmds(hdmi, 1); 1557 return 0; 1558 } 1559 1560 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 1561 dw_hdmi_phy_gen2_pddq(hdmi, 0); 1562 1563 /* Wait for PHY PLL lock */ 1564 for (i = 0; i < 5; ++i) { 1565 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 1566 if (val) 1567 break; 1568 1569 usleep_range(1000, 2000); 1570 } 1571 1572 if (!val) { 1573 dev_err(hdmi->dev, "PHY PLL failed to lock\n"); 1574 return -ETIMEDOUT; 1575 } 1576 1577 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); 1578 return 0; 1579 } 1580 1581 /* 1582 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 1583 * information the DWC MHL PHY has the same register layout and is thus also 1584 * supported by this function. 1585 */ 1586 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 1587 const struct dw_hdmi_plat_data *pdata, 1588 unsigned long mpixelclock) 1589 { 1590 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 1591 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 1592 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 1593 1594 /* TOFIX Will need 420 specific PHY configuration tables */ 1595 1596 /* PLL/MPLL Cfg - always match on final entry */ 1597 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 1598 if (mpixelclock <= mpll_config->mpixelclock) 1599 break; 1600 1601 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 1602 if (mpixelclock <= curr_ctrl->mpixelclock) 1603 break; 1604 1605 for (; phy_config->mpixelclock != ~0UL; phy_config++) 1606 if (mpixelclock <= phy_config->mpixelclock) 1607 break; 1608 1609 if (mpll_config->mpixelclock == ~0UL || 1610 curr_ctrl->mpixelclock == ~0UL || 1611 phy_config->mpixelclock == ~0UL) 1612 return -EINVAL; 1613 1614 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 1615 HDMI_3D_TX_PHY_CPCE_CTRL); 1616 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 1617 HDMI_3D_TX_PHY_GMPCTRL); 1618 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 1619 HDMI_3D_TX_PHY_CURRCTRL); 1620 1621 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 1622 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 1623 HDMI_3D_TX_PHY_MSM_CTRL); 1624 1625 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 1626 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 1627 HDMI_3D_TX_PHY_CKSYMTXCTRL); 1628 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 1629 HDMI_3D_TX_PHY_VLEVCTRL); 1630 1631 /* Override and disable clock termination. */ 1632 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 1633 HDMI_3D_TX_PHY_CKCALCTRL); 1634 1635 return 0; 1636 } 1637 1638 static int hdmi_phy_configure(struct dw_hdmi *hdmi, 1639 const struct drm_display_info *display) 1640 { 1641 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1642 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 1643 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 1644 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1645 int ret; 1646 1647 dw_hdmi_phy_power_off(hdmi); 1648 1649 dw_hdmi_set_high_tmds_clock_ratio(hdmi, display); 1650 1651 /* Leave low power consumption mode by asserting SVSRET. */ 1652 if (phy->has_svsret) 1653 dw_hdmi_phy_enable_svsret(hdmi, 1); 1654 1655 dw_hdmi_phy_gen2_reset(hdmi); 1656 1657 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 1658 1659 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); 1660 1661 /* Write to the PHY as configured by the platform */ 1662 if (pdata->configure_phy) 1663 ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock); 1664 else 1665 ret = phy->configure(hdmi, pdata, mpixelclock); 1666 if (ret) { 1667 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", 1668 mpixelclock); 1669 return ret; 1670 } 1671 1672 /* Wait for resuming transmission of TMDS clock and data */ 1673 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1674 msleep(100); 1675 1676 return dw_hdmi_phy_power_on(hdmi); 1677 } 1678 1679 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 1680 const struct drm_display_info *display, 1681 const struct drm_display_mode *mode) 1682 { 1683 int i, ret; 1684 1685 /* HDMI Phy spec says to do the phy initialization sequence twice */ 1686 for (i = 0; i < 2; i++) { 1687 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 1688 dw_hdmi_phy_sel_interface_control(hdmi, 0); 1689 1690 ret = hdmi_phy_configure(hdmi, display); 1691 if (ret) 1692 return ret; 1693 } 1694 1695 return 0; 1696 } 1697 1698 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 1699 { 1700 dw_hdmi_phy_power_off(hdmi); 1701 } 1702 1703 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 1704 void *data) 1705 { 1706 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 1707 connector_status_connected : connector_status_disconnected; 1708 } 1709 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); 1710 1711 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 1712 bool force, bool disabled, bool rxsense) 1713 { 1714 u8 old_mask = hdmi->phy_mask; 1715 1716 if (force || disabled || !rxsense) 1717 hdmi->phy_mask |= HDMI_PHY_RX_SENSE; 1718 else 1719 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; 1720 1721 if (old_mask != hdmi->phy_mask) 1722 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1723 } 1724 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd); 1725 1726 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) 1727 { 1728 /* 1729 * Configure the PHY RX SENSE and HPD interrupts polarities and clear 1730 * any pending interrupt. 1731 */ 1732 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); 1733 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1734 HDMI_IH_PHY_STAT0); 1735 1736 /* Enable cable hot plug irq. */ 1737 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1738 1739 /* Clear and unmute interrupts. */ 1740 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1741 HDMI_IH_PHY_STAT0); 1742 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 1743 HDMI_IH_MUTE_PHY_STAT0); 1744 } 1745 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd); 1746 1747 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 1748 .init = dw_hdmi_phy_init, 1749 .disable = dw_hdmi_phy_disable, 1750 .read_hpd = dw_hdmi_phy_read_hpd, 1751 .update_hpd = dw_hdmi_phy_update_hpd, 1752 .setup_hpd = dw_hdmi_phy_setup_hpd, 1753 }; 1754 1755 /* ----------------------------------------------------------------------------- 1756 * HDMI TX Setup 1757 */ 1758 1759 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) 1760 { 1761 u8 de; 1762 1763 if (hdmi->hdmi_data.video_mode.mdataenablepolarity) 1764 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1765 else 1766 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; 1767 1768 /* disable rx detect */ 1769 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, 1770 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 1771 1772 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); 1773 1774 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, 1775 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); 1776 } 1777 1778 static void hdmi_config_AVI(struct dw_hdmi *hdmi, 1779 const struct drm_connector *connector, 1780 const struct drm_display_mode *mode) 1781 { 1782 struct hdmi_avi_infoframe frame; 1783 u8 val; 1784 1785 /* Initialise info frame from DRM mode */ 1786 drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); 1787 1788 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 1789 drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode, 1790 hdmi->hdmi_data.rgb_limited_range ? 1791 HDMI_QUANTIZATION_RANGE_LIMITED : 1792 HDMI_QUANTIZATION_RANGE_FULL); 1793 } else { 1794 frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 1795 frame.ycc_quantization_range = 1796 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 1797 } 1798 1799 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1800 frame.colorspace = HDMI_COLORSPACE_YUV444; 1801 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1802 frame.colorspace = HDMI_COLORSPACE_YUV422; 1803 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1804 frame.colorspace = HDMI_COLORSPACE_YUV420; 1805 else 1806 frame.colorspace = HDMI_COLORSPACE_RGB; 1807 1808 /* Set up colorimetry */ 1809 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 1810 switch (hdmi->hdmi_data.enc_out_encoding) { 1811 case V4L2_YCBCR_ENC_601: 1812 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1813 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1814 else 1815 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1816 frame.extended_colorimetry = 1817 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1818 break; 1819 case V4L2_YCBCR_ENC_709: 1820 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1821 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1822 else 1823 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1824 frame.extended_colorimetry = 1825 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1826 break; 1827 default: /* Carries no data */ 1828 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1829 frame.extended_colorimetry = 1830 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1831 break; 1832 } 1833 } else { 1834 frame.colorimetry = HDMI_COLORIMETRY_NONE; 1835 frame.extended_colorimetry = 1836 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1837 } 1838 1839 /* 1840 * The Designware IP uses a different byte format from standard 1841 * AVI info frames, though generally the bits are in the correct 1842 * bytes. 1843 */ 1844 1845 /* 1846 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, 1847 * scan info in bits 4,5 rather than 0,1 and active aspect present in 1848 * bit 6 rather than 4. 1849 */ 1850 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); 1851 if (frame.active_aspect & 15) 1852 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1853 if (frame.top_bar || frame.bottom_bar) 1854 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1855 if (frame.left_bar || frame.right_bar) 1856 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1857 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1858 1859 /* AVI data byte 2 differences: none */ 1860 val = ((frame.colorimetry & 0x3) << 6) | 1861 ((frame.picture_aspect & 0x3) << 4) | 1862 (frame.active_aspect & 0xf); 1863 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1864 1865 /* AVI data byte 3 differences: none */ 1866 val = ((frame.extended_colorimetry & 0x7) << 4) | 1867 ((frame.quantization_range & 0x3) << 2) | 1868 (frame.nups & 0x3); 1869 if (frame.itc) 1870 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1871 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1872 1873 /* AVI data byte 4 differences: none */ 1874 val = frame.video_code & 0x7f; 1875 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1876 1877 /* AVI Data Byte 5- set up input and output pixel repetition */ 1878 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1879 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1880 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1881 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1882 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1883 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1884 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1885 1886 /* 1887 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1888 * ycc range in bits 2,3 rather than 6,7 1889 */ 1890 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1891 (frame.content_type & 0x3); 1892 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1893 1894 /* AVI Data Bytes 6-13 */ 1895 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1896 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1897 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1898 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1899 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1900 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1901 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1902 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1903 } 1904 1905 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1906 const struct drm_connector *connector, 1907 const struct drm_display_mode *mode) 1908 { 1909 struct hdmi_vendor_infoframe frame; 1910 u8 buffer[10]; 1911 ssize_t err; 1912 1913 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, connector, 1914 mode); 1915 if (err < 0) 1916 /* 1917 * Going into that statement does not means vendor infoframe 1918 * fails. It just informed us that vendor infoframe is not 1919 * needed for the selected mode. Only 4k or stereoscopic 3D 1920 * mode requires vendor infoframe. So just simply return. 1921 */ 1922 return; 1923 1924 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1925 if (err < 0) { 1926 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1927 err); 1928 return; 1929 } 1930 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1931 HDMI_FC_DATAUTO0_VSD_MASK); 1932 1933 /* Set the length of HDMI vendor specific InfoFrame payload */ 1934 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1935 1936 /* Set 24bit IEEE Registration Identifier */ 1937 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1938 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1939 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1940 1941 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1942 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1943 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1944 1945 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1946 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1947 1948 /* Packet frame interpolation */ 1949 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1950 1951 /* Auto packets per frame and line spacing */ 1952 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1953 1954 /* Configures the Frame Composer On RDRB mode */ 1955 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1956 HDMI_FC_DATAUTO0_VSD_MASK); 1957 } 1958 1959 static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, 1960 const struct drm_connector *connector) 1961 { 1962 const struct drm_connector_state *conn_state = connector->state; 1963 struct hdmi_drm_infoframe frame; 1964 u8 buffer[30]; 1965 ssize_t err; 1966 int i; 1967 1968 if (!hdmi->plat_data->use_drm_infoframe) 1969 return; 1970 1971 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE, 1972 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); 1973 1974 err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state); 1975 if (err < 0) 1976 return; 1977 1978 err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer)); 1979 if (err < 0) { 1980 dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err); 1981 return; 1982 } 1983 1984 hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0); 1985 hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1); 1986 1987 for (i = 0; i < frame.length; i++) 1988 hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i); 1989 1990 hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP); 1991 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE, 1992 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); 1993 } 1994 1995 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1996 const struct drm_display_info *display, 1997 const struct drm_display_mode *mode) 1998 { 1999 u8 inv_val, bytes; 2000 const struct drm_hdmi_info *hdmi_info = &display->hdmi; 2001 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 2002 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 2003 unsigned int vdisplay, hdisplay; 2004 2005 vmode->mpixelclock = mode->clock * 1000; 2006 2007 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); 2008 2009 vmode->mtmdsclock = vmode->mpixelclock; 2010 2011 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 2012 switch (hdmi_bus_fmt_color_depth( 2013 hdmi->hdmi_data.enc_out_bus_format)) { 2014 case 16: 2015 vmode->mtmdsclock = vmode->mpixelclock * 2; 2016 break; 2017 case 12: 2018 vmode->mtmdsclock = vmode->mpixelclock * 3 / 2; 2019 break; 2020 case 10: 2021 vmode->mtmdsclock = vmode->mpixelclock * 5 / 4; 2022 break; 2023 } 2024 } 2025 2026 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 2027 vmode->mtmdsclock /= 2; 2028 2029 dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock); 2030 2031 /* Set up HDMI_FC_INVIDCONF */ 2032 inv_val = (hdmi->hdmi_data.hdcp_enable || 2033 (dw_hdmi_support_scdc(hdmi, display) && 2034 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 2035 hdmi_info->scdc.scrambling.low_rates)) ? 2036 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 2037 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 2038 2039 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 2040 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 2041 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 2042 2043 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 2044 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 2045 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 2046 2047 inv_val |= (vmode->mdataenablepolarity ? 2048 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 2049 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 2050 2051 if (hdmi->vic == 39) 2052 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 2053 else 2054 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 2055 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 2056 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 2057 2058 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 2059 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 2060 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 2061 2062 inv_val |= hdmi->sink_is_hdmi ? 2063 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 2064 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 2065 2066 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 2067 2068 hdisplay = mode->hdisplay; 2069 hblank = mode->htotal - mode->hdisplay; 2070 h_de_hs = mode->hsync_start - mode->hdisplay; 2071 hsync_len = mode->hsync_end - mode->hsync_start; 2072 2073 /* 2074 * When we're setting a YCbCr420 mode, we need 2075 * to adjust the horizontal timing to suit. 2076 */ 2077 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 2078 hdisplay /= 2; 2079 hblank /= 2; 2080 h_de_hs /= 2; 2081 hsync_len /= 2; 2082 } 2083 2084 vdisplay = mode->vdisplay; 2085 vblank = mode->vtotal - mode->vdisplay; 2086 v_de_vs = mode->vsync_start - mode->vdisplay; 2087 vsync_len = mode->vsync_end - mode->vsync_start; 2088 2089 /* 2090 * When we're setting an interlaced mode, we need 2091 * to adjust the vertical timing to suit. 2092 */ 2093 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 2094 vdisplay /= 2; 2095 vblank /= 2; 2096 v_de_vs /= 2; 2097 vsync_len /= 2; 2098 } 2099 2100 /* Scrambling Control */ 2101 if (dw_hdmi_support_scdc(hdmi, display)) { 2102 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 2103 hdmi_info->scdc.scrambling.low_rates) { 2104 /* 2105 * HDMI2.0 Specifies the following procedure: 2106 * After the Source Device has determined that 2107 * SCDC_Present is set (=1), the Source Device should 2108 * write the accurate Version of the Source Device 2109 * to the Source Version field in the SCDCS. 2110 * Source Devices compliant shall set the 2111 * Source Version = 1. 2112 */ 2113 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, 2114 &bytes); 2115 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, 2116 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); 2117 2118 /* Enabled Scrambling in the Sink */ 2119 drm_scdc_set_scrambling(&hdmi->connector, 1); 2120 2121 /* 2122 * To activate the scrambler feature, you must ensure 2123 * that the quasi-static configuration bit 2124 * fc_invidconf.HDCP_keepout is set at configuration 2125 * time, before the required mc_swrstzreq.tmdsswrst_req 2126 * reset request is issued. 2127 */ 2128 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 2129 HDMI_MC_SWRSTZ); 2130 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 2131 } else { 2132 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 2133 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 2134 HDMI_MC_SWRSTZ); 2135 drm_scdc_set_scrambling(&hdmi->connector, 0); 2136 } 2137 } 2138 2139 /* Set up horizontal active pixel width */ 2140 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 2141 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 2142 2143 /* Set up vertical active lines */ 2144 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 2145 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 2146 2147 /* Set up horizontal blanking pixel region width */ 2148 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 2149 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 2150 2151 /* Set up vertical blanking pixel region width */ 2152 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 2153 2154 /* Set up HSYNC active edge delay width (in pixel clks) */ 2155 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 2156 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 2157 2158 /* Set up VSYNC active edge delay (in lines) */ 2159 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 2160 2161 /* Set up HSYNC active pulse width (in pixel clks) */ 2162 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 2163 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 2164 2165 /* Set up VSYNC active edge delay (in lines) */ 2166 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 2167 } 2168 2169 /* HDMI Initialization Step B.4 */ 2170 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 2171 { 2172 /* control period minimum duration */ 2173 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 2174 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 2175 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 2176 2177 /* Set to fill TMDS data channels */ 2178 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 2179 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 2180 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 2181 2182 /* Enable pixel clock and tmds data path */ 2183 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE | 2184 HDMI_MC_CLKDIS_CSCCLK_DISABLE | 2185 HDMI_MC_CLKDIS_AUDCLK_DISABLE | 2186 HDMI_MC_CLKDIS_PREPCLK_DISABLE | 2187 HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 2188 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 2189 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2190 2191 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 2192 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2193 2194 /* Enable csc path */ 2195 if (is_csc_needed(hdmi)) { 2196 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 2197 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2198 2199 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 2200 HDMI_MC_FLOWCTRL); 2201 } else { 2202 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE; 2203 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2204 2205 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 2206 HDMI_MC_FLOWCTRL); 2207 } 2208 } 2209 2210 /* Workaround to clear the overflow condition */ 2211 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 2212 { 2213 unsigned int count; 2214 unsigned int i; 2215 u8 val; 2216 2217 /* 2218 * Under some circumstances the Frame Composer arithmetic unit can miss 2219 * an FC register write due to being busy processing the previous one. 2220 * The issue can be worked around by issuing a TMDS software reset and 2221 * then write one of the FC registers several times. 2222 * 2223 * The number of iterations matters and depends on the HDMI TX revision 2224 * (and possibly on the platform). 2225 * 4 iterations for i.MX6Q(v1.30a) and 1 iteration for others. 2226 * i.MX6DL (v1.31a), Allwinner SoCs (v1.32a), Rockchip RK3288 SoC (v2.00a), 2227 * Amlogic Meson GX SoCs (v2.01a), RK3328/RK3399 SoCs (v2.11a) 2228 * and i.MX8MPlus (v2.13a) have been identified as needing the workaround 2229 * with a single iteration. 2230 */ 2231 2232 switch (hdmi->version) { 2233 case 0x130a: 2234 count = 4; 2235 break; 2236 default: 2237 count = 1; 2238 break; 2239 } 2240 2241 /* TMDS software reset */ 2242 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 2243 2244 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 2245 for (i = 0; i < count; i++) 2246 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 2247 } 2248 2249 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 2250 { 2251 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 2252 HDMI_IH_MUTE_FC_STAT2); 2253 } 2254 2255 static int dw_hdmi_setup(struct dw_hdmi *hdmi, 2256 const struct drm_connector *connector, 2257 const struct drm_display_mode *mode) 2258 { 2259 int ret; 2260 2261 hdmi_disable_overflow_interrupts(hdmi); 2262 2263 hdmi->vic = drm_match_cea_mode(mode); 2264 2265 if (!hdmi->vic) { 2266 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); 2267 } else { 2268 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); 2269 } 2270 2271 if ((hdmi->vic == 6) || (hdmi->vic == 7) || 2272 (hdmi->vic == 21) || (hdmi->vic == 22) || 2273 (hdmi->vic == 2) || (hdmi->vic == 3) || 2274 (hdmi->vic == 17) || (hdmi->vic == 18)) 2275 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 2276 else 2277 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 2278 2279 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 2280 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 2281 2282 if (hdmi->hdmi_data.enc_in_bus_format == MEDIA_BUS_FMT_FIXED) 2283 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2284 2285 /* TOFIX: Get input encoding from plat data or fallback to none */ 2286 if (hdmi->plat_data->input_bus_encoding) 2287 hdmi->hdmi_data.enc_in_encoding = 2288 hdmi->plat_data->input_bus_encoding; 2289 else 2290 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 2291 2292 if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_FIXED) 2293 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2294 2295 hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi && 2296 drm_default_rgb_quant_range(mode) == 2297 HDMI_QUANTIZATION_RANGE_LIMITED; 2298 2299 hdmi->hdmi_data.pix_repet_factor = 0; 2300 hdmi->hdmi_data.hdcp_enable = 0; 2301 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 2302 2303 /* HDMI Initialization Step B.1 */ 2304 hdmi_av_composer(hdmi, &connector->display_info, mode); 2305 2306 /* HDMI Initializateion Step B.2 */ 2307 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, 2308 &connector->display_info, 2309 &hdmi->previous_mode); 2310 if (ret) 2311 return ret; 2312 hdmi->phy.enabled = true; 2313 2314 /* HDMI Initialization Step B.3 */ 2315 dw_hdmi_enable_video_path(hdmi); 2316 2317 if (hdmi->sink_has_audio) { 2318 dev_dbg(hdmi->dev, "sink has audio support\n"); 2319 2320 /* HDMI Initialization Step E - Configure audio */ 2321 hdmi_clk_regenerator_update_pixel_clock(hdmi); 2322 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable); 2323 } 2324 2325 /* not for DVI mode */ 2326 if (hdmi->sink_is_hdmi) { 2327 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); 2328 2329 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 2330 hdmi_config_AVI(hdmi, connector, mode); 2331 hdmi_config_vendor_specific_infoframe(hdmi, connector, mode); 2332 hdmi_config_drm_infoframe(hdmi, connector); 2333 } else { 2334 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); 2335 } 2336 2337 hdmi_video_packetize(hdmi); 2338 hdmi_video_csc(hdmi); 2339 hdmi_video_sample(hdmi); 2340 hdmi_tx_hdcp_config(hdmi); 2341 2342 dw_hdmi_clear_overflow(hdmi); 2343 2344 return 0; 2345 } 2346 2347 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) 2348 { 2349 u8 ih_mute; 2350 2351 /* 2352 * Boot up defaults are: 2353 * HDMI_IH_MUTE = 0x03 (disabled) 2354 * HDMI_IH_MUTE_* = 0x00 (enabled) 2355 * 2356 * Disable top level interrupt bits in HDMI block 2357 */ 2358 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | 2359 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2360 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; 2361 2362 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2363 2364 /* by default mask all interrupts */ 2365 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); 2366 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 2367 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 2368 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 2369 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); 2370 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); 2371 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); 2372 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); 2373 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); 2374 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); 2375 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); 2376 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); 2377 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); 2378 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); 2379 2380 /* Disable interrupts in the IH_MUTE_* registers */ 2381 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2382 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2383 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2384 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2385 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); 2386 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2387 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2388 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2389 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2390 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2391 2392 /* Enable top level interrupt bits in HDMI block */ 2393 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2394 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); 2395 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2396 } 2397 2398 static void dw_hdmi_poweron(struct dw_hdmi *hdmi) 2399 { 2400 hdmi->bridge_is_on = true; 2401 2402 /* 2403 * The curr_conn field is guaranteed to be valid here, as this function 2404 * is only be called when !hdmi->disabled. 2405 */ 2406 dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode); 2407 } 2408 2409 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) 2410 { 2411 if (hdmi->phy.enabled) { 2412 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 2413 hdmi->phy.enabled = false; 2414 } 2415 2416 hdmi->bridge_is_on = false; 2417 } 2418 2419 static void dw_hdmi_update_power(struct dw_hdmi *hdmi) 2420 { 2421 int force = hdmi->force; 2422 2423 if (hdmi->disabled) { 2424 force = DRM_FORCE_OFF; 2425 } else if (force == DRM_FORCE_UNSPECIFIED) { 2426 if (hdmi->rxsense) 2427 force = DRM_FORCE_ON; 2428 else 2429 force = DRM_FORCE_OFF; 2430 } 2431 2432 if (force == DRM_FORCE_OFF) { 2433 if (hdmi->bridge_is_on) 2434 dw_hdmi_poweroff(hdmi); 2435 } else { 2436 if (!hdmi->bridge_is_on) 2437 dw_hdmi_poweron(hdmi); 2438 } 2439 } 2440 2441 /* 2442 * Adjust the detection of RXSENSE according to whether we have a forced 2443 * connection mode enabled, or whether we have been disabled. There is 2444 * no point processing RXSENSE interrupts if we have a forced connection 2445 * state, or DRM has us disabled. 2446 * 2447 * We also disable rxsense interrupts when we think we're disconnected 2448 * to avoid floating TDMS signals giving false rxsense interrupts. 2449 * 2450 * Note: we still need to listen for HPD interrupts even when DRM has us 2451 * disabled so that we can detect a connect event. 2452 */ 2453 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) 2454 { 2455 if (hdmi->phy.ops->update_hpd) 2456 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, 2457 hdmi->force, hdmi->disabled, 2458 hdmi->rxsense); 2459 } 2460 2461 static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi) 2462 { 2463 enum drm_connector_status result; 2464 2465 result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 2466 2467 mutex_lock(&hdmi->mutex); 2468 if (result != hdmi->last_connector_result) { 2469 dev_dbg(hdmi->dev, "read_hpd result: %d", result); 2470 handle_plugged_change(hdmi, 2471 result == connector_status_connected); 2472 hdmi->last_connector_result = result; 2473 } 2474 mutex_unlock(&hdmi->mutex); 2475 2476 return result; 2477 } 2478 2479 static struct edid *dw_hdmi_get_edid(struct dw_hdmi *hdmi, 2480 struct drm_connector *connector) 2481 { 2482 struct edid *edid; 2483 2484 if (!hdmi->ddc) 2485 return NULL; 2486 2487 edid = drm_get_edid(connector, hdmi->ddc); 2488 if (!edid) { 2489 dev_dbg(hdmi->dev, "failed to get edid\n"); 2490 return NULL; 2491 } 2492 2493 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", 2494 edid->width_cm, edid->height_cm); 2495 2496 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); 2497 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2498 2499 return edid; 2500 } 2501 2502 /* ----------------------------------------------------------------------------- 2503 * DRM Connector Operations 2504 */ 2505 2506 static enum drm_connector_status 2507 dw_hdmi_connector_detect(struct drm_connector *connector, bool force) 2508 { 2509 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2510 connector); 2511 return dw_hdmi_detect(hdmi); 2512 } 2513 2514 static int dw_hdmi_connector_get_modes(struct drm_connector *connector) 2515 { 2516 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2517 connector); 2518 struct edid *edid; 2519 int ret; 2520 2521 edid = dw_hdmi_get_edid(hdmi, connector); 2522 if (!edid) 2523 return 0; 2524 2525 drm_connector_update_edid_property(connector, edid); 2526 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); 2527 ret = drm_add_edid_modes(connector, edid); 2528 kfree(edid); 2529 2530 return ret; 2531 } 2532 2533 static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, 2534 struct drm_atomic_state *state) 2535 { 2536 struct drm_connector_state *old_state = 2537 drm_atomic_get_old_connector_state(state, connector); 2538 struct drm_connector_state *new_state = 2539 drm_atomic_get_new_connector_state(state, connector); 2540 struct drm_crtc *crtc = new_state->crtc; 2541 struct drm_crtc_state *crtc_state; 2542 2543 if (!crtc) 2544 return 0; 2545 2546 if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 2547 crtc_state = drm_atomic_get_crtc_state(state, crtc); 2548 if (IS_ERR(crtc_state)) 2549 return PTR_ERR(crtc_state); 2550 2551 crtc_state->mode_changed = true; 2552 } 2553 2554 return 0; 2555 } 2556 2557 static void dw_hdmi_connector_force(struct drm_connector *connector) 2558 { 2559 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2560 connector); 2561 2562 mutex_lock(&hdmi->mutex); 2563 hdmi->force = connector->force; 2564 dw_hdmi_update_power(hdmi); 2565 dw_hdmi_update_phy_mask(hdmi); 2566 mutex_unlock(&hdmi->mutex); 2567 } 2568 2569 static const struct drm_connector_funcs dw_hdmi_connector_funcs = { 2570 .fill_modes = drm_helper_probe_single_connector_modes, 2571 .detect = dw_hdmi_connector_detect, 2572 .destroy = drm_connector_cleanup, 2573 .force = dw_hdmi_connector_force, 2574 .reset = drm_atomic_helper_connector_reset, 2575 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2576 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2577 }; 2578 2579 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { 2580 .get_modes = dw_hdmi_connector_get_modes, 2581 .atomic_check = dw_hdmi_connector_atomic_check, 2582 }; 2583 2584 static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) 2585 { 2586 struct drm_connector *connector = &hdmi->connector; 2587 struct cec_connector_info conn_info; 2588 struct cec_notifier *notifier; 2589 2590 if (hdmi->version >= 0x200a) 2591 connector->ycbcr_420_allowed = 2592 hdmi->plat_data->ycbcr_420_allowed; 2593 else 2594 connector->ycbcr_420_allowed = false; 2595 2596 connector->interlace_allowed = 1; 2597 connector->polled = DRM_CONNECTOR_POLL_HPD; 2598 2599 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); 2600 2601 drm_connector_init_with_ddc(hdmi->bridge.dev, connector, 2602 &dw_hdmi_connector_funcs, 2603 DRM_MODE_CONNECTOR_HDMIA, 2604 hdmi->ddc); 2605 2606 /* 2607 * drm_connector_attach_max_bpc_property() requires the 2608 * connector to have a state. 2609 */ 2610 drm_atomic_helper_connector_reset(connector); 2611 2612 drm_connector_attach_max_bpc_property(connector, 8, 16); 2613 2614 if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe) 2615 drm_connector_attach_hdr_output_metadata_property(connector); 2616 2617 drm_connector_attach_encoder(connector, hdmi->bridge.encoder); 2618 2619 cec_fill_conn_info_from_drm(&conn_info, connector); 2620 2621 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info); 2622 if (!notifier) 2623 return -ENOMEM; 2624 2625 mutex_lock(&hdmi->cec_notifier_mutex); 2626 hdmi->cec_notifier = notifier; 2627 mutex_unlock(&hdmi->cec_notifier_mutex); 2628 2629 return 0; 2630 } 2631 2632 /* ----------------------------------------------------------------------------- 2633 * DRM Bridge Operations 2634 */ 2635 2636 /* 2637 * Possible output formats : 2638 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48, 2639 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36, 2640 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30, 2641 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24, 2642 * - MEDIA_BUS_FMT_YUV16_1X48, 2643 * - MEDIA_BUS_FMT_RGB161616_1X48, 2644 * - MEDIA_BUS_FMT_UYVY12_1X24, 2645 * - MEDIA_BUS_FMT_YUV12_1X36, 2646 * - MEDIA_BUS_FMT_RGB121212_1X36, 2647 * - MEDIA_BUS_FMT_UYVY10_1X20, 2648 * - MEDIA_BUS_FMT_YUV10_1X30, 2649 * - MEDIA_BUS_FMT_RGB101010_1X30, 2650 * - MEDIA_BUS_FMT_UYVY8_1X16, 2651 * - MEDIA_BUS_FMT_YUV8_1X24, 2652 * - MEDIA_BUS_FMT_RGB888_1X24, 2653 */ 2654 2655 /* Can return a maximum of 11 possible output formats for a mode/connector */ 2656 #define MAX_OUTPUT_SEL_FORMATS 11 2657 2658 static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, 2659 struct drm_bridge_state *bridge_state, 2660 struct drm_crtc_state *crtc_state, 2661 struct drm_connector_state *conn_state, 2662 unsigned int *num_output_fmts) 2663 { 2664 struct drm_connector *conn = conn_state->connector; 2665 struct drm_display_info *info = &conn->display_info; 2666 struct drm_display_mode *mode = &crtc_state->mode; 2667 u8 max_bpc = conn_state->max_requested_bpc; 2668 bool is_hdmi2_sink = info->hdmi.scdc.supported || 2669 (info->color_formats & DRM_COLOR_FORMAT_YCBCR420); 2670 u32 *output_fmts; 2671 unsigned int i = 0; 2672 2673 *num_output_fmts = 0; 2674 2675 output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts), 2676 GFP_KERNEL); 2677 if (!output_fmts) 2678 return NULL; 2679 2680 /* If dw-hdmi is the first or only bridge, avoid negociating with ourselves */ 2681 if (list_is_singular(&bridge->encoder->bridge_chain) || 2682 list_is_first(&bridge->chain_node, &bridge->encoder->bridge_chain)) { 2683 *num_output_fmts = 1; 2684 output_fmts[0] = MEDIA_BUS_FMT_FIXED; 2685 2686 return output_fmts; 2687 } 2688 2689 /* 2690 * If the current mode enforces 4:2:0, force the output but format 2691 * to 4:2:0 and do not add the YUV422/444/RGB formats 2692 */ 2693 if (conn->ycbcr_420_allowed && 2694 (drm_mode_is_420_only(info, mode) || 2695 (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) { 2696 2697 /* Order bus formats from 16bit to 8bit if supported */ 2698 if (max_bpc >= 16 && info->bpc == 16 && 2699 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)) 2700 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48; 2701 2702 if (max_bpc >= 12 && info->bpc >= 12 && 2703 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)) 2704 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36; 2705 2706 if (max_bpc >= 10 && info->bpc >= 10 && 2707 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)) 2708 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30; 2709 2710 /* Default 8bit fallback */ 2711 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24; 2712 2713 *num_output_fmts = i; 2714 2715 return output_fmts; 2716 } 2717 2718 /* 2719 * Order bus formats from 16bit to 8bit and from YUV422 to RGB 2720 * if supported. In any case the default RGB888 format is added 2721 */ 2722 2723 /* Default 8bit RGB fallback */ 2724 output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2725 2726 if (max_bpc >= 16 && info->bpc == 16) { 2727 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) 2728 output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2729 2730 output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2731 } 2732 2733 if (max_bpc >= 12 && info->bpc >= 12) { 2734 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) 2735 output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2736 2737 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) 2738 output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2739 2740 output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2741 } 2742 2743 if (max_bpc >= 10 && info->bpc >= 10) { 2744 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) 2745 output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2746 2747 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) 2748 output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2749 2750 output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2751 } 2752 2753 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) 2754 output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2755 2756 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) 2757 output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2758 2759 *num_output_fmts = i; 2760 2761 return output_fmts; 2762 } 2763 2764 /* 2765 * Possible input formats : 2766 * - MEDIA_BUS_FMT_RGB888_1X24 2767 * - MEDIA_BUS_FMT_YUV8_1X24 2768 * - MEDIA_BUS_FMT_UYVY8_1X16 2769 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24 2770 * - MEDIA_BUS_FMT_RGB101010_1X30 2771 * - MEDIA_BUS_FMT_YUV10_1X30 2772 * - MEDIA_BUS_FMT_UYVY10_1X20 2773 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30 2774 * - MEDIA_BUS_FMT_RGB121212_1X36 2775 * - MEDIA_BUS_FMT_YUV12_1X36 2776 * - MEDIA_BUS_FMT_UYVY12_1X24 2777 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36 2778 * - MEDIA_BUS_FMT_RGB161616_1X48 2779 * - MEDIA_BUS_FMT_YUV16_1X48 2780 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48 2781 */ 2782 2783 /* Can return a maximum of 3 possible input formats for an output format */ 2784 #define MAX_INPUT_SEL_FORMATS 3 2785 2786 static u32 *dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 2787 struct drm_bridge_state *bridge_state, 2788 struct drm_crtc_state *crtc_state, 2789 struct drm_connector_state *conn_state, 2790 u32 output_fmt, 2791 unsigned int *num_input_fmts) 2792 { 2793 u32 *input_fmts; 2794 unsigned int i = 0; 2795 2796 *num_input_fmts = 0; 2797 2798 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 2799 GFP_KERNEL); 2800 if (!input_fmts) 2801 return NULL; 2802 2803 switch (output_fmt) { 2804 /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */ 2805 case MEDIA_BUS_FMT_FIXED: 2806 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2807 break; 2808 /* 8bit */ 2809 case MEDIA_BUS_FMT_RGB888_1X24: 2810 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2811 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2812 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2813 break; 2814 case MEDIA_BUS_FMT_YUV8_1X24: 2815 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2816 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2817 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2818 break; 2819 case MEDIA_BUS_FMT_UYVY8_1X16: 2820 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2821 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2822 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2823 break; 2824 2825 /* 10bit */ 2826 case MEDIA_BUS_FMT_RGB101010_1X30: 2827 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2828 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2829 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2830 break; 2831 case MEDIA_BUS_FMT_YUV10_1X30: 2832 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2833 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2834 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2835 break; 2836 case MEDIA_BUS_FMT_UYVY10_1X20: 2837 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2838 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2839 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2840 break; 2841 2842 /* 12bit */ 2843 case MEDIA_BUS_FMT_RGB121212_1X36: 2844 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2845 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2846 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2847 break; 2848 case MEDIA_BUS_FMT_YUV12_1X36: 2849 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2850 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2851 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2852 break; 2853 case MEDIA_BUS_FMT_UYVY12_1X24: 2854 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2855 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2856 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2857 break; 2858 2859 /* 16bit */ 2860 case MEDIA_BUS_FMT_RGB161616_1X48: 2861 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2862 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2863 break; 2864 case MEDIA_BUS_FMT_YUV16_1X48: 2865 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2866 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2867 break; 2868 2869 /*YUV 4:2:0 */ 2870 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 2871 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 2872 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 2873 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 2874 input_fmts[i++] = output_fmt; 2875 break; 2876 } 2877 2878 *num_input_fmts = i; 2879 2880 if (*num_input_fmts == 0) { 2881 kfree(input_fmts); 2882 input_fmts = NULL; 2883 } 2884 2885 return input_fmts; 2886 } 2887 2888 static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge, 2889 struct drm_bridge_state *bridge_state, 2890 struct drm_crtc_state *crtc_state, 2891 struct drm_connector_state *conn_state) 2892 { 2893 struct dw_hdmi *hdmi = bridge->driver_private; 2894 2895 hdmi->hdmi_data.enc_out_bus_format = 2896 bridge_state->output_bus_cfg.format; 2897 2898 hdmi->hdmi_data.enc_in_bus_format = 2899 bridge_state->input_bus_cfg.format; 2900 2901 dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n", 2902 bridge_state->input_bus_cfg.format, 2903 bridge_state->output_bus_cfg.format); 2904 2905 return 0; 2906 } 2907 2908 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge, 2909 enum drm_bridge_attach_flags flags) 2910 { 2911 struct dw_hdmi *hdmi = bridge->driver_private; 2912 2913 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) 2914 return drm_bridge_attach(bridge->encoder, hdmi->next_bridge, 2915 bridge, flags); 2916 2917 return dw_hdmi_connector_create(hdmi); 2918 } 2919 2920 static void dw_hdmi_bridge_detach(struct drm_bridge *bridge) 2921 { 2922 struct dw_hdmi *hdmi = bridge->driver_private; 2923 2924 mutex_lock(&hdmi->cec_notifier_mutex); 2925 cec_notifier_conn_unregister(hdmi->cec_notifier); 2926 hdmi->cec_notifier = NULL; 2927 mutex_unlock(&hdmi->cec_notifier_mutex); 2928 } 2929 2930 static enum drm_mode_status 2931 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 2932 const struct drm_display_info *info, 2933 const struct drm_display_mode *mode) 2934 { 2935 struct dw_hdmi *hdmi = bridge->driver_private; 2936 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 2937 enum drm_mode_status mode_status = MODE_OK; 2938 2939 /* We don't support double-clocked modes */ 2940 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2941 return MODE_BAD; 2942 2943 if (pdata->mode_valid) 2944 mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info, 2945 mode); 2946 2947 return mode_status; 2948 } 2949 2950 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, 2951 const struct drm_display_mode *orig_mode, 2952 const struct drm_display_mode *mode) 2953 { 2954 struct dw_hdmi *hdmi = bridge->driver_private; 2955 2956 mutex_lock(&hdmi->mutex); 2957 2958 /* Store the display mode for plugin/DKMS poweron events */ 2959 drm_mode_copy(&hdmi->previous_mode, mode); 2960 2961 mutex_unlock(&hdmi->mutex); 2962 } 2963 2964 static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, 2965 struct drm_bridge_state *old_state) 2966 { 2967 struct dw_hdmi *hdmi = bridge->driver_private; 2968 2969 mutex_lock(&hdmi->mutex); 2970 hdmi->disabled = true; 2971 hdmi->curr_conn = NULL; 2972 dw_hdmi_update_power(hdmi); 2973 dw_hdmi_update_phy_mask(hdmi); 2974 mutex_unlock(&hdmi->mutex); 2975 } 2976 2977 static void dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, 2978 struct drm_bridge_state *old_state) 2979 { 2980 struct dw_hdmi *hdmi = bridge->driver_private; 2981 struct drm_atomic_state *state = old_state->base.state; 2982 struct drm_connector *connector; 2983 2984 connector = drm_atomic_get_new_connector_for_encoder(state, 2985 bridge->encoder); 2986 2987 mutex_lock(&hdmi->mutex); 2988 hdmi->disabled = false; 2989 hdmi->curr_conn = connector; 2990 dw_hdmi_update_power(hdmi); 2991 dw_hdmi_update_phy_mask(hdmi); 2992 mutex_unlock(&hdmi->mutex); 2993 } 2994 2995 static enum drm_connector_status dw_hdmi_bridge_detect(struct drm_bridge *bridge) 2996 { 2997 struct dw_hdmi *hdmi = bridge->driver_private; 2998 2999 return dw_hdmi_detect(hdmi); 3000 } 3001 3002 static struct edid *dw_hdmi_bridge_get_edid(struct drm_bridge *bridge, 3003 struct drm_connector *connector) 3004 { 3005 struct dw_hdmi *hdmi = bridge->driver_private; 3006 3007 return dw_hdmi_get_edid(hdmi, connector); 3008 } 3009 3010 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { 3011 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 3012 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 3013 .atomic_reset = drm_atomic_helper_bridge_reset, 3014 .attach = dw_hdmi_bridge_attach, 3015 .detach = dw_hdmi_bridge_detach, 3016 .atomic_check = dw_hdmi_bridge_atomic_check, 3017 .atomic_get_output_bus_fmts = dw_hdmi_bridge_atomic_get_output_bus_fmts, 3018 .atomic_get_input_bus_fmts = dw_hdmi_bridge_atomic_get_input_bus_fmts, 3019 .atomic_enable = dw_hdmi_bridge_atomic_enable, 3020 .atomic_disable = dw_hdmi_bridge_atomic_disable, 3021 .mode_set = dw_hdmi_bridge_mode_set, 3022 .mode_valid = dw_hdmi_bridge_mode_valid, 3023 .detect = dw_hdmi_bridge_detect, 3024 .get_edid = dw_hdmi_bridge_get_edid, 3025 }; 3026 3027 /* ----------------------------------------------------------------------------- 3028 * IRQ Handling 3029 */ 3030 3031 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) 3032 { 3033 struct dw_hdmi_i2c *i2c = hdmi->i2c; 3034 unsigned int stat; 3035 3036 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 3037 if (!stat) 3038 return IRQ_NONE; 3039 3040 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0); 3041 3042 i2c->stat = stat; 3043 3044 complete(&i2c->cmp); 3045 3046 return IRQ_HANDLED; 3047 } 3048 3049 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) 3050 { 3051 struct dw_hdmi *hdmi = dev_id; 3052 u8 intr_stat; 3053 irqreturn_t ret = IRQ_NONE; 3054 3055 if (hdmi->i2c) 3056 ret = dw_hdmi_i2c_irq(hdmi); 3057 3058 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 3059 if (intr_stat) { 3060 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 3061 return IRQ_WAKE_THREAD; 3062 } 3063 3064 return ret; 3065 } 3066 3067 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) 3068 { 3069 mutex_lock(&hdmi->mutex); 3070 3071 if (!hdmi->force) { 3072 /* 3073 * If the RX sense status indicates we're disconnected, 3074 * clear the software rxsense status. 3075 */ 3076 if (!rx_sense) 3077 hdmi->rxsense = false; 3078 3079 /* 3080 * Only set the software rxsense status when both 3081 * rxsense and hpd indicates we're connected. 3082 * This avoids what seems to be bad behaviour in 3083 * at least iMX6S versions of the phy. 3084 */ 3085 if (hpd) 3086 hdmi->rxsense = true; 3087 3088 dw_hdmi_update_power(hdmi); 3089 dw_hdmi_update_phy_mask(hdmi); 3090 } 3091 mutex_unlock(&hdmi->mutex); 3092 } 3093 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); 3094 3095 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) 3096 { 3097 struct dw_hdmi *hdmi = dev_id; 3098 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; 3099 enum drm_connector_status status = connector_status_unknown; 3100 3101 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 3102 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); 3103 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); 3104 3105 phy_pol_mask = 0; 3106 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) 3107 phy_pol_mask |= HDMI_PHY_HPD; 3108 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) 3109 phy_pol_mask |= HDMI_PHY_RX_SENSE0; 3110 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) 3111 phy_pol_mask |= HDMI_PHY_RX_SENSE1; 3112 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) 3113 phy_pol_mask |= HDMI_PHY_RX_SENSE2; 3114 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) 3115 phy_pol_mask |= HDMI_PHY_RX_SENSE3; 3116 3117 if (phy_pol_mask) 3118 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); 3119 3120 /* 3121 * RX sense tells us whether the TDMS transmitters are detecting 3122 * load - in other words, there's something listening on the 3123 * other end of the link. Use this to decide whether we should 3124 * power on the phy as HPD may be toggled by the sink to merely 3125 * ask the source to re-read the EDID. 3126 */ 3127 if (intr_stat & 3128 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { 3129 dw_hdmi_setup_rx_sense(hdmi, 3130 phy_stat & HDMI_PHY_HPD, 3131 phy_stat & HDMI_PHY_RX_SENSE); 3132 3133 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) { 3134 mutex_lock(&hdmi->cec_notifier_mutex); 3135 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); 3136 mutex_unlock(&hdmi->cec_notifier_mutex); 3137 } 3138 3139 if (phy_stat & HDMI_PHY_HPD) 3140 status = connector_status_connected; 3141 3142 if (!(phy_stat & (HDMI_PHY_HPD | HDMI_PHY_RX_SENSE))) 3143 status = connector_status_disconnected; 3144 } 3145 3146 if (status != connector_status_unknown) { 3147 dev_dbg(hdmi->dev, "EVENT=%s\n", 3148 status == connector_status_connected ? 3149 "plugin" : "plugout"); 3150 3151 if (hdmi->bridge.dev) { 3152 drm_helper_hpd_irq_event(hdmi->bridge.dev); 3153 drm_bridge_hpd_notify(&hdmi->bridge, status); 3154 } 3155 } 3156 3157 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); 3158 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 3159 HDMI_IH_MUTE_PHY_STAT0); 3160 3161 return IRQ_HANDLED; 3162 } 3163 3164 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 3165 { 3166 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 3167 .name = "DWC HDMI TX PHY", 3168 .gen = 1, 3169 }, { 3170 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 3171 .name = "DWC MHL PHY + HEAC PHY", 3172 .gen = 2, 3173 .has_svsret = true, 3174 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3175 }, { 3176 .type = DW_HDMI_PHY_DWC_MHL_PHY, 3177 .name = "DWC MHL PHY", 3178 .gen = 2, 3179 .has_svsret = true, 3180 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3181 }, { 3182 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 3183 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 3184 .gen = 2, 3185 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3186 }, { 3187 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 3188 .name = "DWC HDMI 3D TX PHY", 3189 .gen = 2, 3190 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3191 }, { 3192 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 3193 .name = "DWC HDMI 2.0 TX PHY", 3194 .gen = 2, 3195 .has_svsret = true, 3196 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3197 }, { 3198 .type = DW_HDMI_PHY_VENDOR_PHY, 3199 .name = "Vendor PHY", 3200 } 3201 }; 3202 3203 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 3204 { 3205 unsigned int i; 3206 u8 phy_type; 3207 3208 phy_type = hdmi->plat_data->phy_force_vendor ? 3209 DW_HDMI_PHY_VENDOR_PHY : 3210 hdmi_readb(hdmi, HDMI_CONFIG2_ID); 3211 3212 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { 3213 /* Vendor PHYs require support from the glue layer. */ 3214 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 3215 dev_err(hdmi->dev, 3216 "Vendor HDMI PHY not supported by glue layer\n"); 3217 return -ENODEV; 3218 } 3219 3220 hdmi->phy.ops = hdmi->plat_data->phy_ops; 3221 hdmi->phy.data = hdmi->plat_data->phy_data; 3222 hdmi->phy.name = hdmi->plat_data->phy_name; 3223 return 0; 3224 } 3225 3226 /* Synopsys PHYs are handled internally. */ 3227 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 3228 if (dw_hdmi_phys[i].type == phy_type) { 3229 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 3230 hdmi->phy.name = dw_hdmi_phys[i].name; 3231 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 3232 3233 if (!dw_hdmi_phys[i].configure && 3234 !hdmi->plat_data->configure_phy) { 3235 dev_err(hdmi->dev, "%s requires platform support\n", 3236 hdmi->phy.name); 3237 return -ENODEV; 3238 } 3239 3240 return 0; 3241 } 3242 } 3243 3244 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); 3245 return -ENODEV; 3246 } 3247 3248 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi) 3249 { 3250 mutex_lock(&hdmi->mutex); 3251 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE; 3252 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 3253 mutex_unlock(&hdmi->mutex); 3254 } 3255 3256 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi) 3257 { 3258 mutex_lock(&hdmi->mutex); 3259 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE; 3260 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 3261 mutex_unlock(&hdmi->mutex); 3262 } 3263 3264 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = { 3265 .write = hdmi_writeb, 3266 .read = hdmi_readb, 3267 .enable = dw_hdmi_cec_enable, 3268 .disable = dw_hdmi_cec_disable, 3269 }; 3270 3271 static const struct regmap_config hdmi_regmap_8bit_config = { 3272 .reg_bits = 32, 3273 .val_bits = 8, 3274 .reg_stride = 1, 3275 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, 3276 }; 3277 3278 static const struct regmap_config hdmi_regmap_32bit_config = { 3279 .reg_bits = 32, 3280 .val_bits = 32, 3281 .reg_stride = 4, 3282 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, 3283 }; 3284 3285 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi) 3286 { 3287 initialize_hdmi_ih_mutes(hdmi); 3288 3289 /* 3290 * Reset HDMI DDC I2C master controller and mute I2CM interrupts. 3291 * Even if we are using a separate i2c adapter doing this doesn't 3292 * hurt. 3293 */ 3294 dw_hdmi_i2c_init(hdmi); 3295 3296 if (hdmi->phy.ops->setup_hpd) 3297 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 3298 } 3299 3300 /* ----------------------------------------------------------------------------- 3301 * Probe/remove API, used from platforms based on the DRM bridge API. 3302 */ 3303 3304 static int dw_hdmi_parse_dt(struct dw_hdmi *hdmi) 3305 { 3306 struct device_node *endpoint; 3307 struct device_node *remote; 3308 3309 if (!hdmi->plat_data->output_port) 3310 return 0; 3311 3312 endpoint = of_graph_get_endpoint_by_regs(hdmi->dev->of_node, 3313 hdmi->plat_data->output_port, 3314 -1); 3315 if (!endpoint) { 3316 /* 3317 * On platforms whose bindings don't make the output port 3318 * mandatory (such as Rockchip) the plat_data->output_port 3319 * field isn't set, so it's safe to make this a fatal error. 3320 */ 3321 dev_err(hdmi->dev, "Missing endpoint in port@%u\n", 3322 hdmi->plat_data->output_port); 3323 return -ENODEV; 3324 } 3325 3326 remote = of_graph_get_remote_port_parent(endpoint); 3327 of_node_put(endpoint); 3328 if (!remote) { 3329 dev_err(hdmi->dev, "Endpoint in port@%u unconnected\n", 3330 hdmi->plat_data->output_port); 3331 return -ENODEV; 3332 } 3333 3334 if (!of_device_is_available(remote)) { 3335 dev_err(hdmi->dev, "port@%u remote device is disabled\n", 3336 hdmi->plat_data->output_port); 3337 of_node_put(remote); 3338 return -ENODEV; 3339 } 3340 3341 hdmi->next_bridge = of_drm_find_bridge(remote); 3342 of_node_put(remote); 3343 if (!hdmi->next_bridge) 3344 return -EPROBE_DEFER; 3345 3346 return 0; 3347 } 3348 3349 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, 3350 const struct dw_hdmi_plat_data *plat_data) 3351 { 3352 struct device *dev = &pdev->dev; 3353 struct device_node *np = dev->of_node; 3354 struct platform_device_info pdevinfo; 3355 struct device_node *ddc_node; 3356 struct dw_hdmi_cec_data cec; 3357 struct dw_hdmi *hdmi; 3358 struct resource *iores = NULL; 3359 int irq; 3360 int ret; 3361 u32 val = 1; 3362 u8 prod_id0; 3363 u8 prod_id1; 3364 u8 config0; 3365 u8 config3; 3366 3367 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 3368 if (!hdmi) 3369 return ERR_PTR(-ENOMEM); 3370 3371 hdmi->plat_data = plat_data; 3372 hdmi->dev = dev; 3373 hdmi->sample_rate = 48000; 3374 hdmi->channels = 2; 3375 hdmi->disabled = true; 3376 hdmi->rxsense = true; 3377 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); 3378 hdmi->mc_clkdis = 0x7f; 3379 hdmi->last_connector_result = connector_status_disconnected; 3380 3381 mutex_init(&hdmi->mutex); 3382 mutex_init(&hdmi->audio_mutex); 3383 mutex_init(&hdmi->cec_notifier_mutex); 3384 spin_lock_init(&hdmi->audio_lock); 3385 3386 ret = dw_hdmi_parse_dt(hdmi); 3387 if (ret < 0) 3388 return ERR_PTR(ret); 3389 3390 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 3391 if (ddc_node) { 3392 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); 3393 of_node_put(ddc_node); 3394 if (!hdmi->ddc) { 3395 dev_dbg(hdmi->dev, "failed to read ddc node\n"); 3396 return ERR_PTR(-EPROBE_DEFER); 3397 } 3398 3399 } else { 3400 dev_dbg(hdmi->dev, "no ddc property found\n"); 3401 } 3402 3403 if (!plat_data->regm) { 3404 const struct regmap_config *reg_config; 3405 3406 of_property_read_u32(np, "reg-io-width", &val); 3407 switch (val) { 3408 case 4: 3409 reg_config = &hdmi_regmap_32bit_config; 3410 hdmi->reg_shift = 2; 3411 break; 3412 case 1: 3413 reg_config = &hdmi_regmap_8bit_config; 3414 break; 3415 default: 3416 dev_err(dev, "reg-io-width must be 1 or 4\n"); 3417 return ERR_PTR(-EINVAL); 3418 } 3419 3420 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3421 hdmi->regs = devm_ioremap_resource(dev, iores); 3422 if (IS_ERR(hdmi->regs)) { 3423 ret = PTR_ERR(hdmi->regs); 3424 goto err_res; 3425 } 3426 3427 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); 3428 if (IS_ERR(hdmi->regm)) { 3429 dev_err(dev, "Failed to configure regmap\n"); 3430 ret = PTR_ERR(hdmi->regm); 3431 goto err_res; 3432 } 3433 } else { 3434 hdmi->regm = plat_data->regm; 3435 } 3436 3437 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); 3438 if (IS_ERR(hdmi->isfr_clk)) { 3439 ret = PTR_ERR(hdmi->isfr_clk); 3440 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); 3441 goto err_res; 3442 } 3443 3444 ret = clk_prepare_enable(hdmi->isfr_clk); 3445 if (ret) { 3446 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret); 3447 goto err_res; 3448 } 3449 3450 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); 3451 if (IS_ERR(hdmi->iahb_clk)) { 3452 ret = PTR_ERR(hdmi->iahb_clk); 3453 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); 3454 goto err_isfr; 3455 } 3456 3457 ret = clk_prepare_enable(hdmi->iahb_clk); 3458 if (ret) { 3459 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret); 3460 goto err_isfr; 3461 } 3462 3463 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec"); 3464 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) { 3465 hdmi->cec_clk = NULL; 3466 } else if (IS_ERR(hdmi->cec_clk)) { 3467 ret = PTR_ERR(hdmi->cec_clk); 3468 if (ret != -EPROBE_DEFER) 3469 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n", 3470 ret); 3471 3472 hdmi->cec_clk = NULL; 3473 goto err_iahb; 3474 } else { 3475 ret = clk_prepare_enable(hdmi->cec_clk); 3476 if (ret) { 3477 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n", 3478 ret); 3479 goto err_iahb; 3480 } 3481 } 3482 3483 /* Product and revision IDs */ 3484 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 3485 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 3486 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); 3487 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); 3488 3489 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || 3490 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { 3491 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", 3492 hdmi->version, prod_id0, prod_id1); 3493 ret = -ENODEV; 3494 goto err_iahb; 3495 } 3496 3497 ret = dw_hdmi_detect_phy(hdmi); 3498 if (ret < 0) 3499 goto err_iahb; 3500 3501 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", 3502 hdmi->version >> 12, hdmi->version & 0xfff, 3503 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", 3504 hdmi->phy.name); 3505 3506 dw_hdmi_init_hw(hdmi); 3507 3508 irq = platform_get_irq(pdev, 0); 3509 if (irq < 0) { 3510 ret = irq; 3511 goto err_iahb; 3512 } 3513 3514 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, 3515 dw_hdmi_irq, IRQF_SHARED, 3516 dev_name(dev), hdmi); 3517 if (ret) 3518 goto err_iahb; 3519 3520 /* 3521 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator 3522 * N and cts values before enabling phy 3523 */ 3524 hdmi_init_clk_regenerator(hdmi); 3525 3526 /* If DDC bus is not specified, try to register HDMI I2C bus */ 3527 if (!hdmi->ddc) { 3528 /* Look for (optional) stuff related to unwedging */ 3529 hdmi->pinctrl = devm_pinctrl_get(dev); 3530 if (!IS_ERR(hdmi->pinctrl)) { 3531 hdmi->unwedge_state = 3532 pinctrl_lookup_state(hdmi->pinctrl, "unwedge"); 3533 hdmi->default_state = 3534 pinctrl_lookup_state(hdmi->pinctrl, "default"); 3535 3536 if (IS_ERR(hdmi->default_state) || 3537 IS_ERR(hdmi->unwedge_state)) { 3538 if (!IS_ERR(hdmi->unwedge_state)) 3539 dev_warn(dev, 3540 "Unwedge requires default pinctrl\n"); 3541 hdmi->default_state = NULL; 3542 hdmi->unwedge_state = NULL; 3543 } 3544 } 3545 3546 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); 3547 if (IS_ERR(hdmi->ddc)) 3548 hdmi->ddc = NULL; 3549 } 3550 3551 hdmi->bridge.driver_private = hdmi; 3552 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; 3553 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID 3554 | DRM_BRIDGE_OP_HPD; 3555 hdmi->bridge.interlace_allowed = true; 3556 #ifdef CONFIG_OF 3557 hdmi->bridge.of_node = pdev->dev.of_node; 3558 #endif 3559 3560 memset(&pdevinfo, 0, sizeof(pdevinfo)); 3561 pdevinfo.parent = dev; 3562 pdevinfo.id = PLATFORM_DEVID_AUTO; 3563 3564 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); 3565 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 3566 3567 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { 3568 struct dw_hdmi_audio_data audio; 3569 3570 audio.phys = iores->start; 3571 audio.base = hdmi->regs; 3572 audio.irq = irq; 3573 audio.hdmi = hdmi; 3574 audio.get_eld = hdmi_audio_get_eld; 3575 hdmi->enable_audio = dw_hdmi_ahb_audio_enable; 3576 hdmi->disable_audio = dw_hdmi_ahb_audio_disable; 3577 3578 pdevinfo.name = "dw-hdmi-ahb-audio"; 3579 pdevinfo.data = &audio; 3580 pdevinfo.size_data = sizeof(audio); 3581 pdevinfo.dma_mask = DMA_BIT_MASK(32); 3582 hdmi->audio = platform_device_register_full(&pdevinfo); 3583 } else if (config0 & HDMI_CONFIG0_I2S) { 3584 struct dw_hdmi_i2s_audio_data audio; 3585 3586 audio.hdmi = hdmi; 3587 audio.get_eld = hdmi_audio_get_eld; 3588 audio.write = hdmi_writeb; 3589 audio.read = hdmi_readb; 3590 hdmi->enable_audio = dw_hdmi_i2s_audio_enable; 3591 hdmi->disable_audio = dw_hdmi_i2s_audio_disable; 3592 3593 pdevinfo.name = "dw-hdmi-i2s-audio"; 3594 pdevinfo.data = &audio; 3595 pdevinfo.size_data = sizeof(audio); 3596 pdevinfo.dma_mask = DMA_BIT_MASK(32); 3597 hdmi->audio = platform_device_register_full(&pdevinfo); 3598 } else if (iores && config3 & HDMI_CONFIG3_GPAUD) { 3599 struct dw_hdmi_audio_data audio; 3600 3601 audio.phys = iores->start; 3602 audio.base = hdmi->regs; 3603 audio.irq = irq; 3604 audio.hdmi = hdmi; 3605 audio.get_eld = hdmi_audio_get_eld; 3606 3607 hdmi->enable_audio = dw_hdmi_gp_audio_enable; 3608 hdmi->disable_audio = dw_hdmi_gp_audio_disable; 3609 3610 pdevinfo.name = "dw-hdmi-gp-audio"; 3611 pdevinfo.id = PLATFORM_DEVID_NONE; 3612 pdevinfo.data = &audio; 3613 pdevinfo.size_data = sizeof(audio); 3614 pdevinfo.dma_mask = DMA_BIT_MASK(32); 3615 hdmi->audio = platform_device_register_full(&pdevinfo); 3616 } 3617 3618 if (!plat_data->disable_cec && (config0 & HDMI_CONFIG0_CEC)) { 3619 cec.hdmi = hdmi; 3620 cec.ops = &dw_hdmi_cec_ops; 3621 cec.irq = irq; 3622 3623 pdevinfo.name = "dw-hdmi-cec"; 3624 pdevinfo.data = &cec; 3625 pdevinfo.size_data = sizeof(cec); 3626 pdevinfo.dma_mask = 0; 3627 3628 hdmi->cec = platform_device_register_full(&pdevinfo); 3629 } 3630 3631 drm_bridge_add(&hdmi->bridge); 3632 3633 return hdmi; 3634 3635 err_iahb: 3636 clk_disable_unprepare(hdmi->iahb_clk); 3637 clk_disable_unprepare(hdmi->cec_clk); 3638 err_isfr: 3639 clk_disable_unprepare(hdmi->isfr_clk); 3640 err_res: 3641 i2c_put_adapter(hdmi->ddc); 3642 3643 return ERR_PTR(ret); 3644 } 3645 EXPORT_SYMBOL_GPL(dw_hdmi_probe); 3646 3647 void dw_hdmi_remove(struct dw_hdmi *hdmi) 3648 { 3649 drm_bridge_remove(&hdmi->bridge); 3650 3651 if (hdmi->audio && !IS_ERR(hdmi->audio)) 3652 platform_device_unregister(hdmi->audio); 3653 if (!IS_ERR(hdmi->cec)) 3654 platform_device_unregister(hdmi->cec); 3655 3656 /* Disable all interrupts */ 3657 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 3658 3659 clk_disable_unprepare(hdmi->iahb_clk); 3660 clk_disable_unprepare(hdmi->isfr_clk); 3661 clk_disable_unprepare(hdmi->cec_clk); 3662 3663 if (hdmi->i2c) 3664 i2c_del_adapter(&hdmi->i2c->adap); 3665 else 3666 i2c_put_adapter(hdmi->ddc); 3667 } 3668 EXPORT_SYMBOL_GPL(dw_hdmi_remove); 3669 3670 /* ----------------------------------------------------------------------------- 3671 * Bind/unbind API, used from platforms based on the component framework. 3672 */ 3673 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, 3674 struct drm_encoder *encoder, 3675 const struct dw_hdmi_plat_data *plat_data) 3676 { 3677 struct dw_hdmi *hdmi; 3678 int ret; 3679 3680 hdmi = dw_hdmi_probe(pdev, plat_data); 3681 if (IS_ERR(hdmi)) 3682 return hdmi; 3683 3684 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0); 3685 if (ret) { 3686 dw_hdmi_remove(hdmi); 3687 return ERR_PTR(ret); 3688 } 3689 3690 return hdmi; 3691 } 3692 EXPORT_SYMBOL_GPL(dw_hdmi_bind); 3693 3694 void dw_hdmi_unbind(struct dw_hdmi *hdmi) 3695 { 3696 dw_hdmi_remove(hdmi); 3697 } 3698 EXPORT_SYMBOL_GPL(dw_hdmi_unbind); 3699 3700 void dw_hdmi_resume(struct dw_hdmi *hdmi) 3701 { 3702 dw_hdmi_init_hw(hdmi); 3703 } 3704 EXPORT_SYMBOL_GPL(dw_hdmi_resume); 3705 3706 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 3707 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); 3708 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); 3709 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>"); 3710 MODULE_DESCRIPTION("DW HDMI transmitter driver"); 3711 MODULE_LICENSE("GPL"); 3712 MODULE_ALIAS("platform:dw-hdmi"); 3713