1 /* 2 * DesignWare High-Definition Multimedia Interface (HDMI) driver 3 * 4 * Copyright (C) 2013-2015 Mentor Graphics Inc. 5 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 6 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 */ 14 #include <linux/module.h> 15 #include <linux/irq.h> 16 #include <linux/delay.h> 17 #include <linux/err.h> 18 #include <linux/clk.h> 19 #include <linux/hdmi.h> 20 #include <linux/mutex.h> 21 #include <linux/of_device.h> 22 #include <linux/regmap.h> 23 #include <linux/spinlock.h> 24 25 #include <drm/drm_of.h> 26 #include <drm/drmP.h> 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_encoder_slave.h> 31 #include <drm/bridge/dw_hdmi.h> 32 33 #include "dw-hdmi.h" 34 #include "dw-hdmi-audio.h" 35 36 #define DDC_SEGMENT_ADDR 0x30 37 #define HDMI_EDID_LEN 512 38 39 #define RGB 0 40 #define YCBCR444 1 41 #define YCBCR422_16BITS 2 42 #define YCBCR422_8BITS 3 43 #define XVYCC444 4 44 45 enum hdmi_datamap { 46 RGB444_8B = 0x01, 47 RGB444_10B = 0x03, 48 RGB444_12B = 0x05, 49 RGB444_16B = 0x07, 50 YCbCr444_8B = 0x09, 51 YCbCr444_10B = 0x0B, 52 YCbCr444_12B = 0x0D, 53 YCbCr444_16B = 0x0F, 54 YCbCr422_8B = 0x16, 55 YCbCr422_10B = 0x14, 56 YCbCr422_12B = 0x12, 57 }; 58 59 static const u16 csc_coeff_default[3][4] = { 60 { 0x2000, 0x0000, 0x0000, 0x0000 }, 61 { 0x0000, 0x2000, 0x0000, 0x0000 }, 62 { 0x0000, 0x0000, 0x2000, 0x0000 } 63 }; 64 65 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 66 { 0x2000, 0x6926, 0x74fd, 0x010e }, 67 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 68 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 69 }; 70 71 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 72 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 73 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 74 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 75 }; 76 77 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 78 { 0x2591, 0x1322, 0x074b, 0x0000 }, 79 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 80 { 0x6acd, 0x7534, 0x2000, 0x0200 } 81 }; 82 83 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 84 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 85 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 86 { 0x6756, 0x78ab, 0x2000, 0x0200 } 87 }; 88 89 struct hdmi_vmode { 90 bool mdataenablepolarity; 91 92 unsigned int mpixelclock; 93 unsigned int mpixelrepetitioninput; 94 unsigned int mpixelrepetitionoutput; 95 }; 96 97 struct hdmi_data_info { 98 unsigned int enc_in_format; 99 unsigned int enc_out_format; 100 unsigned int enc_color_depth; 101 unsigned int colorimetry; 102 unsigned int pix_repet_factor; 103 unsigned int hdcp_enable; 104 struct hdmi_vmode video_mode; 105 }; 106 107 struct dw_hdmi_i2c { 108 struct i2c_adapter adap; 109 110 struct mutex lock; /* used to serialize data transfers */ 111 struct completion cmp; 112 u8 stat; 113 114 u8 slave_reg; 115 bool is_regaddr; 116 bool is_segment; 117 }; 118 119 struct dw_hdmi_phy_data { 120 enum dw_hdmi_phy_type type; 121 const char *name; 122 unsigned int gen; 123 bool has_svsret; 124 int (*configure)(struct dw_hdmi *hdmi, 125 const struct dw_hdmi_plat_data *pdata, 126 unsigned long mpixelclock); 127 }; 128 129 struct dw_hdmi { 130 struct drm_connector connector; 131 struct drm_bridge bridge; 132 133 unsigned int version; 134 135 struct platform_device *audio; 136 struct device *dev; 137 struct clk *isfr_clk; 138 struct clk *iahb_clk; 139 struct dw_hdmi_i2c *i2c; 140 141 struct hdmi_data_info hdmi_data; 142 const struct dw_hdmi_plat_data *plat_data; 143 144 int vic; 145 146 u8 edid[HDMI_EDID_LEN]; 147 bool cable_plugin; 148 149 struct { 150 const struct dw_hdmi_phy_ops *ops; 151 const char *name; 152 void *data; 153 bool enabled; 154 } phy; 155 156 struct drm_display_mode previous_mode; 157 158 struct i2c_adapter *ddc; 159 void __iomem *regs; 160 bool sink_is_hdmi; 161 bool sink_has_audio; 162 163 struct mutex mutex; /* for state below and previous_mode */ 164 enum drm_connector_force force; /* mutex-protected force state */ 165 bool disabled; /* DRM has disabled our bridge */ 166 bool bridge_is_on; /* indicates the bridge is on */ 167 bool rxsense; /* rxsense state */ 168 u8 phy_mask; /* desired phy int mask settings */ 169 170 spinlock_t audio_lock; 171 struct mutex audio_mutex; 172 unsigned int sample_rate; 173 unsigned int audio_cts; 174 unsigned int audio_n; 175 bool audio_enable; 176 177 unsigned int reg_shift; 178 struct regmap *regm; 179 }; 180 181 #define HDMI_IH_PHY_STAT0_RX_SENSE \ 182 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ 183 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) 184 185 #define HDMI_PHY_RX_SENSE \ 186 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ 187 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) 188 189 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 190 { 191 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); 192 } 193 194 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 195 { 196 unsigned int val = 0; 197 198 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); 199 200 return val; 201 } 202 203 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 204 { 205 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); 206 } 207 208 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 209 u8 shift, u8 mask) 210 { 211 hdmi_modb(hdmi, data << shift, mask, reg); 212 } 213 214 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 215 { 216 /* Software reset */ 217 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 218 219 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ 220 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); 221 222 /* Set done, not acknowledged and arbitration interrupt polarities */ 223 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 224 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 225 HDMI_I2CM_CTLINT); 226 227 /* Clear DONE and ERROR interrupts */ 228 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 229 HDMI_IH_I2CM_STAT0); 230 231 /* Mute DONE and ERROR interrupts */ 232 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 233 HDMI_IH_MUTE_I2CM_STAT0); 234 } 235 236 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 237 unsigned char *buf, unsigned int length) 238 { 239 struct dw_hdmi_i2c *i2c = hdmi->i2c; 240 int stat; 241 242 if (!i2c->is_regaddr) { 243 dev_dbg(hdmi->dev, "set read register address to 0\n"); 244 i2c->slave_reg = 0x00; 245 i2c->is_regaddr = true; 246 } 247 248 while (length--) { 249 reinit_completion(&i2c->cmp); 250 251 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 252 if (i2c->is_segment) 253 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 254 HDMI_I2CM_OPERATION); 255 else 256 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 257 HDMI_I2CM_OPERATION); 258 259 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 260 if (!stat) 261 return -EAGAIN; 262 263 /* Check for error condition on the bus */ 264 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 265 return -EIO; 266 267 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 268 } 269 i2c->is_segment = false; 270 271 return 0; 272 } 273 274 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 275 unsigned char *buf, unsigned int length) 276 { 277 struct dw_hdmi_i2c *i2c = hdmi->i2c; 278 int stat; 279 280 if (!i2c->is_regaddr) { 281 /* Use the first write byte as register address */ 282 i2c->slave_reg = buf[0]; 283 length--; 284 buf++; 285 i2c->is_regaddr = true; 286 } 287 288 while (length--) { 289 reinit_completion(&i2c->cmp); 290 291 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 292 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 293 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 294 HDMI_I2CM_OPERATION); 295 296 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 297 if (!stat) 298 return -EAGAIN; 299 300 /* Check for error condition on the bus */ 301 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 302 return -EIO; 303 } 304 305 return 0; 306 } 307 308 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, 309 struct i2c_msg *msgs, int num) 310 { 311 struct dw_hdmi *hdmi = i2c_get_adapdata(adap); 312 struct dw_hdmi_i2c *i2c = hdmi->i2c; 313 u8 addr = msgs[0].addr; 314 int i, ret = 0; 315 316 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); 317 318 for (i = 0; i < num; i++) { 319 if (msgs[i].len == 0) { 320 dev_dbg(hdmi->dev, 321 "unsupported transfer %d/%d, no data\n", 322 i + 1, num); 323 return -EOPNOTSUPP; 324 } 325 } 326 327 mutex_lock(&i2c->lock); 328 329 /* Unmute DONE and ERROR interrupts */ 330 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 331 332 /* Set slave device address taken from the first I2C message */ 333 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 334 335 /* Set slave device register address on transfer */ 336 i2c->is_regaddr = false; 337 338 /* Set segment pointer for I2C extended read mode operation */ 339 i2c->is_segment = false; 340 341 for (i = 0; i < num; i++) { 342 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", 343 i + 1, num, msgs[i].len, msgs[i].flags); 344 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 345 i2c->is_segment = true; 346 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 347 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 348 } else { 349 if (msgs[i].flags & I2C_M_RD) 350 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 351 msgs[i].len); 352 else 353 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 354 msgs[i].len); 355 } 356 if (ret < 0) 357 break; 358 } 359 360 if (!ret) 361 ret = num; 362 363 /* Mute DONE and ERROR interrupts */ 364 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 365 HDMI_IH_MUTE_I2CM_STAT0); 366 367 mutex_unlock(&i2c->lock); 368 369 return ret; 370 } 371 372 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) 373 { 374 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 375 } 376 377 static const struct i2c_algorithm dw_hdmi_algorithm = { 378 .master_xfer = dw_hdmi_i2c_xfer, 379 .functionality = dw_hdmi_i2c_func, 380 }; 381 382 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) 383 { 384 struct i2c_adapter *adap; 385 struct dw_hdmi_i2c *i2c; 386 int ret; 387 388 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 389 if (!i2c) 390 return ERR_PTR(-ENOMEM); 391 392 mutex_init(&i2c->lock); 393 init_completion(&i2c->cmp); 394 395 adap = &i2c->adap; 396 adap->class = I2C_CLASS_DDC; 397 adap->owner = THIS_MODULE; 398 adap->dev.parent = hdmi->dev; 399 adap->algo = &dw_hdmi_algorithm; 400 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name)); 401 i2c_set_adapdata(adap, hdmi); 402 403 ret = i2c_add_adapter(adap); 404 if (ret) { 405 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 406 devm_kfree(hdmi->dev, i2c); 407 return ERR_PTR(ret); 408 } 409 410 hdmi->i2c = i2c; 411 412 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 413 414 return adap; 415 } 416 417 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 418 unsigned int n) 419 { 420 /* Must be set/cleared first */ 421 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 422 423 /* nshift factor = 0 */ 424 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 425 426 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 427 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 428 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 429 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 430 431 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 432 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 433 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 434 } 435 436 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) 437 { 438 unsigned int n = (128 * freq) / 1000; 439 unsigned int mult = 1; 440 441 while (freq > 48000) { 442 mult *= 2; 443 freq /= 2; 444 } 445 446 switch (freq) { 447 case 32000: 448 if (pixel_clk == 25175000) 449 n = 4576; 450 else if (pixel_clk == 27027000) 451 n = 4096; 452 else if (pixel_clk == 74176000 || pixel_clk == 148352000) 453 n = 11648; 454 else 455 n = 4096; 456 n *= mult; 457 break; 458 459 case 44100: 460 if (pixel_clk == 25175000) 461 n = 7007; 462 else if (pixel_clk == 74176000) 463 n = 17836; 464 else if (pixel_clk == 148352000) 465 n = 8918; 466 else 467 n = 6272; 468 n *= mult; 469 break; 470 471 case 48000: 472 if (pixel_clk == 25175000) 473 n = 6864; 474 else if (pixel_clk == 27027000) 475 n = 6144; 476 else if (pixel_clk == 74176000) 477 n = 11648; 478 else if (pixel_clk == 148352000) 479 n = 5824; 480 else 481 n = 6144; 482 n *= mult; 483 break; 484 485 default: 486 break; 487 } 488 489 return n; 490 } 491 492 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, 493 unsigned long pixel_clk, unsigned int sample_rate) 494 { 495 unsigned long ftdms = pixel_clk; 496 unsigned int n, cts; 497 u64 tmp; 498 499 n = hdmi_compute_n(sample_rate, pixel_clk); 500 501 /* 502 * Compute the CTS value from the N value. Note that CTS and N 503 * can be up to 20 bits in total, so we need 64-bit math. Also 504 * note that our TDMS clock is not fully accurate; it is accurate 505 * to kHz. This can introduce an unnecessary remainder in the 506 * calculation below, so we don't try to warn about that. 507 */ 508 tmp = (u64)ftdms * n; 509 do_div(tmp, 128 * sample_rate); 510 cts = tmp; 511 512 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", 513 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, 514 n, cts); 515 516 spin_lock_irq(&hdmi->audio_lock); 517 hdmi->audio_n = n; 518 hdmi->audio_cts = cts; 519 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 520 spin_unlock_irq(&hdmi->audio_lock); 521 } 522 523 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) 524 { 525 mutex_lock(&hdmi->audio_mutex); 526 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); 527 mutex_unlock(&hdmi->audio_mutex); 528 } 529 530 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 531 { 532 mutex_lock(&hdmi->audio_mutex); 533 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock, 534 hdmi->sample_rate); 535 mutex_unlock(&hdmi->audio_mutex); 536 } 537 538 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 539 { 540 mutex_lock(&hdmi->audio_mutex); 541 hdmi->sample_rate = rate; 542 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock, 543 hdmi->sample_rate); 544 mutex_unlock(&hdmi->audio_mutex); 545 } 546 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); 547 548 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 549 { 550 unsigned long flags; 551 552 spin_lock_irqsave(&hdmi->audio_lock, flags); 553 hdmi->audio_enable = true; 554 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 555 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 556 } 557 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); 558 559 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 560 { 561 unsigned long flags; 562 563 spin_lock_irqsave(&hdmi->audio_lock, flags); 564 hdmi->audio_enable = false; 565 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 566 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 567 } 568 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); 569 570 /* 571 * this submodule is responsible for the video data synchronization. 572 * for example, for RGB 4:4:4 input, the data map is defined as 573 * pin{47~40} <==> R[7:0] 574 * pin{31~24} <==> G[7:0] 575 * pin{15~8} <==> B[7:0] 576 */ 577 static void hdmi_video_sample(struct dw_hdmi *hdmi) 578 { 579 int color_format = 0; 580 u8 val; 581 582 if (hdmi->hdmi_data.enc_in_format == RGB) { 583 if (hdmi->hdmi_data.enc_color_depth == 8) 584 color_format = 0x01; 585 else if (hdmi->hdmi_data.enc_color_depth == 10) 586 color_format = 0x03; 587 else if (hdmi->hdmi_data.enc_color_depth == 12) 588 color_format = 0x05; 589 else if (hdmi->hdmi_data.enc_color_depth == 16) 590 color_format = 0x07; 591 else 592 return; 593 } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) { 594 if (hdmi->hdmi_data.enc_color_depth == 8) 595 color_format = 0x09; 596 else if (hdmi->hdmi_data.enc_color_depth == 10) 597 color_format = 0x0B; 598 else if (hdmi->hdmi_data.enc_color_depth == 12) 599 color_format = 0x0D; 600 else if (hdmi->hdmi_data.enc_color_depth == 16) 601 color_format = 0x0F; 602 else 603 return; 604 } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) { 605 if (hdmi->hdmi_data.enc_color_depth == 8) 606 color_format = 0x16; 607 else if (hdmi->hdmi_data.enc_color_depth == 10) 608 color_format = 0x14; 609 else if (hdmi->hdmi_data.enc_color_depth == 12) 610 color_format = 0x12; 611 else 612 return; 613 } 614 615 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 616 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 617 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 618 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 619 620 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 621 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 622 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 623 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 624 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 625 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 626 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 627 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 628 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 629 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 630 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 631 } 632 633 static int is_color_space_conversion(struct dw_hdmi *hdmi) 634 { 635 return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format; 636 } 637 638 static int is_color_space_decimation(struct dw_hdmi *hdmi) 639 { 640 if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS) 641 return 0; 642 if (hdmi->hdmi_data.enc_in_format == RGB || 643 hdmi->hdmi_data.enc_in_format == YCBCR444) 644 return 1; 645 return 0; 646 } 647 648 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 649 { 650 if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS) 651 return 0; 652 if (hdmi->hdmi_data.enc_out_format == RGB || 653 hdmi->hdmi_data.enc_out_format == YCBCR444) 654 return 1; 655 return 0; 656 } 657 658 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 659 { 660 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 661 unsigned i; 662 u32 csc_scale = 1; 663 664 if (is_color_space_conversion(hdmi)) { 665 if (hdmi->hdmi_data.enc_out_format == RGB) { 666 if (hdmi->hdmi_data.colorimetry == 667 HDMI_COLORIMETRY_ITU_601) 668 csc_coeff = &csc_coeff_rgb_out_eitu601; 669 else 670 csc_coeff = &csc_coeff_rgb_out_eitu709; 671 } else if (hdmi->hdmi_data.enc_in_format == RGB) { 672 if (hdmi->hdmi_data.colorimetry == 673 HDMI_COLORIMETRY_ITU_601) 674 csc_coeff = &csc_coeff_rgb_in_eitu601; 675 else 676 csc_coeff = &csc_coeff_rgb_in_eitu709; 677 csc_scale = 0; 678 } 679 } 680 681 /* The CSC registers are sequential, alternating MSB then LSB */ 682 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 683 u16 coeff_a = (*csc_coeff)[0][i]; 684 u16 coeff_b = (*csc_coeff)[1][i]; 685 u16 coeff_c = (*csc_coeff)[2][i]; 686 687 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 688 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 689 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 690 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 691 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 692 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 693 } 694 695 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 696 HDMI_CSC_SCALE); 697 } 698 699 static void hdmi_video_csc(struct dw_hdmi *hdmi) 700 { 701 int color_depth = 0; 702 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 703 int decimation = 0; 704 705 /* YCC422 interpolation to 444 mode */ 706 if (is_color_space_interpolation(hdmi)) 707 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 708 else if (is_color_space_decimation(hdmi)) 709 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 710 711 if (hdmi->hdmi_data.enc_color_depth == 8) 712 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 713 else if (hdmi->hdmi_data.enc_color_depth == 10) 714 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 715 else if (hdmi->hdmi_data.enc_color_depth == 12) 716 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 717 else if (hdmi->hdmi_data.enc_color_depth == 16) 718 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 719 else 720 return; 721 722 /* Configure the CSC registers */ 723 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 724 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 725 HDMI_CSC_SCALE); 726 727 dw_hdmi_update_csc_coeffs(hdmi); 728 } 729 730 /* 731 * HDMI video packetizer is used to packetize the data. 732 * for example, if input is YCC422 mode or repeater is used, 733 * data should be repacked this module can be bypassed. 734 */ 735 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 736 { 737 unsigned int color_depth = 0; 738 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 739 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 740 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 741 u8 val, vp_conf; 742 743 if (hdmi_data->enc_out_format == RGB || 744 hdmi_data->enc_out_format == YCBCR444) { 745 if (!hdmi_data->enc_color_depth) { 746 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 747 } else if (hdmi_data->enc_color_depth == 8) { 748 color_depth = 4; 749 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 750 } else if (hdmi_data->enc_color_depth == 10) { 751 color_depth = 5; 752 } else if (hdmi_data->enc_color_depth == 12) { 753 color_depth = 6; 754 } else if (hdmi_data->enc_color_depth == 16) { 755 color_depth = 7; 756 } else { 757 return; 758 } 759 } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) { 760 if (!hdmi_data->enc_color_depth || 761 hdmi_data->enc_color_depth == 8) 762 remap_size = HDMI_VP_REMAP_YCC422_16bit; 763 else if (hdmi_data->enc_color_depth == 10) 764 remap_size = HDMI_VP_REMAP_YCC422_20bit; 765 else if (hdmi_data->enc_color_depth == 12) 766 remap_size = HDMI_VP_REMAP_YCC422_24bit; 767 else 768 return; 769 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 770 } else { 771 return; 772 } 773 774 /* set the packetizer registers */ 775 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 776 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | 777 ((hdmi_data->pix_repet_factor << 778 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & 779 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); 780 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 781 782 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 783 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 784 785 /* Data from pixel repeater block */ 786 if (hdmi_data->pix_repet_factor > 1) { 787 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 788 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 789 } else { /* data from packetizer block */ 790 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 791 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 792 } 793 794 hdmi_modb(hdmi, vp_conf, 795 HDMI_VP_CONF_PR_EN_MASK | 796 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 797 798 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 799 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 800 801 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 802 803 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 804 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 805 HDMI_VP_CONF_PP_EN_ENABLE | 806 HDMI_VP_CONF_YCC422_EN_DISABLE; 807 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 808 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 809 HDMI_VP_CONF_PP_EN_DISABLE | 810 HDMI_VP_CONF_YCC422_EN_ENABLE; 811 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 812 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 813 HDMI_VP_CONF_PP_EN_DISABLE | 814 HDMI_VP_CONF_YCC422_EN_DISABLE; 815 } else { 816 return; 817 } 818 819 hdmi_modb(hdmi, vp_conf, 820 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 821 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 822 823 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 824 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 825 HDMI_VP_STUFF_PP_STUFFING_MASK | 826 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 827 828 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 829 HDMI_VP_CONF); 830 } 831 832 /* ----------------------------------------------------------------------------- 833 * Synopsys PHY Handling 834 */ 835 836 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 837 unsigned char bit) 838 { 839 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 840 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 841 } 842 843 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 844 { 845 u32 val; 846 847 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 848 if (msec-- == 0) 849 return false; 850 udelay(1000); 851 } 852 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 853 854 return true; 855 } 856 857 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 858 unsigned char addr) 859 { 860 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 861 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 862 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 863 HDMI_PHY_I2CM_DATAO_1_ADDR); 864 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 865 HDMI_PHY_I2CM_DATAO_0_ADDR); 866 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 867 HDMI_PHY_I2CM_OPERATION_ADDR); 868 hdmi_phy_wait_i2c_done(hdmi, 1000); 869 } 870 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); 871 872 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 873 { 874 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 875 HDMI_PHY_CONF0_PDZ_OFFSET, 876 HDMI_PHY_CONF0_PDZ_MASK); 877 } 878 879 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 880 { 881 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 882 HDMI_PHY_CONF0_ENTMDS_OFFSET, 883 HDMI_PHY_CONF0_ENTMDS_MASK); 884 } 885 886 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 887 { 888 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 889 HDMI_PHY_CONF0_SVSRET_OFFSET, 890 HDMI_PHY_CONF0_SVSRET_MASK); 891 } 892 893 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 894 { 895 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 896 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 897 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 898 } 899 900 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 901 { 902 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 903 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 904 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 905 } 906 907 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 908 { 909 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 910 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 911 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 912 } 913 914 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 915 { 916 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 917 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 918 HDMI_PHY_CONF0_SELDIPIF_MASK); 919 } 920 921 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 922 { 923 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 924 unsigned int i; 925 u16 val; 926 927 if (phy->gen == 1) { 928 dw_hdmi_phy_enable_tmds(hdmi, 0); 929 dw_hdmi_phy_enable_powerdown(hdmi, true); 930 return; 931 } 932 933 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 934 935 /* 936 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 937 * to low power mode. 938 */ 939 for (i = 0; i < 5; ++i) { 940 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 941 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 942 break; 943 944 usleep_range(1000, 2000); 945 } 946 947 if (val & HDMI_PHY_TX_PHY_LOCK) 948 dev_warn(hdmi->dev, "PHY failed to power down\n"); 949 else 950 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); 951 952 dw_hdmi_phy_gen2_pddq(hdmi, 1); 953 } 954 955 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 956 { 957 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 958 unsigned int i; 959 u8 val; 960 961 if (phy->gen == 1) { 962 dw_hdmi_phy_enable_powerdown(hdmi, false); 963 964 /* Toggle TMDS enable. */ 965 dw_hdmi_phy_enable_tmds(hdmi, 0); 966 dw_hdmi_phy_enable_tmds(hdmi, 1); 967 return 0; 968 } 969 970 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 971 dw_hdmi_phy_gen2_pddq(hdmi, 0); 972 973 /* Wait for PHY PLL lock */ 974 for (i = 0; i < 5; ++i) { 975 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 976 if (val) 977 break; 978 979 usleep_range(1000, 2000); 980 } 981 982 if (!val) { 983 dev_err(hdmi->dev, "PHY PLL failed to lock\n"); 984 return -ETIMEDOUT; 985 } 986 987 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); 988 return 0; 989 } 990 991 /* 992 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 993 * information the DWC MHL PHY has the same register layout and is thus also 994 * supported by this function. 995 */ 996 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 997 const struct dw_hdmi_plat_data *pdata, 998 unsigned long mpixelclock) 999 { 1000 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 1001 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 1002 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 1003 1004 /* PLL/MPLL Cfg - always match on final entry */ 1005 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 1006 if (mpixelclock <= mpll_config->mpixelclock) 1007 break; 1008 1009 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 1010 if (mpixelclock <= curr_ctrl->mpixelclock) 1011 break; 1012 1013 for (; phy_config->mpixelclock != ~0UL; phy_config++) 1014 if (mpixelclock <= phy_config->mpixelclock) 1015 break; 1016 1017 if (mpll_config->mpixelclock == ~0UL || 1018 curr_ctrl->mpixelclock == ~0UL || 1019 phy_config->mpixelclock == ~0UL) 1020 return -EINVAL; 1021 1022 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 1023 HDMI_3D_TX_PHY_CPCE_CTRL); 1024 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 1025 HDMI_3D_TX_PHY_GMPCTRL); 1026 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 1027 HDMI_3D_TX_PHY_CURRCTRL); 1028 1029 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 1030 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 1031 HDMI_3D_TX_PHY_MSM_CTRL); 1032 1033 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 1034 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 1035 HDMI_3D_TX_PHY_CKSYMTXCTRL); 1036 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 1037 HDMI_3D_TX_PHY_VLEVCTRL); 1038 1039 /* Override and disable clock termination. */ 1040 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 1041 HDMI_3D_TX_PHY_CKCALCTRL); 1042 1043 return 0; 1044 } 1045 1046 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 1047 { 1048 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1049 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 1050 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 1051 int ret; 1052 1053 dw_hdmi_phy_power_off(hdmi); 1054 1055 /* Leave low power consumption mode by asserting SVSRET. */ 1056 if (phy->has_svsret) 1057 dw_hdmi_phy_enable_svsret(hdmi, 1); 1058 1059 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 1060 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1061 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1062 1063 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 1064 1065 hdmi_phy_test_clear(hdmi, 1); 1066 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, 1067 HDMI_PHY_I2CM_SLAVE_ADDR); 1068 hdmi_phy_test_clear(hdmi, 0); 1069 1070 /* Write to the PHY as configured by the platform */ 1071 if (pdata->configure_phy) 1072 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 1073 else 1074 ret = phy->configure(hdmi, pdata, mpixelclock); 1075 if (ret) { 1076 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", 1077 mpixelclock); 1078 return ret; 1079 } 1080 1081 return dw_hdmi_phy_power_on(hdmi); 1082 } 1083 1084 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 1085 struct drm_display_mode *mode) 1086 { 1087 int i, ret; 1088 1089 /* HDMI Phy spec says to do the phy initialization sequence twice */ 1090 for (i = 0; i < 2; i++) { 1091 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 1092 dw_hdmi_phy_sel_interface_control(hdmi, 0); 1093 1094 ret = hdmi_phy_configure(hdmi); 1095 if (ret) 1096 return ret; 1097 } 1098 1099 return 0; 1100 } 1101 1102 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 1103 { 1104 dw_hdmi_phy_power_off(hdmi); 1105 } 1106 1107 static enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 1108 void *data) 1109 { 1110 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 1111 connector_status_connected : connector_status_disconnected; 1112 } 1113 1114 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 1115 .init = dw_hdmi_phy_init, 1116 .disable = dw_hdmi_phy_disable, 1117 .read_hpd = dw_hdmi_phy_read_hpd, 1118 }; 1119 1120 /* ----------------------------------------------------------------------------- 1121 * HDMI TX Setup 1122 */ 1123 1124 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) 1125 { 1126 u8 de; 1127 1128 if (hdmi->hdmi_data.video_mode.mdataenablepolarity) 1129 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1130 else 1131 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; 1132 1133 /* disable rx detect */ 1134 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, 1135 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 1136 1137 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); 1138 1139 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, 1140 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); 1141 } 1142 1143 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1144 { 1145 struct hdmi_avi_infoframe frame; 1146 u8 val; 1147 1148 /* Initialise info frame from DRM mode */ 1149 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 1150 1151 if (hdmi->hdmi_data.enc_out_format == YCBCR444) 1152 frame.colorspace = HDMI_COLORSPACE_YUV444; 1153 else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS) 1154 frame.colorspace = HDMI_COLORSPACE_YUV422; 1155 else 1156 frame.colorspace = HDMI_COLORSPACE_RGB; 1157 1158 /* Set up colorimetry */ 1159 if (hdmi->hdmi_data.enc_out_format == XVYCC444) { 1160 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1161 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601) 1162 frame.extended_colorimetry = 1163 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1164 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/ 1165 frame.extended_colorimetry = 1166 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1167 } else if (hdmi->hdmi_data.enc_out_format != RGB) { 1168 frame.colorimetry = hdmi->hdmi_data.colorimetry; 1169 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1170 } else { /* Carries no data */ 1171 frame.colorimetry = HDMI_COLORIMETRY_NONE; 1172 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1173 } 1174 1175 frame.scan_mode = HDMI_SCAN_MODE_NONE; 1176 1177 /* 1178 * The Designware IP uses a different byte format from standard 1179 * AVI info frames, though generally the bits are in the correct 1180 * bytes. 1181 */ 1182 1183 /* 1184 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, 1185 * scan info in bits 4,5 rather than 0,1 and active aspect present in 1186 * bit 6 rather than 4. 1187 */ 1188 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); 1189 if (frame.active_aspect & 15) 1190 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1191 if (frame.top_bar || frame.bottom_bar) 1192 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1193 if (frame.left_bar || frame.right_bar) 1194 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1195 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1196 1197 /* AVI data byte 2 differences: none */ 1198 val = ((frame.colorimetry & 0x3) << 6) | 1199 ((frame.picture_aspect & 0x3) << 4) | 1200 (frame.active_aspect & 0xf); 1201 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1202 1203 /* AVI data byte 3 differences: none */ 1204 val = ((frame.extended_colorimetry & 0x7) << 4) | 1205 ((frame.quantization_range & 0x3) << 2) | 1206 (frame.nups & 0x3); 1207 if (frame.itc) 1208 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1209 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1210 1211 /* AVI data byte 4 differences: none */ 1212 val = frame.video_code & 0x7f; 1213 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1214 1215 /* AVI Data Byte 5- set up input and output pixel repetition */ 1216 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1217 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1218 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1219 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1220 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1221 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1222 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1223 1224 /* 1225 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1226 * ycc range in bits 2,3 rather than 6,7 1227 */ 1228 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1229 (frame.content_type & 0x3); 1230 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1231 1232 /* AVI Data Bytes 6-13 */ 1233 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1234 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1235 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1236 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1237 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1238 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1239 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1240 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1241 } 1242 1243 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1244 struct drm_display_mode *mode) 1245 { 1246 struct hdmi_vendor_infoframe frame; 1247 u8 buffer[10]; 1248 ssize_t err; 1249 1250 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode); 1251 if (err < 0) 1252 /* 1253 * Going into that statement does not means vendor infoframe 1254 * fails. It just informed us that vendor infoframe is not 1255 * needed for the selected mode. Only 4k or stereoscopic 3D 1256 * mode requires vendor infoframe. So just simply return. 1257 */ 1258 return; 1259 1260 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1261 if (err < 0) { 1262 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1263 err); 1264 return; 1265 } 1266 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1267 HDMI_FC_DATAUTO0_VSD_MASK); 1268 1269 /* Set the length of HDMI vendor specific InfoFrame payload */ 1270 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1271 1272 /* Set 24bit IEEE Registration Identifier */ 1273 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1274 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1275 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1276 1277 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1278 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1279 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1280 1281 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1282 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1283 1284 /* Packet frame interpolation */ 1285 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1286 1287 /* Auto packets per frame and line spacing */ 1288 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1289 1290 /* Configures the Frame Composer On RDRB mode */ 1291 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1292 HDMI_FC_DATAUTO0_VSD_MASK); 1293 } 1294 1295 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1296 const struct drm_display_mode *mode) 1297 { 1298 u8 inv_val; 1299 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1300 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1301 unsigned int vdisplay; 1302 1303 vmode->mpixelclock = mode->clock * 1000; 1304 1305 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); 1306 1307 /* Set up HDMI_FC_INVIDCONF */ 1308 inv_val = (hdmi->hdmi_data.hdcp_enable ? 1309 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1310 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1311 1312 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1313 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1314 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1315 1316 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1317 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1318 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1319 1320 inv_val |= (vmode->mdataenablepolarity ? 1321 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1322 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1323 1324 if (hdmi->vic == 39) 1325 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1326 else 1327 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1328 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1329 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1330 1331 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1332 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1333 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1334 1335 inv_val |= hdmi->sink_is_hdmi ? 1336 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1337 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1338 1339 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1340 1341 vdisplay = mode->vdisplay; 1342 vblank = mode->vtotal - mode->vdisplay; 1343 v_de_vs = mode->vsync_start - mode->vdisplay; 1344 vsync_len = mode->vsync_end - mode->vsync_start; 1345 1346 /* 1347 * When we're setting an interlaced mode, we need 1348 * to adjust the vertical timing to suit. 1349 */ 1350 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1351 vdisplay /= 2; 1352 vblank /= 2; 1353 v_de_vs /= 2; 1354 vsync_len /= 2; 1355 } 1356 1357 /* Set up horizontal active pixel width */ 1358 hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1); 1359 hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0); 1360 1361 /* Set up vertical active lines */ 1362 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1363 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1364 1365 /* Set up horizontal blanking pixel region width */ 1366 hblank = mode->htotal - mode->hdisplay; 1367 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 1368 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 1369 1370 /* Set up vertical blanking pixel region width */ 1371 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 1372 1373 /* Set up HSYNC active edge delay width (in pixel clks) */ 1374 h_de_hs = mode->hsync_start - mode->hdisplay; 1375 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 1376 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 1377 1378 /* Set up VSYNC active edge delay (in lines) */ 1379 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 1380 1381 /* Set up HSYNC active pulse width (in pixel clks) */ 1382 hsync_len = mode->hsync_end - mode->hsync_start; 1383 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 1384 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 1385 1386 /* Set up VSYNC active edge delay (in lines) */ 1387 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 1388 } 1389 1390 /* HDMI Initialization Step B.4 */ 1391 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 1392 { 1393 u8 clkdis; 1394 1395 /* control period minimum duration */ 1396 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 1397 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 1398 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 1399 1400 /* Set to fill TMDS data channels */ 1401 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 1402 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 1403 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 1404 1405 /* Enable pixel clock and tmds data path */ 1406 clkdis = 0x7F; 1407 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 1408 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1409 1410 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1411 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1412 1413 /* Enable csc path */ 1414 if (is_color_space_conversion(hdmi)) { 1415 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 1416 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1417 } 1418 1419 /* Enable color space conversion if needed */ 1420 if (is_color_space_conversion(hdmi)) 1421 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 1422 HDMI_MC_FLOWCTRL); 1423 else 1424 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 1425 HDMI_MC_FLOWCTRL); 1426 } 1427 1428 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi) 1429 { 1430 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS); 1431 } 1432 1433 /* Workaround to clear the overflow condition */ 1434 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 1435 { 1436 unsigned int count; 1437 unsigned int i; 1438 u8 val; 1439 1440 /* 1441 * Under some circumstances the Frame Composer arithmetic unit can miss 1442 * an FC register write due to being busy processing the previous one. 1443 * The issue can be worked around by issuing a TMDS software reset and 1444 * then write one of the FC registers several times. 1445 * 1446 * The number of iterations matters and depends on the HDMI TX revision 1447 * (and possibly on the platform). So far only i.MX6Q (v1.30a) and 1448 * i.MX6DL (v1.31a) have been identified as needing the workaround, with 1449 * 4 and 1 iterations respectively. 1450 */ 1451 1452 switch (hdmi->version) { 1453 case 0x130a: 1454 count = 4; 1455 break; 1456 case 0x131a: 1457 count = 1; 1458 break; 1459 default: 1460 return; 1461 } 1462 1463 /* TMDS software reset */ 1464 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 1465 1466 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 1467 for (i = 0; i < count; i++) 1468 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 1469 } 1470 1471 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi) 1472 { 1473 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2); 1474 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2); 1475 } 1476 1477 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 1478 { 1479 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 1480 HDMI_IH_MUTE_FC_STAT2); 1481 } 1482 1483 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1484 { 1485 int ret; 1486 1487 hdmi_disable_overflow_interrupts(hdmi); 1488 1489 hdmi->vic = drm_match_cea_mode(mode); 1490 1491 if (!hdmi->vic) { 1492 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); 1493 } else { 1494 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); 1495 } 1496 1497 if ((hdmi->vic == 6) || (hdmi->vic == 7) || 1498 (hdmi->vic == 21) || (hdmi->vic == 22) || 1499 (hdmi->vic == 2) || (hdmi->vic == 3) || 1500 (hdmi->vic == 17) || (hdmi->vic == 18)) 1501 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601; 1502 else 1503 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709; 1504 1505 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 1506 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 1507 1508 /* TODO: Get input format from IPU (via FB driver interface) */ 1509 hdmi->hdmi_data.enc_in_format = RGB; 1510 1511 hdmi->hdmi_data.enc_out_format = RGB; 1512 1513 hdmi->hdmi_data.enc_color_depth = 8; 1514 hdmi->hdmi_data.pix_repet_factor = 0; 1515 hdmi->hdmi_data.hdcp_enable = 0; 1516 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 1517 1518 /* HDMI Initialization Step B.1 */ 1519 hdmi_av_composer(hdmi, mode); 1520 1521 /* HDMI Initializateion Step B.2 */ 1522 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode); 1523 if (ret) 1524 return ret; 1525 hdmi->phy.enabled = true; 1526 1527 /* HDMI Initialization Step B.3 */ 1528 dw_hdmi_enable_video_path(hdmi); 1529 1530 if (hdmi->sink_has_audio) { 1531 dev_dbg(hdmi->dev, "sink has audio support\n"); 1532 1533 /* HDMI Initialization Step E - Configure audio */ 1534 hdmi_clk_regenerator_update_pixel_clock(hdmi); 1535 hdmi_enable_audio_clk(hdmi); 1536 } 1537 1538 /* not for DVI mode */ 1539 if (hdmi->sink_is_hdmi) { 1540 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); 1541 1542 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 1543 hdmi_config_AVI(hdmi, mode); 1544 hdmi_config_vendor_specific_infoframe(hdmi, mode); 1545 } else { 1546 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); 1547 } 1548 1549 hdmi_video_packetize(hdmi); 1550 hdmi_video_csc(hdmi); 1551 hdmi_video_sample(hdmi); 1552 hdmi_tx_hdcp_config(hdmi); 1553 1554 dw_hdmi_clear_overflow(hdmi); 1555 if (hdmi->cable_plugin && hdmi->sink_is_hdmi) 1556 hdmi_enable_overflow_interrupts(hdmi); 1557 1558 return 0; 1559 } 1560 1561 /* Wait until we are registered to enable interrupts */ 1562 static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi) 1563 { 1564 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, 1565 HDMI_PHY_I2CM_INT_ADDR); 1566 1567 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | 1568 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, 1569 HDMI_PHY_I2CM_CTLINT_ADDR); 1570 1571 /* enable cable hot plug irq */ 1572 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1573 1574 /* Clear Hotplug interrupts */ 1575 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1576 HDMI_IH_PHY_STAT0); 1577 1578 return 0; 1579 } 1580 1581 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) 1582 { 1583 u8 ih_mute; 1584 1585 /* 1586 * Boot up defaults are: 1587 * HDMI_IH_MUTE = 0x03 (disabled) 1588 * HDMI_IH_MUTE_* = 0x00 (enabled) 1589 * 1590 * Disable top level interrupt bits in HDMI block 1591 */ 1592 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | 1593 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 1594 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; 1595 1596 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 1597 1598 /* by default mask all interrupts */ 1599 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); 1600 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 1601 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 1602 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 1603 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); 1604 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); 1605 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); 1606 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); 1607 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); 1608 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); 1609 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); 1610 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); 1611 hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK); 1612 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); 1613 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); 1614 1615 /* Disable interrupts in the IH_MUTE_* registers */ 1616 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 1617 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 1618 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 1619 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 1620 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); 1621 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 1622 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 1623 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 1624 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 1625 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 1626 1627 /* Enable top level interrupt bits in HDMI block */ 1628 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 1629 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); 1630 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 1631 } 1632 1633 static void dw_hdmi_poweron(struct dw_hdmi *hdmi) 1634 { 1635 hdmi->bridge_is_on = true; 1636 dw_hdmi_setup(hdmi, &hdmi->previous_mode); 1637 } 1638 1639 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) 1640 { 1641 if (hdmi->phy.enabled) { 1642 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 1643 hdmi->phy.enabled = false; 1644 } 1645 1646 hdmi->bridge_is_on = false; 1647 } 1648 1649 static void dw_hdmi_update_power(struct dw_hdmi *hdmi) 1650 { 1651 int force = hdmi->force; 1652 1653 if (hdmi->disabled) { 1654 force = DRM_FORCE_OFF; 1655 } else if (force == DRM_FORCE_UNSPECIFIED) { 1656 if (hdmi->rxsense) 1657 force = DRM_FORCE_ON; 1658 else 1659 force = DRM_FORCE_OFF; 1660 } 1661 1662 if (force == DRM_FORCE_OFF) { 1663 if (hdmi->bridge_is_on) 1664 dw_hdmi_poweroff(hdmi); 1665 } else { 1666 if (!hdmi->bridge_is_on) 1667 dw_hdmi_poweron(hdmi); 1668 } 1669 } 1670 1671 /* 1672 * Adjust the detection of RXSENSE according to whether we have a forced 1673 * connection mode enabled, or whether we have been disabled. There is 1674 * no point processing RXSENSE interrupts if we have a forced connection 1675 * state, or DRM has us disabled. 1676 * 1677 * We also disable rxsense interrupts when we think we're disconnected 1678 * to avoid floating TDMS signals giving false rxsense interrupts. 1679 * 1680 * Note: we still need to listen for HPD interrupts even when DRM has us 1681 * disabled so that we can detect a connect event. 1682 */ 1683 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) 1684 { 1685 u8 old_mask = hdmi->phy_mask; 1686 1687 if (hdmi->force || hdmi->disabled || !hdmi->rxsense) 1688 hdmi->phy_mask |= HDMI_PHY_RX_SENSE; 1689 else 1690 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; 1691 1692 if (old_mask != hdmi->phy_mask) 1693 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1694 } 1695 1696 static enum drm_connector_status 1697 dw_hdmi_connector_detect(struct drm_connector *connector, bool force) 1698 { 1699 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 1700 connector); 1701 1702 mutex_lock(&hdmi->mutex); 1703 hdmi->force = DRM_FORCE_UNSPECIFIED; 1704 dw_hdmi_update_power(hdmi); 1705 dw_hdmi_update_phy_mask(hdmi); 1706 mutex_unlock(&hdmi->mutex); 1707 1708 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 1709 } 1710 1711 static int dw_hdmi_connector_get_modes(struct drm_connector *connector) 1712 { 1713 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 1714 connector); 1715 struct edid *edid; 1716 int ret = 0; 1717 1718 if (!hdmi->ddc) 1719 return 0; 1720 1721 edid = drm_get_edid(connector, hdmi->ddc); 1722 if (edid) { 1723 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", 1724 edid->width_cm, edid->height_cm); 1725 1726 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); 1727 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 1728 drm_mode_connector_update_edid_property(connector, edid); 1729 ret = drm_add_edid_modes(connector, edid); 1730 /* Store the ELD */ 1731 drm_edid_to_eld(connector, edid); 1732 kfree(edid); 1733 } else { 1734 dev_dbg(hdmi->dev, "failed to get edid\n"); 1735 } 1736 1737 return ret; 1738 } 1739 1740 static enum drm_mode_status 1741 dw_hdmi_connector_mode_valid(struct drm_connector *connector, 1742 struct drm_display_mode *mode) 1743 { 1744 struct dw_hdmi *hdmi = container_of(connector, 1745 struct dw_hdmi, connector); 1746 enum drm_mode_status mode_status = MODE_OK; 1747 1748 /* We don't support double-clocked modes */ 1749 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1750 return MODE_BAD; 1751 1752 if (hdmi->plat_data->mode_valid) 1753 mode_status = hdmi->plat_data->mode_valid(connector, mode); 1754 1755 return mode_status; 1756 } 1757 1758 static void dw_hdmi_connector_force(struct drm_connector *connector) 1759 { 1760 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 1761 connector); 1762 1763 mutex_lock(&hdmi->mutex); 1764 hdmi->force = connector->force; 1765 dw_hdmi_update_power(hdmi); 1766 dw_hdmi_update_phy_mask(hdmi); 1767 mutex_unlock(&hdmi->mutex); 1768 } 1769 1770 static const struct drm_connector_funcs dw_hdmi_connector_funcs = { 1771 .dpms = drm_atomic_helper_connector_dpms, 1772 .fill_modes = drm_helper_probe_single_connector_modes, 1773 .detect = dw_hdmi_connector_detect, 1774 .destroy = drm_connector_cleanup, 1775 .force = dw_hdmi_connector_force, 1776 .reset = drm_atomic_helper_connector_reset, 1777 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1778 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1779 }; 1780 1781 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { 1782 .get_modes = dw_hdmi_connector_get_modes, 1783 .mode_valid = dw_hdmi_connector_mode_valid, 1784 .best_encoder = drm_atomic_helper_best_encoder, 1785 }; 1786 1787 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge) 1788 { 1789 struct dw_hdmi *hdmi = bridge->driver_private; 1790 struct drm_encoder *encoder = bridge->encoder; 1791 struct drm_connector *connector = &hdmi->connector; 1792 1793 connector->interlace_allowed = 1; 1794 connector->polled = DRM_CONNECTOR_POLL_HPD; 1795 1796 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); 1797 1798 drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs, 1799 DRM_MODE_CONNECTOR_HDMIA); 1800 1801 drm_mode_connector_attach_encoder(connector, encoder); 1802 1803 return 0; 1804 } 1805 1806 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, 1807 struct drm_display_mode *orig_mode, 1808 struct drm_display_mode *mode) 1809 { 1810 struct dw_hdmi *hdmi = bridge->driver_private; 1811 1812 mutex_lock(&hdmi->mutex); 1813 1814 /* Store the display mode for plugin/DKMS poweron events */ 1815 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 1816 1817 mutex_unlock(&hdmi->mutex); 1818 } 1819 1820 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge) 1821 { 1822 struct dw_hdmi *hdmi = bridge->driver_private; 1823 1824 mutex_lock(&hdmi->mutex); 1825 hdmi->disabled = true; 1826 dw_hdmi_update_power(hdmi); 1827 dw_hdmi_update_phy_mask(hdmi); 1828 mutex_unlock(&hdmi->mutex); 1829 } 1830 1831 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge) 1832 { 1833 struct dw_hdmi *hdmi = bridge->driver_private; 1834 1835 mutex_lock(&hdmi->mutex); 1836 hdmi->disabled = false; 1837 dw_hdmi_update_power(hdmi); 1838 dw_hdmi_update_phy_mask(hdmi); 1839 mutex_unlock(&hdmi->mutex); 1840 } 1841 1842 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { 1843 .attach = dw_hdmi_bridge_attach, 1844 .enable = dw_hdmi_bridge_enable, 1845 .disable = dw_hdmi_bridge_disable, 1846 .mode_set = dw_hdmi_bridge_mode_set, 1847 }; 1848 1849 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) 1850 { 1851 struct dw_hdmi_i2c *i2c = hdmi->i2c; 1852 unsigned int stat; 1853 1854 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 1855 if (!stat) 1856 return IRQ_NONE; 1857 1858 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0); 1859 1860 i2c->stat = stat; 1861 1862 complete(&i2c->cmp); 1863 1864 return IRQ_HANDLED; 1865 } 1866 1867 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) 1868 { 1869 struct dw_hdmi *hdmi = dev_id; 1870 u8 intr_stat; 1871 irqreturn_t ret = IRQ_NONE; 1872 1873 if (hdmi->i2c) 1874 ret = dw_hdmi_i2c_irq(hdmi); 1875 1876 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 1877 if (intr_stat) { 1878 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 1879 return IRQ_WAKE_THREAD; 1880 } 1881 1882 return ret; 1883 } 1884 1885 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) 1886 { 1887 struct dw_hdmi *hdmi = dev_id; 1888 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; 1889 1890 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 1891 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); 1892 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); 1893 1894 phy_pol_mask = 0; 1895 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) 1896 phy_pol_mask |= HDMI_PHY_HPD; 1897 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) 1898 phy_pol_mask |= HDMI_PHY_RX_SENSE0; 1899 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) 1900 phy_pol_mask |= HDMI_PHY_RX_SENSE1; 1901 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) 1902 phy_pol_mask |= HDMI_PHY_RX_SENSE2; 1903 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) 1904 phy_pol_mask |= HDMI_PHY_RX_SENSE3; 1905 1906 if (phy_pol_mask) 1907 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); 1908 1909 /* 1910 * RX sense tells us whether the TDMS transmitters are detecting 1911 * load - in other words, there's something listening on the 1912 * other end of the link. Use this to decide whether we should 1913 * power on the phy as HPD may be toggled by the sink to merely 1914 * ask the source to re-read the EDID. 1915 */ 1916 if (intr_stat & 1917 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { 1918 mutex_lock(&hdmi->mutex); 1919 if (!hdmi->disabled && !hdmi->force) { 1920 /* 1921 * If the RX sense status indicates we're disconnected, 1922 * clear the software rxsense status. 1923 */ 1924 if (!(phy_stat & HDMI_PHY_RX_SENSE)) 1925 hdmi->rxsense = false; 1926 1927 /* 1928 * Only set the software rxsense status when both 1929 * rxsense and hpd indicates we're connected. 1930 * This avoids what seems to be bad behaviour in 1931 * at least iMX6S versions of the phy. 1932 */ 1933 if (phy_stat & HDMI_PHY_HPD) 1934 hdmi->rxsense = true; 1935 1936 dw_hdmi_update_power(hdmi); 1937 dw_hdmi_update_phy_mask(hdmi); 1938 } 1939 mutex_unlock(&hdmi->mutex); 1940 } 1941 1942 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { 1943 dev_dbg(hdmi->dev, "EVENT=%s\n", 1944 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout"); 1945 if (hdmi->bridge.dev) 1946 drm_helper_hpd_irq_event(hdmi->bridge.dev); 1947 } 1948 1949 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); 1950 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 1951 HDMI_IH_MUTE_PHY_STAT0); 1952 1953 return IRQ_HANDLED; 1954 } 1955 1956 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 1957 { 1958 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 1959 .name = "DWC HDMI TX PHY", 1960 .gen = 1, 1961 }, { 1962 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 1963 .name = "DWC MHL PHY + HEAC PHY", 1964 .gen = 2, 1965 .has_svsret = true, 1966 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 1967 }, { 1968 .type = DW_HDMI_PHY_DWC_MHL_PHY, 1969 .name = "DWC MHL PHY", 1970 .gen = 2, 1971 .has_svsret = true, 1972 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 1973 }, { 1974 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 1975 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 1976 .gen = 2, 1977 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 1978 }, { 1979 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 1980 .name = "DWC HDMI 3D TX PHY", 1981 .gen = 2, 1982 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 1983 }, { 1984 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 1985 .name = "DWC HDMI 2.0 TX PHY", 1986 .gen = 2, 1987 .has_svsret = true, 1988 }, { 1989 .type = DW_HDMI_PHY_VENDOR_PHY, 1990 .name = "Vendor PHY", 1991 } 1992 }; 1993 1994 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 1995 { 1996 unsigned int i; 1997 u8 phy_type; 1998 1999 phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID); 2000 2001 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { 2002 /* Vendor PHYs require support from the glue layer. */ 2003 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 2004 dev_err(hdmi->dev, 2005 "Vendor HDMI PHY not supported by glue layer\n"); 2006 return -ENODEV; 2007 } 2008 2009 hdmi->phy.ops = hdmi->plat_data->phy_ops; 2010 hdmi->phy.data = hdmi->plat_data->phy_data; 2011 hdmi->phy.name = hdmi->plat_data->phy_name; 2012 return 0; 2013 } 2014 2015 /* Synopsys PHYs are handled internally. */ 2016 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 2017 if (dw_hdmi_phys[i].type == phy_type) { 2018 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 2019 hdmi->phy.name = dw_hdmi_phys[i].name; 2020 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 2021 2022 if (!dw_hdmi_phys[i].configure && 2023 !hdmi->plat_data->configure_phy) { 2024 dev_err(hdmi->dev, "%s requires platform support\n", 2025 hdmi->phy.name); 2026 return -ENODEV; 2027 } 2028 2029 return 0; 2030 } 2031 } 2032 2033 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); 2034 return -ENODEV; 2035 } 2036 2037 static const struct regmap_config hdmi_regmap_8bit_config = { 2038 .reg_bits = 32, 2039 .val_bits = 8, 2040 .reg_stride = 1, 2041 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, 2042 }; 2043 2044 static const struct regmap_config hdmi_regmap_32bit_config = { 2045 .reg_bits = 32, 2046 .val_bits = 32, 2047 .reg_stride = 4, 2048 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, 2049 }; 2050 2051 static struct dw_hdmi * 2052 __dw_hdmi_probe(struct platform_device *pdev, 2053 const struct dw_hdmi_plat_data *plat_data) 2054 { 2055 struct device *dev = &pdev->dev; 2056 struct device_node *np = dev->of_node; 2057 struct platform_device_info pdevinfo; 2058 struct device_node *ddc_node; 2059 struct dw_hdmi *hdmi; 2060 struct resource *iores = NULL; 2061 int irq; 2062 int ret; 2063 u32 val = 1; 2064 u8 prod_id0; 2065 u8 prod_id1; 2066 u8 config0; 2067 u8 config3; 2068 2069 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 2070 if (!hdmi) 2071 return ERR_PTR(-ENOMEM); 2072 2073 hdmi->plat_data = plat_data; 2074 hdmi->dev = dev; 2075 hdmi->sample_rate = 48000; 2076 hdmi->disabled = true; 2077 hdmi->rxsense = true; 2078 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); 2079 2080 mutex_init(&hdmi->mutex); 2081 mutex_init(&hdmi->audio_mutex); 2082 spin_lock_init(&hdmi->audio_lock); 2083 2084 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 2085 if (ddc_node) { 2086 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); 2087 of_node_put(ddc_node); 2088 if (!hdmi->ddc) { 2089 dev_dbg(hdmi->dev, "failed to read ddc node\n"); 2090 return ERR_PTR(-EPROBE_DEFER); 2091 } 2092 2093 } else { 2094 dev_dbg(hdmi->dev, "no ddc property found\n"); 2095 } 2096 2097 if (!plat_data->regm) { 2098 const struct regmap_config *reg_config; 2099 2100 of_property_read_u32(np, "reg-io-width", &val); 2101 switch (val) { 2102 case 4: 2103 reg_config = &hdmi_regmap_32bit_config; 2104 hdmi->reg_shift = 2; 2105 break; 2106 case 1: 2107 reg_config = &hdmi_regmap_8bit_config; 2108 break; 2109 default: 2110 dev_err(dev, "reg-io-width must be 1 or 4\n"); 2111 return ERR_PTR(-EINVAL); 2112 } 2113 2114 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2115 hdmi->regs = devm_ioremap_resource(dev, iores); 2116 if (IS_ERR(hdmi->regs)) { 2117 ret = PTR_ERR(hdmi->regs); 2118 goto err_res; 2119 } 2120 2121 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); 2122 if (IS_ERR(hdmi->regm)) { 2123 dev_err(dev, "Failed to configure regmap\n"); 2124 ret = PTR_ERR(hdmi->regm); 2125 goto err_res; 2126 } 2127 } else { 2128 hdmi->regm = plat_data->regm; 2129 } 2130 2131 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); 2132 if (IS_ERR(hdmi->isfr_clk)) { 2133 ret = PTR_ERR(hdmi->isfr_clk); 2134 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); 2135 goto err_res; 2136 } 2137 2138 ret = clk_prepare_enable(hdmi->isfr_clk); 2139 if (ret) { 2140 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret); 2141 goto err_res; 2142 } 2143 2144 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); 2145 if (IS_ERR(hdmi->iahb_clk)) { 2146 ret = PTR_ERR(hdmi->iahb_clk); 2147 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); 2148 goto err_isfr; 2149 } 2150 2151 ret = clk_prepare_enable(hdmi->iahb_clk); 2152 if (ret) { 2153 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret); 2154 goto err_isfr; 2155 } 2156 2157 /* Product and revision IDs */ 2158 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 2159 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 2160 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); 2161 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); 2162 2163 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || 2164 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { 2165 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", 2166 hdmi->version, prod_id0, prod_id1); 2167 ret = -ENODEV; 2168 goto err_iahb; 2169 } 2170 2171 ret = dw_hdmi_detect_phy(hdmi); 2172 if (ret < 0) 2173 goto err_iahb; 2174 2175 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", 2176 hdmi->version >> 12, hdmi->version & 0xfff, 2177 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", 2178 hdmi->phy.name); 2179 2180 initialize_hdmi_ih_mutes(hdmi); 2181 2182 irq = platform_get_irq(pdev, 0); 2183 if (irq < 0) { 2184 ret = irq; 2185 goto err_iahb; 2186 } 2187 2188 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, 2189 dw_hdmi_irq, IRQF_SHARED, 2190 dev_name(dev), hdmi); 2191 if (ret) 2192 goto err_iahb; 2193 2194 /* 2195 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator 2196 * N and cts values before enabling phy 2197 */ 2198 hdmi_init_clk_regenerator(hdmi); 2199 2200 /* If DDC bus is not specified, try to register HDMI I2C bus */ 2201 if (!hdmi->ddc) { 2202 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); 2203 if (IS_ERR(hdmi->ddc)) 2204 hdmi->ddc = NULL; 2205 } 2206 2207 /* 2208 * Configure registers related to HDMI interrupt 2209 * generation before registering IRQ. 2210 */ 2211 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); 2212 2213 /* Clear Hotplug interrupts */ 2214 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 2215 HDMI_IH_PHY_STAT0); 2216 2217 hdmi->bridge.driver_private = hdmi; 2218 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; 2219 #ifdef CONFIG_OF 2220 hdmi->bridge.of_node = pdev->dev.of_node; 2221 #endif 2222 2223 ret = dw_hdmi_fb_registered(hdmi); 2224 if (ret) 2225 goto err_iahb; 2226 2227 /* Unmute interrupts */ 2228 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 2229 HDMI_IH_MUTE_PHY_STAT0); 2230 2231 memset(&pdevinfo, 0, sizeof(pdevinfo)); 2232 pdevinfo.parent = dev; 2233 pdevinfo.id = PLATFORM_DEVID_AUTO; 2234 2235 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); 2236 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 2237 2238 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { 2239 struct dw_hdmi_audio_data audio; 2240 2241 audio.phys = iores->start; 2242 audio.base = hdmi->regs; 2243 audio.irq = irq; 2244 audio.hdmi = hdmi; 2245 audio.eld = hdmi->connector.eld; 2246 2247 pdevinfo.name = "dw-hdmi-ahb-audio"; 2248 pdevinfo.data = &audio; 2249 pdevinfo.size_data = sizeof(audio); 2250 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2251 hdmi->audio = platform_device_register_full(&pdevinfo); 2252 } else if (config0 & HDMI_CONFIG0_I2S) { 2253 struct dw_hdmi_i2s_audio_data audio; 2254 2255 audio.hdmi = hdmi; 2256 audio.write = hdmi_writeb; 2257 audio.read = hdmi_readb; 2258 2259 pdevinfo.name = "dw-hdmi-i2s-audio"; 2260 pdevinfo.data = &audio; 2261 pdevinfo.size_data = sizeof(audio); 2262 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2263 hdmi->audio = platform_device_register_full(&pdevinfo); 2264 } 2265 2266 /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */ 2267 if (hdmi->i2c) 2268 dw_hdmi_i2c_init(hdmi); 2269 2270 platform_set_drvdata(pdev, hdmi); 2271 2272 return hdmi; 2273 2274 err_iahb: 2275 if (hdmi->i2c) { 2276 i2c_del_adapter(&hdmi->i2c->adap); 2277 hdmi->ddc = NULL; 2278 } 2279 2280 clk_disable_unprepare(hdmi->iahb_clk); 2281 err_isfr: 2282 clk_disable_unprepare(hdmi->isfr_clk); 2283 err_res: 2284 i2c_put_adapter(hdmi->ddc); 2285 2286 return ERR_PTR(ret); 2287 } 2288 2289 static void __dw_hdmi_remove(struct dw_hdmi *hdmi) 2290 { 2291 if (hdmi->audio && !IS_ERR(hdmi->audio)) 2292 platform_device_unregister(hdmi->audio); 2293 2294 /* Disable all interrupts */ 2295 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2296 2297 clk_disable_unprepare(hdmi->iahb_clk); 2298 clk_disable_unprepare(hdmi->isfr_clk); 2299 2300 if (hdmi->i2c) 2301 i2c_del_adapter(&hdmi->i2c->adap); 2302 else 2303 i2c_put_adapter(hdmi->ddc); 2304 } 2305 2306 /* ----------------------------------------------------------------------------- 2307 * Probe/remove API, used from platforms based on the DRM bridge API. 2308 */ 2309 int dw_hdmi_probe(struct platform_device *pdev, 2310 const struct dw_hdmi_plat_data *plat_data) 2311 { 2312 struct dw_hdmi *hdmi; 2313 int ret; 2314 2315 hdmi = __dw_hdmi_probe(pdev, plat_data); 2316 if (IS_ERR(hdmi)) 2317 return PTR_ERR(hdmi); 2318 2319 ret = drm_bridge_add(&hdmi->bridge); 2320 if (ret < 0) { 2321 __dw_hdmi_remove(hdmi); 2322 return ret; 2323 } 2324 2325 return 0; 2326 } 2327 EXPORT_SYMBOL_GPL(dw_hdmi_probe); 2328 2329 void dw_hdmi_remove(struct platform_device *pdev) 2330 { 2331 struct dw_hdmi *hdmi = platform_get_drvdata(pdev); 2332 2333 drm_bridge_remove(&hdmi->bridge); 2334 2335 __dw_hdmi_remove(hdmi); 2336 } 2337 EXPORT_SYMBOL_GPL(dw_hdmi_remove); 2338 2339 /* ----------------------------------------------------------------------------- 2340 * Bind/unbind API, used from platforms based on the component framework. 2341 */ 2342 int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder, 2343 const struct dw_hdmi_plat_data *plat_data) 2344 { 2345 struct dw_hdmi *hdmi; 2346 int ret; 2347 2348 hdmi = __dw_hdmi_probe(pdev, plat_data); 2349 if (IS_ERR(hdmi)) 2350 return PTR_ERR(hdmi); 2351 2352 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL); 2353 if (ret) { 2354 dw_hdmi_remove(pdev); 2355 DRM_ERROR("Failed to initialize bridge with drm\n"); 2356 return ret; 2357 } 2358 2359 return 0; 2360 } 2361 EXPORT_SYMBOL_GPL(dw_hdmi_bind); 2362 2363 void dw_hdmi_unbind(struct device *dev) 2364 { 2365 struct dw_hdmi *hdmi = dev_get_drvdata(dev); 2366 2367 __dw_hdmi_remove(hdmi); 2368 } 2369 EXPORT_SYMBOL_GPL(dw_hdmi_unbind); 2370 2371 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 2372 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); 2373 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); 2374 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>"); 2375 MODULE_DESCRIPTION("DW HDMI transmitter driver"); 2376 MODULE_LICENSE("GPL"); 2377 MODULE_ALIAS("platform:dw-hdmi"); 2378