1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * DesignWare High-Definition Multimedia Interface (HDMI) driver
4  *
5  * Copyright (C) 2013-2015 Mentor Graphics Inc.
6  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
7  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
8  */
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/hdmi.h>
13 #include <linux/irq.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/of_device.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/regmap.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/spinlock.h>
21 
22 #include <media/cec-notifier.h>
23 
24 #include <uapi/linux/media-bus-format.h>
25 #include <uapi/linux/videodev2.h>
26 
27 #include <drm/bridge/dw_hdmi.h>
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_bridge.h>
31 #include <drm/drm_edid.h>
32 #include <drm/drm_of.h>
33 #include <drm/drm_print.h>
34 #include <drm/drm_probe_helper.h>
35 #include <drm/drm_scdc_helper.h>
36 
37 #include "dw-hdmi-audio.h"
38 #include "dw-hdmi-cec.h"
39 #include "dw-hdmi.h"
40 
41 #define DDC_CI_ADDR		0x37
42 #define DDC_SEGMENT_ADDR	0x30
43 
44 #define HDMI_EDID_LEN		512
45 
46 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
47 #define SCDC_MIN_SOURCE_VERSION	0x1
48 
49 #define HDMI14_MAX_TMDSCLK	340000000
50 
51 enum hdmi_datamap {
52 	RGB444_8B = 0x01,
53 	RGB444_10B = 0x03,
54 	RGB444_12B = 0x05,
55 	RGB444_16B = 0x07,
56 	YCbCr444_8B = 0x09,
57 	YCbCr444_10B = 0x0B,
58 	YCbCr444_12B = 0x0D,
59 	YCbCr444_16B = 0x0F,
60 	YCbCr422_8B = 0x16,
61 	YCbCr422_10B = 0x14,
62 	YCbCr422_12B = 0x12,
63 };
64 
65 static const u16 csc_coeff_default[3][4] = {
66 	{ 0x2000, 0x0000, 0x0000, 0x0000 },
67 	{ 0x0000, 0x2000, 0x0000, 0x0000 },
68 	{ 0x0000, 0x0000, 0x2000, 0x0000 }
69 };
70 
71 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
72 	{ 0x2000, 0x6926, 0x74fd, 0x010e },
73 	{ 0x2000, 0x2cdd, 0x0000, 0x7e9a },
74 	{ 0x2000, 0x0000, 0x38b4, 0x7e3b }
75 };
76 
77 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
78 	{ 0x2000, 0x7106, 0x7a02, 0x00a7 },
79 	{ 0x2000, 0x3264, 0x0000, 0x7e6d },
80 	{ 0x2000, 0x0000, 0x3b61, 0x7e25 }
81 };
82 
83 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
84 	{ 0x2591, 0x1322, 0x074b, 0x0000 },
85 	{ 0x6535, 0x2000, 0x7acc, 0x0200 },
86 	{ 0x6acd, 0x7534, 0x2000, 0x0200 }
87 };
88 
89 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
90 	{ 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
91 	{ 0x62f0, 0x2000, 0x7d11, 0x0200 },
92 	{ 0x6756, 0x78ab, 0x2000, 0x0200 }
93 };
94 
95 static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = {
96 	{ 0x1b7c, 0x0000, 0x0000, 0x0020 },
97 	{ 0x0000, 0x1b7c, 0x0000, 0x0020 },
98 	{ 0x0000, 0x0000, 0x1b7c, 0x0020 }
99 };
100 
101 struct hdmi_vmode {
102 	bool mdataenablepolarity;
103 
104 	unsigned int mpixelclock;
105 	unsigned int mpixelrepetitioninput;
106 	unsigned int mpixelrepetitionoutput;
107 	unsigned int mtmdsclock;
108 };
109 
110 struct hdmi_data_info {
111 	unsigned int enc_in_bus_format;
112 	unsigned int enc_out_bus_format;
113 	unsigned int enc_in_encoding;
114 	unsigned int enc_out_encoding;
115 	unsigned int pix_repet_factor;
116 	unsigned int hdcp_enable;
117 	struct hdmi_vmode video_mode;
118 	bool rgb_limited_range;
119 };
120 
121 struct dw_hdmi_i2c {
122 	struct i2c_adapter	adap;
123 
124 	struct mutex		lock;	/* used to serialize data transfers */
125 	struct completion	cmp;
126 	u8			stat;
127 
128 	u8			slave_reg;
129 	bool			is_regaddr;
130 	bool			is_segment;
131 };
132 
133 struct dw_hdmi_phy_data {
134 	enum dw_hdmi_phy_type type;
135 	const char *name;
136 	unsigned int gen;
137 	bool has_svsret;
138 	int (*configure)(struct dw_hdmi *hdmi,
139 			 const struct dw_hdmi_plat_data *pdata,
140 			 unsigned long mpixelclock);
141 };
142 
143 struct dw_hdmi {
144 	struct drm_connector connector;
145 	struct drm_bridge bridge;
146 
147 	unsigned int version;
148 
149 	struct platform_device *audio;
150 	struct platform_device *cec;
151 	struct device *dev;
152 	struct clk *isfr_clk;
153 	struct clk *iahb_clk;
154 	struct clk *cec_clk;
155 	struct dw_hdmi_i2c *i2c;
156 
157 	struct hdmi_data_info hdmi_data;
158 	const struct dw_hdmi_plat_data *plat_data;
159 
160 	int vic;
161 
162 	u8 edid[HDMI_EDID_LEN];
163 
164 	struct {
165 		const struct dw_hdmi_phy_ops *ops;
166 		const char *name;
167 		void *data;
168 		bool enabled;
169 	} phy;
170 
171 	struct drm_display_mode previous_mode;
172 
173 	struct i2c_adapter *ddc;
174 	void __iomem *regs;
175 	bool sink_is_hdmi;
176 	bool sink_has_audio;
177 
178 	struct pinctrl *pinctrl;
179 	struct pinctrl_state *default_state;
180 	struct pinctrl_state *unwedge_state;
181 
182 	struct mutex mutex;		/* for state below and previous_mode */
183 	enum drm_connector_force force;	/* mutex-protected force state */
184 	struct drm_connector *curr_conn;/* current connector (only valid when !disabled) */
185 	bool disabled;			/* DRM has disabled our bridge */
186 	bool bridge_is_on;		/* indicates the bridge is on */
187 	bool rxsense;			/* rxsense state */
188 	u8 phy_mask;			/* desired phy int mask settings */
189 	u8 mc_clkdis;			/* clock disable register */
190 
191 	spinlock_t audio_lock;
192 	struct mutex audio_mutex;
193 	unsigned int sample_rate;
194 	unsigned int audio_cts;
195 	unsigned int audio_n;
196 	bool audio_enable;
197 
198 	unsigned int reg_shift;
199 	struct regmap *regm;
200 	void (*enable_audio)(struct dw_hdmi *hdmi);
201 	void (*disable_audio)(struct dw_hdmi *hdmi);
202 
203 	struct mutex cec_notifier_mutex;
204 	struct cec_notifier *cec_notifier;
205 
206 	hdmi_codec_plugged_cb plugged_cb;
207 	struct device *codec_dev;
208 	enum drm_connector_status last_connector_result;
209 };
210 
211 #define HDMI_IH_PHY_STAT0_RX_SENSE \
212 	(HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
213 	 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
214 
215 #define HDMI_PHY_RX_SENSE \
216 	(HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
217 	 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
218 
219 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
220 {
221 	regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
222 }
223 
224 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
225 {
226 	unsigned int val = 0;
227 
228 	regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
229 
230 	return val;
231 }
232 
233 static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged)
234 {
235 	if (hdmi->plugged_cb && hdmi->codec_dev)
236 		hdmi->plugged_cb(hdmi->codec_dev, plugged);
237 }
238 
239 int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn,
240 			   struct device *codec_dev)
241 {
242 	bool plugged;
243 
244 	mutex_lock(&hdmi->mutex);
245 	hdmi->plugged_cb = fn;
246 	hdmi->codec_dev = codec_dev;
247 	plugged = hdmi->last_connector_result == connector_status_connected;
248 	handle_plugged_change(hdmi, plugged);
249 	mutex_unlock(&hdmi->mutex);
250 
251 	return 0;
252 }
253 EXPORT_SYMBOL_GPL(dw_hdmi_set_plugged_cb);
254 
255 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
256 {
257 	regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
258 }
259 
260 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
261 			     u8 shift, u8 mask)
262 {
263 	hdmi_modb(hdmi, data << shift, mask, reg);
264 }
265 
266 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
267 {
268 	hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
269 		    HDMI_PHY_I2CM_INT_ADDR);
270 
271 	hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
272 		    HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
273 		    HDMI_PHY_I2CM_CTLINT_ADDR);
274 
275 	/* Software reset */
276 	hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
277 
278 	/* Set Standard Mode speed (determined to be 100KHz on iMX6) */
279 	hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
280 
281 	/* Set done, not acknowledged and arbitration interrupt polarities */
282 	hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
283 	hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
284 		    HDMI_I2CM_CTLINT);
285 
286 	/* Clear DONE and ERROR interrupts */
287 	hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
288 		    HDMI_IH_I2CM_STAT0);
289 
290 	/* Mute DONE and ERROR interrupts */
291 	hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
292 		    HDMI_IH_MUTE_I2CM_STAT0);
293 }
294 
295 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi)
296 {
297 	/* If no unwedge state then give up */
298 	if (!hdmi->unwedge_state)
299 		return false;
300 
301 	dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n");
302 
303 	/*
304 	 * This is a huge hack to workaround a problem where the dw_hdmi i2c
305 	 * bus could sometimes get wedged.  Once wedged there doesn't appear
306 	 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ)
307 	 * other than pulsing the SDA line.
308 	 *
309 	 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi)
310 	 * by:
311 	 * 1. Remux the pin as a GPIO output, driven low.
312 	 * 2. Wait a little while.  1 ms seems to work, but we'll do 10.
313 	 * 3. Immediately jump to remux the pin as dw_hdmi i2c again.
314 	 *
315 	 * At the moment of remuxing, the line will still be low due to its
316 	 * recent stint as an output, but then it will be pulled high by the
317 	 * (presumed) external pullup.  dw_hdmi seems to see this as a rising
318 	 * edge and that seems to get it out of its jam.
319 	 *
320 	 * This wedging was only ever seen on one TV, and only on one of
321 	 * its HDMI ports.  It happened when the TV was powered on while the
322 	 * device was plugged in.  A scope trace shows the TV bringing both SDA
323 	 * and SCL low, then bringing them both back up at roughly the same
324 	 * time.  Presumably this confuses dw_hdmi because it saw activity but
325 	 * no real STOP (maybe it thinks there's another master on the bus?).
326 	 * Giving it a clean rising edge of SDA while SCL is already high
327 	 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out
328 	 * of its stupor.
329 	 *
330 	 * Note that after coming back alive, transfers seem to immediately
331 	 * resume, so if we unwedge due to a timeout we should wait a little
332 	 * longer for our transfer to finish, since it might have just started
333 	 * now.
334 	 */
335 	pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state);
336 	msleep(10);
337 	pinctrl_select_state(hdmi->pinctrl, hdmi->default_state);
338 
339 	return true;
340 }
341 
342 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi)
343 {
344 	struct dw_hdmi_i2c *i2c = hdmi->i2c;
345 	int stat;
346 
347 	stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
348 	if (!stat) {
349 		/* If we can't unwedge, return timeout */
350 		if (!dw_hdmi_i2c_unwedge(hdmi))
351 			return -EAGAIN;
352 
353 		/* We tried to unwedge; give it another chance */
354 		stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
355 		if (!stat)
356 			return -EAGAIN;
357 	}
358 
359 	/* Check for error condition on the bus */
360 	if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
361 		return -EIO;
362 
363 	return 0;
364 }
365 
366 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
367 			    unsigned char *buf, unsigned int length)
368 {
369 	struct dw_hdmi_i2c *i2c = hdmi->i2c;
370 	int ret;
371 
372 	if (!i2c->is_regaddr) {
373 		dev_dbg(hdmi->dev, "set read register address to 0\n");
374 		i2c->slave_reg = 0x00;
375 		i2c->is_regaddr = true;
376 	}
377 
378 	while (length--) {
379 		reinit_completion(&i2c->cmp);
380 
381 		hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
382 		if (i2c->is_segment)
383 			hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
384 				    HDMI_I2CM_OPERATION);
385 		else
386 			hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
387 				    HDMI_I2CM_OPERATION);
388 
389 		ret = dw_hdmi_i2c_wait(hdmi);
390 		if (ret)
391 			return ret;
392 
393 		*buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
394 	}
395 	i2c->is_segment = false;
396 
397 	return 0;
398 }
399 
400 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
401 			     unsigned char *buf, unsigned int length)
402 {
403 	struct dw_hdmi_i2c *i2c = hdmi->i2c;
404 	int ret;
405 
406 	if (!i2c->is_regaddr) {
407 		/* Use the first write byte as register address */
408 		i2c->slave_reg = buf[0];
409 		length--;
410 		buf++;
411 		i2c->is_regaddr = true;
412 	}
413 
414 	while (length--) {
415 		reinit_completion(&i2c->cmp);
416 
417 		hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
418 		hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
419 		hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
420 			    HDMI_I2CM_OPERATION);
421 
422 		ret = dw_hdmi_i2c_wait(hdmi);
423 		if (ret)
424 			return ret;
425 	}
426 
427 	return 0;
428 }
429 
430 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
431 			    struct i2c_msg *msgs, int num)
432 {
433 	struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
434 	struct dw_hdmi_i2c *i2c = hdmi->i2c;
435 	u8 addr = msgs[0].addr;
436 	int i, ret = 0;
437 
438 	if (addr == DDC_CI_ADDR)
439 		/*
440 		 * The internal I2C controller does not support the multi-byte
441 		 * read and write operations needed for DDC/CI.
442 		 * TOFIX: Blacklist the DDC/CI address until we filter out
443 		 * unsupported I2C operations.
444 		 */
445 		return -EOPNOTSUPP;
446 
447 	dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
448 
449 	for (i = 0; i < num; i++) {
450 		if (msgs[i].len == 0) {
451 			dev_dbg(hdmi->dev,
452 				"unsupported transfer %d/%d, no data\n",
453 				i + 1, num);
454 			return -EOPNOTSUPP;
455 		}
456 	}
457 
458 	mutex_lock(&i2c->lock);
459 
460 	/* Unmute DONE and ERROR interrupts */
461 	hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
462 
463 	/* Set slave device address taken from the first I2C message */
464 	hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
465 
466 	/* Set slave device register address on transfer */
467 	i2c->is_regaddr = false;
468 
469 	/* Set segment pointer for I2C extended read mode operation */
470 	i2c->is_segment = false;
471 
472 	for (i = 0; i < num; i++) {
473 		dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
474 			i + 1, num, msgs[i].len, msgs[i].flags);
475 		if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
476 			i2c->is_segment = true;
477 			hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
478 			hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
479 		} else {
480 			if (msgs[i].flags & I2C_M_RD)
481 				ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
482 						       msgs[i].len);
483 			else
484 				ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
485 							msgs[i].len);
486 		}
487 		if (ret < 0)
488 			break;
489 	}
490 
491 	if (!ret)
492 		ret = num;
493 
494 	/* Mute DONE and ERROR interrupts */
495 	hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
496 		    HDMI_IH_MUTE_I2CM_STAT0);
497 
498 	mutex_unlock(&i2c->lock);
499 
500 	return ret;
501 }
502 
503 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
504 {
505 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
506 }
507 
508 static const struct i2c_algorithm dw_hdmi_algorithm = {
509 	.master_xfer	= dw_hdmi_i2c_xfer,
510 	.functionality	= dw_hdmi_i2c_func,
511 };
512 
513 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
514 {
515 	struct i2c_adapter *adap;
516 	struct dw_hdmi_i2c *i2c;
517 	int ret;
518 
519 	i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
520 	if (!i2c)
521 		return ERR_PTR(-ENOMEM);
522 
523 	mutex_init(&i2c->lock);
524 	init_completion(&i2c->cmp);
525 
526 	adap = &i2c->adap;
527 	adap->class = I2C_CLASS_DDC;
528 	adap->owner = THIS_MODULE;
529 	adap->dev.parent = hdmi->dev;
530 	adap->algo = &dw_hdmi_algorithm;
531 	strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
532 	i2c_set_adapdata(adap, hdmi);
533 
534 	ret = i2c_add_adapter(adap);
535 	if (ret) {
536 		dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
537 		devm_kfree(hdmi->dev, i2c);
538 		return ERR_PTR(ret);
539 	}
540 
541 	hdmi->i2c = i2c;
542 
543 	dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
544 
545 	return adap;
546 }
547 
548 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
549 			   unsigned int n)
550 {
551 	/* Must be set/cleared first */
552 	hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
553 
554 	/* nshift factor = 0 */
555 	hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
556 
557 	/* Use automatic CTS generation mode when CTS is not set */
558 	if (cts)
559 		hdmi_writeb(hdmi, ((cts >> 16) &
560 				   HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
561 				  HDMI_AUD_CTS3_CTS_MANUAL,
562 			    HDMI_AUD_CTS3);
563 	else
564 		hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3);
565 	hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
566 	hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
567 
568 	hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
569 	hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
570 	hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
571 }
572 
573 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
574 {
575 	unsigned int n = (128 * freq) / 1000;
576 	unsigned int mult = 1;
577 
578 	while (freq > 48000) {
579 		mult *= 2;
580 		freq /= 2;
581 	}
582 
583 	switch (freq) {
584 	case 32000:
585 		if (pixel_clk == 25175000)
586 			n = 4576;
587 		else if (pixel_clk == 27027000)
588 			n = 4096;
589 		else if (pixel_clk == 74176000 || pixel_clk == 148352000)
590 			n = 11648;
591 		else
592 			n = 4096;
593 		n *= mult;
594 		break;
595 
596 	case 44100:
597 		if (pixel_clk == 25175000)
598 			n = 7007;
599 		else if (pixel_clk == 74176000)
600 			n = 17836;
601 		else if (pixel_clk == 148352000)
602 			n = 8918;
603 		else
604 			n = 6272;
605 		n *= mult;
606 		break;
607 
608 	case 48000:
609 		if (pixel_clk == 25175000)
610 			n = 6864;
611 		else if (pixel_clk == 27027000)
612 			n = 6144;
613 		else if (pixel_clk == 74176000)
614 			n = 11648;
615 		else if (pixel_clk == 148352000)
616 			n = 5824;
617 		else
618 			n = 6144;
619 		n *= mult;
620 		break;
621 
622 	default:
623 		break;
624 	}
625 
626 	return n;
627 }
628 
629 /*
630  * When transmitting IEC60958 linear PCM audio, these registers allow to
631  * configure the channel status information of all the channel status
632  * bits in the IEC60958 frame. For the moment this configuration is only
633  * used when the I2S audio interface, General Purpose Audio (GPA),
634  * or AHB audio DMA (AHBAUDDMA) interface is active
635  * (for S/PDIF interface this information comes from the stream).
636  */
637 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
638 				u8 *channel_status)
639 {
640 	/*
641 	 * Set channel status register for frequency and word length.
642 	 * Use default values for other registers.
643 	 */
644 	hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7);
645 	hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8);
646 }
647 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status);
648 
649 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
650 	unsigned long pixel_clk, unsigned int sample_rate)
651 {
652 	unsigned long ftdms = pixel_clk;
653 	unsigned int n, cts;
654 	u8 config3;
655 	u64 tmp;
656 
657 	n = hdmi_compute_n(sample_rate, pixel_clk);
658 
659 	config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
660 
661 	/* Only compute CTS when using internal AHB audio */
662 	if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
663 		/*
664 		 * Compute the CTS value from the N value.  Note that CTS and N
665 		 * can be up to 20 bits in total, so we need 64-bit math.  Also
666 		 * note that our TDMS clock is not fully accurate; it is
667 		 * accurate to kHz.  This can introduce an unnecessary remainder
668 		 * in the calculation below, so we don't try to warn about that.
669 		 */
670 		tmp = (u64)ftdms * n;
671 		do_div(tmp, 128 * sample_rate);
672 		cts = tmp;
673 
674 		dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
675 			__func__, sample_rate,
676 			ftdms / 1000000, (ftdms / 1000) % 1000,
677 			n, cts);
678 	} else {
679 		cts = 0;
680 	}
681 
682 	spin_lock_irq(&hdmi->audio_lock);
683 	hdmi->audio_n = n;
684 	hdmi->audio_cts = cts;
685 	hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
686 	spin_unlock_irq(&hdmi->audio_lock);
687 }
688 
689 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
690 {
691 	mutex_lock(&hdmi->audio_mutex);
692 	hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
693 	mutex_unlock(&hdmi->audio_mutex);
694 }
695 
696 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
697 {
698 	mutex_lock(&hdmi->audio_mutex);
699 	hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
700 				 hdmi->sample_rate);
701 	mutex_unlock(&hdmi->audio_mutex);
702 }
703 
704 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
705 {
706 	mutex_lock(&hdmi->audio_mutex);
707 	hdmi->sample_rate = rate;
708 	hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
709 				 hdmi->sample_rate);
710 	mutex_unlock(&hdmi->audio_mutex);
711 }
712 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
713 
714 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
715 {
716 	u8 layout;
717 
718 	mutex_lock(&hdmi->audio_mutex);
719 
720 	/*
721 	 * For >2 channel PCM audio, we need to select layout 1
722 	 * and set an appropriate channel map.
723 	 */
724 	if (cnt > 2)
725 		layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1;
726 	else
727 		layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0;
728 
729 	hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK,
730 		  HDMI_FC_AUDSCONF);
731 
732 	/* Set the audio infoframes channel count */
733 	hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET,
734 		  HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0);
735 
736 	mutex_unlock(&hdmi->audio_mutex);
737 }
738 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count);
739 
740 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca)
741 {
742 	mutex_lock(&hdmi->audio_mutex);
743 
744 	hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2);
745 
746 	mutex_unlock(&hdmi->audio_mutex);
747 }
748 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation);
749 
750 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
751 {
752 	if (enable)
753 		hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
754 	else
755 		hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
756 	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
757 }
758 
759 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
760 {
761 	hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
762 }
763 
764 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
765 {
766 	hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
767 }
768 
769 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
770 {
771 	hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
772 	hdmi_enable_audio_clk(hdmi, true);
773 }
774 
775 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
776 {
777 	hdmi_enable_audio_clk(hdmi, false);
778 }
779 
780 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
781 {
782 	unsigned long flags;
783 
784 	spin_lock_irqsave(&hdmi->audio_lock, flags);
785 	hdmi->audio_enable = true;
786 	if (hdmi->enable_audio)
787 		hdmi->enable_audio(hdmi);
788 	spin_unlock_irqrestore(&hdmi->audio_lock, flags);
789 }
790 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
791 
792 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
793 {
794 	unsigned long flags;
795 
796 	spin_lock_irqsave(&hdmi->audio_lock, flags);
797 	hdmi->audio_enable = false;
798 	if (hdmi->disable_audio)
799 		hdmi->disable_audio(hdmi);
800 	spin_unlock_irqrestore(&hdmi->audio_lock, flags);
801 }
802 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
803 
804 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
805 {
806 	switch (bus_format) {
807 	case MEDIA_BUS_FMT_RGB888_1X24:
808 	case MEDIA_BUS_FMT_RGB101010_1X30:
809 	case MEDIA_BUS_FMT_RGB121212_1X36:
810 	case MEDIA_BUS_FMT_RGB161616_1X48:
811 		return true;
812 
813 	default:
814 		return false;
815 	}
816 }
817 
818 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
819 {
820 	switch (bus_format) {
821 	case MEDIA_BUS_FMT_YUV8_1X24:
822 	case MEDIA_BUS_FMT_YUV10_1X30:
823 	case MEDIA_BUS_FMT_YUV12_1X36:
824 	case MEDIA_BUS_FMT_YUV16_1X48:
825 		return true;
826 
827 	default:
828 		return false;
829 	}
830 }
831 
832 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
833 {
834 	switch (bus_format) {
835 	case MEDIA_BUS_FMT_UYVY8_1X16:
836 	case MEDIA_BUS_FMT_UYVY10_1X20:
837 	case MEDIA_BUS_FMT_UYVY12_1X24:
838 		return true;
839 
840 	default:
841 		return false;
842 	}
843 }
844 
845 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
846 {
847 	switch (bus_format) {
848 	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
849 	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
850 	case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
851 	case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
852 		return true;
853 
854 	default:
855 		return false;
856 	}
857 }
858 
859 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
860 {
861 	switch (bus_format) {
862 	case MEDIA_BUS_FMT_RGB888_1X24:
863 	case MEDIA_BUS_FMT_YUV8_1X24:
864 	case MEDIA_BUS_FMT_UYVY8_1X16:
865 	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
866 		return 8;
867 
868 	case MEDIA_BUS_FMT_RGB101010_1X30:
869 	case MEDIA_BUS_FMT_YUV10_1X30:
870 	case MEDIA_BUS_FMT_UYVY10_1X20:
871 	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
872 		return 10;
873 
874 	case MEDIA_BUS_FMT_RGB121212_1X36:
875 	case MEDIA_BUS_FMT_YUV12_1X36:
876 	case MEDIA_BUS_FMT_UYVY12_1X24:
877 	case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
878 		return 12;
879 
880 	case MEDIA_BUS_FMT_RGB161616_1X48:
881 	case MEDIA_BUS_FMT_YUV16_1X48:
882 	case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
883 		return 16;
884 
885 	default:
886 		return 0;
887 	}
888 }
889 
890 /*
891  * this submodule is responsible for the video data synchronization.
892  * for example, for RGB 4:4:4 input, the data map is defined as
893  *			pin{47~40} <==> R[7:0]
894  *			pin{31~24} <==> G[7:0]
895  *			pin{15~8}  <==> B[7:0]
896  */
897 static void hdmi_video_sample(struct dw_hdmi *hdmi)
898 {
899 	int color_format = 0;
900 	u8 val;
901 
902 	switch (hdmi->hdmi_data.enc_in_bus_format) {
903 	case MEDIA_BUS_FMT_RGB888_1X24:
904 		color_format = 0x01;
905 		break;
906 	case MEDIA_BUS_FMT_RGB101010_1X30:
907 		color_format = 0x03;
908 		break;
909 	case MEDIA_BUS_FMT_RGB121212_1X36:
910 		color_format = 0x05;
911 		break;
912 	case MEDIA_BUS_FMT_RGB161616_1X48:
913 		color_format = 0x07;
914 		break;
915 
916 	case MEDIA_BUS_FMT_YUV8_1X24:
917 	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
918 		color_format = 0x09;
919 		break;
920 	case MEDIA_BUS_FMT_YUV10_1X30:
921 	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
922 		color_format = 0x0B;
923 		break;
924 	case MEDIA_BUS_FMT_YUV12_1X36:
925 	case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
926 		color_format = 0x0D;
927 		break;
928 	case MEDIA_BUS_FMT_YUV16_1X48:
929 	case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
930 		color_format = 0x0F;
931 		break;
932 
933 	case MEDIA_BUS_FMT_UYVY8_1X16:
934 		color_format = 0x16;
935 		break;
936 	case MEDIA_BUS_FMT_UYVY10_1X20:
937 		color_format = 0x14;
938 		break;
939 	case MEDIA_BUS_FMT_UYVY12_1X24:
940 		color_format = 0x12;
941 		break;
942 
943 	default:
944 		return;
945 	}
946 
947 	val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
948 		((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
949 		HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
950 	hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
951 
952 	/* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
953 	val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
954 		HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
955 		HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
956 	hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
957 	hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
958 	hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
959 	hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
960 	hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
961 	hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
962 	hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
963 }
964 
965 static int is_color_space_conversion(struct dw_hdmi *hdmi)
966 {
967 	struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
968 	bool is_input_rgb, is_output_rgb;
969 
970 	is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format);
971 	is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format);
972 
973 	return (is_input_rgb != is_output_rgb) ||
974 	       (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range);
975 }
976 
977 static int is_color_space_decimation(struct dw_hdmi *hdmi)
978 {
979 	if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
980 		return 0;
981 
982 	if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
983 	    hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
984 		return 1;
985 
986 	return 0;
987 }
988 
989 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
990 {
991 	if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
992 		return 0;
993 
994 	if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
995 	    hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
996 		return 1;
997 
998 	return 0;
999 }
1000 
1001 static bool is_csc_needed(struct dw_hdmi *hdmi)
1002 {
1003 	return is_color_space_conversion(hdmi) ||
1004 	       is_color_space_decimation(hdmi) ||
1005 	       is_color_space_interpolation(hdmi);
1006 }
1007 
1008 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
1009 {
1010 	const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
1011 	bool is_input_rgb, is_output_rgb;
1012 	unsigned i;
1013 	u32 csc_scale = 1;
1014 
1015 	is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format);
1016 	is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format);
1017 
1018 	if (!is_input_rgb && is_output_rgb) {
1019 		if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
1020 			csc_coeff = &csc_coeff_rgb_out_eitu601;
1021 		else
1022 			csc_coeff = &csc_coeff_rgb_out_eitu709;
1023 	} else if (is_input_rgb && !is_output_rgb) {
1024 		if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
1025 			csc_coeff = &csc_coeff_rgb_in_eitu601;
1026 		else
1027 			csc_coeff = &csc_coeff_rgb_in_eitu709;
1028 		csc_scale = 0;
1029 	} else if (is_input_rgb && is_output_rgb &&
1030 		   hdmi->hdmi_data.rgb_limited_range) {
1031 		csc_coeff = &csc_coeff_rgb_full_to_rgb_limited;
1032 	}
1033 
1034 	/* The CSC registers are sequential, alternating MSB then LSB */
1035 	for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
1036 		u16 coeff_a = (*csc_coeff)[0][i];
1037 		u16 coeff_b = (*csc_coeff)[1][i];
1038 		u16 coeff_c = (*csc_coeff)[2][i];
1039 
1040 		hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
1041 		hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
1042 		hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
1043 		hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
1044 		hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
1045 		hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
1046 	}
1047 
1048 	hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
1049 		  HDMI_CSC_SCALE);
1050 }
1051 
1052 static void hdmi_video_csc(struct dw_hdmi *hdmi)
1053 {
1054 	int color_depth = 0;
1055 	int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
1056 	int decimation = 0;
1057 
1058 	/* YCC422 interpolation to 444 mode */
1059 	if (is_color_space_interpolation(hdmi))
1060 		interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
1061 	else if (is_color_space_decimation(hdmi))
1062 		decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
1063 
1064 	switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
1065 	case 8:
1066 		color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
1067 		break;
1068 	case 10:
1069 		color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
1070 		break;
1071 	case 12:
1072 		color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
1073 		break;
1074 	case 16:
1075 		color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
1076 		break;
1077 
1078 	default:
1079 		return;
1080 	}
1081 
1082 	/* Configure the CSC registers */
1083 	hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
1084 	hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
1085 		  HDMI_CSC_SCALE);
1086 
1087 	dw_hdmi_update_csc_coeffs(hdmi);
1088 }
1089 
1090 /*
1091  * HDMI video packetizer is used to packetize the data.
1092  * for example, if input is YCC422 mode or repeater is used,
1093  * data should be repacked this module can be bypassed.
1094  */
1095 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
1096 {
1097 	unsigned int color_depth = 0;
1098 	unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
1099 	unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
1100 	struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1101 	u8 val, vp_conf;
1102 
1103 	if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1104 	    hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
1105 	    hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1106 		switch (hdmi_bus_fmt_color_depth(
1107 					hdmi->hdmi_data.enc_out_bus_format)) {
1108 		case 8:
1109 			color_depth = 4;
1110 			output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1111 			break;
1112 		case 10:
1113 			color_depth = 5;
1114 			break;
1115 		case 12:
1116 			color_depth = 6;
1117 			break;
1118 		case 16:
1119 			color_depth = 7;
1120 			break;
1121 		default:
1122 			output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1123 		}
1124 	} else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1125 		switch (hdmi_bus_fmt_color_depth(
1126 					hdmi->hdmi_data.enc_out_bus_format)) {
1127 		case 0:
1128 		case 8:
1129 			remap_size = HDMI_VP_REMAP_YCC422_16bit;
1130 			break;
1131 		case 10:
1132 			remap_size = HDMI_VP_REMAP_YCC422_20bit;
1133 			break;
1134 		case 12:
1135 			remap_size = HDMI_VP_REMAP_YCC422_24bit;
1136 			break;
1137 
1138 		default:
1139 			return;
1140 		}
1141 		output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
1142 	} else {
1143 		return;
1144 	}
1145 
1146 	/* set the packetizer registers */
1147 	val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
1148 		HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
1149 		((hdmi_data->pix_repet_factor <<
1150 		HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
1151 		HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
1152 	hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
1153 
1154 	hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
1155 		  HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
1156 
1157 	/* Data from pixel repeater block */
1158 	if (hdmi_data->pix_repet_factor > 1) {
1159 		vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
1160 			  HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
1161 	} else { /* data from packetizer block */
1162 		vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
1163 			  HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
1164 	}
1165 
1166 	hdmi_modb(hdmi, vp_conf,
1167 		  HDMI_VP_CONF_PR_EN_MASK |
1168 		  HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
1169 
1170 	hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
1171 		  HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
1172 
1173 	hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
1174 
1175 	if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
1176 		vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1177 			  HDMI_VP_CONF_PP_EN_ENABLE |
1178 			  HDMI_VP_CONF_YCC422_EN_DISABLE;
1179 	} else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
1180 		vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1181 			  HDMI_VP_CONF_PP_EN_DISABLE |
1182 			  HDMI_VP_CONF_YCC422_EN_ENABLE;
1183 	} else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
1184 		vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
1185 			  HDMI_VP_CONF_PP_EN_DISABLE |
1186 			  HDMI_VP_CONF_YCC422_EN_DISABLE;
1187 	} else {
1188 		return;
1189 	}
1190 
1191 	hdmi_modb(hdmi, vp_conf,
1192 		  HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
1193 		  HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
1194 
1195 	hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
1196 			HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
1197 		  HDMI_VP_STUFF_PP_STUFFING_MASK |
1198 		  HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
1199 
1200 	hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
1201 		  HDMI_VP_CONF);
1202 }
1203 
1204 /* -----------------------------------------------------------------------------
1205  * Synopsys PHY Handling
1206  */
1207 
1208 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
1209 				       unsigned char bit)
1210 {
1211 	hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
1212 		  HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
1213 }
1214 
1215 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
1216 {
1217 	u32 val;
1218 
1219 	while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1220 		if (msec-- == 0)
1221 			return false;
1222 		udelay(1000);
1223 	}
1224 	hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1225 
1226 	return true;
1227 }
1228 
1229 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1230 			   unsigned char addr)
1231 {
1232 	hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1233 	hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1234 	hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1235 		    HDMI_PHY_I2CM_DATAO_1_ADDR);
1236 	hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1237 		    HDMI_PHY_I2CM_DATAO_0_ADDR);
1238 	hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1239 		    HDMI_PHY_I2CM_OPERATION_ADDR);
1240 	hdmi_phy_wait_i2c_done(hdmi, 1000);
1241 }
1242 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
1243 
1244 /* Filter out invalid setups to avoid configuring SCDC and scrambling */
1245 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi,
1246 				 const struct drm_display_info *display)
1247 {
1248 	/* Completely disable SCDC support for older controllers */
1249 	if (hdmi->version < 0x200a)
1250 		return false;
1251 
1252 	/* Disable if no DDC bus */
1253 	if (!hdmi->ddc)
1254 		return false;
1255 
1256 	/* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
1257 	if (!display->hdmi.scdc.supported ||
1258 	    !display->hdmi.scdc.scrambling.supported)
1259 		return false;
1260 
1261 	/*
1262 	 * Disable if display only support low TMDS rates and scrambling
1263 	 * for low rates is not supported either
1264 	 */
1265 	if (!display->hdmi.scdc.scrambling.low_rates &&
1266 	    display->max_tmds_clock <= 340000)
1267 		return false;
1268 
1269 	return true;
1270 }
1271 
1272 /*
1273  * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
1274  * - The Source shall suspend transmission of the TMDS clock and data
1275  * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it
1276  * from a 0 to a 1 or from a 1 to a 0
1277  * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from
1278  * the time the TMDS_Bit_Clock_Ratio bit is written until resuming
1279  * transmission of TMDS clock and data
1280  *
1281  * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio()
1282  * helper should called right before enabling the TMDS Clock and Data in
1283  * the PHY configuration callback.
1284  */
1285 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi,
1286 				       const struct drm_display_info *display)
1287 {
1288 	unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1289 
1290 	/* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1291 	if (dw_hdmi_support_scdc(hdmi, display)) {
1292 		if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1293 			drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
1294 		else
1295 			drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
1296 	}
1297 }
1298 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio);
1299 
1300 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1301 {
1302 	hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1303 			 HDMI_PHY_CONF0_PDZ_OFFSET,
1304 			 HDMI_PHY_CONF0_PDZ_MASK);
1305 }
1306 
1307 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1308 {
1309 	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1310 			 HDMI_PHY_CONF0_ENTMDS_OFFSET,
1311 			 HDMI_PHY_CONF0_ENTMDS_MASK);
1312 }
1313 
1314 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
1315 {
1316 	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1317 			 HDMI_PHY_CONF0_SVSRET_OFFSET,
1318 			 HDMI_PHY_CONF0_SVSRET_MASK);
1319 }
1320 
1321 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1322 {
1323 	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1324 			 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1325 			 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1326 }
1327 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq);
1328 
1329 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1330 {
1331 	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1332 			 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1333 			 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1334 }
1335 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron);
1336 
1337 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1338 {
1339 	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1340 			 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1341 			 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1342 }
1343 
1344 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1345 {
1346 	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1347 			 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1348 			 HDMI_PHY_CONF0_SELDIPIF_MASK);
1349 }
1350 
1351 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
1352 {
1353 	/* PHY reset. The reset signal is active high on Gen2 PHYs. */
1354 	hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1355 	hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1356 }
1357 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
1358 
1359 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
1360 {
1361 	hdmi_phy_test_clear(hdmi, 1);
1362 	hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR);
1363 	hdmi_phy_test_clear(hdmi, 0);
1364 }
1365 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr);
1366 
1367 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1368 {
1369 	const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1370 	unsigned int i;
1371 	u16 val;
1372 
1373 	if (phy->gen == 1) {
1374 		dw_hdmi_phy_enable_tmds(hdmi, 0);
1375 		dw_hdmi_phy_enable_powerdown(hdmi, true);
1376 		return;
1377 	}
1378 
1379 	dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1380 
1381 	/*
1382 	 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1383 	 * to low power mode.
1384 	 */
1385 	for (i = 0; i < 5; ++i) {
1386 		val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1387 		if (!(val & HDMI_PHY_TX_PHY_LOCK))
1388 			break;
1389 
1390 		usleep_range(1000, 2000);
1391 	}
1392 
1393 	if (val & HDMI_PHY_TX_PHY_LOCK)
1394 		dev_warn(hdmi->dev, "PHY failed to power down\n");
1395 	else
1396 		dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1397 
1398 	dw_hdmi_phy_gen2_pddq(hdmi, 1);
1399 }
1400 
1401 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1402 {
1403 	const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1404 	unsigned int i;
1405 	u8 val;
1406 
1407 	if (phy->gen == 1) {
1408 		dw_hdmi_phy_enable_powerdown(hdmi, false);
1409 
1410 		/* Toggle TMDS enable. */
1411 		dw_hdmi_phy_enable_tmds(hdmi, 0);
1412 		dw_hdmi_phy_enable_tmds(hdmi, 1);
1413 		return 0;
1414 	}
1415 
1416 	dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1417 	dw_hdmi_phy_gen2_pddq(hdmi, 0);
1418 
1419 	/* Wait for PHY PLL lock */
1420 	for (i = 0; i < 5; ++i) {
1421 		val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1422 		if (val)
1423 			break;
1424 
1425 		usleep_range(1000, 2000);
1426 	}
1427 
1428 	if (!val) {
1429 		dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1430 		return -ETIMEDOUT;
1431 	}
1432 
1433 	dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1434 	return 0;
1435 }
1436 
1437 /*
1438  * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1439  * information the DWC MHL PHY has the same register layout and is thus also
1440  * supported by this function.
1441  */
1442 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1443 		const struct dw_hdmi_plat_data *pdata,
1444 		unsigned long mpixelclock)
1445 {
1446 	const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1447 	const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1448 	const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1449 
1450 	/* TOFIX Will need 420 specific PHY configuration tables */
1451 
1452 	/* PLL/MPLL Cfg - always match on final entry */
1453 	for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1454 		if (mpixelclock <= mpll_config->mpixelclock)
1455 			break;
1456 
1457 	for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1458 		if (mpixelclock <= curr_ctrl->mpixelclock)
1459 			break;
1460 
1461 	for (; phy_config->mpixelclock != ~0UL; phy_config++)
1462 		if (mpixelclock <= phy_config->mpixelclock)
1463 			break;
1464 
1465 	if (mpll_config->mpixelclock == ~0UL ||
1466 	    curr_ctrl->mpixelclock == ~0UL ||
1467 	    phy_config->mpixelclock == ~0UL)
1468 		return -EINVAL;
1469 
1470 	dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1471 			      HDMI_3D_TX_PHY_CPCE_CTRL);
1472 	dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1473 			      HDMI_3D_TX_PHY_GMPCTRL);
1474 	dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1475 			      HDMI_3D_TX_PHY_CURRCTRL);
1476 
1477 	dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1478 	dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1479 			      HDMI_3D_TX_PHY_MSM_CTRL);
1480 
1481 	dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1482 	dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1483 			      HDMI_3D_TX_PHY_CKSYMTXCTRL);
1484 	dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1485 			      HDMI_3D_TX_PHY_VLEVCTRL);
1486 
1487 	/* Override and disable clock termination. */
1488 	dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1489 			      HDMI_3D_TX_PHY_CKCALCTRL);
1490 
1491 	return 0;
1492 }
1493 
1494 static int hdmi_phy_configure(struct dw_hdmi *hdmi,
1495 			      const struct drm_display_info *display)
1496 {
1497 	const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1498 	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1499 	unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1500 	unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1501 	int ret;
1502 
1503 	dw_hdmi_phy_power_off(hdmi);
1504 
1505 	dw_hdmi_set_high_tmds_clock_ratio(hdmi, display);
1506 
1507 	/* Leave low power consumption mode by asserting SVSRET. */
1508 	if (phy->has_svsret)
1509 		dw_hdmi_phy_enable_svsret(hdmi, 1);
1510 
1511 	dw_hdmi_phy_reset(hdmi);
1512 
1513 	hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1514 
1515 	dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
1516 
1517 	/* Write to the PHY as configured by the platform */
1518 	if (pdata->configure_phy)
1519 		ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock);
1520 	else
1521 		ret = phy->configure(hdmi, pdata, mpixelclock);
1522 	if (ret) {
1523 		dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1524 			mpixelclock);
1525 		return ret;
1526 	}
1527 
1528 	/* Wait for resuming transmission of TMDS clock and data */
1529 	if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1530 		msleep(100);
1531 
1532 	return dw_hdmi_phy_power_on(hdmi);
1533 }
1534 
1535 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1536 			    const struct drm_display_info *display,
1537 			    const struct drm_display_mode *mode)
1538 {
1539 	int i, ret;
1540 
1541 	/* HDMI Phy spec says to do the phy initialization sequence twice */
1542 	for (i = 0; i < 2; i++) {
1543 		dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1544 		dw_hdmi_phy_sel_interface_control(hdmi, 0);
1545 
1546 		ret = hdmi_phy_configure(hdmi, display);
1547 		if (ret)
1548 			return ret;
1549 	}
1550 
1551 	return 0;
1552 }
1553 
1554 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1555 {
1556 	dw_hdmi_phy_power_off(hdmi);
1557 }
1558 
1559 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1560 					       void *data)
1561 {
1562 	return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1563 		connector_status_connected : connector_status_disconnected;
1564 }
1565 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd);
1566 
1567 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
1568 			    bool force, bool disabled, bool rxsense)
1569 {
1570 	u8 old_mask = hdmi->phy_mask;
1571 
1572 	if (force || disabled || !rxsense)
1573 		hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1574 	else
1575 		hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1576 
1577 	if (old_mask != hdmi->phy_mask)
1578 		hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1579 }
1580 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd);
1581 
1582 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
1583 {
1584 	/*
1585 	 * Configure the PHY RX SENSE and HPD interrupts polarities and clear
1586 	 * any pending interrupt.
1587 	 */
1588 	hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1589 	hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1590 		    HDMI_IH_PHY_STAT0);
1591 
1592 	/* Enable cable hot plug irq. */
1593 	hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1594 
1595 	/* Clear and unmute interrupts. */
1596 	hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1597 		    HDMI_IH_PHY_STAT0);
1598 	hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1599 		    HDMI_IH_MUTE_PHY_STAT0);
1600 }
1601 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd);
1602 
1603 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1604 	.init = dw_hdmi_phy_init,
1605 	.disable = dw_hdmi_phy_disable,
1606 	.read_hpd = dw_hdmi_phy_read_hpd,
1607 	.update_hpd = dw_hdmi_phy_update_hpd,
1608 	.setup_hpd = dw_hdmi_phy_setup_hpd,
1609 };
1610 
1611 /* -----------------------------------------------------------------------------
1612  * HDMI TX Setup
1613  */
1614 
1615 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1616 {
1617 	u8 de;
1618 
1619 	if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1620 		de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1621 	else
1622 		de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1623 
1624 	/* disable rx detect */
1625 	hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1626 		  HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1627 
1628 	hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1629 
1630 	hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1631 		  HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1632 }
1633 
1634 static void hdmi_config_AVI(struct dw_hdmi *hdmi,
1635 			    const struct drm_connector *connector,
1636 			    const struct drm_display_mode *mode)
1637 {
1638 	struct hdmi_avi_infoframe frame;
1639 	u8 val;
1640 
1641 	/* Initialise info frame from DRM mode */
1642 	drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1643 
1644 	if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1645 		drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode,
1646 						   hdmi->hdmi_data.rgb_limited_range ?
1647 						   HDMI_QUANTIZATION_RANGE_LIMITED :
1648 						   HDMI_QUANTIZATION_RANGE_FULL);
1649 	} else {
1650 		frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
1651 		frame.ycc_quantization_range =
1652 			HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
1653 	}
1654 
1655 	if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1656 		frame.colorspace = HDMI_COLORSPACE_YUV444;
1657 	else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1658 		frame.colorspace = HDMI_COLORSPACE_YUV422;
1659 	else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1660 		frame.colorspace = HDMI_COLORSPACE_YUV420;
1661 	else
1662 		frame.colorspace = HDMI_COLORSPACE_RGB;
1663 
1664 	/* Set up colorimetry */
1665 	if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1666 		switch (hdmi->hdmi_data.enc_out_encoding) {
1667 		case V4L2_YCBCR_ENC_601:
1668 			if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1669 				frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1670 			else
1671 				frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1672 			frame.extended_colorimetry =
1673 					HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1674 			break;
1675 		case V4L2_YCBCR_ENC_709:
1676 			if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1677 				frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1678 			else
1679 				frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1680 			frame.extended_colorimetry =
1681 					HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1682 			break;
1683 		default: /* Carries no data */
1684 			frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1685 			frame.extended_colorimetry =
1686 					HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1687 			break;
1688 		}
1689 	} else {
1690 		frame.colorimetry = HDMI_COLORIMETRY_NONE;
1691 		frame.extended_colorimetry =
1692 			HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1693 	}
1694 
1695 	/*
1696 	 * The Designware IP uses a different byte format from standard
1697 	 * AVI info frames, though generally the bits are in the correct
1698 	 * bytes.
1699 	 */
1700 
1701 	/*
1702 	 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1703 	 * scan info in bits 4,5 rather than 0,1 and active aspect present in
1704 	 * bit 6 rather than 4.
1705 	 */
1706 	val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
1707 	if (frame.active_aspect & 15)
1708 		val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1709 	if (frame.top_bar || frame.bottom_bar)
1710 		val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1711 	if (frame.left_bar || frame.right_bar)
1712 		val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1713 	hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1714 
1715 	/* AVI data byte 2 differences: none */
1716 	val = ((frame.colorimetry & 0x3) << 6) |
1717 	      ((frame.picture_aspect & 0x3) << 4) |
1718 	      (frame.active_aspect & 0xf);
1719 	hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1720 
1721 	/* AVI data byte 3 differences: none */
1722 	val = ((frame.extended_colorimetry & 0x7) << 4) |
1723 	      ((frame.quantization_range & 0x3) << 2) |
1724 	      (frame.nups & 0x3);
1725 	if (frame.itc)
1726 		val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1727 	hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1728 
1729 	/* AVI data byte 4 differences: none */
1730 	val = frame.video_code & 0x7f;
1731 	hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1732 
1733 	/* AVI Data Byte 5- set up input and output pixel repetition */
1734 	val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1735 		HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1736 		HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1737 		((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1738 		HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1739 		HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1740 	hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1741 
1742 	/*
1743 	 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1744 	 * ycc range in bits 2,3 rather than 6,7
1745 	 */
1746 	val = ((frame.ycc_quantization_range & 0x3) << 2) |
1747 	      (frame.content_type & 0x3);
1748 	hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1749 
1750 	/* AVI Data Bytes 6-13 */
1751 	hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1752 	hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1753 	hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1754 	hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1755 	hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1756 	hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1757 	hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1758 	hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1759 }
1760 
1761 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1762 						  const struct drm_connector *connector,
1763 						  const struct drm_display_mode *mode)
1764 {
1765 	struct hdmi_vendor_infoframe frame;
1766 	u8 buffer[10];
1767 	ssize_t err;
1768 
1769 	err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, connector,
1770 							  mode);
1771 	if (err < 0)
1772 		/*
1773 		 * Going into that statement does not means vendor infoframe
1774 		 * fails. It just informed us that vendor infoframe is not
1775 		 * needed for the selected mode. Only 4k or stereoscopic 3D
1776 		 * mode requires vendor infoframe. So just simply return.
1777 		 */
1778 		return;
1779 
1780 	err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1781 	if (err < 0) {
1782 		dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1783 			err);
1784 		return;
1785 	}
1786 	hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1787 			HDMI_FC_DATAUTO0_VSD_MASK);
1788 
1789 	/* Set the length of HDMI vendor specific InfoFrame payload */
1790 	hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1791 
1792 	/* Set 24bit IEEE Registration Identifier */
1793 	hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1794 	hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1795 	hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1796 
1797 	/* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1798 	hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1799 	hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1800 
1801 	if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1802 		hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1803 
1804 	/* Packet frame interpolation */
1805 	hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1806 
1807 	/* Auto packets per frame and line spacing */
1808 	hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1809 
1810 	/* Configures the Frame Composer On RDRB mode */
1811 	hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1812 			HDMI_FC_DATAUTO0_VSD_MASK);
1813 }
1814 
1815 static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi,
1816 				      const struct drm_connector *connector)
1817 {
1818 	const struct drm_connector_state *conn_state = connector->state;
1819 	struct hdmi_drm_infoframe frame;
1820 	u8 buffer[30];
1821 	ssize_t err;
1822 	int i;
1823 
1824 	if (!hdmi->plat_data->use_drm_infoframe)
1825 		return;
1826 
1827 	hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE,
1828 		  HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
1829 
1830 	err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
1831 	if (err < 0)
1832 		return;
1833 
1834 	err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer));
1835 	if (err < 0) {
1836 		dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err);
1837 		return;
1838 	}
1839 
1840 	hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0);
1841 	hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);
1842 
1843 	for (i = 0; i < frame.length; i++)
1844 		hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i);
1845 
1846 	hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP);
1847 	hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE,
1848 		  HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
1849 }
1850 
1851 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1852 			     const struct drm_display_info *display,
1853 			     const struct drm_display_mode *mode)
1854 {
1855 	u8 inv_val, bytes;
1856 	const struct drm_hdmi_info *hdmi_info = &display->hdmi;
1857 	struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1858 	int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1859 	unsigned int vdisplay, hdisplay;
1860 
1861 	vmode->mpixelclock = mode->clock * 1000;
1862 
1863 	dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1864 
1865 	vmode->mtmdsclock = vmode->mpixelclock;
1866 
1867 	if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1868 		switch (hdmi_bus_fmt_color_depth(
1869 				hdmi->hdmi_data.enc_out_bus_format)) {
1870 		case 16:
1871 			vmode->mtmdsclock = vmode->mpixelclock * 2;
1872 			break;
1873 		case 12:
1874 			vmode->mtmdsclock = vmode->mpixelclock * 3 / 2;
1875 			break;
1876 		case 10:
1877 			vmode->mtmdsclock = vmode->mpixelclock * 5 / 4;
1878 			break;
1879 		}
1880 	}
1881 
1882 	if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1883 		vmode->mtmdsclock /= 2;
1884 
1885 	dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock);
1886 
1887 	/* Set up HDMI_FC_INVIDCONF */
1888 	inv_val = (hdmi->hdmi_data.hdcp_enable ||
1889 		   (dw_hdmi_support_scdc(hdmi, display) &&
1890 		    (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1891 		     hdmi_info->scdc.scrambling.low_rates)) ?
1892 		HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1893 		HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1894 
1895 	inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1896 		HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1897 		HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1898 
1899 	inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1900 		HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1901 		HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1902 
1903 	inv_val |= (vmode->mdataenablepolarity ?
1904 		HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1905 		HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1906 
1907 	if (hdmi->vic == 39)
1908 		inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1909 	else
1910 		inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1911 			HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1912 			HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1913 
1914 	inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1915 		HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1916 		HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1917 
1918 	inv_val |= hdmi->sink_is_hdmi ?
1919 		HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1920 		HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1921 
1922 	hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1923 
1924 	hdisplay = mode->hdisplay;
1925 	hblank = mode->htotal - mode->hdisplay;
1926 	h_de_hs = mode->hsync_start - mode->hdisplay;
1927 	hsync_len = mode->hsync_end - mode->hsync_start;
1928 
1929 	/*
1930 	 * When we're setting a YCbCr420 mode, we need
1931 	 * to adjust the horizontal timing to suit.
1932 	 */
1933 	if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1934 		hdisplay /= 2;
1935 		hblank /= 2;
1936 		h_de_hs /= 2;
1937 		hsync_len /= 2;
1938 	}
1939 
1940 	vdisplay = mode->vdisplay;
1941 	vblank = mode->vtotal - mode->vdisplay;
1942 	v_de_vs = mode->vsync_start - mode->vdisplay;
1943 	vsync_len = mode->vsync_end - mode->vsync_start;
1944 
1945 	/*
1946 	 * When we're setting an interlaced mode, we need
1947 	 * to adjust the vertical timing to suit.
1948 	 */
1949 	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1950 		vdisplay /= 2;
1951 		vblank /= 2;
1952 		v_de_vs /= 2;
1953 		vsync_len /= 2;
1954 	}
1955 
1956 	/* Scrambling Control */
1957 	if (dw_hdmi_support_scdc(hdmi, display)) {
1958 		if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1959 		    hdmi_info->scdc.scrambling.low_rates) {
1960 			/*
1961 			 * HDMI2.0 Specifies the following procedure:
1962 			 * After the Source Device has determined that
1963 			 * SCDC_Present is set (=1), the Source Device should
1964 			 * write the accurate Version of the Source Device
1965 			 * to the Source Version field in the SCDCS.
1966 			 * Source Devices compliant shall set the
1967 			 * Source Version = 1.
1968 			 */
1969 			drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION,
1970 				       &bytes);
1971 			drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,
1972 				min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
1973 
1974 			/* Enabled Scrambling in the Sink */
1975 			drm_scdc_set_scrambling(hdmi->ddc, 1);
1976 
1977 			/*
1978 			 * To activate the scrambler feature, you must ensure
1979 			 * that the quasi-static configuration bit
1980 			 * fc_invidconf.HDCP_keepout is set at configuration
1981 			 * time, before the required mc_swrstzreq.tmdsswrst_req
1982 			 * reset request is issued.
1983 			 */
1984 			hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1985 				    HDMI_MC_SWRSTZ);
1986 			hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1987 		} else {
1988 			hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1989 			hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1990 				    HDMI_MC_SWRSTZ);
1991 			drm_scdc_set_scrambling(hdmi->ddc, 0);
1992 		}
1993 	}
1994 
1995 	/* Set up horizontal active pixel width */
1996 	hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1997 	hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
1998 
1999 	/* Set up vertical active lines */
2000 	hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
2001 	hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
2002 
2003 	/* Set up horizontal blanking pixel region width */
2004 	hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
2005 	hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
2006 
2007 	/* Set up vertical blanking pixel region width */
2008 	hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
2009 
2010 	/* Set up HSYNC active edge delay width (in pixel clks) */
2011 	hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
2012 	hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
2013 
2014 	/* Set up VSYNC active edge delay (in lines) */
2015 	hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
2016 
2017 	/* Set up HSYNC active pulse width (in pixel clks) */
2018 	hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
2019 	hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
2020 
2021 	/* Set up VSYNC active edge delay (in lines) */
2022 	hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
2023 }
2024 
2025 /* HDMI Initialization Step B.4 */
2026 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
2027 {
2028 	/* control period minimum duration */
2029 	hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
2030 	hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
2031 	hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
2032 
2033 	/* Set to fill TMDS data channels */
2034 	hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
2035 	hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
2036 	hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
2037 
2038 	/* Enable pixel clock and tmds data path */
2039 	hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
2040 			   HDMI_MC_CLKDIS_CSCCLK_DISABLE |
2041 			   HDMI_MC_CLKDIS_AUDCLK_DISABLE |
2042 			   HDMI_MC_CLKDIS_PREPCLK_DISABLE |
2043 			   HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
2044 	hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
2045 	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2046 
2047 	hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
2048 	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2049 
2050 	/* Enable csc path */
2051 	if (is_csc_needed(hdmi)) {
2052 		hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2053 		hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2054 
2055 		hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
2056 			    HDMI_MC_FLOWCTRL);
2057 	} else {
2058 		hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2059 		hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2060 
2061 		hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
2062 			    HDMI_MC_FLOWCTRL);
2063 	}
2064 }
2065 
2066 /* Workaround to clear the overflow condition */
2067 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
2068 {
2069 	unsigned int count;
2070 	unsigned int i;
2071 	u8 val;
2072 
2073 	/*
2074 	 * Under some circumstances the Frame Composer arithmetic unit can miss
2075 	 * an FC register write due to being busy processing the previous one.
2076 	 * The issue can be worked around by issuing a TMDS software reset and
2077 	 * then write one of the FC registers several times.
2078 	 *
2079 	 * The number of iterations matters and depends on the HDMI TX revision
2080 	 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL
2081 	 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified
2082 	 * as needing the workaround, with 4 iterations for v1.30a and 1
2083 	 * iteration for others.
2084 	 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
2085 	 * the workaround with a single iteration.
2086 	 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have
2087 	 * been identified as needing the workaround with a single iteration.
2088 	 */
2089 
2090 	switch (hdmi->version) {
2091 	case 0x130a:
2092 		count = 4;
2093 		break;
2094 	case 0x131a:
2095 	case 0x132a:
2096 	case 0x200a:
2097 	case 0x201a:
2098 	case 0x211a:
2099 	case 0x212a:
2100 		count = 1;
2101 		break;
2102 	default:
2103 		return;
2104 	}
2105 
2106 	/* TMDS software reset */
2107 	hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
2108 
2109 	val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
2110 	for (i = 0; i < count; i++)
2111 		hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
2112 }
2113 
2114 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
2115 {
2116 	hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
2117 		    HDMI_IH_MUTE_FC_STAT2);
2118 }
2119 
2120 static int dw_hdmi_setup(struct dw_hdmi *hdmi,
2121 			 const struct drm_connector *connector,
2122 			 const struct drm_display_mode *mode)
2123 {
2124 	int ret;
2125 
2126 	hdmi_disable_overflow_interrupts(hdmi);
2127 
2128 	hdmi->vic = drm_match_cea_mode(mode);
2129 
2130 	if (!hdmi->vic) {
2131 		dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
2132 	} else {
2133 		dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
2134 	}
2135 
2136 	if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
2137 	    (hdmi->vic == 21) || (hdmi->vic == 22) ||
2138 	    (hdmi->vic == 2) || (hdmi->vic == 3) ||
2139 	    (hdmi->vic == 17) || (hdmi->vic == 18))
2140 		hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
2141 	else
2142 		hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
2143 
2144 	hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
2145 	hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
2146 
2147 	if (hdmi->hdmi_data.enc_in_bus_format == MEDIA_BUS_FMT_FIXED)
2148 		hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2149 
2150 	/* TOFIX: Get input encoding from plat data or fallback to none */
2151 	if (hdmi->plat_data->input_bus_encoding)
2152 		hdmi->hdmi_data.enc_in_encoding =
2153 			hdmi->plat_data->input_bus_encoding;
2154 	else
2155 		hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
2156 
2157 	if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_FIXED)
2158 		hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2159 
2160 	hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi &&
2161 		drm_default_rgb_quant_range(mode) ==
2162 		HDMI_QUANTIZATION_RANGE_LIMITED;
2163 
2164 	hdmi->hdmi_data.pix_repet_factor = 0;
2165 	hdmi->hdmi_data.hdcp_enable = 0;
2166 	hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
2167 
2168 	/* HDMI Initialization Step B.1 */
2169 	hdmi_av_composer(hdmi, &connector->display_info, mode);
2170 
2171 	/* HDMI Initializateion Step B.2 */
2172 	ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data,
2173 				  &connector->display_info,
2174 				  &hdmi->previous_mode);
2175 	if (ret)
2176 		return ret;
2177 	hdmi->phy.enabled = true;
2178 
2179 	/* HDMI Initialization Step B.3 */
2180 	dw_hdmi_enable_video_path(hdmi);
2181 
2182 	if (hdmi->sink_has_audio) {
2183 		dev_dbg(hdmi->dev, "sink has audio support\n");
2184 
2185 		/* HDMI Initialization Step E - Configure audio */
2186 		hdmi_clk_regenerator_update_pixel_clock(hdmi);
2187 		hdmi_enable_audio_clk(hdmi, hdmi->audio_enable);
2188 	}
2189 
2190 	/* not for DVI mode */
2191 	if (hdmi->sink_is_hdmi) {
2192 		dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
2193 
2194 		/* HDMI Initialization Step F - Configure AVI InfoFrame */
2195 		hdmi_config_AVI(hdmi, connector, mode);
2196 		hdmi_config_vendor_specific_infoframe(hdmi, connector, mode);
2197 		hdmi_config_drm_infoframe(hdmi, connector);
2198 	} else {
2199 		dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
2200 	}
2201 
2202 	hdmi_video_packetize(hdmi);
2203 	hdmi_video_csc(hdmi);
2204 	hdmi_video_sample(hdmi);
2205 	hdmi_tx_hdcp_config(hdmi);
2206 
2207 	dw_hdmi_clear_overflow(hdmi);
2208 
2209 	return 0;
2210 }
2211 
2212 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
2213 {
2214 	u8 ih_mute;
2215 
2216 	/*
2217 	 * Boot up defaults are:
2218 	 * HDMI_IH_MUTE   = 0x03 (disabled)
2219 	 * HDMI_IH_MUTE_* = 0x00 (enabled)
2220 	 *
2221 	 * Disable top level interrupt bits in HDMI block
2222 	 */
2223 	ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
2224 		  HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2225 		  HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
2226 
2227 	hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2228 
2229 	/* by default mask all interrupts */
2230 	hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
2231 	hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
2232 	hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
2233 	hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
2234 	hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
2235 	hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
2236 	hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
2237 	hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
2238 	hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
2239 	hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
2240 	hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
2241 	hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
2242 	hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
2243 	hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
2244 
2245 	/* Disable interrupts in the IH_MUTE_* registers */
2246 	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
2247 	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
2248 	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
2249 	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
2250 	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
2251 	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
2252 	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
2253 	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
2254 	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
2255 	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
2256 
2257 	/* Enable top level interrupt bits in HDMI block */
2258 	ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2259 		    HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
2260 	hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2261 }
2262 
2263 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
2264 {
2265 	hdmi->bridge_is_on = true;
2266 
2267 	/*
2268 	 * The curr_conn field is guaranteed to be valid here, as this function
2269 	 * is only be called when !hdmi->disabled.
2270 	 */
2271 	dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
2272 }
2273 
2274 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
2275 {
2276 	if (hdmi->phy.enabled) {
2277 		hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
2278 		hdmi->phy.enabled = false;
2279 	}
2280 
2281 	hdmi->bridge_is_on = false;
2282 }
2283 
2284 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
2285 {
2286 	int force = hdmi->force;
2287 
2288 	if (hdmi->disabled) {
2289 		force = DRM_FORCE_OFF;
2290 	} else if (force == DRM_FORCE_UNSPECIFIED) {
2291 		if (hdmi->rxsense)
2292 			force = DRM_FORCE_ON;
2293 		else
2294 			force = DRM_FORCE_OFF;
2295 	}
2296 
2297 	if (force == DRM_FORCE_OFF) {
2298 		if (hdmi->bridge_is_on)
2299 			dw_hdmi_poweroff(hdmi);
2300 	} else {
2301 		if (!hdmi->bridge_is_on)
2302 			dw_hdmi_poweron(hdmi);
2303 	}
2304 }
2305 
2306 /*
2307  * Adjust the detection of RXSENSE according to whether we have a forced
2308  * connection mode enabled, or whether we have been disabled.  There is
2309  * no point processing RXSENSE interrupts if we have a forced connection
2310  * state, or DRM has us disabled.
2311  *
2312  * We also disable rxsense interrupts when we think we're disconnected
2313  * to avoid floating TDMS signals giving false rxsense interrupts.
2314  *
2315  * Note: we still need to listen for HPD interrupts even when DRM has us
2316  * disabled so that we can detect a connect event.
2317  */
2318 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
2319 {
2320 	if (hdmi->phy.ops->update_hpd)
2321 		hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
2322 					  hdmi->force, hdmi->disabled,
2323 					  hdmi->rxsense);
2324 }
2325 
2326 static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi)
2327 {
2328 	enum drm_connector_status result;
2329 
2330 	result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
2331 
2332 	mutex_lock(&hdmi->mutex);
2333 	if (result != hdmi->last_connector_result) {
2334 		dev_dbg(hdmi->dev, "read_hpd result: %d", result);
2335 		handle_plugged_change(hdmi,
2336 				      result == connector_status_connected);
2337 		hdmi->last_connector_result = result;
2338 	}
2339 	mutex_unlock(&hdmi->mutex);
2340 
2341 	return result;
2342 }
2343 
2344 static struct edid *dw_hdmi_get_edid(struct dw_hdmi *hdmi,
2345 				     struct drm_connector *connector)
2346 {
2347 	struct edid *edid;
2348 
2349 	if (!hdmi->ddc)
2350 		return NULL;
2351 
2352 	edid = drm_get_edid(connector, hdmi->ddc);
2353 	if (!edid) {
2354 		dev_dbg(hdmi->dev, "failed to get edid\n");
2355 		return NULL;
2356 	}
2357 
2358 	dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
2359 		edid->width_cm, edid->height_cm);
2360 
2361 	hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
2362 	hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2363 
2364 	return edid;
2365 }
2366 
2367 /* -----------------------------------------------------------------------------
2368  * DRM Connector Operations
2369  */
2370 
2371 static enum drm_connector_status
2372 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
2373 {
2374 	struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2375 					     connector);
2376 	return dw_hdmi_detect(hdmi);
2377 }
2378 
2379 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
2380 {
2381 	struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2382 					     connector);
2383 	struct edid *edid;
2384 	int ret;
2385 
2386 	edid = dw_hdmi_get_edid(hdmi, connector);
2387 	if (!edid)
2388 		return 0;
2389 
2390 	drm_connector_update_edid_property(connector, edid);
2391 	cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
2392 	ret = drm_add_edid_modes(connector, edid);
2393 	kfree(edid);
2394 
2395 	return ret;
2396 }
2397 
2398 static bool hdr_metadata_equal(const struct drm_connector_state *old_state,
2399 			       const struct drm_connector_state *new_state)
2400 {
2401 	struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
2402 	struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
2403 
2404 	if (!old_blob || !new_blob)
2405 		return old_blob == new_blob;
2406 
2407 	if (old_blob->length != new_blob->length)
2408 		return false;
2409 
2410 	return !memcmp(old_blob->data, new_blob->data, old_blob->length);
2411 }
2412 
2413 static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
2414 					  struct drm_atomic_state *state)
2415 {
2416 	struct drm_connector_state *old_state =
2417 		drm_atomic_get_old_connector_state(state, connector);
2418 	struct drm_connector_state *new_state =
2419 		drm_atomic_get_new_connector_state(state, connector);
2420 	struct drm_crtc *crtc = new_state->crtc;
2421 	struct drm_crtc_state *crtc_state;
2422 
2423 	if (!crtc)
2424 		return 0;
2425 
2426 	if (!hdr_metadata_equal(old_state, new_state)) {
2427 		crtc_state = drm_atomic_get_crtc_state(state, crtc);
2428 		if (IS_ERR(crtc_state))
2429 			return PTR_ERR(crtc_state);
2430 
2431 		crtc_state->mode_changed = true;
2432 	}
2433 
2434 	return 0;
2435 }
2436 
2437 static void dw_hdmi_connector_force(struct drm_connector *connector)
2438 {
2439 	struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2440 					     connector);
2441 
2442 	mutex_lock(&hdmi->mutex);
2443 	hdmi->force = connector->force;
2444 	dw_hdmi_update_power(hdmi);
2445 	dw_hdmi_update_phy_mask(hdmi);
2446 	mutex_unlock(&hdmi->mutex);
2447 }
2448 
2449 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
2450 	.fill_modes = drm_helper_probe_single_connector_modes,
2451 	.detect = dw_hdmi_connector_detect,
2452 	.destroy = drm_connector_cleanup,
2453 	.force = dw_hdmi_connector_force,
2454 	.reset = drm_atomic_helper_connector_reset,
2455 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2456 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2457 };
2458 
2459 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
2460 	.get_modes = dw_hdmi_connector_get_modes,
2461 	.atomic_check = dw_hdmi_connector_atomic_check,
2462 };
2463 
2464 static int dw_hdmi_connector_create(struct dw_hdmi *hdmi)
2465 {
2466 	struct drm_connector *connector = &hdmi->connector;
2467 	struct cec_connector_info conn_info;
2468 	struct cec_notifier *notifier;
2469 
2470 	if (hdmi->version >= 0x200a)
2471 		connector->ycbcr_420_allowed =
2472 			hdmi->plat_data->ycbcr_420_allowed;
2473 	else
2474 		connector->ycbcr_420_allowed = false;
2475 
2476 	connector->interlace_allowed = 1;
2477 	connector->polled = DRM_CONNECTOR_POLL_HPD;
2478 
2479 	drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
2480 
2481 	drm_connector_init_with_ddc(hdmi->bridge.dev, connector,
2482 				    &dw_hdmi_connector_funcs,
2483 				    DRM_MODE_CONNECTOR_HDMIA,
2484 				    hdmi->ddc);
2485 
2486 	/*
2487 	 * drm_connector_attach_max_bpc_property() requires the
2488 	 * connector to have a state.
2489 	 */
2490 	drm_atomic_helper_connector_reset(connector);
2491 
2492 	drm_connector_attach_max_bpc_property(connector, 8, 16);
2493 
2494 	if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe)
2495 		drm_object_attach_property(&connector->base,
2496 			connector->dev->mode_config.hdr_output_metadata_property, 0);
2497 
2498 	drm_connector_attach_encoder(connector, hdmi->bridge.encoder);
2499 
2500 	cec_fill_conn_info_from_drm(&conn_info, connector);
2501 
2502 	notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);
2503 	if (!notifier)
2504 		return -ENOMEM;
2505 
2506 	mutex_lock(&hdmi->cec_notifier_mutex);
2507 	hdmi->cec_notifier = notifier;
2508 	mutex_unlock(&hdmi->cec_notifier_mutex);
2509 
2510 	return 0;
2511 }
2512 
2513 /* -----------------------------------------------------------------------------
2514  * DRM Bridge Operations
2515  */
2516 
2517 /*
2518  * Possible output formats :
2519  * - MEDIA_BUS_FMT_UYYVYY16_0_5X48,
2520  * - MEDIA_BUS_FMT_UYYVYY12_0_5X36,
2521  * - MEDIA_BUS_FMT_UYYVYY10_0_5X30,
2522  * - MEDIA_BUS_FMT_UYYVYY8_0_5X24,
2523  * - MEDIA_BUS_FMT_YUV16_1X48,
2524  * - MEDIA_BUS_FMT_RGB161616_1X48,
2525  * - MEDIA_BUS_FMT_UYVY12_1X24,
2526  * - MEDIA_BUS_FMT_YUV12_1X36,
2527  * - MEDIA_BUS_FMT_RGB121212_1X36,
2528  * - MEDIA_BUS_FMT_UYVY10_1X20,
2529  * - MEDIA_BUS_FMT_YUV10_1X30,
2530  * - MEDIA_BUS_FMT_RGB101010_1X30,
2531  * - MEDIA_BUS_FMT_UYVY8_1X16,
2532  * - MEDIA_BUS_FMT_YUV8_1X24,
2533  * - MEDIA_BUS_FMT_RGB888_1X24,
2534  */
2535 
2536 /* Can return a maximum of 11 possible output formats for a mode/connector */
2537 #define MAX_OUTPUT_SEL_FORMATS	11
2538 
2539 static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
2540 					struct drm_bridge_state *bridge_state,
2541 					struct drm_crtc_state *crtc_state,
2542 					struct drm_connector_state *conn_state,
2543 					unsigned int *num_output_fmts)
2544 {
2545 	struct drm_connector *conn = conn_state->connector;
2546 	struct drm_display_info *info = &conn->display_info;
2547 	struct drm_display_mode *mode = &crtc_state->mode;
2548 	u8 max_bpc = conn_state->max_requested_bpc;
2549 	bool is_hdmi2_sink = info->hdmi.scdc.supported ||
2550 			     (info->color_formats & DRM_COLOR_FORMAT_YCRCB420);
2551 	u32 *output_fmts;
2552 	unsigned int i = 0;
2553 
2554 	*num_output_fmts = 0;
2555 
2556 	output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
2557 			      GFP_KERNEL);
2558 	if (!output_fmts)
2559 		return NULL;
2560 
2561 	/* If dw-hdmi is the only bridge, avoid negociating with ourselves */
2562 	if (list_is_singular(&bridge->encoder->bridge_chain)) {
2563 		*num_output_fmts = 1;
2564 		output_fmts[0] = MEDIA_BUS_FMT_FIXED;
2565 
2566 		return output_fmts;
2567 	}
2568 
2569 	/*
2570 	 * If the current mode enforces 4:2:0, force the output but format
2571 	 * to 4:2:0 and do not add the YUV422/444/RGB formats
2572 	 */
2573 	if (conn->ycbcr_420_allowed &&
2574 	    (drm_mode_is_420_only(info, mode) ||
2575 	     (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) {
2576 
2577 		/* Order bus formats from 16bit to 8bit if supported */
2578 		if (max_bpc >= 16 && info->bpc == 16 &&
2579 		    (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48))
2580 			output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48;
2581 
2582 		if (max_bpc >= 12 && info->bpc >= 12 &&
2583 		    (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
2584 			output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36;
2585 
2586 		if (max_bpc >= 10 && info->bpc >= 10 &&
2587 		    (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30))
2588 			output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30;
2589 
2590 		/* Default 8bit fallback */
2591 		output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24;
2592 
2593 		*num_output_fmts = i;
2594 
2595 		return output_fmts;
2596 	}
2597 
2598 	/*
2599 	 * Order bus formats from 16bit to 8bit and from YUV422 to RGB
2600 	 * if supported. In any case the default RGB888 format is added
2601 	 */
2602 
2603 	if (max_bpc >= 16 && info->bpc == 16) {
2604 		if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
2605 			output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
2606 
2607 		output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
2608 	}
2609 
2610 	if (max_bpc >= 12 && info->bpc >= 12) {
2611 		if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
2612 			output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2613 
2614 		if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
2615 			output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2616 
2617 		output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2618 	}
2619 
2620 	if (max_bpc >= 10 && info->bpc >= 10) {
2621 		if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
2622 			output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2623 
2624 		if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
2625 			output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
2626 
2627 		output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
2628 	}
2629 
2630 	if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
2631 		output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2632 
2633 	if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
2634 		output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2635 
2636 	/* Default 8bit RGB fallback */
2637 	output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2638 
2639 	*num_output_fmts = i;
2640 
2641 	return output_fmts;
2642 }
2643 
2644 /*
2645  * Possible input formats :
2646  * - MEDIA_BUS_FMT_RGB888_1X24
2647  * - MEDIA_BUS_FMT_YUV8_1X24
2648  * - MEDIA_BUS_FMT_UYVY8_1X16
2649  * - MEDIA_BUS_FMT_UYYVYY8_0_5X24
2650  * - MEDIA_BUS_FMT_RGB101010_1X30
2651  * - MEDIA_BUS_FMT_YUV10_1X30
2652  * - MEDIA_BUS_FMT_UYVY10_1X20
2653  * - MEDIA_BUS_FMT_UYYVYY10_0_5X30
2654  * - MEDIA_BUS_FMT_RGB121212_1X36
2655  * - MEDIA_BUS_FMT_YUV12_1X36
2656  * - MEDIA_BUS_FMT_UYVY12_1X24
2657  * - MEDIA_BUS_FMT_UYYVYY12_0_5X36
2658  * - MEDIA_BUS_FMT_RGB161616_1X48
2659  * - MEDIA_BUS_FMT_YUV16_1X48
2660  * - MEDIA_BUS_FMT_UYYVYY16_0_5X48
2661  */
2662 
2663 /* Can return a maximum of 3 possible input formats for an output format */
2664 #define MAX_INPUT_SEL_FORMATS	3
2665 
2666 static u32 *dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
2667 					struct drm_bridge_state *bridge_state,
2668 					struct drm_crtc_state *crtc_state,
2669 					struct drm_connector_state *conn_state,
2670 					u32 output_fmt,
2671 					unsigned int *num_input_fmts)
2672 {
2673 	u32 *input_fmts;
2674 	unsigned int i = 0;
2675 
2676 	*num_input_fmts = 0;
2677 
2678 	input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
2679 			     GFP_KERNEL);
2680 	if (!input_fmts)
2681 		return NULL;
2682 
2683 	switch (output_fmt) {
2684 	/* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */
2685 	case MEDIA_BUS_FMT_FIXED:
2686 		input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2687 		break;
2688 	/* 8bit */
2689 	case MEDIA_BUS_FMT_RGB888_1X24:
2690 		input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2691 		input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2692 		input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2693 		break;
2694 	case MEDIA_BUS_FMT_YUV8_1X24:
2695 		input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2696 		input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2697 		input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2698 		break;
2699 	case MEDIA_BUS_FMT_UYVY8_1X16:
2700 		input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2701 		input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2702 		input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2703 		break;
2704 
2705 	/* 10bit */
2706 	case MEDIA_BUS_FMT_RGB101010_1X30:
2707 		input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
2708 		input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
2709 		input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2710 		break;
2711 	case MEDIA_BUS_FMT_YUV10_1X30:
2712 		input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
2713 		input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2714 		input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
2715 		break;
2716 	case MEDIA_BUS_FMT_UYVY10_1X20:
2717 		input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2718 		input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
2719 		input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
2720 		break;
2721 
2722 	/* 12bit */
2723 	case MEDIA_BUS_FMT_RGB121212_1X36:
2724 		input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2725 		input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2726 		input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2727 		break;
2728 	case MEDIA_BUS_FMT_YUV12_1X36:
2729 		input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2730 		input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2731 		input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2732 		break;
2733 	case MEDIA_BUS_FMT_UYVY12_1X24:
2734 		input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2735 		input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2736 		input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2737 		break;
2738 
2739 	/* 16bit */
2740 	case MEDIA_BUS_FMT_RGB161616_1X48:
2741 		input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
2742 		input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
2743 		break;
2744 	case MEDIA_BUS_FMT_YUV16_1X48:
2745 		input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
2746 		input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
2747 		break;
2748 
2749 	/*YUV 4:2:0 */
2750 	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
2751 	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
2752 	case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
2753 	case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
2754 		input_fmts[i++] = output_fmt;
2755 		break;
2756 	}
2757 
2758 	*num_input_fmts = i;
2759 
2760 	if (*num_input_fmts == 0) {
2761 		kfree(input_fmts);
2762 		input_fmts = NULL;
2763 	}
2764 
2765 	return input_fmts;
2766 }
2767 
2768 static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge,
2769 				       struct drm_bridge_state *bridge_state,
2770 				       struct drm_crtc_state *crtc_state,
2771 				       struct drm_connector_state *conn_state)
2772 {
2773 	struct dw_hdmi *hdmi = bridge->driver_private;
2774 
2775 	hdmi->hdmi_data.enc_out_bus_format =
2776 			bridge_state->output_bus_cfg.format;
2777 
2778 	hdmi->hdmi_data.enc_in_bus_format =
2779 			bridge_state->input_bus_cfg.format;
2780 
2781 	dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n",
2782 		bridge_state->input_bus_cfg.format,
2783 		bridge_state->output_bus_cfg.format);
2784 
2785 	return 0;
2786 }
2787 
2788 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge,
2789 				 enum drm_bridge_attach_flags flags)
2790 {
2791 	struct dw_hdmi *hdmi = bridge->driver_private;
2792 
2793 	if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
2794 		return 0;
2795 
2796 	return dw_hdmi_connector_create(hdmi);
2797 }
2798 
2799 static void dw_hdmi_bridge_detach(struct drm_bridge *bridge)
2800 {
2801 	struct dw_hdmi *hdmi = bridge->driver_private;
2802 
2803 	mutex_lock(&hdmi->cec_notifier_mutex);
2804 	cec_notifier_conn_unregister(hdmi->cec_notifier);
2805 	hdmi->cec_notifier = NULL;
2806 	mutex_unlock(&hdmi->cec_notifier_mutex);
2807 }
2808 
2809 static enum drm_mode_status
2810 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
2811 			  const struct drm_display_info *info,
2812 			  const struct drm_display_mode *mode)
2813 {
2814 	struct dw_hdmi *hdmi = bridge->driver_private;
2815 	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
2816 	enum drm_mode_status mode_status = MODE_OK;
2817 
2818 	/* We don't support double-clocked modes */
2819 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2820 		return MODE_BAD;
2821 
2822 	if (pdata->mode_valid)
2823 		mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info,
2824 						mode);
2825 
2826 	return mode_status;
2827 }
2828 
2829 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
2830 				    const struct drm_display_mode *orig_mode,
2831 				    const struct drm_display_mode *mode)
2832 {
2833 	struct dw_hdmi *hdmi = bridge->driver_private;
2834 
2835 	mutex_lock(&hdmi->mutex);
2836 
2837 	/* Store the display mode for plugin/DKMS poweron events */
2838 	memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2839 
2840 	mutex_unlock(&hdmi->mutex);
2841 }
2842 
2843 static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
2844 					  struct drm_bridge_state *old_state)
2845 {
2846 	struct dw_hdmi *hdmi = bridge->driver_private;
2847 
2848 	mutex_lock(&hdmi->mutex);
2849 	hdmi->disabled = true;
2850 	hdmi->curr_conn = NULL;
2851 	dw_hdmi_update_power(hdmi);
2852 	dw_hdmi_update_phy_mask(hdmi);
2853 	mutex_unlock(&hdmi->mutex);
2854 }
2855 
2856 static void dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
2857 					 struct drm_bridge_state *old_state)
2858 {
2859 	struct dw_hdmi *hdmi = bridge->driver_private;
2860 	struct drm_atomic_state *state = old_state->base.state;
2861 	struct drm_connector *connector;
2862 
2863 	connector = drm_atomic_get_new_connector_for_encoder(state,
2864 							     bridge->encoder);
2865 
2866 	mutex_lock(&hdmi->mutex);
2867 	hdmi->disabled = false;
2868 	hdmi->curr_conn = connector;
2869 	dw_hdmi_update_power(hdmi);
2870 	dw_hdmi_update_phy_mask(hdmi);
2871 	mutex_unlock(&hdmi->mutex);
2872 }
2873 
2874 static enum drm_connector_status dw_hdmi_bridge_detect(struct drm_bridge *bridge)
2875 {
2876 	struct dw_hdmi *hdmi = bridge->driver_private;
2877 
2878 	return dw_hdmi_detect(hdmi);
2879 }
2880 
2881 static struct edid *dw_hdmi_bridge_get_edid(struct drm_bridge *bridge,
2882 					    struct drm_connector *connector)
2883 {
2884 	struct dw_hdmi *hdmi = bridge->driver_private;
2885 
2886 	return dw_hdmi_get_edid(hdmi, connector);
2887 }
2888 
2889 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2890 	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
2891 	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
2892 	.atomic_reset = drm_atomic_helper_bridge_reset,
2893 	.attach = dw_hdmi_bridge_attach,
2894 	.detach = dw_hdmi_bridge_detach,
2895 	.atomic_check = dw_hdmi_bridge_atomic_check,
2896 	.atomic_get_output_bus_fmts = dw_hdmi_bridge_atomic_get_output_bus_fmts,
2897 	.atomic_get_input_bus_fmts = dw_hdmi_bridge_atomic_get_input_bus_fmts,
2898 	.atomic_enable = dw_hdmi_bridge_atomic_enable,
2899 	.atomic_disable = dw_hdmi_bridge_atomic_disable,
2900 	.mode_set = dw_hdmi_bridge_mode_set,
2901 	.mode_valid = dw_hdmi_bridge_mode_valid,
2902 	.detect = dw_hdmi_bridge_detect,
2903 	.get_edid = dw_hdmi_bridge_get_edid,
2904 };
2905 
2906 /* -----------------------------------------------------------------------------
2907  * IRQ Handling
2908  */
2909 
2910 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2911 {
2912 	struct dw_hdmi_i2c *i2c = hdmi->i2c;
2913 	unsigned int stat;
2914 
2915 	stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2916 	if (!stat)
2917 		return IRQ_NONE;
2918 
2919 	hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2920 
2921 	i2c->stat = stat;
2922 
2923 	complete(&i2c->cmp);
2924 
2925 	return IRQ_HANDLED;
2926 }
2927 
2928 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
2929 {
2930 	struct dw_hdmi *hdmi = dev_id;
2931 	u8 intr_stat;
2932 	irqreturn_t ret = IRQ_NONE;
2933 
2934 	if (hdmi->i2c)
2935 		ret = dw_hdmi_i2c_irq(hdmi);
2936 
2937 	intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2938 	if (intr_stat) {
2939 		hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2940 		return IRQ_WAKE_THREAD;
2941 	}
2942 
2943 	return ret;
2944 }
2945 
2946 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
2947 {
2948 	mutex_lock(&hdmi->mutex);
2949 
2950 	if (!hdmi->force) {
2951 		/*
2952 		 * If the RX sense status indicates we're disconnected,
2953 		 * clear the software rxsense status.
2954 		 */
2955 		if (!rx_sense)
2956 			hdmi->rxsense = false;
2957 
2958 		/*
2959 		 * Only set the software rxsense status when both
2960 		 * rxsense and hpd indicates we're connected.
2961 		 * This avoids what seems to be bad behaviour in
2962 		 * at least iMX6S versions of the phy.
2963 		 */
2964 		if (hpd)
2965 			hdmi->rxsense = true;
2966 
2967 		dw_hdmi_update_power(hdmi);
2968 		dw_hdmi_update_phy_mask(hdmi);
2969 	}
2970 	mutex_unlock(&hdmi->mutex);
2971 }
2972 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
2973 
2974 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
2975 {
2976 	struct dw_hdmi *hdmi = dev_id;
2977 	u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
2978 
2979 	intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2980 	phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
2981 	phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2982 
2983 	phy_pol_mask = 0;
2984 	if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2985 		phy_pol_mask |= HDMI_PHY_HPD;
2986 	if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2987 		phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2988 	if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2989 		phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2990 	if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2991 		phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2992 	if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2993 		phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2994 
2995 	if (phy_pol_mask)
2996 		hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2997 
2998 	/*
2999 	 * RX sense tells us whether the TDMS transmitters are detecting
3000 	 * load - in other words, there's something listening on the
3001 	 * other end of the link.  Use this to decide whether we should
3002 	 * power on the phy as HPD may be toggled by the sink to merely
3003 	 * ask the source to re-read the EDID.
3004 	 */
3005 	if (intr_stat &
3006 	    (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
3007 		dw_hdmi_setup_rx_sense(hdmi,
3008 				       phy_stat & HDMI_PHY_HPD,
3009 				       phy_stat & HDMI_PHY_RX_SENSE);
3010 
3011 		if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) {
3012 			mutex_lock(&hdmi->cec_notifier_mutex);
3013 			cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
3014 			mutex_unlock(&hdmi->cec_notifier_mutex);
3015 		}
3016 	}
3017 
3018 	if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
3019 		enum drm_connector_status status = phy_int_pol & HDMI_PHY_HPD
3020 						 ? connector_status_connected
3021 						 : connector_status_disconnected;
3022 
3023 		dev_dbg(hdmi->dev, "EVENT=%s\n",
3024 			status == connector_status_connected ?
3025 			"plugin" : "plugout");
3026 
3027 		if (hdmi->bridge.dev) {
3028 			drm_helper_hpd_irq_event(hdmi->bridge.dev);
3029 			drm_bridge_hpd_notify(&hdmi->bridge, status);
3030 		}
3031 	}
3032 
3033 	hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
3034 	hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
3035 		    HDMI_IH_MUTE_PHY_STAT0);
3036 
3037 	return IRQ_HANDLED;
3038 }
3039 
3040 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
3041 	{
3042 		.type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
3043 		.name = "DWC HDMI TX PHY",
3044 		.gen = 1,
3045 	}, {
3046 		.type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
3047 		.name = "DWC MHL PHY + HEAC PHY",
3048 		.gen = 2,
3049 		.has_svsret = true,
3050 		.configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3051 	}, {
3052 		.type = DW_HDMI_PHY_DWC_MHL_PHY,
3053 		.name = "DWC MHL PHY",
3054 		.gen = 2,
3055 		.has_svsret = true,
3056 		.configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3057 	}, {
3058 		.type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
3059 		.name = "DWC HDMI 3D TX PHY + HEAC PHY",
3060 		.gen = 2,
3061 		.configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3062 	}, {
3063 		.type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
3064 		.name = "DWC HDMI 3D TX PHY",
3065 		.gen = 2,
3066 		.configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3067 	}, {
3068 		.type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
3069 		.name = "DWC HDMI 2.0 TX PHY",
3070 		.gen = 2,
3071 		.has_svsret = true,
3072 		.configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3073 	}, {
3074 		.type = DW_HDMI_PHY_VENDOR_PHY,
3075 		.name = "Vendor PHY",
3076 	}
3077 };
3078 
3079 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
3080 {
3081 	unsigned int i;
3082 	u8 phy_type;
3083 
3084 	phy_type = hdmi->plat_data->phy_force_vendor ?
3085 				DW_HDMI_PHY_VENDOR_PHY :
3086 				hdmi_readb(hdmi, HDMI_CONFIG2_ID);
3087 
3088 	if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
3089 		/* Vendor PHYs require support from the glue layer. */
3090 		if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
3091 			dev_err(hdmi->dev,
3092 				"Vendor HDMI PHY not supported by glue layer\n");
3093 			return -ENODEV;
3094 		}
3095 
3096 		hdmi->phy.ops = hdmi->plat_data->phy_ops;
3097 		hdmi->phy.data = hdmi->plat_data->phy_data;
3098 		hdmi->phy.name = hdmi->plat_data->phy_name;
3099 		return 0;
3100 	}
3101 
3102 	/* Synopsys PHYs are handled internally. */
3103 	for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
3104 		if (dw_hdmi_phys[i].type == phy_type) {
3105 			hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
3106 			hdmi->phy.name = dw_hdmi_phys[i].name;
3107 			hdmi->phy.data = (void *)&dw_hdmi_phys[i];
3108 
3109 			if (!dw_hdmi_phys[i].configure &&
3110 			    !hdmi->plat_data->configure_phy) {
3111 				dev_err(hdmi->dev, "%s requires platform support\n",
3112 					hdmi->phy.name);
3113 				return -ENODEV;
3114 			}
3115 
3116 			return 0;
3117 		}
3118 	}
3119 
3120 	dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
3121 	return -ENODEV;
3122 }
3123 
3124 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
3125 {
3126 	mutex_lock(&hdmi->mutex);
3127 	hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
3128 	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
3129 	mutex_unlock(&hdmi->mutex);
3130 }
3131 
3132 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
3133 {
3134 	mutex_lock(&hdmi->mutex);
3135 	hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
3136 	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
3137 	mutex_unlock(&hdmi->mutex);
3138 }
3139 
3140 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
3141 	.write = hdmi_writeb,
3142 	.read = hdmi_readb,
3143 	.enable = dw_hdmi_cec_enable,
3144 	.disable = dw_hdmi_cec_disable,
3145 };
3146 
3147 static const struct regmap_config hdmi_regmap_8bit_config = {
3148 	.reg_bits	= 32,
3149 	.val_bits	= 8,
3150 	.reg_stride	= 1,
3151 	.max_register	= HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
3152 };
3153 
3154 static const struct regmap_config hdmi_regmap_32bit_config = {
3155 	.reg_bits	= 32,
3156 	.val_bits	= 32,
3157 	.reg_stride	= 4,
3158 	.max_register	= HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
3159 };
3160 
3161 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi)
3162 {
3163 	initialize_hdmi_ih_mutes(hdmi);
3164 
3165 	/*
3166 	 * Reset HDMI DDC I2C master controller and mute I2CM interrupts.
3167 	 * Even if we are using a separate i2c adapter doing this doesn't
3168 	 * hurt.
3169 	 */
3170 	dw_hdmi_i2c_init(hdmi);
3171 
3172 	if (hdmi->phy.ops->setup_hpd)
3173 		hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
3174 }
3175 
3176 /* -----------------------------------------------------------------------------
3177  * Probe/remove API, used from platforms based on the DRM bridge API.
3178  */
3179 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
3180 			      const struct dw_hdmi_plat_data *plat_data)
3181 {
3182 	struct device *dev = &pdev->dev;
3183 	struct device_node *np = dev->of_node;
3184 	struct platform_device_info pdevinfo;
3185 	struct device_node *ddc_node;
3186 	struct dw_hdmi_cec_data cec;
3187 	struct dw_hdmi *hdmi;
3188 	struct resource *iores = NULL;
3189 	int irq;
3190 	int ret;
3191 	u32 val = 1;
3192 	u8 prod_id0;
3193 	u8 prod_id1;
3194 	u8 config0;
3195 	u8 config3;
3196 
3197 	hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
3198 	if (!hdmi)
3199 		return ERR_PTR(-ENOMEM);
3200 
3201 	hdmi->plat_data = plat_data;
3202 	hdmi->dev = dev;
3203 	hdmi->sample_rate = 48000;
3204 	hdmi->disabled = true;
3205 	hdmi->rxsense = true;
3206 	hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
3207 	hdmi->mc_clkdis = 0x7f;
3208 	hdmi->last_connector_result = connector_status_disconnected;
3209 
3210 	mutex_init(&hdmi->mutex);
3211 	mutex_init(&hdmi->audio_mutex);
3212 	mutex_init(&hdmi->cec_notifier_mutex);
3213 	spin_lock_init(&hdmi->audio_lock);
3214 
3215 	ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
3216 	if (ddc_node) {
3217 		hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
3218 		of_node_put(ddc_node);
3219 		if (!hdmi->ddc) {
3220 			dev_dbg(hdmi->dev, "failed to read ddc node\n");
3221 			return ERR_PTR(-EPROBE_DEFER);
3222 		}
3223 
3224 	} else {
3225 		dev_dbg(hdmi->dev, "no ddc property found\n");
3226 	}
3227 
3228 	if (!plat_data->regm) {
3229 		const struct regmap_config *reg_config;
3230 
3231 		of_property_read_u32(np, "reg-io-width", &val);
3232 		switch (val) {
3233 		case 4:
3234 			reg_config = &hdmi_regmap_32bit_config;
3235 			hdmi->reg_shift = 2;
3236 			break;
3237 		case 1:
3238 			reg_config = &hdmi_regmap_8bit_config;
3239 			break;
3240 		default:
3241 			dev_err(dev, "reg-io-width must be 1 or 4\n");
3242 			return ERR_PTR(-EINVAL);
3243 		}
3244 
3245 		iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3246 		hdmi->regs = devm_ioremap_resource(dev, iores);
3247 		if (IS_ERR(hdmi->regs)) {
3248 			ret = PTR_ERR(hdmi->regs);
3249 			goto err_res;
3250 		}
3251 
3252 		hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
3253 		if (IS_ERR(hdmi->regm)) {
3254 			dev_err(dev, "Failed to configure regmap\n");
3255 			ret = PTR_ERR(hdmi->regm);
3256 			goto err_res;
3257 		}
3258 	} else {
3259 		hdmi->regm = plat_data->regm;
3260 	}
3261 
3262 	hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
3263 	if (IS_ERR(hdmi->isfr_clk)) {
3264 		ret = PTR_ERR(hdmi->isfr_clk);
3265 		dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
3266 		goto err_res;
3267 	}
3268 
3269 	ret = clk_prepare_enable(hdmi->isfr_clk);
3270 	if (ret) {
3271 		dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
3272 		goto err_res;
3273 	}
3274 
3275 	hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
3276 	if (IS_ERR(hdmi->iahb_clk)) {
3277 		ret = PTR_ERR(hdmi->iahb_clk);
3278 		dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
3279 		goto err_isfr;
3280 	}
3281 
3282 	ret = clk_prepare_enable(hdmi->iahb_clk);
3283 	if (ret) {
3284 		dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
3285 		goto err_isfr;
3286 	}
3287 
3288 	hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec");
3289 	if (PTR_ERR(hdmi->cec_clk) == -ENOENT) {
3290 		hdmi->cec_clk = NULL;
3291 	} else if (IS_ERR(hdmi->cec_clk)) {
3292 		ret = PTR_ERR(hdmi->cec_clk);
3293 		if (ret != -EPROBE_DEFER)
3294 			dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
3295 				ret);
3296 
3297 		hdmi->cec_clk = NULL;
3298 		goto err_iahb;
3299 	} else {
3300 		ret = clk_prepare_enable(hdmi->cec_clk);
3301 		if (ret) {
3302 			dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n",
3303 				ret);
3304 			goto err_iahb;
3305 		}
3306 	}
3307 
3308 	/* Product and revision IDs */
3309 	hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
3310 		      | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
3311 	prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
3312 	prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
3313 
3314 	if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
3315 	    (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
3316 		dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
3317 			hdmi->version, prod_id0, prod_id1);
3318 		ret = -ENODEV;
3319 		goto err_iahb;
3320 	}
3321 
3322 	ret = dw_hdmi_detect_phy(hdmi);
3323 	if (ret < 0)
3324 		goto err_iahb;
3325 
3326 	dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
3327 		 hdmi->version >> 12, hdmi->version & 0xfff,
3328 		 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
3329 		 hdmi->phy.name);
3330 
3331 	dw_hdmi_init_hw(hdmi);
3332 
3333 	irq = platform_get_irq(pdev, 0);
3334 	if (irq < 0) {
3335 		ret = irq;
3336 		goto err_iahb;
3337 	}
3338 
3339 	ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
3340 					dw_hdmi_irq, IRQF_SHARED,
3341 					dev_name(dev), hdmi);
3342 	if (ret)
3343 		goto err_iahb;
3344 
3345 	/*
3346 	 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
3347 	 * N and cts values before enabling phy
3348 	 */
3349 	hdmi_init_clk_regenerator(hdmi);
3350 
3351 	/* If DDC bus is not specified, try to register HDMI I2C bus */
3352 	if (!hdmi->ddc) {
3353 		/* Look for (optional) stuff related to unwedging */
3354 		hdmi->pinctrl = devm_pinctrl_get(dev);
3355 		if (!IS_ERR(hdmi->pinctrl)) {
3356 			hdmi->unwedge_state =
3357 				pinctrl_lookup_state(hdmi->pinctrl, "unwedge");
3358 			hdmi->default_state =
3359 				pinctrl_lookup_state(hdmi->pinctrl, "default");
3360 
3361 			if (IS_ERR(hdmi->default_state) ||
3362 			    IS_ERR(hdmi->unwedge_state)) {
3363 				if (!IS_ERR(hdmi->unwedge_state))
3364 					dev_warn(dev,
3365 						 "Unwedge requires default pinctrl\n");
3366 				hdmi->default_state = NULL;
3367 				hdmi->unwedge_state = NULL;
3368 			}
3369 		}
3370 
3371 		hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
3372 		if (IS_ERR(hdmi->ddc))
3373 			hdmi->ddc = NULL;
3374 	}
3375 
3376 	hdmi->bridge.driver_private = hdmi;
3377 	hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
3378 	hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
3379 			 | DRM_BRIDGE_OP_HPD;
3380 #ifdef CONFIG_OF
3381 	hdmi->bridge.of_node = pdev->dev.of_node;
3382 #endif
3383 
3384 	memset(&pdevinfo, 0, sizeof(pdevinfo));
3385 	pdevinfo.parent = dev;
3386 	pdevinfo.id = PLATFORM_DEVID_AUTO;
3387 
3388 	config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
3389 	config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
3390 
3391 	if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {
3392 		struct dw_hdmi_audio_data audio;
3393 
3394 		audio.phys = iores->start;
3395 		audio.base = hdmi->regs;
3396 		audio.irq = irq;
3397 		audio.hdmi = hdmi;
3398 		audio.eld = hdmi->connector.eld;
3399 		hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
3400 		hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
3401 
3402 		pdevinfo.name = "dw-hdmi-ahb-audio";
3403 		pdevinfo.data = &audio;
3404 		pdevinfo.size_data = sizeof(audio);
3405 		pdevinfo.dma_mask = DMA_BIT_MASK(32);
3406 		hdmi->audio = platform_device_register_full(&pdevinfo);
3407 	} else if (config0 & HDMI_CONFIG0_I2S) {
3408 		struct dw_hdmi_i2s_audio_data audio;
3409 
3410 		audio.hdmi	= hdmi;
3411 		audio.eld	= hdmi->connector.eld;
3412 		audio.write	= hdmi_writeb;
3413 		audio.read	= hdmi_readb;
3414 		hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
3415 		hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
3416 
3417 		pdevinfo.name = "dw-hdmi-i2s-audio";
3418 		pdevinfo.data = &audio;
3419 		pdevinfo.size_data = sizeof(audio);
3420 		pdevinfo.dma_mask = DMA_BIT_MASK(32);
3421 		hdmi->audio = platform_device_register_full(&pdevinfo);
3422 	}
3423 
3424 	if (config0 & HDMI_CONFIG0_CEC) {
3425 		cec.hdmi = hdmi;
3426 		cec.ops = &dw_hdmi_cec_ops;
3427 		cec.irq = irq;
3428 
3429 		pdevinfo.name = "dw-hdmi-cec";
3430 		pdevinfo.data = &cec;
3431 		pdevinfo.size_data = sizeof(cec);
3432 		pdevinfo.dma_mask = 0;
3433 
3434 		hdmi->cec = platform_device_register_full(&pdevinfo);
3435 	}
3436 
3437 	drm_bridge_add(&hdmi->bridge);
3438 
3439 	return hdmi;
3440 
3441 err_iahb:
3442 	clk_disable_unprepare(hdmi->iahb_clk);
3443 	clk_disable_unprepare(hdmi->cec_clk);
3444 err_isfr:
3445 	clk_disable_unprepare(hdmi->isfr_clk);
3446 err_res:
3447 	i2c_put_adapter(hdmi->ddc);
3448 
3449 	return ERR_PTR(ret);
3450 }
3451 EXPORT_SYMBOL_GPL(dw_hdmi_probe);
3452 
3453 void dw_hdmi_remove(struct dw_hdmi *hdmi)
3454 {
3455 	drm_bridge_remove(&hdmi->bridge);
3456 
3457 	if (hdmi->audio && !IS_ERR(hdmi->audio))
3458 		platform_device_unregister(hdmi->audio);
3459 	if (!IS_ERR(hdmi->cec))
3460 		platform_device_unregister(hdmi->cec);
3461 
3462 	/* Disable all interrupts */
3463 	hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
3464 
3465 	clk_disable_unprepare(hdmi->iahb_clk);
3466 	clk_disable_unprepare(hdmi->isfr_clk);
3467 	clk_disable_unprepare(hdmi->cec_clk);
3468 
3469 	if (hdmi->i2c)
3470 		i2c_del_adapter(&hdmi->i2c->adap);
3471 	else
3472 		i2c_put_adapter(hdmi->ddc);
3473 }
3474 EXPORT_SYMBOL_GPL(dw_hdmi_remove);
3475 
3476 /* -----------------------------------------------------------------------------
3477  * Bind/unbind API, used from platforms based on the component framework.
3478  */
3479 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
3480 			     struct drm_encoder *encoder,
3481 			     const struct dw_hdmi_plat_data *plat_data)
3482 {
3483 	struct dw_hdmi *hdmi;
3484 	int ret;
3485 
3486 	hdmi = dw_hdmi_probe(pdev, plat_data);
3487 	if (IS_ERR(hdmi))
3488 		return hdmi;
3489 
3490 	ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0);
3491 	if (ret) {
3492 		dw_hdmi_remove(hdmi);
3493 		DRM_ERROR("Failed to initialize bridge with drm\n");
3494 		return ERR_PTR(ret);
3495 	}
3496 
3497 	return hdmi;
3498 }
3499 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
3500 
3501 void dw_hdmi_unbind(struct dw_hdmi *hdmi)
3502 {
3503 	dw_hdmi_remove(hdmi);
3504 }
3505 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
3506 
3507 void dw_hdmi_resume(struct dw_hdmi *hdmi)
3508 {
3509 	dw_hdmi_init_hw(hdmi);
3510 }
3511 EXPORT_SYMBOL_GPL(dw_hdmi_resume);
3512 
3513 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
3514 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
3515 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
3516 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
3517 MODULE_DESCRIPTION("DW HDMI transmitter driver");
3518 MODULE_LICENSE("GPL");
3519 MODULE_ALIAS("platform:dw-hdmi");
3520