1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DesignWare High-Definition Multimedia Interface (HDMI) driver 4 * 5 * Copyright (C) 2013-2015 Mentor Graphics Inc. 6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 8 */ 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/hdmi.h> 13 #include <linux/irq.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of_device.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/regmap.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/spinlock.h> 21 22 #include <media/cec-notifier.h> 23 24 #include <uapi/linux/media-bus-format.h> 25 #include <uapi/linux/videodev2.h> 26 27 #include <drm/bridge/dw_hdmi.h> 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_bridge.h> 31 #include <drm/drm_edid.h> 32 #include <drm/drm_of.h> 33 #include <drm/drm_print.h> 34 #include <drm/drm_probe_helper.h> 35 #include <drm/drm_scdc_helper.h> 36 37 #include "dw-hdmi-audio.h" 38 #include "dw-hdmi-cec.h" 39 #include "dw-hdmi.h" 40 41 #define DDC_CI_ADDR 0x37 42 #define DDC_SEGMENT_ADDR 0x30 43 44 #define HDMI_EDID_LEN 512 45 46 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ 47 #define SCDC_MIN_SOURCE_VERSION 0x1 48 49 #define HDMI14_MAX_TMDSCLK 340000000 50 51 enum hdmi_datamap { 52 RGB444_8B = 0x01, 53 RGB444_10B = 0x03, 54 RGB444_12B = 0x05, 55 RGB444_16B = 0x07, 56 YCbCr444_8B = 0x09, 57 YCbCr444_10B = 0x0B, 58 YCbCr444_12B = 0x0D, 59 YCbCr444_16B = 0x0F, 60 YCbCr422_8B = 0x16, 61 YCbCr422_10B = 0x14, 62 YCbCr422_12B = 0x12, 63 }; 64 65 static const u16 csc_coeff_default[3][4] = { 66 { 0x2000, 0x0000, 0x0000, 0x0000 }, 67 { 0x0000, 0x2000, 0x0000, 0x0000 }, 68 { 0x0000, 0x0000, 0x2000, 0x0000 } 69 }; 70 71 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 72 { 0x2000, 0x6926, 0x74fd, 0x010e }, 73 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 74 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 75 }; 76 77 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 78 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 79 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 80 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 81 }; 82 83 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 84 { 0x2591, 0x1322, 0x074b, 0x0000 }, 85 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 86 { 0x6acd, 0x7534, 0x2000, 0x0200 } 87 }; 88 89 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 90 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 91 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 92 { 0x6756, 0x78ab, 0x2000, 0x0200 } 93 }; 94 95 static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = { 96 { 0x1b7c, 0x0000, 0x0000, 0x0020 }, 97 { 0x0000, 0x1b7c, 0x0000, 0x0020 }, 98 { 0x0000, 0x0000, 0x1b7c, 0x0020 } 99 }; 100 101 struct hdmi_vmode { 102 bool mdataenablepolarity; 103 104 unsigned int mpixelclock; 105 unsigned int mpixelrepetitioninput; 106 unsigned int mpixelrepetitionoutput; 107 unsigned int mtmdsclock; 108 }; 109 110 struct hdmi_data_info { 111 unsigned int enc_in_bus_format; 112 unsigned int enc_out_bus_format; 113 unsigned int enc_in_encoding; 114 unsigned int enc_out_encoding; 115 unsigned int pix_repet_factor; 116 unsigned int hdcp_enable; 117 struct hdmi_vmode video_mode; 118 bool rgb_limited_range; 119 }; 120 121 struct dw_hdmi_i2c { 122 struct i2c_adapter adap; 123 124 struct mutex lock; /* used to serialize data transfers */ 125 struct completion cmp; 126 u8 stat; 127 128 u8 slave_reg; 129 bool is_regaddr; 130 bool is_segment; 131 }; 132 133 struct dw_hdmi_phy_data { 134 enum dw_hdmi_phy_type type; 135 const char *name; 136 unsigned int gen; 137 bool has_svsret; 138 int (*configure)(struct dw_hdmi *hdmi, 139 const struct dw_hdmi_plat_data *pdata, 140 unsigned long mpixelclock); 141 }; 142 143 struct dw_hdmi { 144 struct drm_connector connector; 145 struct drm_bridge bridge; 146 struct drm_bridge *next_bridge; 147 148 unsigned int version; 149 150 struct platform_device *audio; 151 struct platform_device *cec; 152 struct device *dev; 153 struct clk *isfr_clk; 154 struct clk *iahb_clk; 155 struct clk *cec_clk; 156 struct dw_hdmi_i2c *i2c; 157 158 struct hdmi_data_info hdmi_data; 159 const struct dw_hdmi_plat_data *plat_data; 160 161 int vic; 162 163 u8 edid[HDMI_EDID_LEN]; 164 165 struct { 166 const struct dw_hdmi_phy_ops *ops; 167 const char *name; 168 void *data; 169 bool enabled; 170 } phy; 171 172 struct drm_display_mode previous_mode; 173 174 struct i2c_adapter *ddc; 175 void __iomem *regs; 176 bool sink_is_hdmi; 177 bool sink_has_audio; 178 179 struct pinctrl *pinctrl; 180 struct pinctrl_state *default_state; 181 struct pinctrl_state *unwedge_state; 182 183 struct mutex mutex; /* for state below and previous_mode */ 184 enum drm_connector_force force; /* mutex-protected force state */ 185 struct drm_connector *curr_conn;/* current connector (only valid when !disabled) */ 186 bool disabled; /* DRM has disabled our bridge */ 187 bool bridge_is_on; /* indicates the bridge is on */ 188 bool rxsense; /* rxsense state */ 189 u8 phy_mask; /* desired phy int mask settings */ 190 u8 mc_clkdis; /* clock disable register */ 191 192 spinlock_t audio_lock; 193 struct mutex audio_mutex; 194 unsigned int sample_rate; 195 unsigned int audio_cts; 196 unsigned int audio_n; 197 bool audio_enable; 198 199 unsigned int reg_shift; 200 struct regmap *regm; 201 void (*enable_audio)(struct dw_hdmi *hdmi); 202 void (*disable_audio)(struct dw_hdmi *hdmi); 203 204 struct mutex cec_notifier_mutex; 205 struct cec_notifier *cec_notifier; 206 207 hdmi_codec_plugged_cb plugged_cb; 208 struct device *codec_dev; 209 enum drm_connector_status last_connector_result; 210 }; 211 212 #define HDMI_IH_PHY_STAT0_RX_SENSE \ 213 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ 214 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) 215 216 #define HDMI_PHY_RX_SENSE \ 217 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ 218 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) 219 220 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 221 { 222 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); 223 } 224 225 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 226 { 227 unsigned int val = 0; 228 229 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); 230 231 return val; 232 } 233 234 static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged) 235 { 236 if (hdmi->plugged_cb && hdmi->codec_dev) 237 hdmi->plugged_cb(hdmi->codec_dev, plugged); 238 } 239 240 int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn, 241 struct device *codec_dev) 242 { 243 bool plugged; 244 245 mutex_lock(&hdmi->mutex); 246 hdmi->plugged_cb = fn; 247 hdmi->codec_dev = codec_dev; 248 plugged = hdmi->last_connector_result == connector_status_connected; 249 handle_plugged_change(hdmi, plugged); 250 mutex_unlock(&hdmi->mutex); 251 252 return 0; 253 } 254 EXPORT_SYMBOL_GPL(dw_hdmi_set_plugged_cb); 255 256 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 257 { 258 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); 259 } 260 261 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 262 u8 shift, u8 mask) 263 { 264 hdmi_modb(hdmi, data << shift, mask, reg); 265 } 266 267 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 268 { 269 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, 270 HDMI_PHY_I2CM_INT_ADDR); 271 272 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | 273 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, 274 HDMI_PHY_I2CM_CTLINT_ADDR); 275 276 /* Software reset */ 277 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 278 279 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ 280 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); 281 282 /* Set done, not acknowledged and arbitration interrupt polarities */ 283 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 284 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 285 HDMI_I2CM_CTLINT); 286 287 /* Clear DONE and ERROR interrupts */ 288 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 289 HDMI_IH_I2CM_STAT0); 290 291 /* Mute DONE and ERROR interrupts */ 292 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 293 HDMI_IH_MUTE_I2CM_STAT0); 294 } 295 296 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi) 297 { 298 /* If no unwedge state then give up */ 299 if (!hdmi->unwedge_state) 300 return false; 301 302 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n"); 303 304 /* 305 * This is a huge hack to workaround a problem where the dw_hdmi i2c 306 * bus could sometimes get wedged. Once wedged there doesn't appear 307 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ) 308 * other than pulsing the SDA line. 309 * 310 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi) 311 * by: 312 * 1. Remux the pin as a GPIO output, driven low. 313 * 2. Wait a little while. 1 ms seems to work, but we'll do 10. 314 * 3. Immediately jump to remux the pin as dw_hdmi i2c again. 315 * 316 * At the moment of remuxing, the line will still be low due to its 317 * recent stint as an output, but then it will be pulled high by the 318 * (presumed) external pullup. dw_hdmi seems to see this as a rising 319 * edge and that seems to get it out of its jam. 320 * 321 * This wedging was only ever seen on one TV, and only on one of 322 * its HDMI ports. It happened when the TV was powered on while the 323 * device was plugged in. A scope trace shows the TV bringing both SDA 324 * and SCL low, then bringing them both back up at roughly the same 325 * time. Presumably this confuses dw_hdmi because it saw activity but 326 * no real STOP (maybe it thinks there's another master on the bus?). 327 * Giving it a clean rising edge of SDA while SCL is already high 328 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out 329 * of its stupor. 330 * 331 * Note that after coming back alive, transfers seem to immediately 332 * resume, so if we unwedge due to a timeout we should wait a little 333 * longer for our transfer to finish, since it might have just started 334 * now. 335 */ 336 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state); 337 msleep(10); 338 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state); 339 340 return true; 341 } 342 343 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi) 344 { 345 struct dw_hdmi_i2c *i2c = hdmi->i2c; 346 int stat; 347 348 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 349 if (!stat) { 350 /* If we can't unwedge, return timeout */ 351 if (!dw_hdmi_i2c_unwedge(hdmi)) 352 return -EAGAIN; 353 354 /* We tried to unwedge; give it another chance */ 355 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 356 if (!stat) 357 return -EAGAIN; 358 } 359 360 /* Check for error condition on the bus */ 361 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 362 return -EIO; 363 364 return 0; 365 } 366 367 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 368 unsigned char *buf, unsigned int length) 369 { 370 struct dw_hdmi_i2c *i2c = hdmi->i2c; 371 int ret; 372 373 if (!i2c->is_regaddr) { 374 dev_dbg(hdmi->dev, "set read register address to 0\n"); 375 i2c->slave_reg = 0x00; 376 i2c->is_regaddr = true; 377 } 378 379 while (length--) { 380 reinit_completion(&i2c->cmp); 381 382 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 383 if (i2c->is_segment) 384 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 385 HDMI_I2CM_OPERATION); 386 else 387 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 388 HDMI_I2CM_OPERATION); 389 390 ret = dw_hdmi_i2c_wait(hdmi); 391 if (ret) 392 return ret; 393 394 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 395 } 396 i2c->is_segment = false; 397 398 return 0; 399 } 400 401 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 402 unsigned char *buf, unsigned int length) 403 { 404 struct dw_hdmi_i2c *i2c = hdmi->i2c; 405 int ret; 406 407 if (!i2c->is_regaddr) { 408 /* Use the first write byte as register address */ 409 i2c->slave_reg = buf[0]; 410 length--; 411 buf++; 412 i2c->is_regaddr = true; 413 } 414 415 while (length--) { 416 reinit_completion(&i2c->cmp); 417 418 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 419 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 420 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 421 HDMI_I2CM_OPERATION); 422 423 ret = dw_hdmi_i2c_wait(hdmi); 424 if (ret) 425 return ret; 426 } 427 428 return 0; 429 } 430 431 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, 432 struct i2c_msg *msgs, int num) 433 { 434 struct dw_hdmi *hdmi = i2c_get_adapdata(adap); 435 struct dw_hdmi_i2c *i2c = hdmi->i2c; 436 u8 addr = msgs[0].addr; 437 int i, ret = 0; 438 439 if (addr == DDC_CI_ADDR) 440 /* 441 * The internal I2C controller does not support the multi-byte 442 * read and write operations needed for DDC/CI. 443 * TOFIX: Blacklist the DDC/CI address until we filter out 444 * unsupported I2C operations. 445 */ 446 return -EOPNOTSUPP; 447 448 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); 449 450 for (i = 0; i < num; i++) { 451 if (msgs[i].len == 0) { 452 dev_dbg(hdmi->dev, 453 "unsupported transfer %d/%d, no data\n", 454 i + 1, num); 455 return -EOPNOTSUPP; 456 } 457 } 458 459 mutex_lock(&i2c->lock); 460 461 /* Unmute DONE and ERROR interrupts */ 462 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 463 464 /* Set slave device address taken from the first I2C message */ 465 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 466 467 /* Set slave device register address on transfer */ 468 i2c->is_regaddr = false; 469 470 /* Set segment pointer for I2C extended read mode operation */ 471 i2c->is_segment = false; 472 473 for (i = 0; i < num; i++) { 474 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", 475 i + 1, num, msgs[i].len, msgs[i].flags); 476 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 477 i2c->is_segment = true; 478 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 479 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 480 } else { 481 if (msgs[i].flags & I2C_M_RD) 482 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 483 msgs[i].len); 484 else 485 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 486 msgs[i].len); 487 } 488 if (ret < 0) 489 break; 490 } 491 492 if (!ret) 493 ret = num; 494 495 /* Mute DONE and ERROR interrupts */ 496 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 497 HDMI_IH_MUTE_I2CM_STAT0); 498 499 mutex_unlock(&i2c->lock); 500 501 return ret; 502 } 503 504 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) 505 { 506 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 507 } 508 509 static const struct i2c_algorithm dw_hdmi_algorithm = { 510 .master_xfer = dw_hdmi_i2c_xfer, 511 .functionality = dw_hdmi_i2c_func, 512 }; 513 514 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) 515 { 516 struct i2c_adapter *adap; 517 struct dw_hdmi_i2c *i2c; 518 int ret; 519 520 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 521 if (!i2c) 522 return ERR_PTR(-ENOMEM); 523 524 mutex_init(&i2c->lock); 525 init_completion(&i2c->cmp); 526 527 adap = &i2c->adap; 528 adap->class = I2C_CLASS_DDC; 529 adap->owner = THIS_MODULE; 530 adap->dev.parent = hdmi->dev; 531 adap->algo = &dw_hdmi_algorithm; 532 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name)); 533 i2c_set_adapdata(adap, hdmi); 534 535 ret = i2c_add_adapter(adap); 536 if (ret) { 537 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 538 devm_kfree(hdmi->dev, i2c); 539 return ERR_PTR(ret); 540 } 541 542 hdmi->i2c = i2c; 543 544 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 545 546 return adap; 547 } 548 549 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 550 unsigned int n) 551 { 552 /* Must be set/cleared first */ 553 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 554 555 /* nshift factor = 0 */ 556 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 557 558 /* Use automatic CTS generation mode when CTS is not set */ 559 if (cts) 560 hdmi_writeb(hdmi, ((cts >> 16) & 561 HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 562 HDMI_AUD_CTS3_CTS_MANUAL, 563 HDMI_AUD_CTS3); 564 else 565 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3); 566 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 567 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 568 569 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 570 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 571 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 572 } 573 574 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) 575 { 576 unsigned int n = (128 * freq) / 1000; 577 unsigned int mult = 1; 578 579 while (freq > 48000) { 580 mult *= 2; 581 freq /= 2; 582 } 583 584 switch (freq) { 585 case 32000: 586 if (pixel_clk == 25175000) 587 n = 4576; 588 else if (pixel_clk == 27027000) 589 n = 4096; 590 else if (pixel_clk == 74176000 || pixel_clk == 148352000) 591 n = 11648; 592 else 593 n = 4096; 594 n *= mult; 595 break; 596 597 case 44100: 598 if (pixel_clk == 25175000) 599 n = 7007; 600 else if (pixel_clk == 74176000) 601 n = 17836; 602 else if (pixel_clk == 148352000) 603 n = 8918; 604 else 605 n = 6272; 606 n *= mult; 607 break; 608 609 case 48000: 610 if (pixel_clk == 25175000) 611 n = 6864; 612 else if (pixel_clk == 27027000) 613 n = 6144; 614 else if (pixel_clk == 74176000) 615 n = 11648; 616 else if (pixel_clk == 148352000) 617 n = 5824; 618 else 619 n = 6144; 620 n *= mult; 621 break; 622 623 default: 624 break; 625 } 626 627 return n; 628 } 629 630 /* 631 * When transmitting IEC60958 linear PCM audio, these registers allow to 632 * configure the channel status information of all the channel status 633 * bits in the IEC60958 frame. For the moment this configuration is only 634 * used when the I2S audio interface, General Purpose Audio (GPA), 635 * or AHB audio DMA (AHBAUDDMA) interface is active 636 * (for S/PDIF interface this information comes from the stream). 637 */ 638 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, 639 u8 *channel_status) 640 { 641 /* 642 * Set channel status register for frequency and word length. 643 * Use default values for other registers. 644 */ 645 hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7); 646 hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8); 647 } 648 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status); 649 650 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, 651 unsigned long pixel_clk, unsigned int sample_rate) 652 { 653 unsigned long ftdms = pixel_clk; 654 unsigned int n, cts; 655 u8 config3; 656 u64 tmp; 657 658 n = hdmi_compute_n(sample_rate, pixel_clk); 659 660 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 661 662 /* Only compute CTS when using internal AHB audio */ 663 if (config3 & HDMI_CONFIG3_AHBAUDDMA) { 664 /* 665 * Compute the CTS value from the N value. Note that CTS and N 666 * can be up to 20 bits in total, so we need 64-bit math. Also 667 * note that our TDMS clock is not fully accurate; it is 668 * accurate to kHz. This can introduce an unnecessary remainder 669 * in the calculation below, so we don't try to warn about that. 670 */ 671 tmp = (u64)ftdms * n; 672 do_div(tmp, 128 * sample_rate); 673 cts = tmp; 674 675 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", 676 __func__, sample_rate, 677 ftdms / 1000000, (ftdms / 1000) % 1000, 678 n, cts); 679 } else { 680 cts = 0; 681 } 682 683 spin_lock_irq(&hdmi->audio_lock); 684 hdmi->audio_n = n; 685 hdmi->audio_cts = cts; 686 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 687 spin_unlock_irq(&hdmi->audio_lock); 688 } 689 690 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) 691 { 692 mutex_lock(&hdmi->audio_mutex); 693 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); 694 mutex_unlock(&hdmi->audio_mutex); 695 } 696 697 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 698 { 699 mutex_lock(&hdmi->audio_mutex); 700 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 701 hdmi->sample_rate); 702 mutex_unlock(&hdmi->audio_mutex); 703 } 704 705 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 706 { 707 mutex_lock(&hdmi->audio_mutex); 708 hdmi->sample_rate = rate; 709 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 710 hdmi->sample_rate); 711 mutex_unlock(&hdmi->audio_mutex); 712 } 713 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); 714 715 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt) 716 { 717 u8 layout; 718 719 mutex_lock(&hdmi->audio_mutex); 720 721 /* 722 * For >2 channel PCM audio, we need to select layout 1 723 * and set an appropriate channel map. 724 */ 725 if (cnt > 2) 726 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1; 727 else 728 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0; 729 730 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK, 731 HDMI_FC_AUDSCONF); 732 733 /* Set the audio infoframes channel count */ 734 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET, 735 HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0); 736 737 mutex_unlock(&hdmi->audio_mutex); 738 } 739 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count); 740 741 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca) 742 { 743 mutex_lock(&hdmi->audio_mutex); 744 745 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2); 746 747 mutex_unlock(&hdmi->audio_mutex); 748 } 749 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation); 750 751 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) 752 { 753 if (enable) 754 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; 755 else 756 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; 757 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 758 } 759 760 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi) 761 { 762 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 763 } 764 765 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi) 766 { 767 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 768 } 769 770 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi) 771 { 772 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 773 hdmi_enable_audio_clk(hdmi, true); 774 } 775 776 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi) 777 { 778 hdmi_enable_audio_clk(hdmi, false); 779 } 780 781 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 782 { 783 unsigned long flags; 784 785 spin_lock_irqsave(&hdmi->audio_lock, flags); 786 hdmi->audio_enable = true; 787 if (hdmi->enable_audio) 788 hdmi->enable_audio(hdmi); 789 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 790 } 791 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); 792 793 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 794 { 795 unsigned long flags; 796 797 spin_lock_irqsave(&hdmi->audio_lock, flags); 798 hdmi->audio_enable = false; 799 if (hdmi->disable_audio) 800 hdmi->disable_audio(hdmi); 801 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 802 } 803 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); 804 805 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 806 { 807 switch (bus_format) { 808 case MEDIA_BUS_FMT_RGB888_1X24: 809 case MEDIA_BUS_FMT_RGB101010_1X30: 810 case MEDIA_BUS_FMT_RGB121212_1X36: 811 case MEDIA_BUS_FMT_RGB161616_1X48: 812 return true; 813 814 default: 815 return false; 816 } 817 } 818 819 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 820 { 821 switch (bus_format) { 822 case MEDIA_BUS_FMT_YUV8_1X24: 823 case MEDIA_BUS_FMT_YUV10_1X30: 824 case MEDIA_BUS_FMT_YUV12_1X36: 825 case MEDIA_BUS_FMT_YUV16_1X48: 826 return true; 827 828 default: 829 return false; 830 } 831 } 832 833 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 834 { 835 switch (bus_format) { 836 case MEDIA_BUS_FMT_UYVY8_1X16: 837 case MEDIA_BUS_FMT_UYVY10_1X20: 838 case MEDIA_BUS_FMT_UYVY12_1X24: 839 return true; 840 841 default: 842 return false; 843 } 844 } 845 846 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 847 { 848 switch (bus_format) { 849 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 850 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 851 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 852 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 853 return true; 854 855 default: 856 return false; 857 } 858 } 859 860 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 861 { 862 switch (bus_format) { 863 case MEDIA_BUS_FMT_RGB888_1X24: 864 case MEDIA_BUS_FMT_YUV8_1X24: 865 case MEDIA_BUS_FMT_UYVY8_1X16: 866 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 867 return 8; 868 869 case MEDIA_BUS_FMT_RGB101010_1X30: 870 case MEDIA_BUS_FMT_YUV10_1X30: 871 case MEDIA_BUS_FMT_UYVY10_1X20: 872 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 873 return 10; 874 875 case MEDIA_BUS_FMT_RGB121212_1X36: 876 case MEDIA_BUS_FMT_YUV12_1X36: 877 case MEDIA_BUS_FMT_UYVY12_1X24: 878 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 879 return 12; 880 881 case MEDIA_BUS_FMT_RGB161616_1X48: 882 case MEDIA_BUS_FMT_YUV16_1X48: 883 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 884 return 16; 885 886 default: 887 return 0; 888 } 889 } 890 891 /* 892 * this submodule is responsible for the video data synchronization. 893 * for example, for RGB 4:4:4 input, the data map is defined as 894 * pin{47~40} <==> R[7:0] 895 * pin{31~24} <==> G[7:0] 896 * pin{15~8} <==> B[7:0] 897 */ 898 static void hdmi_video_sample(struct dw_hdmi *hdmi) 899 { 900 int color_format = 0; 901 u8 val; 902 903 switch (hdmi->hdmi_data.enc_in_bus_format) { 904 case MEDIA_BUS_FMT_RGB888_1X24: 905 color_format = 0x01; 906 break; 907 case MEDIA_BUS_FMT_RGB101010_1X30: 908 color_format = 0x03; 909 break; 910 case MEDIA_BUS_FMT_RGB121212_1X36: 911 color_format = 0x05; 912 break; 913 case MEDIA_BUS_FMT_RGB161616_1X48: 914 color_format = 0x07; 915 break; 916 917 case MEDIA_BUS_FMT_YUV8_1X24: 918 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 919 color_format = 0x09; 920 break; 921 case MEDIA_BUS_FMT_YUV10_1X30: 922 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 923 color_format = 0x0B; 924 break; 925 case MEDIA_BUS_FMT_YUV12_1X36: 926 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 927 color_format = 0x0D; 928 break; 929 case MEDIA_BUS_FMT_YUV16_1X48: 930 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 931 color_format = 0x0F; 932 break; 933 934 case MEDIA_BUS_FMT_UYVY8_1X16: 935 color_format = 0x16; 936 break; 937 case MEDIA_BUS_FMT_UYVY10_1X20: 938 color_format = 0x14; 939 break; 940 case MEDIA_BUS_FMT_UYVY12_1X24: 941 color_format = 0x12; 942 break; 943 944 default: 945 return; 946 } 947 948 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 949 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 950 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 951 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 952 953 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 954 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 955 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 956 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 957 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 958 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 959 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 960 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 961 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 962 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 963 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 964 } 965 966 static int is_color_space_conversion(struct dw_hdmi *hdmi) 967 { 968 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 969 bool is_input_rgb, is_output_rgb; 970 971 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format); 972 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format); 973 974 return (is_input_rgb != is_output_rgb) || 975 (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range); 976 } 977 978 static int is_color_space_decimation(struct dw_hdmi *hdmi) 979 { 980 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 981 return 0; 982 983 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 984 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 985 return 1; 986 987 return 0; 988 } 989 990 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 991 { 992 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 993 return 0; 994 995 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 996 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 997 return 1; 998 999 return 0; 1000 } 1001 1002 static bool is_csc_needed(struct dw_hdmi *hdmi) 1003 { 1004 return is_color_space_conversion(hdmi) || 1005 is_color_space_decimation(hdmi) || 1006 is_color_space_interpolation(hdmi); 1007 } 1008 1009 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 1010 { 1011 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 1012 bool is_input_rgb, is_output_rgb; 1013 unsigned i; 1014 u32 csc_scale = 1; 1015 1016 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format); 1017 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format); 1018 1019 if (!is_input_rgb && is_output_rgb) { 1020 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) 1021 csc_coeff = &csc_coeff_rgb_out_eitu601; 1022 else 1023 csc_coeff = &csc_coeff_rgb_out_eitu709; 1024 } else if (is_input_rgb && !is_output_rgb) { 1025 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) 1026 csc_coeff = &csc_coeff_rgb_in_eitu601; 1027 else 1028 csc_coeff = &csc_coeff_rgb_in_eitu709; 1029 csc_scale = 0; 1030 } else if (is_input_rgb && is_output_rgb && 1031 hdmi->hdmi_data.rgb_limited_range) { 1032 csc_coeff = &csc_coeff_rgb_full_to_rgb_limited; 1033 } 1034 1035 /* The CSC registers are sequential, alternating MSB then LSB */ 1036 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 1037 u16 coeff_a = (*csc_coeff)[0][i]; 1038 u16 coeff_b = (*csc_coeff)[1][i]; 1039 u16 coeff_c = (*csc_coeff)[2][i]; 1040 1041 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 1042 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 1043 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 1044 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 1045 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 1046 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 1047 } 1048 1049 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 1050 HDMI_CSC_SCALE); 1051 } 1052 1053 static void hdmi_video_csc(struct dw_hdmi *hdmi) 1054 { 1055 int color_depth = 0; 1056 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 1057 int decimation = 0; 1058 1059 /* YCC422 interpolation to 444 mode */ 1060 if (is_color_space_interpolation(hdmi)) 1061 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 1062 else if (is_color_space_decimation(hdmi)) 1063 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 1064 1065 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 1066 case 8: 1067 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 1068 break; 1069 case 10: 1070 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 1071 break; 1072 case 12: 1073 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 1074 break; 1075 case 16: 1076 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 1077 break; 1078 1079 default: 1080 return; 1081 } 1082 1083 /* Configure the CSC registers */ 1084 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 1085 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 1086 HDMI_CSC_SCALE); 1087 1088 dw_hdmi_update_csc_coeffs(hdmi); 1089 } 1090 1091 /* 1092 * HDMI video packetizer is used to packetize the data. 1093 * for example, if input is YCC422 mode or repeater is used, 1094 * data should be repacked this module can be bypassed. 1095 */ 1096 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 1097 { 1098 unsigned int color_depth = 0; 1099 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 1100 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 1101 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1102 u8 val, vp_conf; 1103 1104 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1105 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 1106 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1107 switch (hdmi_bus_fmt_color_depth( 1108 hdmi->hdmi_data.enc_out_bus_format)) { 1109 case 8: 1110 color_depth = 4; 1111 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1112 break; 1113 case 10: 1114 color_depth = 5; 1115 break; 1116 case 12: 1117 color_depth = 6; 1118 break; 1119 case 16: 1120 color_depth = 7; 1121 break; 1122 default: 1123 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1124 } 1125 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1126 switch (hdmi_bus_fmt_color_depth( 1127 hdmi->hdmi_data.enc_out_bus_format)) { 1128 case 0: 1129 case 8: 1130 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1131 break; 1132 case 10: 1133 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1134 break; 1135 case 12: 1136 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1137 break; 1138 1139 default: 1140 return; 1141 } 1142 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1143 } else { 1144 return; 1145 } 1146 1147 /* set the packetizer registers */ 1148 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1149 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | 1150 ((hdmi_data->pix_repet_factor << 1151 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & 1152 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); 1153 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1154 1155 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1156 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1157 1158 /* Data from pixel repeater block */ 1159 if (hdmi_data->pix_repet_factor > 1) { 1160 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1161 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1162 } else { /* data from packetizer block */ 1163 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1164 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1165 } 1166 1167 hdmi_modb(hdmi, vp_conf, 1168 HDMI_VP_CONF_PR_EN_MASK | 1169 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1170 1171 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 1172 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 1173 1174 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1175 1176 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1177 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1178 HDMI_VP_CONF_PP_EN_ENABLE | 1179 HDMI_VP_CONF_YCC422_EN_DISABLE; 1180 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1181 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1182 HDMI_VP_CONF_PP_EN_DISABLE | 1183 HDMI_VP_CONF_YCC422_EN_ENABLE; 1184 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1185 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1186 HDMI_VP_CONF_PP_EN_DISABLE | 1187 HDMI_VP_CONF_YCC422_EN_DISABLE; 1188 } else { 1189 return; 1190 } 1191 1192 hdmi_modb(hdmi, vp_conf, 1193 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1194 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1195 1196 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1197 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1198 HDMI_VP_STUFF_PP_STUFFING_MASK | 1199 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1200 1201 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1202 HDMI_VP_CONF); 1203 } 1204 1205 /* ----------------------------------------------------------------------------- 1206 * Synopsys PHY Handling 1207 */ 1208 1209 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 1210 unsigned char bit) 1211 { 1212 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 1213 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 1214 } 1215 1216 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 1217 { 1218 u32 val; 1219 1220 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 1221 if (msec-- == 0) 1222 return false; 1223 udelay(1000); 1224 } 1225 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 1226 1227 return true; 1228 } 1229 1230 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 1231 unsigned char addr) 1232 { 1233 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 1234 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 1235 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 1236 HDMI_PHY_I2CM_DATAO_1_ADDR); 1237 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 1238 HDMI_PHY_I2CM_DATAO_0_ADDR); 1239 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 1240 HDMI_PHY_I2CM_OPERATION_ADDR); 1241 hdmi_phy_wait_i2c_done(hdmi, 1000); 1242 } 1243 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); 1244 1245 /* Filter out invalid setups to avoid configuring SCDC and scrambling */ 1246 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi, 1247 const struct drm_display_info *display) 1248 { 1249 /* Completely disable SCDC support for older controllers */ 1250 if (hdmi->version < 0x200a) 1251 return false; 1252 1253 /* Disable if no DDC bus */ 1254 if (!hdmi->ddc) 1255 return false; 1256 1257 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */ 1258 if (!display->hdmi.scdc.supported || 1259 !display->hdmi.scdc.scrambling.supported) 1260 return false; 1261 1262 /* 1263 * Disable if display only support low TMDS rates and scrambling 1264 * for low rates is not supported either 1265 */ 1266 if (!display->hdmi.scdc.scrambling.low_rates && 1267 display->max_tmds_clock <= 340000) 1268 return false; 1269 1270 return true; 1271 } 1272 1273 /* 1274 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates: 1275 * - The Source shall suspend transmission of the TMDS clock and data 1276 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it 1277 * from a 0 to a 1 or from a 1 to a 0 1278 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from 1279 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming 1280 * transmission of TMDS clock and data 1281 * 1282 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio() 1283 * helper should called right before enabling the TMDS Clock and Data in 1284 * the PHY configuration callback. 1285 */ 1286 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi, 1287 const struct drm_display_info *display) 1288 { 1289 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1290 1291 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 1292 if (dw_hdmi_support_scdc(hdmi, display)) { 1293 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1294 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1); 1295 else 1296 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0); 1297 } 1298 } 1299 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio); 1300 1301 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 1302 { 1303 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 1304 HDMI_PHY_CONF0_PDZ_OFFSET, 1305 HDMI_PHY_CONF0_PDZ_MASK); 1306 } 1307 1308 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 1309 { 1310 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1311 HDMI_PHY_CONF0_ENTMDS_OFFSET, 1312 HDMI_PHY_CONF0_ENTMDS_MASK); 1313 } 1314 1315 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 1316 { 1317 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1318 HDMI_PHY_CONF0_SVSRET_OFFSET, 1319 HDMI_PHY_CONF0_SVSRET_MASK); 1320 } 1321 1322 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 1323 { 1324 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1325 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 1326 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 1327 } 1328 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq); 1329 1330 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 1331 { 1332 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1333 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 1334 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 1335 } 1336 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron); 1337 1338 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 1339 { 1340 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1341 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 1342 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 1343 } 1344 1345 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 1346 { 1347 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1348 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 1349 HDMI_PHY_CONF0_SELDIPIF_MASK); 1350 } 1351 1352 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi) 1353 { 1354 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 1355 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1356 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1357 } 1358 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset); 1359 1360 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) 1361 { 1362 hdmi_phy_test_clear(hdmi, 1); 1363 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR); 1364 hdmi_phy_test_clear(hdmi, 0); 1365 } 1366 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr); 1367 1368 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 1369 { 1370 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1371 unsigned int i; 1372 u16 val; 1373 1374 if (phy->gen == 1) { 1375 dw_hdmi_phy_enable_tmds(hdmi, 0); 1376 dw_hdmi_phy_enable_powerdown(hdmi, true); 1377 return; 1378 } 1379 1380 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 1381 1382 /* 1383 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 1384 * to low power mode. 1385 */ 1386 for (i = 0; i < 5; ++i) { 1387 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 1388 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 1389 break; 1390 1391 usleep_range(1000, 2000); 1392 } 1393 1394 if (val & HDMI_PHY_TX_PHY_LOCK) 1395 dev_warn(hdmi->dev, "PHY failed to power down\n"); 1396 else 1397 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); 1398 1399 dw_hdmi_phy_gen2_pddq(hdmi, 1); 1400 } 1401 1402 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 1403 { 1404 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1405 unsigned int i; 1406 u8 val; 1407 1408 if (phy->gen == 1) { 1409 dw_hdmi_phy_enable_powerdown(hdmi, false); 1410 1411 /* Toggle TMDS enable. */ 1412 dw_hdmi_phy_enable_tmds(hdmi, 0); 1413 dw_hdmi_phy_enable_tmds(hdmi, 1); 1414 return 0; 1415 } 1416 1417 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 1418 dw_hdmi_phy_gen2_pddq(hdmi, 0); 1419 1420 /* Wait for PHY PLL lock */ 1421 for (i = 0; i < 5; ++i) { 1422 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 1423 if (val) 1424 break; 1425 1426 usleep_range(1000, 2000); 1427 } 1428 1429 if (!val) { 1430 dev_err(hdmi->dev, "PHY PLL failed to lock\n"); 1431 return -ETIMEDOUT; 1432 } 1433 1434 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); 1435 return 0; 1436 } 1437 1438 /* 1439 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 1440 * information the DWC MHL PHY has the same register layout and is thus also 1441 * supported by this function. 1442 */ 1443 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 1444 const struct dw_hdmi_plat_data *pdata, 1445 unsigned long mpixelclock) 1446 { 1447 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 1448 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 1449 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 1450 1451 /* TOFIX Will need 420 specific PHY configuration tables */ 1452 1453 /* PLL/MPLL Cfg - always match on final entry */ 1454 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 1455 if (mpixelclock <= mpll_config->mpixelclock) 1456 break; 1457 1458 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 1459 if (mpixelclock <= curr_ctrl->mpixelclock) 1460 break; 1461 1462 for (; phy_config->mpixelclock != ~0UL; phy_config++) 1463 if (mpixelclock <= phy_config->mpixelclock) 1464 break; 1465 1466 if (mpll_config->mpixelclock == ~0UL || 1467 curr_ctrl->mpixelclock == ~0UL || 1468 phy_config->mpixelclock == ~0UL) 1469 return -EINVAL; 1470 1471 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 1472 HDMI_3D_TX_PHY_CPCE_CTRL); 1473 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 1474 HDMI_3D_TX_PHY_GMPCTRL); 1475 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 1476 HDMI_3D_TX_PHY_CURRCTRL); 1477 1478 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 1479 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 1480 HDMI_3D_TX_PHY_MSM_CTRL); 1481 1482 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 1483 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 1484 HDMI_3D_TX_PHY_CKSYMTXCTRL); 1485 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 1486 HDMI_3D_TX_PHY_VLEVCTRL); 1487 1488 /* Override and disable clock termination. */ 1489 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 1490 HDMI_3D_TX_PHY_CKCALCTRL); 1491 1492 return 0; 1493 } 1494 1495 static int hdmi_phy_configure(struct dw_hdmi *hdmi, 1496 const struct drm_display_info *display) 1497 { 1498 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1499 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 1500 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 1501 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1502 int ret; 1503 1504 dw_hdmi_phy_power_off(hdmi); 1505 1506 dw_hdmi_set_high_tmds_clock_ratio(hdmi, display); 1507 1508 /* Leave low power consumption mode by asserting SVSRET. */ 1509 if (phy->has_svsret) 1510 dw_hdmi_phy_enable_svsret(hdmi, 1); 1511 1512 dw_hdmi_phy_reset(hdmi); 1513 1514 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 1515 1516 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); 1517 1518 /* Write to the PHY as configured by the platform */ 1519 if (pdata->configure_phy) 1520 ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock); 1521 else 1522 ret = phy->configure(hdmi, pdata, mpixelclock); 1523 if (ret) { 1524 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", 1525 mpixelclock); 1526 return ret; 1527 } 1528 1529 /* Wait for resuming transmission of TMDS clock and data */ 1530 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1531 msleep(100); 1532 1533 return dw_hdmi_phy_power_on(hdmi); 1534 } 1535 1536 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 1537 const struct drm_display_info *display, 1538 const struct drm_display_mode *mode) 1539 { 1540 int i, ret; 1541 1542 /* HDMI Phy spec says to do the phy initialization sequence twice */ 1543 for (i = 0; i < 2; i++) { 1544 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 1545 dw_hdmi_phy_sel_interface_control(hdmi, 0); 1546 1547 ret = hdmi_phy_configure(hdmi, display); 1548 if (ret) 1549 return ret; 1550 } 1551 1552 return 0; 1553 } 1554 1555 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 1556 { 1557 dw_hdmi_phy_power_off(hdmi); 1558 } 1559 1560 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 1561 void *data) 1562 { 1563 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 1564 connector_status_connected : connector_status_disconnected; 1565 } 1566 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); 1567 1568 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 1569 bool force, bool disabled, bool rxsense) 1570 { 1571 u8 old_mask = hdmi->phy_mask; 1572 1573 if (force || disabled || !rxsense) 1574 hdmi->phy_mask |= HDMI_PHY_RX_SENSE; 1575 else 1576 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; 1577 1578 if (old_mask != hdmi->phy_mask) 1579 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1580 } 1581 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd); 1582 1583 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) 1584 { 1585 /* 1586 * Configure the PHY RX SENSE and HPD interrupts polarities and clear 1587 * any pending interrupt. 1588 */ 1589 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); 1590 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1591 HDMI_IH_PHY_STAT0); 1592 1593 /* Enable cable hot plug irq. */ 1594 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1595 1596 /* Clear and unmute interrupts. */ 1597 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1598 HDMI_IH_PHY_STAT0); 1599 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 1600 HDMI_IH_MUTE_PHY_STAT0); 1601 } 1602 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd); 1603 1604 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 1605 .init = dw_hdmi_phy_init, 1606 .disable = dw_hdmi_phy_disable, 1607 .read_hpd = dw_hdmi_phy_read_hpd, 1608 .update_hpd = dw_hdmi_phy_update_hpd, 1609 .setup_hpd = dw_hdmi_phy_setup_hpd, 1610 }; 1611 1612 /* ----------------------------------------------------------------------------- 1613 * HDMI TX Setup 1614 */ 1615 1616 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) 1617 { 1618 u8 de; 1619 1620 if (hdmi->hdmi_data.video_mode.mdataenablepolarity) 1621 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1622 else 1623 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; 1624 1625 /* disable rx detect */ 1626 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, 1627 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 1628 1629 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); 1630 1631 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, 1632 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); 1633 } 1634 1635 static void hdmi_config_AVI(struct dw_hdmi *hdmi, 1636 const struct drm_connector *connector, 1637 const struct drm_display_mode *mode) 1638 { 1639 struct hdmi_avi_infoframe frame; 1640 u8 val; 1641 1642 /* Initialise info frame from DRM mode */ 1643 drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); 1644 1645 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 1646 drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode, 1647 hdmi->hdmi_data.rgb_limited_range ? 1648 HDMI_QUANTIZATION_RANGE_LIMITED : 1649 HDMI_QUANTIZATION_RANGE_FULL); 1650 } else { 1651 frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 1652 frame.ycc_quantization_range = 1653 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 1654 } 1655 1656 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1657 frame.colorspace = HDMI_COLORSPACE_YUV444; 1658 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1659 frame.colorspace = HDMI_COLORSPACE_YUV422; 1660 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1661 frame.colorspace = HDMI_COLORSPACE_YUV420; 1662 else 1663 frame.colorspace = HDMI_COLORSPACE_RGB; 1664 1665 /* Set up colorimetry */ 1666 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 1667 switch (hdmi->hdmi_data.enc_out_encoding) { 1668 case V4L2_YCBCR_ENC_601: 1669 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1670 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1671 else 1672 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1673 frame.extended_colorimetry = 1674 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1675 break; 1676 case V4L2_YCBCR_ENC_709: 1677 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1678 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1679 else 1680 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1681 frame.extended_colorimetry = 1682 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1683 break; 1684 default: /* Carries no data */ 1685 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1686 frame.extended_colorimetry = 1687 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1688 break; 1689 } 1690 } else { 1691 frame.colorimetry = HDMI_COLORIMETRY_NONE; 1692 frame.extended_colorimetry = 1693 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1694 } 1695 1696 /* 1697 * The Designware IP uses a different byte format from standard 1698 * AVI info frames, though generally the bits are in the correct 1699 * bytes. 1700 */ 1701 1702 /* 1703 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, 1704 * scan info in bits 4,5 rather than 0,1 and active aspect present in 1705 * bit 6 rather than 4. 1706 */ 1707 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); 1708 if (frame.active_aspect & 15) 1709 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1710 if (frame.top_bar || frame.bottom_bar) 1711 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1712 if (frame.left_bar || frame.right_bar) 1713 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1714 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1715 1716 /* AVI data byte 2 differences: none */ 1717 val = ((frame.colorimetry & 0x3) << 6) | 1718 ((frame.picture_aspect & 0x3) << 4) | 1719 (frame.active_aspect & 0xf); 1720 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1721 1722 /* AVI data byte 3 differences: none */ 1723 val = ((frame.extended_colorimetry & 0x7) << 4) | 1724 ((frame.quantization_range & 0x3) << 2) | 1725 (frame.nups & 0x3); 1726 if (frame.itc) 1727 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1728 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1729 1730 /* AVI data byte 4 differences: none */ 1731 val = frame.video_code & 0x7f; 1732 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1733 1734 /* AVI Data Byte 5- set up input and output pixel repetition */ 1735 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1736 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1737 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1738 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1739 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1740 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1741 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1742 1743 /* 1744 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1745 * ycc range in bits 2,3 rather than 6,7 1746 */ 1747 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1748 (frame.content_type & 0x3); 1749 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1750 1751 /* AVI Data Bytes 6-13 */ 1752 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1753 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1754 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1755 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1756 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1757 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1758 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1759 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1760 } 1761 1762 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1763 const struct drm_connector *connector, 1764 const struct drm_display_mode *mode) 1765 { 1766 struct hdmi_vendor_infoframe frame; 1767 u8 buffer[10]; 1768 ssize_t err; 1769 1770 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, connector, 1771 mode); 1772 if (err < 0) 1773 /* 1774 * Going into that statement does not means vendor infoframe 1775 * fails. It just informed us that vendor infoframe is not 1776 * needed for the selected mode. Only 4k or stereoscopic 3D 1777 * mode requires vendor infoframe. So just simply return. 1778 */ 1779 return; 1780 1781 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1782 if (err < 0) { 1783 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1784 err); 1785 return; 1786 } 1787 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1788 HDMI_FC_DATAUTO0_VSD_MASK); 1789 1790 /* Set the length of HDMI vendor specific InfoFrame payload */ 1791 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1792 1793 /* Set 24bit IEEE Registration Identifier */ 1794 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1795 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1796 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1797 1798 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1799 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1800 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1801 1802 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1803 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1804 1805 /* Packet frame interpolation */ 1806 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1807 1808 /* Auto packets per frame and line spacing */ 1809 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1810 1811 /* Configures the Frame Composer On RDRB mode */ 1812 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1813 HDMI_FC_DATAUTO0_VSD_MASK); 1814 } 1815 1816 static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, 1817 const struct drm_connector *connector) 1818 { 1819 const struct drm_connector_state *conn_state = connector->state; 1820 struct hdmi_drm_infoframe frame; 1821 u8 buffer[30]; 1822 ssize_t err; 1823 int i; 1824 1825 if (!hdmi->plat_data->use_drm_infoframe) 1826 return; 1827 1828 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE, 1829 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); 1830 1831 err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state); 1832 if (err < 0) 1833 return; 1834 1835 err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer)); 1836 if (err < 0) { 1837 dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err); 1838 return; 1839 } 1840 1841 hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0); 1842 hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1); 1843 1844 for (i = 0; i < frame.length; i++) 1845 hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i); 1846 1847 hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP); 1848 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE, 1849 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); 1850 } 1851 1852 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1853 const struct drm_display_info *display, 1854 const struct drm_display_mode *mode) 1855 { 1856 u8 inv_val, bytes; 1857 const struct drm_hdmi_info *hdmi_info = &display->hdmi; 1858 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1859 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1860 unsigned int vdisplay, hdisplay; 1861 1862 vmode->mpixelclock = mode->clock * 1000; 1863 1864 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); 1865 1866 vmode->mtmdsclock = vmode->mpixelclock; 1867 1868 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1869 switch (hdmi_bus_fmt_color_depth( 1870 hdmi->hdmi_data.enc_out_bus_format)) { 1871 case 16: 1872 vmode->mtmdsclock = vmode->mpixelclock * 2; 1873 break; 1874 case 12: 1875 vmode->mtmdsclock = vmode->mpixelclock * 3 / 2; 1876 break; 1877 case 10: 1878 vmode->mtmdsclock = vmode->mpixelclock * 5 / 4; 1879 break; 1880 } 1881 } 1882 1883 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1884 vmode->mtmdsclock /= 2; 1885 1886 dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock); 1887 1888 /* Set up HDMI_FC_INVIDCONF */ 1889 inv_val = (hdmi->hdmi_data.hdcp_enable || 1890 (dw_hdmi_support_scdc(hdmi, display) && 1891 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 1892 hdmi_info->scdc.scrambling.low_rates)) ? 1893 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1894 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1895 1896 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1897 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1898 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1899 1900 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1901 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1902 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1903 1904 inv_val |= (vmode->mdataenablepolarity ? 1905 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1906 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1907 1908 if (hdmi->vic == 39) 1909 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1910 else 1911 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1912 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1913 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1914 1915 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1916 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1917 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1918 1919 inv_val |= hdmi->sink_is_hdmi ? 1920 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1921 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1922 1923 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1924 1925 hdisplay = mode->hdisplay; 1926 hblank = mode->htotal - mode->hdisplay; 1927 h_de_hs = mode->hsync_start - mode->hdisplay; 1928 hsync_len = mode->hsync_end - mode->hsync_start; 1929 1930 /* 1931 * When we're setting a YCbCr420 mode, we need 1932 * to adjust the horizontal timing to suit. 1933 */ 1934 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1935 hdisplay /= 2; 1936 hblank /= 2; 1937 h_de_hs /= 2; 1938 hsync_len /= 2; 1939 } 1940 1941 vdisplay = mode->vdisplay; 1942 vblank = mode->vtotal - mode->vdisplay; 1943 v_de_vs = mode->vsync_start - mode->vdisplay; 1944 vsync_len = mode->vsync_end - mode->vsync_start; 1945 1946 /* 1947 * When we're setting an interlaced mode, we need 1948 * to adjust the vertical timing to suit. 1949 */ 1950 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1951 vdisplay /= 2; 1952 vblank /= 2; 1953 v_de_vs /= 2; 1954 vsync_len /= 2; 1955 } 1956 1957 /* Scrambling Control */ 1958 if (dw_hdmi_support_scdc(hdmi, display)) { 1959 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 1960 hdmi_info->scdc.scrambling.low_rates) { 1961 /* 1962 * HDMI2.0 Specifies the following procedure: 1963 * After the Source Device has determined that 1964 * SCDC_Present is set (=1), the Source Device should 1965 * write the accurate Version of the Source Device 1966 * to the Source Version field in the SCDCS. 1967 * Source Devices compliant shall set the 1968 * Source Version = 1. 1969 */ 1970 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, 1971 &bytes); 1972 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, 1973 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); 1974 1975 /* Enabled Scrambling in the Sink */ 1976 drm_scdc_set_scrambling(hdmi->ddc, 1); 1977 1978 /* 1979 * To activate the scrambler feature, you must ensure 1980 * that the quasi-static configuration bit 1981 * fc_invidconf.HDCP_keepout is set at configuration 1982 * time, before the required mc_swrstzreq.tmdsswrst_req 1983 * reset request is issued. 1984 */ 1985 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 1986 HDMI_MC_SWRSTZ); 1987 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 1988 } else { 1989 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 1990 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 1991 HDMI_MC_SWRSTZ); 1992 drm_scdc_set_scrambling(hdmi->ddc, 0); 1993 } 1994 } 1995 1996 /* Set up horizontal active pixel width */ 1997 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 1998 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 1999 2000 /* Set up vertical active lines */ 2001 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 2002 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 2003 2004 /* Set up horizontal blanking pixel region width */ 2005 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 2006 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 2007 2008 /* Set up vertical blanking pixel region width */ 2009 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 2010 2011 /* Set up HSYNC active edge delay width (in pixel clks) */ 2012 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 2013 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 2014 2015 /* Set up VSYNC active edge delay (in lines) */ 2016 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 2017 2018 /* Set up HSYNC active pulse width (in pixel clks) */ 2019 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 2020 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 2021 2022 /* Set up VSYNC active edge delay (in lines) */ 2023 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 2024 } 2025 2026 /* HDMI Initialization Step B.4 */ 2027 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 2028 { 2029 /* control period minimum duration */ 2030 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 2031 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 2032 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 2033 2034 /* Set to fill TMDS data channels */ 2035 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 2036 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 2037 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 2038 2039 /* Enable pixel clock and tmds data path */ 2040 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE | 2041 HDMI_MC_CLKDIS_CSCCLK_DISABLE | 2042 HDMI_MC_CLKDIS_AUDCLK_DISABLE | 2043 HDMI_MC_CLKDIS_PREPCLK_DISABLE | 2044 HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 2045 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 2046 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2047 2048 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 2049 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2050 2051 /* Enable csc path */ 2052 if (is_csc_needed(hdmi)) { 2053 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 2054 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2055 2056 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 2057 HDMI_MC_FLOWCTRL); 2058 } else { 2059 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE; 2060 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2061 2062 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 2063 HDMI_MC_FLOWCTRL); 2064 } 2065 } 2066 2067 /* Workaround to clear the overflow condition */ 2068 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 2069 { 2070 unsigned int count; 2071 unsigned int i; 2072 u8 val; 2073 2074 /* 2075 * Under some circumstances the Frame Composer arithmetic unit can miss 2076 * an FC register write due to being busy processing the previous one. 2077 * The issue can be worked around by issuing a TMDS software reset and 2078 * then write one of the FC registers several times. 2079 * 2080 * The number of iterations matters and depends on the HDMI TX revision 2081 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL 2082 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified 2083 * as needing the workaround, with 4 iterations for v1.30a and 1 2084 * iteration for others. 2085 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing 2086 * the workaround with a single iteration. 2087 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have 2088 * been identified as needing the workaround with a single iteration. 2089 */ 2090 2091 switch (hdmi->version) { 2092 case 0x130a: 2093 count = 4; 2094 break; 2095 case 0x131a: 2096 case 0x132a: 2097 case 0x200a: 2098 case 0x201a: 2099 case 0x211a: 2100 case 0x212a: 2101 count = 1; 2102 break; 2103 default: 2104 return; 2105 } 2106 2107 /* TMDS software reset */ 2108 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 2109 2110 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 2111 for (i = 0; i < count; i++) 2112 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 2113 } 2114 2115 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 2116 { 2117 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 2118 HDMI_IH_MUTE_FC_STAT2); 2119 } 2120 2121 static int dw_hdmi_setup(struct dw_hdmi *hdmi, 2122 const struct drm_connector *connector, 2123 const struct drm_display_mode *mode) 2124 { 2125 int ret; 2126 2127 hdmi_disable_overflow_interrupts(hdmi); 2128 2129 hdmi->vic = drm_match_cea_mode(mode); 2130 2131 if (!hdmi->vic) { 2132 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); 2133 } else { 2134 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); 2135 } 2136 2137 if ((hdmi->vic == 6) || (hdmi->vic == 7) || 2138 (hdmi->vic == 21) || (hdmi->vic == 22) || 2139 (hdmi->vic == 2) || (hdmi->vic == 3) || 2140 (hdmi->vic == 17) || (hdmi->vic == 18)) 2141 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 2142 else 2143 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 2144 2145 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 2146 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 2147 2148 if (hdmi->hdmi_data.enc_in_bus_format == MEDIA_BUS_FMT_FIXED) 2149 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2150 2151 /* TOFIX: Get input encoding from plat data or fallback to none */ 2152 if (hdmi->plat_data->input_bus_encoding) 2153 hdmi->hdmi_data.enc_in_encoding = 2154 hdmi->plat_data->input_bus_encoding; 2155 else 2156 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 2157 2158 if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_FIXED) 2159 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2160 2161 hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi && 2162 drm_default_rgb_quant_range(mode) == 2163 HDMI_QUANTIZATION_RANGE_LIMITED; 2164 2165 hdmi->hdmi_data.pix_repet_factor = 0; 2166 hdmi->hdmi_data.hdcp_enable = 0; 2167 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 2168 2169 /* HDMI Initialization Step B.1 */ 2170 hdmi_av_composer(hdmi, &connector->display_info, mode); 2171 2172 /* HDMI Initializateion Step B.2 */ 2173 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, 2174 &connector->display_info, 2175 &hdmi->previous_mode); 2176 if (ret) 2177 return ret; 2178 hdmi->phy.enabled = true; 2179 2180 /* HDMI Initialization Step B.3 */ 2181 dw_hdmi_enable_video_path(hdmi); 2182 2183 if (hdmi->sink_has_audio) { 2184 dev_dbg(hdmi->dev, "sink has audio support\n"); 2185 2186 /* HDMI Initialization Step E - Configure audio */ 2187 hdmi_clk_regenerator_update_pixel_clock(hdmi); 2188 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable); 2189 } 2190 2191 /* not for DVI mode */ 2192 if (hdmi->sink_is_hdmi) { 2193 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); 2194 2195 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 2196 hdmi_config_AVI(hdmi, connector, mode); 2197 hdmi_config_vendor_specific_infoframe(hdmi, connector, mode); 2198 hdmi_config_drm_infoframe(hdmi, connector); 2199 } else { 2200 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); 2201 } 2202 2203 hdmi_video_packetize(hdmi); 2204 hdmi_video_csc(hdmi); 2205 hdmi_video_sample(hdmi); 2206 hdmi_tx_hdcp_config(hdmi); 2207 2208 dw_hdmi_clear_overflow(hdmi); 2209 2210 return 0; 2211 } 2212 2213 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) 2214 { 2215 u8 ih_mute; 2216 2217 /* 2218 * Boot up defaults are: 2219 * HDMI_IH_MUTE = 0x03 (disabled) 2220 * HDMI_IH_MUTE_* = 0x00 (enabled) 2221 * 2222 * Disable top level interrupt bits in HDMI block 2223 */ 2224 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | 2225 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2226 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; 2227 2228 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2229 2230 /* by default mask all interrupts */ 2231 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); 2232 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 2233 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 2234 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 2235 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); 2236 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); 2237 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); 2238 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); 2239 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); 2240 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); 2241 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); 2242 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); 2243 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); 2244 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); 2245 2246 /* Disable interrupts in the IH_MUTE_* registers */ 2247 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2248 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2249 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2250 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2251 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); 2252 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2253 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2254 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2255 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2256 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2257 2258 /* Enable top level interrupt bits in HDMI block */ 2259 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2260 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); 2261 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2262 } 2263 2264 static void dw_hdmi_poweron(struct dw_hdmi *hdmi) 2265 { 2266 hdmi->bridge_is_on = true; 2267 2268 /* 2269 * The curr_conn field is guaranteed to be valid here, as this function 2270 * is only be called when !hdmi->disabled. 2271 */ 2272 dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode); 2273 } 2274 2275 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) 2276 { 2277 if (hdmi->phy.enabled) { 2278 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 2279 hdmi->phy.enabled = false; 2280 } 2281 2282 hdmi->bridge_is_on = false; 2283 } 2284 2285 static void dw_hdmi_update_power(struct dw_hdmi *hdmi) 2286 { 2287 int force = hdmi->force; 2288 2289 if (hdmi->disabled) { 2290 force = DRM_FORCE_OFF; 2291 } else if (force == DRM_FORCE_UNSPECIFIED) { 2292 if (hdmi->rxsense) 2293 force = DRM_FORCE_ON; 2294 else 2295 force = DRM_FORCE_OFF; 2296 } 2297 2298 if (force == DRM_FORCE_OFF) { 2299 if (hdmi->bridge_is_on) 2300 dw_hdmi_poweroff(hdmi); 2301 } else { 2302 if (!hdmi->bridge_is_on) 2303 dw_hdmi_poweron(hdmi); 2304 } 2305 } 2306 2307 /* 2308 * Adjust the detection of RXSENSE according to whether we have a forced 2309 * connection mode enabled, or whether we have been disabled. There is 2310 * no point processing RXSENSE interrupts if we have a forced connection 2311 * state, or DRM has us disabled. 2312 * 2313 * We also disable rxsense interrupts when we think we're disconnected 2314 * to avoid floating TDMS signals giving false rxsense interrupts. 2315 * 2316 * Note: we still need to listen for HPD interrupts even when DRM has us 2317 * disabled so that we can detect a connect event. 2318 */ 2319 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) 2320 { 2321 if (hdmi->phy.ops->update_hpd) 2322 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, 2323 hdmi->force, hdmi->disabled, 2324 hdmi->rxsense); 2325 } 2326 2327 static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi) 2328 { 2329 enum drm_connector_status result; 2330 2331 result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 2332 2333 mutex_lock(&hdmi->mutex); 2334 if (result != hdmi->last_connector_result) { 2335 dev_dbg(hdmi->dev, "read_hpd result: %d", result); 2336 handle_plugged_change(hdmi, 2337 result == connector_status_connected); 2338 hdmi->last_connector_result = result; 2339 } 2340 mutex_unlock(&hdmi->mutex); 2341 2342 return result; 2343 } 2344 2345 static struct edid *dw_hdmi_get_edid(struct dw_hdmi *hdmi, 2346 struct drm_connector *connector) 2347 { 2348 struct edid *edid; 2349 2350 if (!hdmi->ddc) 2351 return NULL; 2352 2353 edid = drm_get_edid(connector, hdmi->ddc); 2354 if (!edid) { 2355 dev_dbg(hdmi->dev, "failed to get edid\n"); 2356 return NULL; 2357 } 2358 2359 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", 2360 edid->width_cm, edid->height_cm); 2361 2362 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); 2363 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2364 2365 return edid; 2366 } 2367 2368 /* ----------------------------------------------------------------------------- 2369 * DRM Connector Operations 2370 */ 2371 2372 static enum drm_connector_status 2373 dw_hdmi_connector_detect(struct drm_connector *connector, bool force) 2374 { 2375 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2376 connector); 2377 return dw_hdmi_detect(hdmi); 2378 } 2379 2380 static int dw_hdmi_connector_get_modes(struct drm_connector *connector) 2381 { 2382 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2383 connector); 2384 struct edid *edid; 2385 int ret; 2386 2387 edid = dw_hdmi_get_edid(hdmi, connector); 2388 if (!edid) 2389 return 0; 2390 2391 drm_connector_update_edid_property(connector, edid); 2392 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); 2393 ret = drm_add_edid_modes(connector, edid); 2394 kfree(edid); 2395 2396 return ret; 2397 } 2398 2399 static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, 2400 struct drm_atomic_state *state) 2401 { 2402 struct drm_connector_state *old_state = 2403 drm_atomic_get_old_connector_state(state, connector); 2404 struct drm_connector_state *new_state = 2405 drm_atomic_get_new_connector_state(state, connector); 2406 struct drm_crtc *crtc = new_state->crtc; 2407 struct drm_crtc_state *crtc_state; 2408 2409 if (!crtc) 2410 return 0; 2411 2412 if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 2413 crtc_state = drm_atomic_get_crtc_state(state, crtc); 2414 if (IS_ERR(crtc_state)) 2415 return PTR_ERR(crtc_state); 2416 2417 crtc_state->mode_changed = true; 2418 } 2419 2420 return 0; 2421 } 2422 2423 static void dw_hdmi_connector_force(struct drm_connector *connector) 2424 { 2425 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2426 connector); 2427 2428 mutex_lock(&hdmi->mutex); 2429 hdmi->force = connector->force; 2430 dw_hdmi_update_power(hdmi); 2431 dw_hdmi_update_phy_mask(hdmi); 2432 mutex_unlock(&hdmi->mutex); 2433 } 2434 2435 static const struct drm_connector_funcs dw_hdmi_connector_funcs = { 2436 .fill_modes = drm_helper_probe_single_connector_modes, 2437 .detect = dw_hdmi_connector_detect, 2438 .destroy = drm_connector_cleanup, 2439 .force = dw_hdmi_connector_force, 2440 .reset = drm_atomic_helper_connector_reset, 2441 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2442 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2443 }; 2444 2445 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { 2446 .get_modes = dw_hdmi_connector_get_modes, 2447 .atomic_check = dw_hdmi_connector_atomic_check, 2448 }; 2449 2450 static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) 2451 { 2452 struct drm_connector *connector = &hdmi->connector; 2453 struct cec_connector_info conn_info; 2454 struct cec_notifier *notifier; 2455 2456 if (hdmi->version >= 0x200a) 2457 connector->ycbcr_420_allowed = 2458 hdmi->plat_data->ycbcr_420_allowed; 2459 else 2460 connector->ycbcr_420_allowed = false; 2461 2462 connector->interlace_allowed = 1; 2463 connector->polled = DRM_CONNECTOR_POLL_HPD; 2464 2465 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); 2466 2467 drm_connector_init_with_ddc(hdmi->bridge.dev, connector, 2468 &dw_hdmi_connector_funcs, 2469 DRM_MODE_CONNECTOR_HDMIA, 2470 hdmi->ddc); 2471 2472 /* 2473 * drm_connector_attach_max_bpc_property() requires the 2474 * connector to have a state. 2475 */ 2476 drm_atomic_helper_connector_reset(connector); 2477 2478 drm_connector_attach_max_bpc_property(connector, 8, 16); 2479 2480 if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe) 2481 drm_connector_attach_hdr_output_metadata_property(connector); 2482 2483 drm_connector_attach_encoder(connector, hdmi->bridge.encoder); 2484 2485 cec_fill_conn_info_from_drm(&conn_info, connector); 2486 2487 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info); 2488 if (!notifier) 2489 return -ENOMEM; 2490 2491 mutex_lock(&hdmi->cec_notifier_mutex); 2492 hdmi->cec_notifier = notifier; 2493 mutex_unlock(&hdmi->cec_notifier_mutex); 2494 2495 return 0; 2496 } 2497 2498 /* ----------------------------------------------------------------------------- 2499 * DRM Bridge Operations 2500 */ 2501 2502 /* 2503 * Possible output formats : 2504 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48, 2505 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36, 2506 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30, 2507 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24, 2508 * - MEDIA_BUS_FMT_YUV16_1X48, 2509 * - MEDIA_BUS_FMT_RGB161616_1X48, 2510 * - MEDIA_BUS_FMT_UYVY12_1X24, 2511 * - MEDIA_BUS_FMT_YUV12_1X36, 2512 * - MEDIA_BUS_FMT_RGB121212_1X36, 2513 * - MEDIA_BUS_FMT_UYVY10_1X20, 2514 * - MEDIA_BUS_FMT_YUV10_1X30, 2515 * - MEDIA_BUS_FMT_RGB101010_1X30, 2516 * - MEDIA_BUS_FMT_UYVY8_1X16, 2517 * - MEDIA_BUS_FMT_YUV8_1X24, 2518 * - MEDIA_BUS_FMT_RGB888_1X24, 2519 */ 2520 2521 /* Can return a maximum of 11 possible output formats for a mode/connector */ 2522 #define MAX_OUTPUT_SEL_FORMATS 11 2523 2524 static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, 2525 struct drm_bridge_state *bridge_state, 2526 struct drm_crtc_state *crtc_state, 2527 struct drm_connector_state *conn_state, 2528 unsigned int *num_output_fmts) 2529 { 2530 struct drm_connector *conn = conn_state->connector; 2531 struct drm_display_info *info = &conn->display_info; 2532 struct drm_display_mode *mode = &crtc_state->mode; 2533 u8 max_bpc = conn_state->max_requested_bpc; 2534 bool is_hdmi2_sink = info->hdmi.scdc.supported || 2535 (info->color_formats & DRM_COLOR_FORMAT_YCRCB420); 2536 u32 *output_fmts; 2537 unsigned int i = 0; 2538 2539 *num_output_fmts = 0; 2540 2541 output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts), 2542 GFP_KERNEL); 2543 if (!output_fmts) 2544 return NULL; 2545 2546 /* If dw-hdmi is the only bridge, avoid negociating with ourselves */ 2547 if (list_is_singular(&bridge->encoder->bridge_chain)) { 2548 *num_output_fmts = 1; 2549 output_fmts[0] = MEDIA_BUS_FMT_FIXED; 2550 2551 return output_fmts; 2552 } 2553 2554 /* 2555 * If the current mode enforces 4:2:0, force the output but format 2556 * to 4:2:0 and do not add the YUV422/444/RGB formats 2557 */ 2558 if (conn->ycbcr_420_allowed && 2559 (drm_mode_is_420_only(info, mode) || 2560 (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) { 2561 2562 /* Order bus formats from 16bit to 8bit if supported */ 2563 if (max_bpc >= 16 && info->bpc == 16 && 2564 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)) 2565 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48; 2566 2567 if (max_bpc >= 12 && info->bpc >= 12 && 2568 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)) 2569 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36; 2570 2571 if (max_bpc >= 10 && info->bpc >= 10 && 2572 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)) 2573 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30; 2574 2575 /* Default 8bit fallback */ 2576 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24; 2577 2578 *num_output_fmts = i; 2579 2580 return output_fmts; 2581 } 2582 2583 /* 2584 * Order bus formats from 16bit to 8bit and from YUV422 to RGB 2585 * if supported. In any case the default RGB888 format is added 2586 */ 2587 2588 if (max_bpc >= 16 && info->bpc == 16) { 2589 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) 2590 output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2591 2592 output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2593 } 2594 2595 if (max_bpc >= 12 && info->bpc >= 12) { 2596 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) 2597 output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2598 2599 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) 2600 output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2601 2602 output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2603 } 2604 2605 if (max_bpc >= 10 && info->bpc >= 10) { 2606 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) 2607 output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2608 2609 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) 2610 output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2611 2612 output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2613 } 2614 2615 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) 2616 output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2617 2618 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) 2619 output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2620 2621 /* Default 8bit RGB fallback */ 2622 output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2623 2624 *num_output_fmts = i; 2625 2626 return output_fmts; 2627 } 2628 2629 /* 2630 * Possible input formats : 2631 * - MEDIA_BUS_FMT_RGB888_1X24 2632 * - MEDIA_BUS_FMT_YUV8_1X24 2633 * - MEDIA_BUS_FMT_UYVY8_1X16 2634 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24 2635 * - MEDIA_BUS_FMT_RGB101010_1X30 2636 * - MEDIA_BUS_FMT_YUV10_1X30 2637 * - MEDIA_BUS_FMT_UYVY10_1X20 2638 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30 2639 * - MEDIA_BUS_FMT_RGB121212_1X36 2640 * - MEDIA_BUS_FMT_YUV12_1X36 2641 * - MEDIA_BUS_FMT_UYVY12_1X24 2642 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36 2643 * - MEDIA_BUS_FMT_RGB161616_1X48 2644 * - MEDIA_BUS_FMT_YUV16_1X48 2645 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48 2646 */ 2647 2648 /* Can return a maximum of 3 possible input formats for an output format */ 2649 #define MAX_INPUT_SEL_FORMATS 3 2650 2651 static u32 *dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 2652 struct drm_bridge_state *bridge_state, 2653 struct drm_crtc_state *crtc_state, 2654 struct drm_connector_state *conn_state, 2655 u32 output_fmt, 2656 unsigned int *num_input_fmts) 2657 { 2658 u32 *input_fmts; 2659 unsigned int i = 0; 2660 2661 *num_input_fmts = 0; 2662 2663 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 2664 GFP_KERNEL); 2665 if (!input_fmts) 2666 return NULL; 2667 2668 switch (output_fmt) { 2669 /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */ 2670 case MEDIA_BUS_FMT_FIXED: 2671 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2672 break; 2673 /* 8bit */ 2674 case MEDIA_BUS_FMT_RGB888_1X24: 2675 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2676 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2677 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2678 break; 2679 case MEDIA_BUS_FMT_YUV8_1X24: 2680 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2681 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2682 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2683 break; 2684 case MEDIA_BUS_FMT_UYVY8_1X16: 2685 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2686 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2687 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2688 break; 2689 2690 /* 10bit */ 2691 case MEDIA_BUS_FMT_RGB101010_1X30: 2692 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2693 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2694 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2695 break; 2696 case MEDIA_BUS_FMT_YUV10_1X30: 2697 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2698 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2699 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2700 break; 2701 case MEDIA_BUS_FMT_UYVY10_1X20: 2702 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2703 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2704 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2705 break; 2706 2707 /* 12bit */ 2708 case MEDIA_BUS_FMT_RGB121212_1X36: 2709 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2710 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2711 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2712 break; 2713 case MEDIA_BUS_FMT_YUV12_1X36: 2714 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2715 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2716 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2717 break; 2718 case MEDIA_BUS_FMT_UYVY12_1X24: 2719 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2720 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2721 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2722 break; 2723 2724 /* 16bit */ 2725 case MEDIA_BUS_FMT_RGB161616_1X48: 2726 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2727 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2728 break; 2729 case MEDIA_BUS_FMT_YUV16_1X48: 2730 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2731 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2732 break; 2733 2734 /*YUV 4:2:0 */ 2735 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 2736 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 2737 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 2738 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 2739 input_fmts[i++] = output_fmt; 2740 break; 2741 } 2742 2743 *num_input_fmts = i; 2744 2745 if (*num_input_fmts == 0) { 2746 kfree(input_fmts); 2747 input_fmts = NULL; 2748 } 2749 2750 return input_fmts; 2751 } 2752 2753 static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge, 2754 struct drm_bridge_state *bridge_state, 2755 struct drm_crtc_state *crtc_state, 2756 struct drm_connector_state *conn_state) 2757 { 2758 struct dw_hdmi *hdmi = bridge->driver_private; 2759 2760 hdmi->hdmi_data.enc_out_bus_format = 2761 bridge_state->output_bus_cfg.format; 2762 2763 hdmi->hdmi_data.enc_in_bus_format = 2764 bridge_state->input_bus_cfg.format; 2765 2766 dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n", 2767 bridge_state->input_bus_cfg.format, 2768 bridge_state->output_bus_cfg.format); 2769 2770 return 0; 2771 } 2772 2773 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge, 2774 enum drm_bridge_attach_flags flags) 2775 { 2776 struct dw_hdmi *hdmi = bridge->driver_private; 2777 2778 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) 2779 return drm_bridge_attach(bridge->encoder, hdmi->next_bridge, 2780 bridge, flags); 2781 2782 return dw_hdmi_connector_create(hdmi); 2783 } 2784 2785 static void dw_hdmi_bridge_detach(struct drm_bridge *bridge) 2786 { 2787 struct dw_hdmi *hdmi = bridge->driver_private; 2788 2789 mutex_lock(&hdmi->cec_notifier_mutex); 2790 cec_notifier_conn_unregister(hdmi->cec_notifier); 2791 hdmi->cec_notifier = NULL; 2792 mutex_unlock(&hdmi->cec_notifier_mutex); 2793 } 2794 2795 static enum drm_mode_status 2796 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 2797 const struct drm_display_info *info, 2798 const struct drm_display_mode *mode) 2799 { 2800 struct dw_hdmi *hdmi = bridge->driver_private; 2801 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 2802 enum drm_mode_status mode_status = MODE_OK; 2803 2804 /* We don't support double-clocked modes */ 2805 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2806 return MODE_BAD; 2807 2808 if (pdata->mode_valid) 2809 mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info, 2810 mode); 2811 2812 return mode_status; 2813 } 2814 2815 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, 2816 const struct drm_display_mode *orig_mode, 2817 const struct drm_display_mode *mode) 2818 { 2819 struct dw_hdmi *hdmi = bridge->driver_private; 2820 2821 mutex_lock(&hdmi->mutex); 2822 2823 /* Store the display mode for plugin/DKMS poweron events */ 2824 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 2825 2826 mutex_unlock(&hdmi->mutex); 2827 } 2828 2829 static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, 2830 struct drm_bridge_state *old_state) 2831 { 2832 struct dw_hdmi *hdmi = bridge->driver_private; 2833 2834 mutex_lock(&hdmi->mutex); 2835 hdmi->disabled = true; 2836 hdmi->curr_conn = NULL; 2837 dw_hdmi_update_power(hdmi); 2838 dw_hdmi_update_phy_mask(hdmi); 2839 mutex_unlock(&hdmi->mutex); 2840 } 2841 2842 static void dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, 2843 struct drm_bridge_state *old_state) 2844 { 2845 struct dw_hdmi *hdmi = bridge->driver_private; 2846 struct drm_atomic_state *state = old_state->base.state; 2847 struct drm_connector *connector; 2848 2849 connector = drm_atomic_get_new_connector_for_encoder(state, 2850 bridge->encoder); 2851 2852 mutex_lock(&hdmi->mutex); 2853 hdmi->disabled = false; 2854 hdmi->curr_conn = connector; 2855 dw_hdmi_update_power(hdmi); 2856 dw_hdmi_update_phy_mask(hdmi); 2857 mutex_unlock(&hdmi->mutex); 2858 } 2859 2860 static enum drm_connector_status dw_hdmi_bridge_detect(struct drm_bridge *bridge) 2861 { 2862 struct dw_hdmi *hdmi = bridge->driver_private; 2863 2864 return dw_hdmi_detect(hdmi); 2865 } 2866 2867 static struct edid *dw_hdmi_bridge_get_edid(struct drm_bridge *bridge, 2868 struct drm_connector *connector) 2869 { 2870 struct dw_hdmi *hdmi = bridge->driver_private; 2871 2872 return dw_hdmi_get_edid(hdmi, connector); 2873 } 2874 2875 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { 2876 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 2877 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 2878 .atomic_reset = drm_atomic_helper_bridge_reset, 2879 .attach = dw_hdmi_bridge_attach, 2880 .detach = dw_hdmi_bridge_detach, 2881 .atomic_check = dw_hdmi_bridge_atomic_check, 2882 .atomic_get_output_bus_fmts = dw_hdmi_bridge_atomic_get_output_bus_fmts, 2883 .atomic_get_input_bus_fmts = dw_hdmi_bridge_atomic_get_input_bus_fmts, 2884 .atomic_enable = dw_hdmi_bridge_atomic_enable, 2885 .atomic_disable = dw_hdmi_bridge_atomic_disable, 2886 .mode_set = dw_hdmi_bridge_mode_set, 2887 .mode_valid = dw_hdmi_bridge_mode_valid, 2888 .detect = dw_hdmi_bridge_detect, 2889 .get_edid = dw_hdmi_bridge_get_edid, 2890 }; 2891 2892 /* ----------------------------------------------------------------------------- 2893 * IRQ Handling 2894 */ 2895 2896 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) 2897 { 2898 struct dw_hdmi_i2c *i2c = hdmi->i2c; 2899 unsigned int stat; 2900 2901 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 2902 if (!stat) 2903 return IRQ_NONE; 2904 2905 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0); 2906 2907 i2c->stat = stat; 2908 2909 complete(&i2c->cmp); 2910 2911 return IRQ_HANDLED; 2912 } 2913 2914 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) 2915 { 2916 struct dw_hdmi *hdmi = dev_id; 2917 u8 intr_stat; 2918 irqreturn_t ret = IRQ_NONE; 2919 2920 if (hdmi->i2c) 2921 ret = dw_hdmi_i2c_irq(hdmi); 2922 2923 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2924 if (intr_stat) { 2925 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2926 return IRQ_WAKE_THREAD; 2927 } 2928 2929 return ret; 2930 } 2931 2932 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) 2933 { 2934 mutex_lock(&hdmi->mutex); 2935 2936 if (!hdmi->force) { 2937 /* 2938 * If the RX sense status indicates we're disconnected, 2939 * clear the software rxsense status. 2940 */ 2941 if (!rx_sense) 2942 hdmi->rxsense = false; 2943 2944 /* 2945 * Only set the software rxsense status when both 2946 * rxsense and hpd indicates we're connected. 2947 * This avoids what seems to be bad behaviour in 2948 * at least iMX6S versions of the phy. 2949 */ 2950 if (hpd) 2951 hdmi->rxsense = true; 2952 2953 dw_hdmi_update_power(hdmi); 2954 dw_hdmi_update_phy_mask(hdmi); 2955 } 2956 mutex_unlock(&hdmi->mutex); 2957 } 2958 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); 2959 2960 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) 2961 { 2962 struct dw_hdmi *hdmi = dev_id; 2963 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; 2964 2965 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2966 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); 2967 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); 2968 2969 phy_pol_mask = 0; 2970 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) 2971 phy_pol_mask |= HDMI_PHY_HPD; 2972 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) 2973 phy_pol_mask |= HDMI_PHY_RX_SENSE0; 2974 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) 2975 phy_pol_mask |= HDMI_PHY_RX_SENSE1; 2976 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) 2977 phy_pol_mask |= HDMI_PHY_RX_SENSE2; 2978 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) 2979 phy_pol_mask |= HDMI_PHY_RX_SENSE3; 2980 2981 if (phy_pol_mask) 2982 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); 2983 2984 /* 2985 * RX sense tells us whether the TDMS transmitters are detecting 2986 * load - in other words, there's something listening on the 2987 * other end of the link. Use this to decide whether we should 2988 * power on the phy as HPD may be toggled by the sink to merely 2989 * ask the source to re-read the EDID. 2990 */ 2991 if (intr_stat & 2992 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { 2993 dw_hdmi_setup_rx_sense(hdmi, 2994 phy_stat & HDMI_PHY_HPD, 2995 phy_stat & HDMI_PHY_RX_SENSE); 2996 2997 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) { 2998 mutex_lock(&hdmi->cec_notifier_mutex); 2999 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); 3000 mutex_unlock(&hdmi->cec_notifier_mutex); 3001 } 3002 } 3003 3004 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { 3005 enum drm_connector_status status = phy_int_pol & HDMI_PHY_HPD 3006 ? connector_status_connected 3007 : connector_status_disconnected; 3008 3009 dev_dbg(hdmi->dev, "EVENT=%s\n", 3010 status == connector_status_connected ? 3011 "plugin" : "plugout"); 3012 3013 if (hdmi->bridge.dev) { 3014 drm_helper_hpd_irq_event(hdmi->bridge.dev); 3015 drm_bridge_hpd_notify(&hdmi->bridge, status); 3016 } 3017 } 3018 3019 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); 3020 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 3021 HDMI_IH_MUTE_PHY_STAT0); 3022 3023 return IRQ_HANDLED; 3024 } 3025 3026 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 3027 { 3028 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 3029 .name = "DWC HDMI TX PHY", 3030 .gen = 1, 3031 }, { 3032 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 3033 .name = "DWC MHL PHY + HEAC PHY", 3034 .gen = 2, 3035 .has_svsret = true, 3036 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3037 }, { 3038 .type = DW_HDMI_PHY_DWC_MHL_PHY, 3039 .name = "DWC MHL PHY", 3040 .gen = 2, 3041 .has_svsret = true, 3042 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3043 }, { 3044 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 3045 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 3046 .gen = 2, 3047 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3048 }, { 3049 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 3050 .name = "DWC HDMI 3D TX PHY", 3051 .gen = 2, 3052 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3053 }, { 3054 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 3055 .name = "DWC HDMI 2.0 TX PHY", 3056 .gen = 2, 3057 .has_svsret = true, 3058 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3059 }, { 3060 .type = DW_HDMI_PHY_VENDOR_PHY, 3061 .name = "Vendor PHY", 3062 } 3063 }; 3064 3065 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 3066 { 3067 unsigned int i; 3068 u8 phy_type; 3069 3070 phy_type = hdmi->plat_data->phy_force_vendor ? 3071 DW_HDMI_PHY_VENDOR_PHY : 3072 hdmi_readb(hdmi, HDMI_CONFIG2_ID); 3073 3074 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { 3075 /* Vendor PHYs require support from the glue layer. */ 3076 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 3077 dev_err(hdmi->dev, 3078 "Vendor HDMI PHY not supported by glue layer\n"); 3079 return -ENODEV; 3080 } 3081 3082 hdmi->phy.ops = hdmi->plat_data->phy_ops; 3083 hdmi->phy.data = hdmi->plat_data->phy_data; 3084 hdmi->phy.name = hdmi->plat_data->phy_name; 3085 return 0; 3086 } 3087 3088 /* Synopsys PHYs are handled internally. */ 3089 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 3090 if (dw_hdmi_phys[i].type == phy_type) { 3091 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 3092 hdmi->phy.name = dw_hdmi_phys[i].name; 3093 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 3094 3095 if (!dw_hdmi_phys[i].configure && 3096 !hdmi->plat_data->configure_phy) { 3097 dev_err(hdmi->dev, "%s requires platform support\n", 3098 hdmi->phy.name); 3099 return -ENODEV; 3100 } 3101 3102 return 0; 3103 } 3104 } 3105 3106 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); 3107 return -ENODEV; 3108 } 3109 3110 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi) 3111 { 3112 mutex_lock(&hdmi->mutex); 3113 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE; 3114 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 3115 mutex_unlock(&hdmi->mutex); 3116 } 3117 3118 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi) 3119 { 3120 mutex_lock(&hdmi->mutex); 3121 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE; 3122 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 3123 mutex_unlock(&hdmi->mutex); 3124 } 3125 3126 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = { 3127 .write = hdmi_writeb, 3128 .read = hdmi_readb, 3129 .enable = dw_hdmi_cec_enable, 3130 .disable = dw_hdmi_cec_disable, 3131 }; 3132 3133 static const struct regmap_config hdmi_regmap_8bit_config = { 3134 .reg_bits = 32, 3135 .val_bits = 8, 3136 .reg_stride = 1, 3137 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, 3138 }; 3139 3140 static const struct regmap_config hdmi_regmap_32bit_config = { 3141 .reg_bits = 32, 3142 .val_bits = 32, 3143 .reg_stride = 4, 3144 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, 3145 }; 3146 3147 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi) 3148 { 3149 initialize_hdmi_ih_mutes(hdmi); 3150 3151 /* 3152 * Reset HDMI DDC I2C master controller and mute I2CM interrupts. 3153 * Even if we are using a separate i2c adapter doing this doesn't 3154 * hurt. 3155 */ 3156 dw_hdmi_i2c_init(hdmi); 3157 3158 if (hdmi->phy.ops->setup_hpd) 3159 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 3160 } 3161 3162 /* ----------------------------------------------------------------------------- 3163 * Probe/remove API, used from platforms based on the DRM bridge API. 3164 */ 3165 3166 static int dw_hdmi_parse_dt(struct dw_hdmi *hdmi) 3167 { 3168 struct device_node *endpoint; 3169 struct device_node *remote; 3170 3171 if (!hdmi->plat_data->output_port) 3172 return 0; 3173 3174 endpoint = of_graph_get_endpoint_by_regs(hdmi->dev->of_node, 3175 hdmi->plat_data->output_port, 3176 -1); 3177 if (!endpoint) { 3178 /* 3179 * On platforms whose bindings don't make the output port 3180 * mandatory (such as Rockchip) the plat_data->output_port 3181 * field isn't set, so it's safe to make this a fatal error. 3182 */ 3183 dev_err(hdmi->dev, "Missing endpoint in port@%u\n", 3184 hdmi->plat_data->output_port); 3185 return -ENODEV; 3186 } 3187 3188 remote = of_graph_get_remote_port_parent(endpoint); 3189 of_node_put(endpoint); 3190 if (!remote) { 3191 dev_err(hdmi->dev, "Endpoint in port@%u unconnected\n", 3192 hdmi->plat_data->output_port); 3193 return -ENODEV; 3194 } 3195 3196 if (!of_device_is_available(remote)) { 3197 dev_err(hdmi->dev, "port@%u remote device is disabled\n", 3198 hdmi->plat_data->output_port); 3199 of_node_put(remote); 3200 return -ENODEV; 3201 } 3202 3203 hdmi->next_bridge = of_drm_find_bridge(remote); 3204 of_node_put(remote); 3205 if (!hdmi->next_bridge) 3206 return -EPROBE_DEFER; 3207 3208 return 0; 3209 } 3210 3211 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, 3212 const struct dw_hdmi_plat_data *plat_data) 3213 { 3214 struct device *dev = &pdev->dev; 3215 struct device_node *np = dev->of_node; 3216 struct platform_device_info pdevinfo; 3217 struct device_node *ddc_node; 3218 struct dw_hdmi_cec_data cec; 3219 struct dw_hdmi *hdmi; 3220 struct resource *iores = NULL; 3221 int irq; 3222 int ret; 3223 u32 val = 1; 3224 u8 prod_id0; 3225 u8 prod_id1; 3226 u8 config0; 3227 u8 config3; 3228 3229 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 3230 if (!hdmi) 3231 return ERR_PTR(-ENOMEM); 3232 3233 hdmi->plat_data = plat_data; 3234 hdmi->dev = dev; 3235 hdmi->sample_rate = 48000; 3236 hdmi->disabled = true; 3237 hdmi->rxsense = true; 3238 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); 3239 hdmi->mc_clkdis = 0x7f; 3240 hdmi->last_connector_result = connector_status_disconnected; 3241 3242 mutex_init(&hdmi->mutex); 3243 mutex_init(&hdmi->audio_mutex); 3244 mutex_init(&hdmi->cec_notifier_mutex); 3245 spin_lock_init(&hdmi->audio_lock); 3246 3247 ret = dw_hdmi_parse_dt(hdmi); 3248 if (ret < 0) 3249 return ERR_PTR(ret); 3250 3251 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 3252 if (ddc_node) { 3253 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); 3254 of_node_put(ddc_node); 3255 if (!hdmi->ddc) { 3256 dev_dbg(hdmi->dev, "failed to read ddc node\n"); 3257 return ERR_PTR(-EPROBE_DEFER); 3258 } 3259 3260 } else { 3261 dev_dbg(hdmi->dev, "no ddc property found\n"); 3262 } 3263 3264 if (!plat_data->regm) { 3265 const struct regmap_config *reg_config; 3266 3267 of_property_read_u32(np, "reg-io-width", &val); 3268 switch (val) { 3269 case 4: 3270 reg_config = &hdmi_regmap_32bit_config; 3271 hdmi->reg_shift = 2; 3272 break; 3273 case 1: 3274 reg_config = &hdmi_regmap_8bit_config; 3275 break; 3276 default: 3277 dev_err(dev, "reg-io-width must be 1 or 4\n"); 3278 return ERR_PTR(-EINVAL); 3279 } 3280 3281 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3282 hdmi->regs = devm_ioremap_resource(dev, iores); 3283 if (IS_ERR(hdmi->regs)) { 3284 ret = PTR_ERR(hdmi->regs); 3285 goto err_res; 3286 } 3287 3288 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); 3289 if (IS_ERR(hdmi->regm)) { 3290 dev_err(dev, "Failed to configure regmap\n"); 3291 ret = PTR_ERR(hdmi->regm); 3292 goto err_res; 3293 } 3294 } else { 3295 hdmi->regm = plat_data->regm; 3296 } 3297 3298 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); 3299 if (IS_ERR(hdmi->isfr_clk)) { 3300 ret = PTR_ERR(hdmi->isfr_clk); 3301 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); 3302 goto err_res; 3303 } 3304 3305 ret = clk_prepare_enable(hdmi->isfr_clk); 3306 if (ret) { 3307 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret); 3308 goto err_res; 3309 } 3310 3311 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); 3312 if (IS_ERR(hdmi->iahb_clk)) { 3313 ret = PTR_ERR(hdmi->iahb_clk); 3314 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); 3315 goto err_isfr; 3316 } 3317 3318 ret = clk_prepare_enable(hdmi->iahb_clk); 3319 if (ret) { 3320 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret); 3321 goto err_isfr; 3322 } 3323 3324 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec"); 3325 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) { 3326 hdmi->cec_clk = NULL; 3327 } else if (IS_ERR(hdmi->cec_clk)) { 3328 ret = PTR_ERR(hdmi->cec_clk); 3329 if (ret != -EPROBE_DEFER) 3330 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n", 3331 ret); 3332 3333 hdmi->cec_clk = NULL; 3334 goto err_iahb; 3335 } else { 3336 ret = clk_prepare_enable(hdmi->cec_clk); 3337 if (ret) { 3338 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n", 3339 ret); 3340 goto err_iahb; 3341 } 3342 } 3343 3344 /* Product and revision IDs */ 3345 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 3346 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 3347 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); 3348 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); 3349 3350 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || 3351 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { 3352 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", 3353 hdmi->version, prod_id0, prod_id1); 3354 ret = -ENODEV; 3355 goto err_iahb; 3356 } 3357 3358 ret = dw_hdmi_detect_phy(hdmi); 3359 if (ret < 0) 3360 goto err_iahb; 3361 3362 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", 3363 hdmi->version >> 12, hdmi->version & 0xfff, 3364 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", 3365 hdmi->phy.name); 3366 3367 dw_hdmi_init_hw(hdmi); 3368 3369 irq = platform_get_irq(pdev, 0); 3370 if (irq < 0) { 3371 ret = irq; 3372 goto err_iahb; 3373 } 3374 3375 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, 3376 dw_hdmi_irq, IRQF_SHARED, 3377 dev_name(dev), hdmi); 3378 if (ret) 3379 goto err_iahb; 3380 3381 /* 3382 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator 3383 * N and cts values before enabling phy 3384 */ 3385 hdmi_init_clk_regenerator(hdmi); 3386 3387 /* If DDC bus is not specified, try to register HDMI I2C bus */ 3388 if (!hdmi->ddc) { 3389 /* Look for (optional) stuff related to unwedging */ 3390 hdmi->pinctrl = devm_pinctrl_get(dev); 3391 if (!IS_ERR(hdmi->pinctrl)) { 3392 hdmi->unwedge_state = 3393 pinctrl_lookup_state(hdmi->pinctrl, "unwedge"); 3394 hdmi->default_state = 3395 pinctrl_lookup_state(hdmi->pinctrl, "default"); 3396 3397 if (IS_ERR(hdmi->default_state) || 3398 IS_ERR(hdmi->unwedge_state)) { 3399 if (!IS_ERR(hdmi->unwedge_state)) 3400 dev_warn(dev, 3401 "Unwedge requires default pinctrl\n"); 3402 hdmi->default_state = NULL; 3403 hdmi->unwedge_state = NULL; 3404 } 3405 } 3406 3407 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); 3408 if (IS_ERR(hdmi->ddc)) 3409 hdmi->ddc = NULL; 3410 } 3411 3412 hdmi->bridge.driver_private = hdmi; 3413 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; 3414 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID 3415 | DRM_BRIDGE_OP_HPD; 3416 #ifdef CONFIG_OF 3417 hdmi->bridge.of_node = pdev->dev.of_node; 3418 #endif 3419 3420 memset(&pdevinfo, 0, sizeof(pdevinfo)); 3421 pdevinfo.parent = dev; 3422 pdevinfo.id = PLATFORM_DEVID_AUTO; 3423 3424 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); 3425 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 3426 3427 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { 3428 struct dw_hdmi_audio_data audio; 3429 3430 audio.phys = iores->start; 3431 audio.base = hdmi->regs; 3432 audio.irq = irq; 3433 audio.hdmi = hdmi; 3434 audio.eld = hdmi->connector.eld; 3435 hdmi->enable_audio = dw_hdmi_ahb_audio_enable; 3436 hdmi->disable_audio = dw_hdmi_ahb_audio_disable; 3437 3438 pdevinfo.name = "dw-hdmi-ahb-audio"; 3439 pdevinfo.data = &audio; 3440 pdevinfo.size_data = sizeof(audio); 3441 pdevinfo.dma_mask = DMA_BIT_MASK(32); 3442 hdmi->audio = platform_device_register_full(&pdevinfo); 3443 } else if (config0 & HDMI_CONFIG0_I2S) { 3444 struct dw_hdmi_i2s_audio_data audio; 3445 3446 audio.hdmi = hdmi; 3447 audio.eld = hdmi->connector.eld; 3448 audio.write = hdmi_writeb; 3449 audio.read = hdmi_readb; 3450 hdmi->enable_audio = dw_hdmi_i2s_audio_enable; 3451 hdmi->disable_audio = dw_hdmi_i2s_audio_disable; 3452 3453 pdevinfo.name = "dw-hdmi-i2s-audio"; 3454 pdevinfo.data = &audio; 3455 pdevinfo.size_data = sizeof(audio); 3456 pdevinfo.dma_mask = DMA_BIT_MASK(32); 3457 hdmi->audio = platform_device_register_full(&pdevinfo); 3458 } 3459 3460 if (!plat_data->disable_cec && (config0 & HDMI_CONFIG0_CEC)) { 3461 cec.hdmi = hdmi; 3462 cec.ops = &dw_hdmi_cec_ops; 3463 cec.irq = irq; 3464 3465 pdevinfo.name = "dw-hdmi-cec"; 3466 pdevinfo.data = &cec; 3467 pdevinfo.size_data = sizeof(cec); 3468 pdevinfo.dma_mask = 0; 3469 3470 hdmi->cec = platform_device_register_full(&pdevinfo); 3471 } 3472 3473 drm_bridge_add(&hdmi->bridge); 3474 3475 return hdmi; 3476 3477 err_iahb: 3478 clk_disable_unprepare(hdmi->iahb_clk); 3479 clk_disable_unprepare(hdmi->cec_clk); 3480 err_isfr: 3481 clk_disable_unprepare(hdmi->isfr_clk); 3482 err_res: 3483 i2c_put_adapter(hdmi->ddc); 3484 3485 return ERR_PTR(ret); 3486 } 3487 EXPORT_SYMBOL_GPL(dw_hdmi_probe); 3488 3489 void dw_hdmi_remove(struct dw_hdmi *hdmi) 3490 { 3491 drm_bridge_remove(&hdmi->bridge); 3492 3493 if (hdmi->audio && !IS_ERR(hdmi->audio)) 3494 platform_device_unregister(hdmi->audio); 3495 if (!IS_ERR(hdmi->cec)) 3496 platform_device_unregister(hdmi->cec); 3497 3498 /* Disable all interrupts */ 3499 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 3500 3501 clk_disable_unprepare(hdmi->iahb_clk); 3502 clk_disable_unprepare(hdmi->isfr_clk); 3503 clk_disable_unprepare(hdmi->cec_clk); 3504 3505 if (hdmi->i2c) 3506 i2c_del_adapter(&hdmi->i2c->adap); 3507 else 3508 i2c_put_adapter(hdmi->ddc); 3509 } 3510 EXPORT_SYMBOL_GPL(dw_hdmi_remove); 3511 3512 /* ----------------------------------------------------------------------------- 3513 * Bind/unbind API, used from platforms based on the component framework. 3514 */ 3515 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, 3516 struct drm_encoder *encoder, 3517 const struct dw_hdmi_plat_data *plat_data) 3518 { 3519 struct dw_hdmi *hdmi; 3520 int ret; 3521 3522 hdmi = dw_hdmi_probe(pdev, plat_data); 3523 if (IS_ERR(hdmi)) 3524 return hdmi; 3525 3526 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0); 3527 if (ret) { 3528 dw_hdmi_remove(hdmi); 3529 return ERR_PTR(ret); 3530 } 3531 3532 return hdmi; 3533 } 3534 EXPORT_SYMBOL_GPL(dw_hdmi_bind); 3535 3536 void dw_hdmi_unbind(struct dw_hdmi *hdmi) 3537 { 3538 dw_hdmi_remove(hdmi); 3539 } 3540 EXPORT_SYMBOL_GPL(dw_hdmi_unbind); 3541 3542 void dw_hdmi_resume(struct dw_hdmi *hdmi) 3543 { 3544 dw_hdmi_init_hw(hdmi); 3545 } 3546 EXPORT_SYMBOL_GPL(dw_hdmi_resume); 3547 3548 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 3549 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); 3550 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); 3551 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>"); 3552 MODULE_DESCRIPTION("DW HDMI transmitter driver"); 3553 MODULE_LICENSE("GPL"); 3554 MODULE_ALIAS("platform:dw-hdmi"); 3555