1 /* 2 * DesignWare High-Definition Multimedia Interface (HDMI) driver 3 * 4 * Copyright (C) 2013-2015 Mentor Graphics Inc. 5 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 6 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 */ 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/hdmi.h> 18 #include <linux/irq.h> 19 #include <linux/module.h> 20 #include <linux/mutex.h> 21 #include <linux/of_device.h> 22 #include <linux/regmap.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/spinlock.h> 25 26 #include <media/cec-notifier.h> 27 28 #include <uapi/linux/media-bus-format.h> 29 #include <uapi/linux/videodev2.h> 30 31 #include <drm/bridge/dw_hdmi.h> 32 #include <drm/drm_atomic_helper.h> 33 #include <drm/drm_edid.h> 34 #include <drm/drm_encoder_slave.h> 35 #include <drm/drm_of.h> 36 #include <drm/drm_print.h> 37 #include <drm/drm_probe_helper.h> 38 #include <drm/drm_scdc_helper.h> 39 40 #include "dw-hdmi-audio.h" 41 #include "dw-hdmi-cec.h" 42 #include "dw-hdmi.h" 43 44 #define DDC_SEGMENT_ADDR 0x30 45 46 #define HDMI_EDID_LEN 512 47 48 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ 49 #define SCDC_MIN_SOURCE_VERSION 0x1 50 51 #define HDMI14_MAX_TMDSCLK 340000000 52 53 enum hdmi_datamap { 54 RGB444_8B = 0x01, 55 RGB444_10B = 0x03, 56 RGB444_12B = 0x05, 57 RGB444_16B = 0x07, 58 YCbCr444_8B = 0x09, 59 YCbCr444_10B = 0x0B, 60 YCbCr444_12B = 0x0D, 61 YCbCr444_16B = 0x0F, 62 YCbCr422_8B = 0x16, 63 YCbCr422_10B = 0x14, 64 YCbCr422_12B = 0x12, 65 }; 66 67 static const u16 csc_coeff_default[3][4] = { 68 { 0x2000, 0x0000, 0x0000, 0x0000 }, 69 { 0x0000, 0x2000, 0x0000, 0x0000 }, 70 { 0x0000, 0x0000, 0x2000, 0x0000 } 71 }; 72 73 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 74 { 0x2000, 0x6926, 0x74fd, 0x010e }, 75 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 76 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 77 }; 78 79 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 80 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 81 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 82 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 83 }; 84 85 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 86 { 0x2591, 0x1322, 0x074b, 0x0000 }, 87 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 88 { 0x6acd, 0x7534, 0x2000, 0x0200 } 89 }; 90 91 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 92 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 93 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 94 { 0x6756, 0x78ab, 0x2000, 0x0200 } 95 }; 96 97 struct hdmi_vmode { 98 bool mdataenablepolarity; 99 100 unsigned int mpixelclock; 101 unsigned int mpixelrepetitioninput; 102 unsigned int mpixelrepetitionoutput; 103 unsigned int mtmdsclock; 104 }; 105 106 struct hdmi_data_info { 107 unsigned int enc_in_bus_format; 108 unsigned int enc_out_bus_format; 109 unsigned int enc_in_encoding; 110 unsigned int enc_out_encoding; 111 unsigned int pix_repet_factor; 112 unsigned int hdcp_enable; 113 struct hdmi_vmode video_mode; 114 }; 115 116 struct dw_hdmi_i2c { 117 struct i2c_adapter adap; 118 119 struct mutex lock; /* used to serialize data transfers */ 120 struct completion cmp; 121 u8 stat; 122 123 u8 slave_reg; 124 bool is_regaddr; 125 bool is_segment; 126 }; 127 128 struct dw_hdmi_phy_data { 129 enum dw_hdmi_phy_type type; 130 const char *name; 131 unsigned int gen; 132 bool has_svsret; 133 int (*configure)(struct dw_hdmi *hdmi, 134 const struct dw_hdmi_plat_data *pdata, 135 unsigned long mpixelclock); 136 }; 137 138 struct dw_hdmi { 139 struct drm_connector connector; 140 struct drm_bridge bridge; 141 142 unsigned int version; 143 144 struct platform_device *audio; 145 struct platform_device *cec; 146 struct device *dev; 147 struct clk *isfr_clk; 148 struct clk *iahb_clk; 149 struct clk *cec_clk; 150 struct dw_hdmi_i2c *i2c; 151 152 struct hdmi_data_info hdmi_data; 153 const struct dw_hdmi_plat_data *plat_data; 154 155 int vic; 156 157 u8 edid[HDMI_EDID_LEN]; 158 159 struct { 160 const struct dw_hdmi_phy_ops *ops; 161 const char *name; 162 void *data; 163 bool enabled; 164 } phy; 165 166 struct drm_display_mode previous_mode; 167 168 struct i2c_adapter *ddc; 169 void __iomem *regs; 170 bool sink_is_hdmi; 171 bool sink_has_audio; 172 173 struct mutex mutex; /* for state below and previous_mode */ 174 enum drm_connector_force force; /* mutex-protected force state */ 175 bool disabled; /* DRM has disabled our bridge */ 176 bool bridge_is_on; /* indicates the bridge is on */ 177 bool rxsense; /* rxsense state */ 178 u8 phy_mask; /* desired phy int mask settings */ 179 u8 mc_clkdis; /* clock disable register */ 180 181 spinlock_t audio_lock; 182 struct mutex audio_mutex; 183 unsigned int sample_rate; 184 unsigned int audio_cts; 185 unsigned int audio_n; 186 bool audio_enable; 187 188 unsigned int reg_shift; 189 struct regmap *regm; 190 void (*enable_audio)(struct dw_hdmi *hdmi); 191 void (*disable_audio)(struct dw_hdmi *hdmi); 192 193 struct cec_notifier *cec_notifier; 194 }; 195 196 #define HDMI_IH_PHY_STAT0_RX_SENSE \ 197 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ 198 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) 199 200 #define HDMI_PHY_RX_SENSE \ 201 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ 202 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) 203 204 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 205 { 206 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); 207 } 208 209 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 210 { 211 unsigned int val = 0; 212 213 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); 214 215 return val; 216 } 217 218 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 219 { 220 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); 221 } 222 223 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 224 u8 shift, u8 mask) 225 { 226 hdmi_modb(hdmi, data << shift, mask, reg); 227 } 228 229 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 230 { 231 /* Software reset */ 232 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 233 234 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ 235 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); 236 237 /* Set done, not acknowledged and arbitration interrupt polarities */ 238 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 239 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 240 HDMI_I2CM_CTLINT); 241 242 /* Clear DONE and ERROR interrupts */ 243 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 244 HDMI_IH_I2CM_STAT0); 245 246 /* Mute DONE and ERROR interrupts */ 247 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 248 HDMI_IH_MUTE_I2CM_STAT0); 249 } 250 251 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 252 unsigned char *buf, unsigned int length) 253 { 254 struct dw_hdmi_i2c *i2c = hdmi->i2c; 255 int stat; 256 257 if (!i2c->is_regaddr) { 258 dev_dbg(hdmi->dev, "set read register address to 0\n"); 259 i2c->slave_reg = 0x00; 260 i2c->is_regaddr = true; 261 } 262 263 while (length--) { 264 reinit_completion(&i2c->cmp); 265 266 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 267 if (i2c->is_segment) 268 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 269 HDMI_I2CM_OPERATION); 270 else 271 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 272 HDMI_I2CM_OPERATION); 273 274 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 275 if (!stat) 276 return -EAGAIN; 277 278 /* Check for error condition on the bus */ 279 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 280 return -EIO; 281 282 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 283 } 284 i2c->is_segment = false; 285 286 return 0; 287 } 288 289 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 290 unsigned char *buf, unsigned int length) 291 { 292 struct dw_hdmi_i2c *i2c = hdmi->i2c; 293 int stat; 294 295 if (!i2c->is_regaddr) { 296 /* Use the first write byte as register address */ 297 i2c->slave_reg = buf[0]; 298 length--; 299 buf++; 300 i2c->is_regaddr = true; 301 } 302 303 while (length--) { 304 reinit_completion(&i2c->cmp); 305 306 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 307 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 308 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 309 HDMI_I2CM_OPERATION); 310 311 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 312 if (!stat) 313 return -EAGAIN; 314 315 /* Check for error condition on the bus */ 316 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 317 return -EIO; 318 } 319 320 return 0; 321 } 322 323 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, 324 struct i2c_msg *msgs, int num) 325 { 326 struct dw_hdmi *hdmi = i2c_get_adapdata(adap); 327 struct dw_hdmi_i2c *i2c = hdmi->i2c; 328 u8 addr = msgs[0].addr; 329 int i, ret = 0; 330 331 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); 332 333 for (i = 0; i < num; i++) { 334 if (msgs[i].len == 0) { 335 dev_dbg(hdmi->dev, 336 "unsupported transfer %d/%d, no data\n", 337 i + 1, num); 338 return -EOPNOTSUPP; 339 } 340 } 341 342 mutex_lock(&i2c->lock); 343 344 /* Unmute DONE and ERROR interrupts */ 345 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 346 347 /* Set slave device address taken from the first I2C message */ 348 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 349 350 /* Set slave device register address on transfer */ 351 i2c->is_regaddr = false; 352 353 /* Set segment pointer for I2C extended read mode operation */ 354 i2c->is_segment = false; 355 356 for (i = 0; i < num; i++) { 357 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", 358 i + 1, num, msgs[i].len, msgs[i].flags); 359 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 360 i2c->is_segment = true; 361 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 362 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 363 } else { 364 if (msgs[i].flags & I2C_M_RD) 365 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 366 msgs[i].len); 367 else 368 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 369 msgs[i].len); 370 } 371 if (ret < 0) 372 break; 373 } 374 375 if (!ret) 376 ret = num; 377 378 /* Mute DONE and ERROR interrupts */ 379 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 380 HDMI_IH_MUTE_I2CM_STAT0); 381 382 mutex_unlock(&i2c->lock); 383 384 return ret; 385 } 386 387 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) 388 { 389 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 390 } 391 392 static const struct i2c_algorithm dw_hdmi_algorithm = { 393 .master_xfer = dw_hdmi_i2c_xfer, 394 .functionality = dw_hdmi_i2c_func, 395 }; 396 397 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) 398 { 399 struct i2c_adapter *adap; 400 struct dw_hdmi_i2c *i2c; 401 int ret; 402 403 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 404 if (!i2c) 405 return ERR_PTR(-ENOMEM); 406 407 mutex_init(&i2c->lock); 408 init_completion(&i2c->cmp); 409 410 adap = &i2c->adap; 411 adap->class = I2C_CLASS_DDC; 412 adap->owner = THIS_MODULE; 413 adap->dev.parent = hdmi->dev; 414 adap->algo = &dw_hdmi_algorithm; 415 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name)); 416 i2c_set_adapdata(adap, hdmi); 417 418 ret = i2c_add_adapter(adap); 419 if (ret) { 420 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 421 devm_kfree(hdmi->dev, i2c); 422 return ERR_PTR(ret); 423 } 424 425 hdmi->i2c = i2c; 426 427 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 428 429 return adap; 430 } 431 432 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 433 unsigned int n) 434 { 435 /* Must be set/cleared first */ 436 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 437 438 /* nshift factor = 0 */ 439 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 440 441 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 442 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 443 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 444 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 445 446 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 447 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 448 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 449 } 450 451 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) 452 { 453 unsigned int n = (128 * freq) / 1000; 454 unsigned int mult = 1; 455 456 while (freq > 48000) { 457 mult *= 2; 458 freq /= 2; 459 } 460 461 switch (freq) { 462 case 32000: 463 if (pixel_clk == 25175000) 464 n = 4576; 465 else if (pixel_clk == 27027000) 466 n = 4096; 467 else if (pixel_clk == 74176000 || pixel_clk == 148352000) 468 n = 11648; 469 else 470 n = 4096; 471 n *= mult; 472 break; 473 474 case 44100: 475 if (pixel_clk == 25175000) 476 n = 7007; 477 else if (pixel_clk == 74176000) 478 n = 17836; 479 else if (pixel_clk == 148352000) 480 n = 8918; 481 else 482 n = 6272; 483 n *= mult; 484 break; 485 486 case 48000: 487 if (pixel_clk == 25175000) 488 n = 6864; 489 else if (pixel_clk == 27027000) 490 n = 6144; 491 else if (pixel_clk == 74176000) 492 n = 11648; 493 else if (pixel_clk == 148352000) 494 n = 5824; 495 else 496 n = 6144; 497 n *= mult; 498 break; 499 500 default: 501 break; 502 } 503 504 return n; 505 } 506 507 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, 508 unsigned long pixel_clk, unsigned int sample_rate) 509 { 510 unsigned long ftdms = pixel_clk; 511 unsigned int n, cts; 512 u64 tmp; 513 514 n = hdmi_compute_n(sample_rate, pixel_clk); 515 516 /* 517 * Compute the CTS value from the N value. Note that CTS and N 518 * can be up to 20 bits in total, so we need 64-bit math. Also 519 * note that our TDMS clock is not fully accurate; it is accurate 520 * to kHz. This can introduce an unnecessary remainder in the 521 * calculation below, so we don't try to warn about that. 522 */ 523 tmp = (u64)ftdms * n; 524 do_div(tmp, 128 * sample_rate); 525 cts = tmp; 526 527 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", 528 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, 529 n, cts); 530 531 spin_lock_irq(&hdmi->audio_lock); 532 hdmi->audio_n = n; 533 hdmi->audio_cts = cts; 534 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 535 spin_unlock_irq(&hdmi->audio_lock); 536 } 537 538 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) 539 { 540 mutex_lock(&hdmi->audio_mutex); 541 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); 542 mutex_unlock(&hdmi->audio_mutex); 543 } 544 545 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 546 { 547 mutex_lock(&hdmi->audio_mutex); 548 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 549 hdmi->sample_rate); 550 mutex_unlock(&hdmi->audio_mutex); 551 } 552 553 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 554 { 555 mutex_lock(&hdmi->audio_mutex); 556 hdmi->sample_rate = rate; 557 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 558 hdmi->sample_rate); 559 mutex_unlock(&hdmi->audio_mutex); 560 } 561 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); 562 563 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) 564 { 565 if (enable) 566 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; 567 else 568 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; 569 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 570 } 571 572 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi) 573 { 574 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 575 } 576 577 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi) 578 { 579 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 580 } 581 582 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi) 583 { 584 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 585 hdmi_enable_audio_clk(hdmi, true); 586 } 587 588 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi) 589 { 590 hdmi_enable_audio_clk(hdmi, false); 591 } 592 593 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 594 { 595 unsigned long flags; 596 597 spin_lock_irqsave(&hdmi->audio_lock, flags); 598 hdmi->audio_enable = true; 599 if (hdmi->enable_audio) 600 hdmi->enable_audio(hdmi); 601 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 602 } 603 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); 604 605 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 606 { 607 unsigned long flags; 608 609 spin_lock_irqsave(&hdmi->audio_lock, flags); 610 hdmi->audio_enable = false; 611 if (hdmi->disable_audio) 612 hdmi->disable_audio(hdmi); 613 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 614 } 615 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); 616 617 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 618 { 619 switch (bus_format) { 620 case MEDIA_BUS_FMT_RGB888_1X24: 621 case MEDIA_BUS_FMT_RGB101010_1X30: 622 case MEDIA_BUS_FMT_RGB121212_1X36: 623 case MEDIA_BUS_FMT_RGB161616_1X48: 624 return true; 625 626 default: 627 return false; 628 } 629 } 630 631 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 632 { 633 switch (bus_format) { 634 case MEDIA_BUS_FMT_YUV8_1X24: 635 case MEDIA_BUS_FMT_YUV10_1X30: 636 case MEDIA_BUS_FMT_YUV12_1X36: 637 case MEDIA_BUS_FMT_YUV16_1X48: 638 return true; 639 640 default: 641 return false; 642 } 643 } 644 645 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 646 { 647 switch (bus_format) { 648 case MEDIA_BUS_FMT_UYVY8_1X16: 649 case MEDIA_BUS_FMT_UYVY10_1X20: 650 case MEDIA_BUS_FMT_UYVY12_1X24: 651 return true; 652 653 default: 654 return false; 655 } 656 } 657 658 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 659 { 660 switch (bus_format) { 661 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 662 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 663 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 664 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 665 return true; 666 667 default: 668 return false; 669 } 670 } 671 672 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 673 { 674 switch (bus_format) { 675 case MEDIA_BUS_FMT_RGB888_1X24: 676 case MEDIA_BUS_FMT_YUV8_1X24: 677 case MEDIA_BUS_FMT_UYVY8_1X16: 678 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 679 return 8; 680 681 case MEDIA_BUS_FMT_RGB101010_1X30: 682 case MEDIA_BUS_FMT_YUV10_1X30: 683 case MEDIA_BUS_FMT_UYVY10_1X20: 684 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 685 return 10; 686 687 case MEDIA_BUS_FMT_RGB121212_1X36: 688 case MEDIA_BUS_FMT_YUV12_1X36: 689 case MEDIA_BUS_FMT_UYVY12_1X24: 690 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 691 return 12; 692 693 case MEDIA_BUS_FMT_RGB161616_1X48: 694 case MEDIA_BUS_FMT_YUV16_1X48: 695 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 696 return 16; 697 698 default: 699 return 0; 700 } 701 } 702 703 /* 704 * this submodule is responsible for the video data synchronization. 705 * for example, for RGB 4:4:4 input, the data map is defined as 706 * pin{47~40} <==> R[7:0] 707 * pin{31~24} <==> G[7:0] 708 * pin{15~8} <==> B[7:0] 709 */ 710 static void hdmi_video_sample(struct dw_hdmi *hdmi) 711 { 712 int color_format = 0; 713 u8 val; 714 715 switch (hdmi->hdmi_data.enc_in_bus_format) { 716 case MEDIA_BUS_FMT_RGB888_1X24: 717 color_format = 0x01; 718 break; 719 case MEDIA_BUS_FMT_RGB101010_1X30: 720 color_format = 0x03; 721 break; 722 case MEDIA_BUS_FMT_RGB121212_1X36: 723 color_format = 0x05; 724 break; 725 case MEDIA_BUS_FMT_RGB161616_1X48: 726 color_format = 0x07; 727 break; 728 729 case MEDIA_BUS_FMT_YUV8_1X24: 730 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 731 color_format = 0x09; 732 break; 733 case MEDIA_BUS_FMT_YUV10_1X30: 734 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 735 color_format = 0x0B; 736 break; 737 case MEDIA_BUS_FMT_YUV12_1X36: 738 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 739 color_format = 0x0D; 740 break; 741 case MEDIA_BUS_FMT_YUV16_1X48: 742 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 743 color_format = 0x0F; 744 break; 745 746 case MEDIA_BUS_FMT_UYVY8_1X16: 747 color_format = 0x16; 748 break; 749 case MEDIA_BUS_FMT_UYVY10_1X20: 750 color_format = 0x14; 751 break; 752 case MEDIA_BUS_FMT_UYVY12_1X24: 753 color_format = 0x12; 754 break; 755 756 default: 757 return; 758 } 759 760 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 761 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 762 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 763 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 764 765 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 766 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 767 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 768 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 769 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 770 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 771 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 772 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 773 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 774 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 775 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 776 } 777 778 static int is_color_space_conversion(struct dw_hdmi *hdmi) 779 { 780 return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format; 781 } 782 783 static int is_color_space_decimation(struct dw_hdmi *hdmi) 784 { 785 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 786 return 0; 787 788 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 789 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 790 return 1; 791 792 return 0; 793 } 794 795 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 796 { 797 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 798 return 0; 799 800 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 801 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 802 return 1; 803 804 return 0; 805 } 806 807 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 808 { 809 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 810 unsigned i; 811 u32 csc_scale = 1; 812 813 if (is_color_space_conversion(hdmi)) { 814 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 815 if (hdmi->hdmi_data.enc_out_encoding == 816 V4L2_YCBCR_ENC_601) 817 csc_coeff = &csc_coeff_rgb_out_eitu601; 818 else 819 csc_coeff = &csc_coeff_rgb_out_eitu709; 820 } else if (hdmi_bus_fmt_is_rgb( 821 hdmi->hdmi_data.enc_in_bus_format)) { 822 if (hdmi->hdmi_data.enc_out_encoding == 823 V4L2_YCBCR_ENC_601) 824 csc_coeff = &csc_coeff_rgb_in_eitu601; 825 else 826 csc_coeff = &csc_coeff_rgb_in_eitu709; 827 csc_scale = 0; 828 } 829 } 830 831 /* The CSC registers are sequential, alternating MSB then LSB */ 832 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 833 u16 coeff_a = (*csc_coeff)[0][i]; 834 u16 coeff_b = (*csc_coeff)[1][i]; 835 u16 coeff_c = (*csc_coeff)[2][i]; 836 837 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 838 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 839 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 840 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 841 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 842 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 843 } 844 845 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 846 HDMI_CSC_SCALE); 847 } 848 849 static void hdmi_video_csc(struct dw_hdmi *hdmi) 850 { 851 int color_depth = 0; 852 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 853 int decimation = 0; 854 855 /* YCC422 interpolation to 444 mode */ 856 if (is_color_space_interpolation(hdmi)) 857 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 858 else if (is_color_space_decimation(hdmi)) 859 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 860 861 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 862 case 8: 863 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 864 break; 865 case 10: 866 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 867 break; 868 case 12: 869 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 870 break; 871 case 16: 872 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 873 break; 874 875 default: 876 return; 877 } 878 879 /* Configure the CSC registers */ 880 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 881 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 882 HDMI_CSC_SCALE); 883 884 dw_hdmi_update_csc_coeffs(hdmi); 885 } 886 887 /* 888 * HDMI video packetizer is used to packetize the data. 889 * for example, if input is YCC422 mode or repeater is used, 890 * data should be repacked this module can be bypassed. 891 */ 892 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 893 { 894 unsigned int color_depth = 0; 895 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 896 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 897 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 898 u8 val, vp_conf; 899 900 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 901 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 902 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 903 switch (hdmi_bus_fmt_color_depth( 904 hdmi->hdmi_data.enc_out_bus_format)) { 905 case 8: 906 color_depth = 4; 907 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 908 break; 909 case 10: 910 color_depth = 5; 911 break; 912 case 12: 913 color_depth = 6; 914 break; 915 case 16: 916 color_depth = 7; 917 break; 918 default: 919 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 920 } 921 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 922 switch (hdmi_bus_fmt_color_depth( 923 hdmi->hdmi_data.enc_out_bus_format)) { 924 case 0: 925 case 8: 926 remap_size = HDMI_VP_REMAP_YCC422_16bit; 927 break; 928 case 10: 929 remap_size = HDMI_VP_REMAP_YCC422_20bit; 930 break; 931 case 12: 932 remap_size = HDMI_VP_REMAP_YCC422_24bit; 933 break; 934 935 default: 936 return; 937 } 938 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 939 } else { 940 return; 941 } 942 943 /* set the packetizer registers */ 944 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 945 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | 946 ((hdmi_data->pix_repet_factor << 947 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & 948 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); 949 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 950 951 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 952 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 953 954 /* Data from pixel repeater block */ 955 if (hdmi_data->pix_repet_factor > 1) { 956 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 957 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 958 } else { /* data from packetizer block */ 959 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 960 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 961 } 962 963 hdmi_modb(hdmi, vp_conf, 964 HDMI_VP_CONF_PR_EN_MASK | 965 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 966 967 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 968 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 969 970 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 971 972 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 973 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 974 HDMI_VP_CONF_PP_EN_ENABLE | 975 HDMI_VP_CONF_YCC422_EN_DISABLE; 976 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 977 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 978 HDMI_VP_CONF_PP_EN_DISABLE | 979 HDMI_VP_CONF_YCC422_EN_ENABLE; 980 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 981 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 982 HDMI_VP_CONF_PP_EN_DISABLE | 983 HDMI_VP_CONF_YCC422_EN_DISABLE; 984 } else { 985 return; 986 } 987 988 hdmi_modb(hdmi, vp_conf, 989 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 990 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 991 992 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 993 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 994 HDMI_VP_STUFF_PP_STUFFING_MASK | 995 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 996 997 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 998 HDMI_VP_CONF); 999 } 1000 1001 /* ----------------------------------------------------------------------------- 1002 * Synopsys PHY Handling 1003 */ 1004 1005 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 1006 unsigned char bit) 1007 { 1008 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 1009 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 1010 } 1011 1012 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 1013 { 1014 u32 val; 1015 1016 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 1017 if (msec-- == 0) 1018 return false; 1019 udelay(1000); 1020 } 1021 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 1022 1023 return true; 1024 } 1025 1026 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 1027 unsigned char addr) 1028 { 1029 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 1030 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 1031 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 1032 HDMI_PHY_I2CM_DATAO_1_ADDR); 1033 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 1034 HDMI_PHY_I2CM_DATAO_0_ADDR); 1035 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 1036 HDMI_PHY_I2CM_OPERATION_ADDR); 1037 hdmi_phy_wait_i2c_done(hdmi, 1000); 1038 } 1039 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); 1040 1041 /* Filter out invalid setups to avoid configuring SCDC and scrambling */ 1042 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi) 1043 { 1044 struct drm_display_info *display = &hdmi->connector.display_info; 1045 1046 /* Completely disable SCDC support for older controllers */ 1047 if (hdmi->version < 0x200a) 1048 return false; 1049 1050 /* Disable if no DDC bus */ 1051 if (!hdmi->ddc) 1052 return false; 1053 1054 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */ 1055 if (!display->hdmi.scdc.supported || 1056 !display->hdmi.scdc.scrambling.supported) 1057 return false; 1058 1059 /* 1060 * Disable if display only support low TMDS rates and scrambling 1061 * for low rates is not supported either 1062 */ 1063 if (!display->hdmi.scdc.scrambling.low_rates && 1064 display->max_tmds_clock <= 340000) 1065 return false; 1066 1067 return true; 1068 } 1069 1070 /* 1071 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates: 1072 * - The Source shall suspend transmission of the TMDS clock and data 1073 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it 1074 * from a 0 to a 1 or from a 1 to a 0 1075 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from 1076 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming 1077 * transmission of TMDS clock and data 1078 * 1079 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio() 1080 * helper should called right before enabling the TMDS Clock and Data in 1081 * the PHY configuration callback. 1082 */ 1083 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi) 1084 { 1085 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1086 1087 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 1088 if (dw_hdmi_support_scdc(hdmi)) { 1089 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1090 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1); 1091 else 1092 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0); 1093 } 1094 } 1095 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio); 1096 1097 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 1098 { 1099 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 1100 HDMI_PHY_CONF0_PDZ_OFFSET, 1101 HDMI_PHY_CONF0_PDZ_MASK); 1102 } 1103 1104 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 1105 { 1106 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1107 HDMI_PHY_CONF0_ENTMDS_OFFSET, 1108 HDMI_PHY_CONF0_ENTMDS_MASK); 1109 } 1110 1111 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 1112 { 1113 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1114 HDMI_PHY_CONF0_SVSRET_OFFSET, 1115 HDMI_PHY_CONF0_SVSRET_MASK); 1116 } 1117 1118 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 1119 { 1120 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1121 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 1122 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 1123 } 1124 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq); 1125 1126 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 1127 { 1128 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1129 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 1130 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 1131 } 1132 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron); 1133 1134 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 1135 { 1136 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1137 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 1138 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 1139 } 1140 1141 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 1142 { 1143 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1144 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 1145 HDMI_PHY_CONF0_SELDIPIF_MASK); 1146 } 1147 1148 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi) 1149 { 1150 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 1151 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1152 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1153 } 1154 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset); 1155 1156 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) 1157 { 1158 hdmi_phy_test_clear(hdmi, 1); 1159 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR); 1160 hdmi_phy_test_clear(hdmi, 0); 1161 } 1162 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr); 1163 1164 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 1165 { 1166 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1167 unsigned int i; 1168 u16 val; 1169 1170 if (phy->gen == 1) { 1171 dw_hdmi_phy_enable_tmds(hdmi, 0); 1172 dw_hdmi_phy_enable_powerdown(hdmi, true); 1173 return; 1174 } 1175 1176 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 1177 1178 /* 1179 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 1180 * to low power mode. 1181 */ 1182 for (i = 0; i < 5; ++i) { 1183 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 1184 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 1185 break; 1186 1187 usleep_range(1000, 2000); 1188 } 1189 1190 if (val & HDMI_PHY_TX_PHY_LOCK) 1191 dev_warn(hdmi->dev, "PHY failed to power down\n"); 1192 else 1193 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); 1194 1195 dw_hdmi_phy_gen2_pddq(hdmi, 1); 1196 } 1197 1198 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 1199 { 1200 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1201 unsigned int i; 1202 u8 val; 1203 1204 if (phy->gen == 1) { 1205 dw_hdmi_phy_enable_powerdown(hdmi, false); 1206 1207 /* Toggle TMDS enable. */ 1208 dw_hdmi_phy_enable_tmds(hdmi, 0); 1209 dw_hdmi_phy_enable_tmds(hdmi, 1); 1210 return 0; 1211 } 1212 1213 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 1214 dw_hdmi_phy_gen2_pddq(hdmi, 0); 1215 1216 /* Wait for PHY PLL lock */ 1217 for (i = 0; i < 5; ++i) { 1218 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 1219 if (val) 1220 break; 1221 1222 usleep_range(1000, 2000); 1223 } 1224 1225 if (!val) { 1226 dev_err(hdmi->dev, "PHY PLL failed to lock\n"); 1227 return -ETIMEDOUT; 1228 } 1229 1230 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); 1231 return 0; 1232 } 1233 1234 /* 1235 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 1236 * information the DWC MHL PHY has the same register layout and is thus also 1237 * supported by this function. 1238 */ 1239 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 1240 const struct dw_hdmi_plat_data *pdata, 1241 unsigned long mpixelclock) 1242 { 1243 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 1244 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 1245 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 1246 1247 /* TOFIX Will need 420 specific PHY configuration tables */ 1248 1249 /* PLL/MPLL Cfg - always match on final entry */ 1250 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 1251 if (mpixelclock <= mpll_config->mpixelclock) 1252 break; 1253 1254 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 1255 if (mpixelclock <= curr_ctrl->mpixelclock) 1256 break; 1257 1258 for (; phy_config->mpixelclock != ~0UL; phy_config++) 1259 if (mpixelclock <= phy_config->mpixelclock) 1260 break; 1261 1262 if (mpll_config->mpixelclock == ~0UL || 1263 curr_ctrl->mpixelclock == ~0UL || 1264 phy_config->mpixelclock == ~0UL) 1265 return -EINVAL; 1266 1267 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 1268 HDMI_3D_TX_PHY_CPCE_CTRL); 1269 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 1270 HDMI_3D_TX_PHY_GMPCTRL); 1271 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 1272 HDMI_3D_TX_PHY_CURRCTRL); 1273 1274 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 1275 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 1276 HDMI_3D_TX_PHY_MSM_CTRL); 1277 1278 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 1279 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 1280 HDMI_3D_TX_PHY_CKSYMTXCTRL); 1281 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 1282 HDMI_3D_TX_PHY_VLEVCTRL); 1283 1284 /* Override and disable clock termination. */ 1285 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 1286 HDMI_3D_TX_PHY_CKCALCTRL); 1287 1288 return 0; 1289 } 1290 1291 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 1292 { 1293 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1294 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 1295 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 1296 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1297 int ret; 1298 1299 dw_hdmi_phy_power_off(hdmi); 1300 1301 dw_hdmi_set_high_tmds_clock_ratio(hdmi); 1302 1303 /* Leave low power consumption mode by asserting SVSRET. */ 1304 if (phy->has_svsret) 1305 dw_hdmi_phy_enable_svsret(hdmi, 1); 1306 1307 dw_hdmi_phy_reset(hdmi); 1308 1309 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 1310 1311 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); 1312 1313 /* Write to the PHY as configured by the platform */ 1314 if (pdata->configure_phy) 1315 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 1316 else 1317 ret = phy->configure(hdmi, pdata, mpixelclock); 1318 if (ret) { 1319 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", 1320 mpixelclock); 1321 return ret; 1322 } 1323 1324 /* Wait for resuming transmission of TMDS clock and data */ 1325 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1326 msleep(100); 1327 1328 return dw_hdmi_phy_power_on(hdmi); 1329 } 1330 1331 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 1332 struct drm_display_mode *mode) 1333 { 1334 int i, ret; 1335 1336 /* HDMI Phy spec says to do the phy initialization sequence twice */ 1337 for (i = 0; i < 2; i++) { 1338 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 1339 dw_hdmi_phy_sel_interface_control(hdmi, 0); 1340 1341 ret = hdmi_phy_configure(hdmi); 1342 if (ret) 1343 return ret; 1344 } 1345 1346 return 0; 1347 } 1348 1349 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 1350 { 1351 dw_hdmi_phy_power_off(hdmi); 1352 } 1353 1354 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 1355 void *data) 1356 { 1357 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 1358 connector_status_connected : connector_status_disconnected; 1359 } 1360 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); 1361 1362 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 1363 bool force, bool disabled, bool rxsense) 1364 { 1365 u8 old_mask = hdmi->phy_mask; 1366 1367 if (force || disabled || !rxsense) 1368 hdmi->phy_mask |= HDMI_PHY_RX_SENSE; 1369 else 1370 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; 1371 1372 if (old_mask != hdmi->phy_mask) 1373 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1374 } 1375 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd); 1376 1377 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) 1378 { 1379 /* 1380 * Configure the PHY RX SENSE and HPD interrupts polarities and clear 1381 * any pending interrupt. 1382 */ 1383 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); 1384 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1385 HDMI_IH_PHY_STAT0); 1386 1387 /* Enable cable hot plug irq. */ 1388 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1389 1390 /* Clear and unmute interrupts. */ 1391 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1392 HDMI_IH_PHY_STAT0); 1393 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 1394 HDMI_IH_MUTE_PHY_STAT0); 1395 } 1396 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd); 1397 1398 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 1399 .init = dw_hdmi_phy_init, 1400 .disable = dw_hdmi_phy_disable, 1401 .read_hpd = dw_hdmi_phy_read_hpd, 1402 .update_hpd = dw_hdmi_phy_update_hpd, 1403 .setup_hpd = dw_hdmi_phy_setup_hpd, 1404 }; 1405 1406 /* ----------------------------------------------------------------------------- 1407 * HDMI TX Setup 1408 */ 1409 1410 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) 1411 { 1412 u8 de; 1413 1414 if (hdmi->hdmi_data.video_mode.mdataenablepolarity) 1415 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1416 else 1417 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; 1418 1419 /* disable rx detect */ 1420 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, 1421 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 1422 1423 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); 1424 1425 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, 1426 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); 1427 } 1428 1429 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1430 { 1431 struct hdmi_avi_infoframe frame; 1432 u8 val; 1433 1434 /* Initialise info frame from DRM mode */ 1435 drm_hdmi_avi_infoframe_from_display_mode(&frame, 1436 &hdmi->connector, mode); 1437 1438 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1439 frame.colorspace = HDMI_COLORSPACE_YUV444; 1440 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1441 frame.colorspace = HDMI_COLORSPACE_YUV422; 1442 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1443 frame.colorspace = HDMI_COLORSPACE_YUV420; 1444 else 1445 frame.colorspace = HDMI_COLORSPACE_RGB; 1446 1447 /* Set up colorimetry */ 1448 switch (hdmi->hdmi_data.enc_out_encoding) { 1449 case V4L2_YCBCR_ENC_601: 1450 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1451 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1452 else 1453 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1454 frame.extended_colorimetry = 1455 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1456 break; 1457 case V4L2_YCBCR_ENC_709: 1458 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1459 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1460 else 1461 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1462 frame.extended_colorimetry = 1463 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1464 break; 1465 default: /* Carries no data */ 1466 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1467 frame.extended_colorimetry = 1468 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1469 break; 1470 } 1471 1472 frame.scan_mode = HDMI_SCAN_MODE_NONE; 1473 1474 /* 1475 * The Designware IP uses a different byte format from standard 1476 * AVI info frames, though generally the bits are in the correct 1477 * bytes. 1478 */ 1479 1480 /* 1481 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, 1482 * scan info in bits 4,5 rather than 0,1 and active aspect present in 1483 * bit 6 rather than 4. 1484 */ 1485 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); 1486 if (frame.active_aspect & 15) 1487 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1488 if (frame.top_bar || frame.bottom_bar) 1489 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1490 if (frame.left_bar || frame.right_bar) 1491 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1492 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1493 1494 /* AVI data byte 2 differences: none */ 1495 val = ((frame.colorimetry & 0x3) << 6) | 1496 ((frame.picture_aspect & 0x3) << 4) | 1497 (frame.active_aspect & 0xf); 1498 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1499 1500 /* AVI data byte 3 differences: none */ 1501 val = ((frame.extended_colorimetry & 0x7) << 4) | 1502 ((frame.quantization_range & 0x3) << 2) | 1503 (frame.nups & 0x3); 1504 if (frame.itc) 1505 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1506 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1507 1508 /* AVI data byte 4 differences: none */ 1509 val = frame.video_code & 0x7f; 1510 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1511 1512 /* AVI Data Byte 5- set up input and output pixel repetition */ 1513 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1514 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1515 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1516 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1517 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1518 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1519 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1520 1521 /* 1522 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1523 * ycc range in bits 2,3 rather than 6,7 1524 */ 1525 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1526 (frame.content_type & 0x3); 1527 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1528 1529 /* AVI Data Bytes 6-13 */ 1530 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1531 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1532 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1533 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1534 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1535 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1536 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1537 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1538 } 1539 1540 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1541 struct drm_display_mode *mode) 1542 { 1543 struct hdmi_vendor_infoframe frame; 1544 u8 buffer[10]; 1545 ssize_t err; 1546 1547 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, 1548 &hdmi->connector, 1549 mode); 1550 if (err < 0) 1551 /* 1552 * Going into that statement does not means vendor infoframe 1553 * fails. It just informed us that vendor infoframe is not 1554 * needed for the selected mode. Only 4k or stereoscopic 3D 1555 * mode requires vendor infoframe. So just simply return. 1556 */ 1557 return; 1558 1559 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1560 if (err < 0) { 1561 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1562 err); 1563 return; 1564 } 1565 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1566 HDMI_FC_DATAUTO0_VSD_MASK); 1567 1568 /* Set the length of HDMI vendor specific InfoFrame payload */ 1569 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1570 1571 /* Set 24bit IEEE Registration Identifier */ 1572 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1573 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1574 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1575 1576 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1577 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1578 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1579 1580 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1581 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1582 1583 /* Packet frame interpolation */ 1584 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1585 1586 /* Auto packets per frame and line spacing */ 1587 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1588 1589 /* Configures the Frame Composer On RDRB mode */ 1590 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1591 HDMI_FC_DATAUTO0_VSD_MASK); 1592 } 1593 1594 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1595 const struct drm_display_mode *mode) 1596 { 1597 u8 inv_val, bytes; 1598 struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi; 1599 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1600 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1601 unsigned int vdisplay, hdisplay; 1602 1603 vmode->mtmdsclock = vmode->mpixelclock = mode->clock * 1000; 1604 1605 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); 1606 1607 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1608 vmode->mtmdsclock /= 2; 1609 1610 /* Set up HDMI_FC_INVIDCONF */ 1611 inv_val = (hdmi->hdmi_data.hdcp_enable || 1612 (dw_hdmi_support_scdc(hdmi) && 1613 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 1614 hdmi_info->scdc.scrambling.low_rates)) ? 1615 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1616 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1617 1618 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1619 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1620 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1621 1622 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1623 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1624 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1625 1626 inv_val |= (vmode->mdataenablepolarity ? 1627 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1628 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1629 1630 if (hdmi->vic == 39) 1631 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1632 else 1633 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1634 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1635 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1636 1637 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1638 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1639 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1640 1641 inv_val |= hdmi->sink_is_hdmi ? 1642 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1643 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1644 1645 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1646 1647 hdisplay = mode->hdisplay; 1648 hblank = mode->htotal - mode->hdisplay; 1649 h_de_hs = mode->hsync_start - mode->hdisplay; 1650 hsync_len = mode->hsync_end - mode->hsync_start; 1651 1652 /* 1653 * When we're setting a YCbCr420 mode, we need 1654 * to adjust the horizontal timing to suit. 1655 */ 1656 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1657 hdisplay /= 2; 1658 hblank /= 2; 1659 h_de_hs /= 2; 1660 hsync_len /= 2; 1661 } 1662 1663 vdisplay = mode->vdisplay; 1664 vblank = mode->vtotal - mode->vdisplay; 1665 v_de_vs = mode->vsync_start - mode->vdisplay; 1666 vsync_len = mode->vsync_end - mode->vsync_start; 1667 1668 /* 1669 * When we're setting an interlaced mode, we need 1670 * to adjust the vertical timing to suit. 1671 */ 1672 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1673 vdisplay /= 2; 1674 vblank /= 2; 1675 v_de_vs /= 2; 1676 vsync_len /= 2; 1677 } 1678 1679 /* Scrambling Control */ 1680 if (dw_hdmi_support_scdc(hdmi)) { 1681 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 1682 hdmi_info->scdc.scrambling.low_rates) { 1683 /* 1684 * HDMI2.0 Specifies the following procedure: 1685 * After the Source Device has determined that 1686 * SCDC_Present is set (=1), the Source Device should 1687 * write the accurate Version of the Source Device 1688 * to the Source Version field in the SCDCS. 1689 * Source Devices compliant shall set the 1690 * Source Version = 1. 1691 */ 1692 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, 1693 &bytes); 1694 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, 1695 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); 1696 1697 /* Enabled Scrambling in the Sink */ 1698 drm_scdc_set_scrambling(hdmi->ddc, 1); 1699 1700 /* 1701 * To activate the scrambler feature, you must ensure 1702 * that the quasi-static configuration bit 1703 * fc_invidconf.HDCP_keepout is set at configuration 1704 * time, before the required mc_swrstzreq.tmdsswrst_req 1705 * reset request is issued. 1706 */ 1707 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 1708 HDMI_MC_SWRSTZ); 1709 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 1710 } else { 1711 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 1712 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 1713 HDMI_MC_SWRSTZ); 1714 drm_scdc_set_scrambling(hdmi->ddc, 0); 1715 } 1716 } 1717 1718 /* Set up horizontal active pixel width */ 1719 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 1720 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 1721 1722 /* Set up vertical active lines */ 1723 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1724 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1725 1726 /* Set up horizontal blanking pixel region width */ 1727 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 1728 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 1729 1730 /* Set up vertical blanking pixel region width */ 1731 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 1732 1733 /* Set up HSYNC active edge delay width (in pixel clks) */ 1734 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 1735 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 1736 1737 /* Set up VSYNC active edge delay (in lines) */ 1738 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 1739 1740 /* Set up HSYNC active pulse width (in pixel clks) */ 1741 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 1742 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 1743 1744 /* Set up VSYNC active edge delay (in lines) */ 1745 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 1746 } 1747 1748 /* HDMI Initialization Step B.4 */ 1749 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 1750 { 1751 /* control period minimum duration */ 1752 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 1753 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 1754 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 1755 1756 /* Set to fill TMDS data channels */ 1757 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 1758 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 1759 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 1760 1761 /* Enable pixel clock and tmds data path */ 1762 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE | 1763 HDMI_MC_CLKDIS_CSCCLK_DISABLE | 1764 HDMI_MC_CLKDIS_AUDCLK_DISABLE | 1765 HDMI_MC_CLKDIS_PREPCLK_DISABLE | 1766 HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1767 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 1768 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1769 1770 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1771 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1772 1773 /* Enable csc path */ 1774 if (is_color_space_conversion(hdmi)) { 1775 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 1776 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1777 } 1778 1779 /* Enable color space conversion if needed */ 1780 if (is_color_space_conversion(hdmi)) 1781 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 1782 HDMI_MC_FLOWCTRL); 1783 else 1784 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 1785 HDMI_MC_FLOWCTRL); 1786 } 1787 1788 /* Workaround to clear the overflow condition */ 1789 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 1790 { 1791 unsigned int count; 1792 unsigned int i; 1793 u8 val; 1794 1795 /* 1796 * Under some circumstances the Frame Composer arithmetic unit can miss 1797 * an FC register write due to being busy processing the previous one. 1798 * The issue can be worked around by issuing a TMDS software reset and 1799 * then write one of the FC registers several times. 1800 * 1801 * The number of iterations matters and depends on the HDMI TX revision 1802 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL 1803 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified 1804 * as needing the workaround, with 4 iterations for v1.30a and 1 1805 * iteration for others. 1806 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing 1807 * the workaround with a single iteration. 1808 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have 1809 * been identified as needing the workaround with a single iteration. 1810 */ 1811 1812 switch (hdmi->version) { 1813 case 0x130a: 1814 count = 4; 1815 break; 1816 case 0x131a: 1817 case 0x132a: 1818 case 0x200a: 1819 case 0x201a: 1820 case 0x211a: 1821 case 0x212a: 1822 count = 1; 1823 break; 1824 default: 1825 return; 1826 } 1827 1828 /* TMDS software reset */ 1829 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 1830 1831 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 1832 for (i = 0; i < count; i++) 1833 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 1834 } 1835 1836 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 1837 { 1838 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 1839 HDMI_IH_MUTE_FC_STAT2); 1840 } 1841 1842 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1843 { 1844 int ret; 1845 1846 hdmi_disable_overflow_interrupts(hdmi); 1847 1848 hdmi->vic = drm_match_cea_mode(mode); 1849 1850 if (!hdmi->vic) { 1851 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); 1852 } else { 1853 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); 1854 } 1855 1856 if ((hdmi->vic == 6) || (hdmi->vic == 7) || 1857 (hdmi->vic == 21) || (hdmi->vic == 22) || 1858 (hdmi->vic == 2) || (hdmi->vic == 3) || 1859 (hdmi->vic == 17) || (hdmi->vic == 18)) 1860 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 1861 else 1862 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 1863 1864 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 1865 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 1866 1867 /* TOFIX: Get input format from plat data or fallback to RGB888 */ 1868 if (hdmi->plat_data->input_bus_format) 1869 hdmi->hdmi_data.enc_in_bus_format = 1870 hdmi->plat_data->input_bus_format; 1871 else 1872 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1873 1874 /* TOFIX: Get input encoding from plat data or fallback to none */ 1875 if (hdmi->plat_data->input_bus_encoding) 1876 hdmi->hdmi_data.enc_in_encoding = 1877 hdmi->plat_data->input_bus_encoding; 1878 else 1879 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 1880 1881 /* TOFIX: Default to RGB888 output format */ 1882 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1883 1884 hdmi->hdmi_data.pix_repet_factor = 0; 1885 hdmi->hdmi_data.hdcp_enable = 0; 1886 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 1887 1888 /* HDMI Initialization Step B.1 */ 1889 hdmi_av_composer(hdmi, mode); 1890 1891 /* HDMI Initializateion Step B.2 */ 1892 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode); 1893 if (ret) 1894 return ret; 1895 hdmi->phy.enabled = true; 1896 1897 /* HDMI Initialization Step B.3 */ 1898 dw_hdmi_enable_video_path(hdmi); 1899 1900 if (hdmi->sink_has_audio) { 1901 dev_dbg(hdmi->dev, "sink has audio support\n"); 1902 1903 /* HDMI Initialization Step E - Configure audio */ 1904 hdmi_clk_regenerator_update_pixel_clock(hdmi); 1905 hdmi_enable_audio_clk(hdmi, true); 1906 } 1907 1908 /* not for DVI mode */ 1909 if (hdmi->sink_is_hdmi) { 1910 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); 1911 1912 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 1913 hdmi_config_AVI(hdmi, mode); 1914 hdmi_config_vendor_specific_infoframe(hdmi, mode); 1915 } else { 1916 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); 1917 } 1918 1919 hdmi_video_packetize(hdmi); 1920 hdmi_video_csc(hdmi); 1921 hdmi_video_sample(hdmi); 1922 hdmi_tx_hdcp_config(hdmi); 1923 1924 dw_hdmi_clear_overflow(hdmi); 1925 1926 return 0; 1927 } 1928 1929 static void dw_hdmi_setup_i2c(struct dw_hdmi *hdmi) 1930 { 1931 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, 1932 HDMI_PHY_I2CM_INT_ADDR); 1933 1934 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | 1935 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, 1936 HDMI_PHY_I2CM_CTLINT_ADDR); 1937 } 1938 1939 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) 1940 { 1941 u8 ih_mute; 1942 1943 /* 1944 * Boot up defaults are: 1945 * HDMI_IH_MUTE = 0x03 (disabled) 1946 * HDMI_IH_MUTE_* = 0x00 (enabled) 1947 * 1948 * Disable top level interrupt bits in HDMI block 1949 */ 1950 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | 1951 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 1952 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; 1953 1954 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 1955 1956 /* by default mask all interrupts */ 1957 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); 1958 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 1959 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 1960 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 1961 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); 1962 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); 1963 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); 1964 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); 1965 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); 1966 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); 1967 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); 1968 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); 1969 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); 1970 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); 1971 1972 /* Disable interrupts in the IH_MUTE_* registers */ 1973 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 1974 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 1975 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 1976 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 1977 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); 1978 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 1979 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 1980 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 1981 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 1982 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 1983 1984 /* Enable top level interrupt bits in HDMI block */ 1985 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 1986 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); 1987 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 1988 } 1989 1990 static void dw_hdmi_poweron(struct dw_hdmi *hdmi) 1991 { 1992 hdmi->bridge_is_on = true; 1993 dw_hdmi_setup(hdmi, &hdmi->previous_mode); 1994 } 1995 1996 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) 1997 { 1998 if (hdmi->phy.enabled) { 1999 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 2000 hdmi->phy.enabled = false; 2001 } 2002 2003 hdmi->bridge_is_on = false; 2004 } 2005 2006 static void dw_hdmi_update_power(struct dw_hdmi *hdmi) 2007 { 2008 int force = hdmi->force; 2009 2010 if (hdmi->disabled) { 2011 force = DRM_FORCE_OFF; 2012 } else if (force == DRM_FORCE_UNSPECIFIED) { 2013 if (hdmi->rxsense) 2014 force = DRM_FORCE_ON; 2015 else 2016 force = DRM_FORCE_OFF; 2017 } 2018 2019 if (force == DRM_FORCE_OFF) { 2020 if (hdmi->bridge_is_on) 2021 dw_hdmi_poweroff(hdmi); 2022 } else { 2023 if (!hdmi->bridge_is_on) 2024 dw_hdmi_poweron(hdmi); 2025 } 2026 } 2027 2028 /* 2029 * Adjust the detection of RXSENSE according to whether we have a forced 2030 * connection mode enabled, or whether we have been disabled. There is 2031 * no point processing RXSENSE interrupts if we have a forced connection 2032 * state, or DRM has us disabled. 2033 * 2034 * We also disable rxsense interrupts when we think we're disconnected 2035 * to avoid floating TDMS signals giving false rxsense interrupts. 2036 * 2037 * Note: we still need to listen for HPD interrupts even when DRM has us 2038 * disabled so that we can detect a connect event. 2039 */ 2040 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) 2041 { 2042 if (hdmi->phy.ops->update_hpd) 2043 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, 2044 hdmi->force, hdmi->disabled, 2045 hdmi->rxsense); 2046 } 2047 2048 static enum drm_connector_status 2049 dw_hdmi_connector_detect(struct drm_connector *connector, bool force) 2050 { 2051 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2052 connector); 2053 2054 mutex_lock(&hdmi->mutex); 2055 hdmi->force = DRM_FORCE_UNSPECIFIED; 2056 dw_hdmi_update_power(hdmi); 2057 dw_hdmi_update_phy_mask(hdmi); 2058 mutex_unlock(&hdmi->mutex); 2059 2060 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 2061 } 2062 2063 static int dw_hdmi_connector_get_modes(struct drm_connector *connector) 2064 { 2065 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2066 connector); 2067 struct edid *edid; 2068 int ret = 0; 2069 2070 if (!hdmi->ddc) 2071 return 0; 2072 2073 edid = drm_get_edid(connector, hdmi->ddc); 2074 if (edid) { 2075 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", 2076 edid->width_cm, edid->height_cm); 2077 2078 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); 2079 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2080 drm_connector_update_edid_property(connector, edid); 2081 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); 2082 ret = drm_add_edid_modes(connector, edid); 2083 kfree(edid); 2084 } else { 2085 dev_dbg(hdmi->dev, "failed to get edid\n"); 2086 } 2087 2088 return ret; 2089 } 2090 2091 static void dw_hdmi_connector_force(struct drm_connector *connector) 2092 { 2093 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2094 connector); 2095 2096 mutex_lock(&hdmi->mutex); 2097 hdmi->force = connector->force; 2098 dw_hdmi_update_power(hdmi); 2099 dw_hdmi_update_phy_mask(hdmi); 2100 mutex_unlock(&hdmi->mutex); 2101 } 2102 2103 static const struct drm_connector_funcs dw_hdmi_connector_funcs = { 2104 .fill_modes = drm_helper_probe_single_connector_modes, 2105 .detect = dw_hdmi_connector_detect, 2106 .destroy = drm_connector_cleanup, 2107 .force = dw_hdmi_connector_force, 2108 .reset = drm_atomic_helper_connector_reset, 2109 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2110 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2111 }; 2112 2113 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { 2114 .get_modes = dw_hdmi_connector_get_modes, 2115 }; 2116 2117 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge) 2118 { 2119 struct dw_hdmi *hdmi = bridge->driver_private; 2120 struct drm_encoder *encoder = bridge->encoder; 2121 struct drm_connector *connector = &hdmi->connector; 2122 2123 connector->interlace_allowed = 1; 2124 connector->polled = DRM_CONNECTOR_POLL_HPD; 2125 2126 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); 2127 2128 drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs, 2129 DRM_MODE_CONNECTOR_HDMIA); 2130 2131 drm_connector_attach_encoder(connector, encoder); 2132 2133 return 0; 2134 } 2135 2136 static enum drm_mode_status 2137 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 2138 const struct drm_display_mode *mode) 2139 { 2140 struct dw_hdmi *hdmi = bridge->driver_private; 2141 struct drm_connector *connector = &hdmi->connector; 2142 enum drm_mode_status mode_status = MODE_OK; 2143 2144 /* We don't support double-clocked modes */ 2145 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2146 return MODE_BAD; 2147 2148 if (hdmi->plat_data->mode_valid) 2149 mode_status = hdmi->plat_data->mode_valid(connector, mode); 2150 2151 return mode_status; 2152 } 2153 2154 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, 2155 const struct drm_display_mode *orig_mode, 2156 const struct drm_display_mode *mode) 2157 { 2158 struct dw_hdmi *hdmi = bridge->driver_private; 2159 2160 mutex_lock(&hdmi->mutex); 2161 2162 /* Store the display mode for plugin/DKMS poweron events */ 2163 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 2164 2165 mutex_unlock(&hdmi->mutex); 2166 } 2167 2168 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge) 2169 { 2170 struct dw_hdmi *hdmi = bridge->driver_private; 2171 2172 mutex_lock(&hdmi->mutex); 2173 hdmi->disabled = true; 2174 dw_hdmi_update_power(hdmi); 2175 dw_hdmi_update_phy_mask(hdmi); 2176 mutex_unlock(&hdmi->mutex); 2177 } 2178 2179 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge) 2180 { 2181 struct dw_hdmi *hdmi = bridge->driver_private; 2182 2183 mutex_lock(&hdmi->mutex); 2184 hdmi->disabled = false; 2185 dw_hdmi_update_power(hdmi); 2186 dw_hdmi_update_phy_mask(hdmi); 2187 mutex_unlock(&hdmi->mutex); 2188 } 2189 2190 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { 2191 .attach = dw_hdmi_bridge_attach, 2192 .enable = dw_hdmi_bridge_enable, 2193 .disable = dw_hdmi_bridge_disable, 2194 .mode_set = dw_hdmi_bridge_mode_set, 2195 .mode_valid = dw_hdmi_bridge_mode_valid, 2196 }; 2197 2198 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) 2199 { 2200 struct dw_hdmi_i2c *i2c = hdmi->i2c; 2201 unsigned int stat; 2202 2203 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 2204 if (!stat) 2205 return IRQ_NONE; 2206 2207 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0); 2208 2209 i2c->stat = stat; 2210 2211 complete(&i2c->cmp); 2212 2213 return IRQ_HANDLED; 2214 } 2215 2216 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) 2217 { 2218 struct dw_hdmi *hdmi = dev_id; 2219 u8 intr_stat; 2220 irqreturn_t ret = IRQ_NONE; 2221 2222 if (hdmi->i2c) 2223 ret = dw_hdmi_i2c_irq(hdmi); 2224 2225 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2226 if (intr_stat) { 2227 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2228 return IRQ_WAKE_THREAD; 2229 } 2230 2231 return ret; 2232 } 2233 2234 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) 2235 { 2236 mutex_lock(&hdmi->mutex); 2237 2238 if (!hdmi->force) { 2239 /* 2240 * If the RX sense status indicates we're disconnected, 2241 * clear the software rxsense status. 2242 */ 2243 if (!rx_sense) 2244 hdmi->rxsense = false; 2245 2246 /* 2247 * Only set the software rxsense status when both 2248 * rxsense and hpd indicates we're connected. 2249 * This avoids what seems to be bad behaviour in 2250 * at least iMX6S versions of the phy. 2251 */ 2252 if (hpd) 2253 hdmi->rxsense = true; 2254 2255 dw_hdmi_update_power(hdmi); 2256 dw_hdmi_update_phy_mask(hdmi); 2257 } 2258 mutex_unlock(&hdmi->mutex); 2259 } 2260 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); 2261 2262 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) 2263 { 2264 struct dw_hdmi *hdmi = dev_id; 2265 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; 2266 2267 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2268 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); 2269 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); 2270 2271 phy_pol_mask = 0; 2272 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) 2273 phy_pol_mask |= HDMI_PHY_HPD; 2274 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) 2275 phy_pol_mask |= HDMI_PHY_RX_SENSE0; 2276 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) 2277 phy_pol_mask |= HDMI_PHY_RX_SENSE1; 2278 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) 2279 phy_pol_mask |= HDMI_PHY_RX_SENSE2; 2280 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) 2281 phy_pol_mask |= HDMI_PHY_RX_SENSE3; 2282 2283 if (phy_pol_mask) 2284 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); 2285 2286 /* 2287 * RX sense tells us whether the TDMS transmitters are detecting 2288 * load - in other words, there's something listening on the 2289 * other end of the link. Use this to decide whether we should 2290 * power on the phy as HPD may be toggled by the sink to merely 2291 * ask the source to re-read the EDID. 2292 */ 2293 if (intr_stat & 2294 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { 2295 dw_hdmi_setup_rx_sense(hdmi, 2296 phy_stat & HDMI_PHY_HPD, 2297 phy_stat & HDMI_PHY_RX_SENSE); 2298 2299 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) 2300 cec_notifier_set_phys_addr(hdmi->cec_notifier, 2301 CEC_PHYS_ADDR_INVALID); 2302 } 2303 2304 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { 2305 dev_dbg(hdmi->dev, "EVENT=%s\n", 2306 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout"); 2307 if (hdmi->bridge.dev) 2308 drm_helper_hpd_irq_event(hdmi->bridge.dev); 2309 } 2310 2311 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); 2312 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 2313 HDMI_IH_MUTE_PHY_STAT0); 2314 2315 return IRQ_HANDLED; 2316 } 2317 2318 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 2319 { 2320 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 2321 .name = "DWC HDMI TX PHY", 2322 .gen = 1, 2323 }, { 2324 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 2325 .name = "DWC MHL PHY + HEAC PHY", 2326 .gen = 2, 2327 .has_svsret = true, 2328 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2329 }, { 2330 .type = DW_HDMI_PHY_DWC_MHL_PHY, 2331 .name = "DWC MHL PHY", 2332 .gen = 2, 2333 .has_svsret = true, 2334 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2335 }, { 2336 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 2337 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 2338 .gen = 2, 2339 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2340 }, { 2341 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 2342 .name = "DWC HDMI 3D TX PHY", 2343 .gen = 2, 2344 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2345 }, { 2346 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 2347 .name = "DWC HDMI 2.0 TX PHY", 2348 .gen = 2, 2349 .has_svsret = true, 2350 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2351 }, { 2352 .type = DW_HDMI_PHY_VENDOR_PHY, 2353 .name = "Vendor PHY", 2354 } 2355 }; 2356 2357 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 2358 { 2359 unsigned int i; 2360 u8 phy_type; 2361 2362 phy_type = hdmi->plat_data->phy_force_vendor ? 2363 DW_HDMI_PHY_VENDOR_PHY : 2364 hdmi_readb(hdmi, HDMI_CONFIG2_ID); 2365 2366 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { 2367 /* Vendor PHYs require support from the glue layer. */ 2368 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 2369 dev_err(hdmi->dev, 2370 "Vendor HDMI PHY not supported by glue layer\n"); 2371 return -ENODEV; 2372 } 2373 2374 hdmi->phy.ops = hdmi->plat_data->phy_ops; 2375 hdmi->phy.data = hdmi->plat_data->phy_data; 2376 hdmi->phy.name = hdmi->plat_data->phy_name; 2377 return 0; 2378 } 2379 2380 /* Synopsys PHYs are handled internally. */ 2381 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 2382 if (dw_hdmi_phys[i].type == phy_type) { 2383 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 2384 hdmi->phy.name = dw_hdmi_phys[i].name; 2385 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 2386 2387 if (!dw_hdmi_phys[i].configure && 2388 !hdmi->plat_data->configure_phy) { 2389 dev_err(hdmi->dev, "%s requires platform support\n", 2390 hdmi->phy.name); 2391 return -ENODEV; 2392 } 2393 2394 return 0; 2395 } 2396 } 2397 2398 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); 2399 return -ENODEV; 2400 } 2401 2402 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi) 2403 { 2404 mutex_lock(&hdmi->mutex); 2405 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE; 2406 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2407 mutex_unlock(&hdmi->mutex); 2408 } 2409 2410 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi) 2411 { 2412 mutex_lock(&hdmi->mutex); 2413 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE; 2414 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2415 mutex_unlock(&hdmi->mutex); 2416 } 2417 2418 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = { 2419 .write = hdmi_writeb, 2420 .read = hdmi_readb, 2421 .enable = dw_hdmi_cec_enable, 2422 .disable = dw_hdmi_cec_disable, 2423 }; 2424 2425 static const struct regmap_config hdmi_regmap_8bit_config = { 2426 .reg_bits = 32, 2427 .val_bits = 8, 2428 .reg_stride = 1, 2429 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, 2430 }; 2431 2432 static const struct regmap_config hdmi_regmap_32bit_config = { 2433 .reg_bits = 32, 2434 .val_bits = 32, 2435 .reg_stride = 4, 2436 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, 2437 }; 2438 2439 static struct dw_hdmi * 2440 __dw_hdmi_probe(struct platform_device *pdev, 2441 const struct dw_hdmi_plat_data *plat_data) 2442 { 2443 struct device *dev = &pdev->dev; 2444 struct device_node *np = dev->of_node; 2445 struct platform_device_info pdevinfo; 2446 struct device_node *ddc_node; 2447 struct dw_hdmi_cec_data cec; 2448 struct dw_hdmi *hdmi; 2449 struct resource *iores = NULL; 2450 int irq; 2451 int ret; 2452 u32 val = 1; 2453 u8 prod_id0; 2454 u8 prod_id1; 2455 u8 config0; 2456 u8 config3; 2457 2458 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 2459 if (!hdmi) 2460 return ERR_PTR(-ENOMEM); 2461 2462 hdmi->plat_data = plat_data; 2463 hdmi->dev = dev; 2464 hdmi->sample_rate = 48000; 2465 hdmi->disabled = true; 2466 hdmi->rxsense = true; 2467 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); 2468 hdmi->mc_clkdis = 0x7f; 2469 2470 mutex_init(&hdmi->mutex); 2471 mutex_init(&hdmi->audio_mutex); 2472 spin_lock_init(&hdmi->audio_lock); 2473 2474 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 2475 if (ddc_node) { 2476 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); 2477 of_node_put(ddc_node); 2478 if (!hdmi->ddc) { 2479 dev_dbg(hdmi->dev, "failed to read ddc node\n"); 2480 return ERR_PTR(-EPROBE_DEFER); 2481 } 2482 2483 } else { 2484 dev_dbg(hdmi->dev, "no ddc property found\n"); 2485 } 2486 2487 if (!plat_data->regm) { 2488 const struct regmap_config *reg_config; 2489 2490 of_property_read_u32(np, "reg-io-width", &val); 2491 switch (val) { 2492 case 4: 2493 reg_config = &hdmi_regmap_32bit_config; 2494 hdmi->reg_shift = 2; 2495 break; 2496 case 1: 2497 reg_config = &hdmi_regmap_8bit_config; 2498 break; 2499 default: 2500 dev_err(dev, "reg-io-width must be 1 or 4\n"); 2501 return ERR_PTR(-EINVAL); 2502 } 2503 2504 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2505 hdmi->regs = devm_ioremap_resource(dev, iores); 2506 if (IS_ERR(hdmi->regs)) { 2507 ret = PTR_ERR(hdmi->regs); 2508 goto err_res; 2509 } 2510 2511 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); 2512 if (IS_ERR(hdmi->regm)) { 2513 dev_err(dev, "Failed to configure regmap\n"); 2514 ret = PTR_ERR(hdmi->regm); 2515 goto err_res; 2516 } 2517 } else { 2518 hdmi->regm = plat_data->regm; 2519 } 2520 2521 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); 2522 if (IS_ERR(hdmi->isfr_clk)) { 2523 ret = PTR_ERR(hdmi->isfr_clk); 2524 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); 2525 goto err_res; 2526 } 2527 2528 ret = clk_prepare_enable(hdmi->isfr_clk); 2529 if (ret) { 2530 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret); 2531 goto err_res; 2532 } 2533 2534 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); 2535 if (IS_ERR(hdmi->iahb_clk)) { 2536 ret = PTR_ERR(hdmi->iahb_clk); 2537 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); 2538 goto err_isfr; 2539 } 2540 2541 ret = clk_prepare_enable(hdmi->iahb_clk); 2542 if (ret) { 2543 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret); 2544 goto err_isfr; 2545 } 2546 2547 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec"); 2548 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) { 2549 hdmi->cec_clk = NULL; 2550 } else if (IS_ERR(hdmi->cec_clk)) { 2551 ret = PTR_ERR(hdmi->cec_clk); 2552 if (ret != -EPROBE_DEFER) 2553 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n", 2554 ret); 2555 2556 hdmi->cec_clk = NULL; 2557 goto err_iahb; 2558 } else { 2559 ret = clk_prepare_enable(hdmi->cec_clk); 2560 if (ret) { 2561 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n", 2562 ret); 2563 goto err_iahb; 2564 } 2565 } 2566 2567 /* Product and revision IDs */ 2568 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 2569 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 2570 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); 2571 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); 2572 2573 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || 2574 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { 2575 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", 2576 hdmi->version, prod_id0, prod_id1); 2577 ret = -ENODEV; 2578 goto err_iahb; 2579 } 2580 2581 ret = dw_hdmi_detect_phy(hdmi); 2582 if (ret < 0) 2583 goto err_iahb; 2584 2585 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", 2586 hdmi->version >> 12, hdmi->version & 0xfff, 2587 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", 2588 hdmi->phy.name); 2589 2590 initialize_hdmi_ih_mutes(hdmi); 2591 2592 irq = platform_get_irq(pdev, 0); 2593 if (irq < 0) { 2594 ret = irq; 2595 goto err_iahb; 2596 } 2597 2598 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, 2599 dw_hdmi_irq, IRQF_SHARED, 2600 dev_name(dev), hdmi); 2601 if (ret) 2602 goto err_iahb; 2603 2604 hdmi->cec_notifier = cec_notifier_get(dev); 2605 if (!hdmi->cec_notifier) { 2606 ret = -ENOMEM; 2607 goto err_iahb; 2608 } 2609 2610 /* 2611 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator 2612 * N and cts values before enabling phy 2613 */ 2614 hdmi_init_clk_regenerator(hdmi); 2615 2616 /* If DDC bus is not specified, try to register HDMI I2C bus */ 2617 if (!hdmi->ddc) { 2618 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); 2619 if (IS_ERR(hdmi->ddc)) 2620 hdmi->ddc = NULL; 2621 } 2622 2623 hdmi->bridge.driver_private = hdmi; 2624 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; 2625 #ifdef CONFIG_OF 2626 hdmi->bridge.of_node = pdev->dev.of_node; 2627 #endif 2628 2629 dw_hdmi_setup_i2c(hdmi); 2630 if (hdmi->phy.ops->setup_hpd) 2631 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 2632 2633 memset(&pdevinfo, 0, sizeof(pdevinfo)); 2634 pdevinfo.parent = dev; 2635 pdevinfo.id = PLATFORM_DEVID_AUTO; 2636 2637 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); 2638 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 2639 2640 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { 2641 struct dw_hdmi_audio_data audio; 2642 2643 audio.phys = iores->start; 2644 audio.base = hdmi->regs; 2645 audio.irq = irq; 2646 audio.hdmi = hdmi; 2647 audio.eld = hdmi->connector.eld; 2648 hdmi->enable_audio = dw_hdmi_ahb_audio_enable; 2649 hdmi->disable_audio = dw_hdmi_ahb_audio_disable; 2650 2651 pdevinfo.name = "dw-hdmi-ahb-audio"; 2652 pdevinfo.data = &audio; 2653 pdevinfo.size_data = sizeof(audio); 2654 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2655 hdmi->audio = platform_device_register_full(&pdevinfo); 2656 } else if (config0 & HDMI_CONFIG0_I2S) { 2657 struct dw_hdmi_i2s_audio_data audio; 2658 2659 audio.hdmi = hdmi; 2660 audio.write = hdmi_writeb; 2661 audio.read = hdmi_readb; 2662 hdmi->enable_audio = dw_hdmi_i2s_audio_enable; 2663 hdmi->disable_audio = dw_hdmi_i2s_audio_disable; 2664 2665 pdevinfo.name = "dw-hdmi-i2s-audio"; 2666 pdevinfo.data = &audio; 2667 pdevinfo.size_data = sizeof(audio); 2668 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2669 hdmi->audio = platform_device_register_full(&pdevinfo); 2670 } 2671 2672 if (config0 & HDMI_CONFIG0_CEC) { 2673 cec.hdmi = hdmi; 2674 cec.ops = &dw_hdmi_cec_ops; 2675 cec.irq = irq; 2676 2677 pdevinfo.name = "dw-hdmi-cec"; 2678 pdevinfo.data = &cec; 2679 pdevinfo.size_data = sizeof(cec); 2680 pdevinfo.dma_mask = 0; 2681 2682 hdmi->cec = platform_device_register_full(&pdevinfo); 2683 } 2684 2685 /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */ 2686 if (hdmi->i2c) 2687 dw_hdmi_i2c_init(hdmi); 2688 2689 return hdmi; 2690 2691 err_iahb: 2692 if (hdmi->i2c) { 2693 i2c_del_adapter(&hdmi->i2c->adap); 2694 hdmi->ddc = NULL; 2695 } 2696 2697 if (hdmi->cec_notifier) 2698 cec_notifier_put(hdmi->cec_notifier); 2699 2700 clk_disable_unprepare(hdmi->iahb_clk); 2701 if (hdmi->cec_clk) 2702 clk_disable_unprepare(hdmi->cec_clk); 2703 err_isfr: 2704 clk_disable_unprepare(hdmi->isfr_clk); 2705 err_res: 2706 i2c_put_adapter(hdmi->ddc); 2707 2708 return ERR_PTR(ret); 2709 } 2710 2711 static void __dw_hdmi_remove(struct dw_hdmi *hdmi) 2712 { 2713 if (hdmi->audio && !IS_ERR(hdmi->audio)) 2714 platform_device_unregister(hdmi->audio); 2715 if (!IS_ERR(hdmi->cec)) 2716 platform_device_unregister(hdmi->cec); 2717 2718 /* Disable all interrupts */ 2719 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2720 2721 if (hdmi->cec_notifier) 2722 cec_notifier_put(hdmi->cec_notifier); 2723 2724 clk_disable_unprepare(hdmi->iahb_clk); 2725 clk_disable_unprepare(hdmi->isfr_clk); 2726 if (hdmi->cec_clk) 2727 clk_disable_unprepare(hdmi->cec_clk); 2728 2729 if (hdmi->i2c) 2730 i2c_del_adapter(&hdmi->i2c->adap); 2731 else 2732 i2c_put_adapter(hdmi->ddc); 2733 } 2734 2735 /* ----------------------------------------------------------------------------- 2736 * Probe/remove API, used from platforms based on the DRM bridge API. 2737 */ 2738 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, 2739 const struct dw_hdmi_plat_data *plat_data) 2740 { 2741 struct dw_hdmi *hdmi; 2742 2743 hdmi = __dw_hdmi_probe(pdev, plat_data); 2744 if (IS_ERR(hdmi)) 2745 return hdmi; 2746 2747 drm_bridge_add(&hdmi->bridge); 2748 2749 return hdmi; 2750 } 2751 EXPORT_SYMBOL_GPL(dw_hdmi_probe); 2752 2753 void dw_hdmi_remove(struct dw_hdmi *hdmi) 2754 { 2755 drm_bridge_remove(&hdmi->bridge); 2756 2757 __dw_hdmi_remove(hdmi); 2758 } 2759 EXPORT_SYMBOL_GPL(dw_hdmi_remove); 2760 2761 /* ----------------------------------------------------------------------------- 2762 * Bind/unbind API, used from platforms based on the component framework. 2763 */ 2764 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, 2765 struct drm_encoder *encoder, 2766 const struct dw_hdmi_plat_data *plat_data) 2767 { 2768 struct dw_hdmi *hdmi; 2769 int ret; 2770 2771 hdmi = __dw_hdmi_probe(pdev, plat_data); 2772 if (IS_ERR(hdmi)) 2773 return hdmi; 2774 2775 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL); 2776 if (ret) { 2777 dw_hdmi_remove(hdmi); 2778 DRM_ERROR("Failed to initialize bridge with drm\n"); 2779 return ERR_PTR(ret); 2780 } 2781 2782 return hdmi; 2783 } 2784 EXPORT_SYMBOL_GPL(dw_hdmi_bind); 2785 2786 void dw_hdmi_unbind(struct dw_hdmi *hdmi) 2787 { 2788 __dw_hdmi_remove(hdmi); 2789 } 2790 EXPORT_SYMBOL_GPL(dw_hdmi_unbind); 2791 2792 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 2793 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); 2794 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); 2795 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>"); 2796 MODULE_DESCRIPTION("DW HDMI transmitter driver"); 2797 MODULE_LICENSE("GPL"); 2798 MODULE_ALIAS("platform:dw-hdmi"); 2799