1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DesignWare High-Definition Multimedia Interface (HDMI) driver 4 * 5 * Copyright (C) 2013-2015 Mentor Graphics Inc. 6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 8 */ 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/hdmi.h> 13 #include <linux/irq.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of_device.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/regmap.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/spinlock.h> 21 22 #include <media/cec-notifier.h> 23 24 #include <uapi/linux/media-bus-format.h> 25 #include <uapi/linux/videodev2.h> 26 27 #include <drm/bridge/dw_hdmi.h> 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_of.h> 31 #include <drm/drm_print.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_scdc_helper.h> 34 35 #include "dw-hdmi-audio.h" 36 #include "dw-hdmi-cec.h" 37 #include "dw-hdmi.h" 38 39 #define DDC_SEGMENT_ADDR 0x30 40 41 #define HDMI_EDID_LEN 512 42 43 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ 44 #define SCDC_MIN_SOURCE_VERSION 0x1 45 46 #define HDMI14_MAX_TMDSCLK 340000000 47 48 enum hdmi_datamap { 49 RGB444_8B = 0x01, 50 RGB444_10B = 0x03, 51 RGB444_12B = 0x05, 52 RGB444_16B = 0x07, 53 YCbCr444_8B = 0x09, 54 YCbCr444_10B = 0x0B, 55 YCbCr444_12B = 0x0D, 56 YCbCr444_16B = 0x0F, 57 YCbCr422_8B = 0x16, 58 YCbCr422_10B = 0x14, 59 YCbCr422_12B = 0x12, 60 }; 61 62 static const u16 csc_coeff_default[3][4] = { 63 { 0x2000, 0x0000, 0x0000, 0x0000 }, 64 { 0x0000, 0x2000, 0x0000, 0x0000 }, 65 { 0x0000, 0x0000, 0x2000, 0x0000 } 66 }; 67 68 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 69 { 0x2000, 0x6926, 0x74fd, 0x010e }, 70 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 71 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 72 }; 73 74 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 75 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 76 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 77 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 78 }; 79 80 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 81 { 0x2591, 0x1322, 0x074b, 0x0000 }, 82 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 83 { 0x6acd, 0x7534, 0x2000, 0x0200 } 84 }; 85 86 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 87 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 88 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 89 { 0x6756, 0x78ab, 0x2000, 0x0200 } 90 }; 91 92 struct hdmi_vmode { 93 bool mdataenablepolarity; 94 95 unsigned int mpixelclock; 96 unsigned int mpixelrepetitioninput; 97 unsigned int mpixelrepetitionoutput; 98 unsigned int mtmdsclock; 99 }; 100 101 struct hdmi_data_info { 102 unsigned int enc_in_bus_format; 103 unsigned int enc_out_bus_format; 104 unsigned int enc_in_encoding; 105 unsigned int enc_out_encoding; 106 unsigned int pix_repet_factor; 107 unsigned int hdcp_enable; 108 struct hdmi_vmode video_mode; 109 }; 110 111 struct dw_hdmi_i2c { 112 struct i2c_adapter adap; 113 114 struct mutex lock; /* used to serialize data transfers */ 115 struct completion cmp; 116 u8 stat; 117 118 u8 slave_reg; 119 bool is_regaddr; 120 bool is_segment; 121 }; 122 123 struct dw_hdmi_phy_data { 124 enum dw_hdmi_phy_type type; 125 const char *name; 126 unsigned int gen; 127 bool has_svsret; 128 int (*configure)(struct dw_hdmi *hdmi, 129 const struct dw_hdmi_plat_data *pdata, 130 unsigned long mpixelclock); 131 }; 132 133 struct dw_hdmi { 134 struct drm_connector connector; 135 struct drm_bridge bridge; 136 137 unsigned int version; 138 139 struct platform_device *audio; 140 struct platform_device *cec; 141 struct device *dev; 142 struct clk *isfr_clk; 143 struct clk *iahb_clk; 144 struct clk *cec_clk; 145 struct dw_hdmi_i2c *i2c; 146 147 struct hdmi_data_info hdmi_data; 148 const struct dw_hdmi_plat_data *plat_data; 149 150 int vic; 151 152 u8 edid[HDMI_EDID_LEN]; 153 154 struct { 155 const struct dw_hdmi_phy_ops *ops; 156 const char *name; 157 void *data; 158 bool enabled; 159 } phy; 160 161 struct drm_display_mode previous_mode; 162 163 struct i2c_adapter *ddc; 164 void __iomem *regs; 165 bool sink_is_hdmi; 166 bool sink_has_audio; 167 168 struct pinctrl *pinctrl; 169 struct pinctrl_state *default_state; 170 struct pinctrl_state *unwedge_state; 171 172 struct mutex mutex; /* for state below and previous_mode */ 173 enum drm_connector_force force; /* mutex-protected force state */ 174 bool disabled; /* DRM has disabled our bridge */ 175 bool bridge_is_on; /* indicates the bridge is on */ 176 bool rxsense; /* rxsense state */ 177 u8 phy_mask; /* desired phy int mask settings */ 178 u8 mc_clkdis; /* clock disable register */ 179 180 spinlock_t audio_lock; 181 struct mutex audio_mutex; 182 unsigned int sample_rate; 183 unsigned int audio_cts; 184 unsigned int audio_n; 185 bool audio_enable; 186 187 unsigned int reg_shift; 188 struct regmap *regm; 189 void (*enable_audio)(struct dw_hdmi *hdmi); 190 void (*disable_audio)(struct dw_hdmi *hdmi); 191 192 struct mutex cec_notifier_mutex; 193 struct cec_notifier *cec_notifier; 194 }; 195 196 #define HDMI_IH_PHY_STAT0_RX_SENSE \ 197 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ 198 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) 199 200 #define HDMI_PHY_RX_SENSE \ 201 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ 202 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) 203 204 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 205 { 206 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); 207 } 208 209 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 210 { 211 unsigned int val = 0; 212 213 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); 214 215 return val; 216 } 217 218 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 219 { 220 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); 221 } 222 223 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 224 u8 shift, u8 mask) 225 { 226 hdmi_modb(hdmi, data << shift, mask, reg); 227 } 228 229 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 230 { 231 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, 232 HDMI_PHY_I2CM_INT_ADDR); 233 234 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | 235 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, 236 HDMI_PHY_I2CM_CTLINT_ADDR); 237 238 /* Software reset */ 239 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 240 241 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ 242 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); 243 244 /* Set done, not acknowledged and arbitration interrupt polarities */ 245 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 246 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 247 HDMI_I2CM_CTLINT); 248 249 /* Clear DONE and ERROR interrupts */ 250 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 251 HDMI_IH_I2CM_STAT0); 252 253 /* Mute DONE and ERROR interrupts */ 254 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 255 HDMI_IH_MUTE_I2CM_STAT0); 256 } 257 258 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi) 259 { 260 /* If no unwedge state then give up */ 261 if (!hdmi->unwedge_state) 262 return false; 263 264 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n"); 265 266 /* 267 * This is a huge hack to workaround a problem where the dw_hdmi i2c 268 * bus could sometimes get wedged. Once wedged there doesn't appear 269 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ) 270 * other than pulsing the SDA line. 271 * 272 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi) 273 * by: 274 * 1. Remux the pin as a GPIO output, driven low. 275 * 2. Wait a little while. 1 ms seems to work, but we'll do 10. 276 * 3. Immediately jump to remux the pin as dw_hdmi i2c again. 277 * 278 * At the moment of remuxing, the line will still be low due to its 279 * recent stint as an output, but then it will be pulled high by the 280 * (presumed) external pullup. dw_hdmi seems to see this as a rising 281 * edge and that seems to get it out of its jam. 282 * 283 * This wedging was only ever seen on one TV, and only on one of 284 * its HDMI ports. It happened when the TV was powered on while the 285 * device was plugged in. A scope trace shows the TV bringing both SDA 286 * and SCL low, then bringing them both back up at roughly the same 287 * time. Presumably this confuses dw_hdmi because it saw activity but 288 * no real STOP (maybe it thinks there's another master on the bus?). 289 * Giving it a clean rising edge of SDA while SCL is already high 290 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out 291 * of its stupor. 292 * 293 * Note that after coming back alive, transfers seem to immediately 294 * resume, so if we unwedge due to a timeout we should wait a little 295 * longer for our transfer to finish, since it might have just started 296 * now. 297 */ 298 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state); 299 msleep(10); 300 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state); 301 302 return true; 303 } 304 305 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi) 306 { 307 struct dw_hdmi_i2c *i2c = hdmi->i2c; 308 int stat; 309 310 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 311 if (!stat) { 312 /* If we can't unwedge, return timeout */ 313 if (!dw_hdmi_i2c_unwedge(hdmi)) 314 return -EAGAIN; 315 316 /* We tried to unwedge; give it another chance */ 317 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 318 if (!stat) 319 return -EAGAIN; 320 } 321 322 /* Check for error condition on the bus */ 323 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 324 return -EIO; 325 326 return 0; 327 } 328 329 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 330 unsigned char *buf, unsigned int length) 331 { 332 struct dw_hdmi_i2c *i2c = hdmi->i2c; 333 int ret; 334 335 if (!i2c->is_regaddr) { 336 dev_dbg(hdmi->dev, "set read register address to 0\n"); 337 i2c->slave_reg = 0x00; 338 i2c->is_regaddr = true; 339 } 340 341 while (length--) { 342 reinit_completion(&i2c->cmp); 343 344 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 345 if (i2c->is_segment) 346 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 347 HDMI_I2CM_OPERATION); 348 else 349 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 350 HDMI_I2CM_OPERATION); 351 352 ret = dw_hdmi_i2c_wait(hdmi); 353 if (ret) 354 return ret; 355 356 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 357 } 358 i2c->is_segment = false; 359 360 return 0; 361 } 362 363 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 364 unsigned char *buf, unsigned int length) 365 { 366 struct dw_hdmi_i2c *i2c = hdmi->i2c; 367 int ret; 368 369 if (!i2c->is_regaddr) { 370 /* Use the first write byte as register address */ 371 i2c->slave_reg = buf[0]; 372 length--; 373 buf++; 374 i2c->is_regaddr = true; 375 } 376 377 while (length--) { 378 reinit_completion(&i2c->cmp); 379 380 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 381 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 382 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 383 HDMI_I2CM_OPERATION); 384 385 ret = dw_hdmi_i2c_wait(hdmi); 386 if (ret) 387 return ret; 388 } 389 390 return 0; 391 } 392 393 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, 394 struct i2c_msg *msgs, int num) 395 { 396 struct dw_hdmi *hdmi = i2c_get_adapdata(adap); 397 struct dw_hdmi_i2c *i2c = hdmi->i2c; 398 u8 addr = msgs[0].addr; 399 int i, ret = 0; 400 401 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); 402 403 for (i = 0; i < num; i++) { 404 if (msgs[i].len == 0) { 405 dev_dbg(hdmi->dev, 406 "unsupported transfer %d/%d, no data\n", 407 i + 1, num); 408 return -EOPNOTSUPP; 409 } 410 } 411 412 mutex_lock(&i2c->lock); 413 414 /* Unmute DONE and ERROR interrupts */ 415 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 416 417 /* Set slave device address taken from the first I2C message */ 418 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 419 420 /* Set slave device register address on transfer */ 421 i2c->is_regaddr = false; 422 423 /* Set segment pointer for I2C extended read mode operation */ 424 i2c->is_segment = false; 425 426 for (i = 0; i < num; i++) { 427 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", 428 i + 1, num, msgs[i].len, msgs[i].flags); 429 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 430 i2c->is_segment = true; 431 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 432 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 433 } else { 434 if (msgs[i].flags & I2C_M_RD) 435 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 436 msgs[i].len); 437 else 438 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 439 msgs[i].len); 440 } 441 if (ret < 0) 442 break; 443 } 444 445 if (!ret) 446 ret = num; 447 448 /* Mute DONE and ERROR interrupts */ 449 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 450 HDMI_IH_MUTE_I2CM_STAT0); 451 452 mutex_unlock(&i2c->lock); 453 454 return ret; 455 } 456 457 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) 458 { 459 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 460 } 461 462 static const struct i2c_algorithm dw_hdmi_algorithm = { 463 .master_xfer = dw_hdmi_i2c_xfer, 464 .functionality = dw_hdmi_i2c_func, 465 }; 466 467 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) 468 { 469 struct i2c_adapter *adap; 470 struct dw_hdmi_i2c *i2c; 471 int ret; 472 473 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 474 if (!i2c) 475 return ERR_PTR(-ENOMEM); 476 477 mutex_init(&i2c->lock); 478 init_completion(&i2c->cmp); 479 480 adap = &i2c->adap; 481 adap->class = I2C_CLASS_DDC; 482 adap->owner = THIS_MODULE; 483 adap->dev.parent = hdmi->dev; 484 adap->algo = &dw_hdmi_algorithm; 485 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name)); 486 i2c_set_adapdata(adap, hdmi); 487 488 ret = i2c_add_adapter(adap); 489 if (ret) { 490 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 491 devm_kfree(hdmi->dev, i2c); 492 return ERR_PTR(ret); 493 } 494 495 hdmi->i2c = i2c; 496 497 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 498 499 return adap; 500 } 501 502 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 503 unsigned int n) 504 { 505 /* Must be set/cleared first */ 506 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 507 508 /* nshift factor = 0 */ 509 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 510 511 /* Use automatic CTS generation mode when CTS is not set */ 512 if (cts) 513 hdmi_writeb(hdmi, ((cts >> 16) & 514 HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 515 HDMI_AUD_CTS3_CTS_MANUAL, 516 HDMI_AUD_CTS3); 517 else 518 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3); 519 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 520 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 521 522 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 523 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 524 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 525 } 526 527 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) 528 { 529 unsigned int n = (128 * freq) / 1000; 530 unsigned int mult = 1; 531 532 while (freq > 48000) { 533 mult *= 2; 534 freq /= 2; 535 } 536 537 switch (freq) { 538 case 32000: 539 if (pixel_clk == 25175000) 540 n = 4576; 541 else if (pixel_clk == 27027000) 542 n = 4096; 543 else if (pixel_clk == 74176000 || pixel_clk == 148352000) 544 n = 11648; 545 else 546 n = 4096; 547 n *= mult; 548 break; 549 550 case 44100: 551 if (pixel_clk == 25175000) 552 n = 7007; 553 else if (pixel_clk == 74176000) 554 n = 17836; 555 else if (pixel_clk == 148352000) 556 n = 8918; 557 else 558 n = 6272; 559 n *= mult; 560 break; 561 562 case 48000: 563 if (pixel_clk == 25175000) 564 n = 6864; 565 else if (pixel_clk == 27027000) 566 n = 6144; 567 else if (pixel_clk == 74176000) 568 n = 11648; 569 else if (pixel_clk == 148352000) 570 n = 5824; 571 else 572 n = 6144; 573 n *= mult; 574 break; 575 576 default: 577 break; 578 } 579 580 return n; 581 } 582 583 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, 584 unsigned long pixel_clk, unsigned int sample_rate) 585 { 586 unsigned long ftdms = pixel_clk; 587 unsigned int n, cts; 588 u8 config3; 589 u64 tmp; 590 591 n = hdmi_compute_n(sample_rate, pixel_clk); 592 593 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 594 595 /* Only compute CTS when using internal AHB audio */ 596 if (config3 & HDMI_CONFIG3_AHBAUDDMA) { 597 /* 598 * Compute the CTS value from the N value. Note that CTS and N 599 * can be up to 20 bits in total, so we need 64-bit math. Also 600 * note that our TDMS clock is not fully accurate; it is 601 * accurate to kHz. This can introduce an unnecessary remainder 602 * in the calculation below, so we don't try to warn about that. 603 */ 604 tmp = (u64)ftdms * n; 605 do_div(tmp, 128 * sample_rate); 606 cts = tmp; 607 608 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", 609 __func__, sample_rate, 610 ftdms / 1000000, (ftdms / 1000) % 1000, 611 n, cts); 612 } else { 613 cts = 0; 614 } 615 616 spin_lock_irq(&hdmi->audio_lock); 617 hdmi->audio_n = n; 618 hdmi->audio_cts = cts; 619 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 620 spin_unlock_irq(&hdmi->audio_lock); 621 } 622 623 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) 624 { 625 mutex_lock(&hdmi->audio_mutex); 626 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); 627 mutex_unlock(&hdmi->audio_mutex); 628 } 629 630 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 631 { 632 mutex_lock(&hdmi->audio_mutex); 633 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 634 hdmi->sample_rate); 635 mutex_unlock(&hdmi->audio_mutex); 636 } 637 638 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 639 { 640 mutex_lock(&hdmi->audio_mutex); 641 hdmi->sample_rate = rate; 642 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 643 hdmi->sample_rate); 644 mutex_unlock(&hdmi->audio_mutex); 645 } 646 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); 647 648 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt) 649 { 650 u8 layout; 651 652 mutex_lock(&hdmi->audio_mutex); 653 654 /* 655 * For >2 channel PCM audio, we need to select layout 1 656 * and set an appropriate channel map. 657 */ 658 if (cnt > 2) 659 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1; 660 else 661 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0; 662 663 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK, 664 HDMI_FC_AUDSCONF); 665 666 /* Set the audio infoframes channel count */ 667 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET, 668 HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0); 669 670 mutex_unlock(&hdmi->audio_mutex); 671 } 672 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count); 673 674 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca) 675 { 676 mutex_lock(&hdmi->audio_mutex); 677 678 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2); 679 680 mutex_unlock(&hdmi->audio_mutex); 681 } 682 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation); 683 684 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) 685 { 686 if (enable) 687 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; 688 else 689 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; 690 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 691 } 692 693 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi) 694 { 695 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 696 } 697 698 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi) 699 { 700 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 701 } 702 703 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi) 704 { 705 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 706 hdmi_enable_audio_clk(hdmi, true); 707 } 708 709 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi) 710 { 711 hdmi_enable_audio_clk(hdmi, false); 712 } 713 714 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 715 { 716 unsigned long flags; 717 718 spin_lock_irqsave(&hdmi->audio_lock, flags); 719 hdmi->audio_enable = true; 720 if (hdmi->enable_audio) 721 hdmi->enable_audio(hdmi); 722 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 723 } 724 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); 725 726 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 727 { 728 unsigned long flags; 729 730 spin_lock_irqsave(&hdmi->audio_lock, flags); 731 hdmi->audio_enable = false; 732 if (hdmi->disable_audio) 733 hdmi->disable_audio(hdmi); 734 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 735 } 736 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); 737 738 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 739 { 740 switch (bus_format) { 741 case MEDIA_BUS_FMT_RGB888_1X24: 742 case MEDIA_BUS_FMT_RGB101010_1X30: 743 case MEDIA_BUS_FMT_RGB121212_1X36: 744 case MEDIA_BUS_FMT_RGB161616_1X48: 745 return true; 746 747 default: 748 return false; 749 } 750 } 751 752 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 753 { 754 switch (bus_format) { 755 case MEDIA_BUS_FMT_YUV8_1X24: 756 case MEDIA_BUS_FMT_YUV10_1X30: 757 case MEDIA_BUS_FMT_YUV12_1X36: 758 case MEDIA_BUS_FMT_YUV16_1X48: 759 return true; 760 761 default: 762 return false; 763 } 764 } 765 766 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 767 { 768 switch (bus_format) { 769 case MEDIA_BUS_FMT_UYVY8_1X16: 770 case MEDIA_BUS_FMT_UYVY10_1X20: 771 case MEDIA_BUS_FMT_UYVY12_1X24: 772 return true; 773 774 default: 775 return false; 776 } 777 } 778 779 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 780 { 781 switch (bus_format) { 782 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 783 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 784 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 785 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 786 return true; 787 788 default: 789 return false; 790 } 791 } 792 793 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 794 { 795 switch (bus_format) { 796 case MEDIA_BUS_FMT_RGB888_1X24: 797 case MEDIA_BUS_FMT_YUV8_1X24: 798 case MEDIA_BUS_FMT_UYVY8_1X16: 799 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 800 return 8; 801 802 case MEDIA_BUS_FMT_RGB101010_1X30: 803 case MEDIA_BUS_FMT_YUV10_1X30: 804 case MEDIA_BUS_FMT_UYVY10_1X20: 805 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 806 return 10; 807 808 case MEDIA_BUS_FMT_RGB121212_1X36: 809 case MEDIA_BUS_FMT_YUV12_1X36: 810 case MEDIA_BUS_FMT_UYVY12_1X24: 811 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 812 return 12; 813 814 case MEDIA_BUS_FMT_RGB161616_1X48: 815 case MEDIA_BUS_FMT_YUV16_1X48: 816 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 817 return 16; 818 819 default: 820 return 0; 821 } 822 } 823 824 /* 825 * this submodule is responsible for the video data synchronization. 826 * for example, for RGB 4:4:4 input, the data map is defined as 827 * pin{47~40} <==> R[7:0] 828 * pin{31~24} <==> G[7:0] 829 * pin{15~8} <==> B[7:0] 830 */ 831 static void hdmi_video_sample(struct dw_hdmi *hdmi) 832 { 833 int color_format = 0; 834 u8 val; 835 836 switch (hdmi->hdmi_data.enc_in_bus_format) { 837 case MEDIA_BUS_FMT_RGB888_1X24: 838 color_format = 0x01; 839 break; 840 case MEDIA_BUS_FMT_RGB101010_1X30: 841 color_format = 0x03; 842 break; 843 case MEDIA_BUS_FMT_RGB121212_1X36: 844 color_format = 0x05; 845 break; 846 case MEDIA_BUS_FMT_RGB161616_1X48: 847 color_format = 0x07; 848 break; 849 850 case MEDIA_BUS_FMT_YUV8_1X24: 851 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 852 color_format = 0x09; 853 break; 854 case MEDIA_BUS_FMT_YUV10_1X30: 855 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 856 color_format = 0x0B; 857 break; 858 case MEDIA_BUS_FMT_YUV12_1X36: 859 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 860 color_format = 0x0D; 861 break; 862 case MEDIA_BUS_FMT_YUV16_1X48: 863 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 864 color_format = 0x0F; 865 break; 866 867 case MEDIA_BUS_FMT_UYVY8_1X16: 868 color_format = 0x16; 869 break; 870 case MEDIA_BUS_FMT_UYVY10_1X20: 871 color_format = 0x14; 872 break; 873 case MEDIA_BUS_FMT_UYVY12_1X24: 874 color_format = 0x12; 875 break; 876 877 default: 878 return; 879 } 880 881 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 882 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 883 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 884 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 885 886 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 887 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 888 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 889 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 890 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 891 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 892 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 893 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 894 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 895 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 896 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 897 } 898 899 static int is_color_space_conversion(struct dw_hdmi *hdmi) 900 { 901 return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format; 902 } 903 904 static int is_color_space_decimation(struct dw_hdmi *hdmi) 905 { 906 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 907 return 0; 908 909 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 910 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 911 return 1; 912 913 return 0; 914 } 915 916 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 917 { 918 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 919 return 0; 920 921 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 922 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 923 return 1; 924 925 return 0; 926 } 927 928 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 929 { 930 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 931 unsigned i; 932 u32 csc_scale = 1; 933 934 if (is_color_space_conversion(hdmi)) { 935 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 936 if (hdmi->hdmi_data.enc_out_encoding == 937 V4L2_YCBCR_ENC_601) 938 csc_coeff = &csc_coeff_rgb_out_eitu601; 939 else 940 csc_coeff = &csc_coeff_rgb_out_eitu709; 941 } else if (hdmi_bus_fmt_is_rgb( 942 hdmi->hdmi_data.enc_in_bus_format)) { 943 if (hdmi->hdmi_data.enc_out_encoding == 944 V4L2_YCBCR_ENC_601) 945 csc_coeff = &csc_coeff_rgb_in_eitu601; 946 else 947 csc_coeff = &csc_coeff_rgb_in_eitu709; 948 csc_scale = 0; 949 } 950 } 951 952 /* The CSC registers are sequential, alternating MSB then LSB */ 953 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 954 u16 coeff_a = (*csc_coeff)[0][i]; 955 u16 coeff_b = (*csc_coeff)[1][i]; 956 u16 coeff_c = (*csc_coeff)[2][i]; 957 958 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 959 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 960 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 961 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 962 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 963 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 964 } 965 966 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 967 HDMI_CSC_SCALE); 968 } 969 970 static void hdmi_video_csc(struct dw_hdmi *hdmi) 971 { 972 int color_depth = 0; 973 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 974 int decimation = 0; 975 976 /* YCC422 interpolation to 444 mode */ 977 if (is_color_space_interpolation(hdmi)) 978 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 979 else if (is_color_space_decimation(hdmi)) 980 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 981 982 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 983 case 8: 984 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 985 break; 986 case 10: 987 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 988 break; 989 case 12: 990 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 991 break; 992 case 16: 993 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 994 break; 995 996 default: 997 return; 998 } 999 1000 /* Configure the CSC registers */ 1001 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 1002 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 1003 HDMI_CSC_SCALE); 1004 1005 dw_hdmi_update_csc_coeffs(hdmi); 1006 } 1007 1008 /* 1009 * HDMI video packetizer is used to packetize the data. 1010 * for example, if input is YCC422 mode or repeater is used, 1011 * data should be repacked this module can be bypassed. 1012 */ 1013 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 1014 { 1015 unsigned int color_depth = 0; 1016 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 1017 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 1018 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1019 u8 val, vp_conf; 1020 1021 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1022 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 1023 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1024 switch (hdmi_bus_fmt_color_depth( 1025 hdmi->hdmi_data.enc_out_bus_format)) { 1026 case 8: 1027 color_depth = 4; 1028 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1029 break; 1030 case 10: 1031 color_depth = 5; 1032 break; 1033 case 12: 1034 color_depth = 6; 1035 break; 1036 case 16: 1037 color_depth = 7; 1038 break; 1039 default: 1040 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1041 } 1042 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1043 switch (hdmi_bus_fmt_color_depth( 1044 hdmi->hdmi_data.enc_out_bus_format)) { 1045 case 0: 1046 case 8: 1047 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1048 break; 1049 case 10: 1050 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1051 break; 1052 case 12: 1053 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1054 break; 1055 1056 default: 1057 return; 1058 } 1059 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1060 } else { 1061 return; 1062 } 1063 1064 /* set the packetizer registers */ 1065 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1066 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | 1067 ((hdmi_data->pix_repet_factor << 1068 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & 1069 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); 1070 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1071 1072 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1073 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1074 1075 /* Data from pixel repeater block */ 1076 if (hdmi_data->pix_repet_factor > 1) { 1077 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1078 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1079 } else { /* data from packetizer block */ 1080 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1081 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1082 } 1083 1084 hdmi_modb(hdmi, vp_conf, 1085 HDMI_VP_CONF_PR_EN_MASK | 1086 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1087 1088 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 1089 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 1090 1091 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1092 1093 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1094 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1095 HDMI_VP_CONF_PP_EN_ENABLE | 1096 HDMI_VP_CONF_YCC422_EN_DISABLE; 1097 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1098 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1099 HDMI_VP_CONF_PP_EN_DISABLE | 1100 HDMI_VP_CONF_YCC422_EN_ENABLE; 1101 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1102 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1103 HDMI_VP_CONF_PP_EN_DISABLE | 1104 HDMI_VP_CONF_YCC422_EN_DISABLE; 1105 } else { 1106 return; 1107 } 1108 1109 hdmi_modb(hdmi, vp_conf, 1110 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1111 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1112 1113 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1114 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1115 HDMI_VP_STUFF_PP_STUFFING_MASK | 1116 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1117 1118 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1119 HDMI_VP_CONF); 1120 } 1121 1122 /* ----------------------------------------------------------------------------- 1123 * Synopsys PHY Handling 1124 */ 1125 1126 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 1127 unsigned char bit) 1128 { 1129 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 1130 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 1131 } 1132 1133 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 1134 { 1135 u32 val; 1136 1137 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 1138 if (msec-- == 0) 1139 return false; 1140 udelay(1000); 1141 } 1142 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 1143 1144 return true; 1145 } 1146 1147 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 1148 unsigned char addr) 1149 { 1150 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 1151 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 1152 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 1153 HDMI_PHY_I2CM_DATAO_1_ADDR); 1154 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 1155 HDMI_PHY_I2CM_DATAO_0_ADDR); 1156 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 1157 HDMI_PHY_I2CM_OPERATION_ADDR); 1158 hdmi_phy_wait_i2c_done(hdmi, 1000); 1159 } 1160 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); 1161 1162 /* Filter out invalid setups to avoid configuring SCDC and scrambling */ 1163 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi) 1164 { 1165 struct drm_display_info *display = &hdmi->connector.display_info; 1166 1167 /* Completely disable SCDC support for older controllers */ 1168 if (hdmi->version < 0x200a) 1169 return false; 1170 1171 /* Disable if no DDC bus */ 1172 if (!hdmi->ddc) 1173 return false; 1174 1175 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */ 1176 if (!display->hdmi.scdc.supported || 1177 !display->hdmi.scdc.scrambling.supported) 1178 return false; 1179 1180 /* 1181 * Disable if display only support low TMDS rates and scrambling 1182 * for low rates is not supported either 1183 */ 1184 if (!display->hdmi.scdc.scrambling.low_rates && 1185 display->max_tmds_clock <= 340000) 1186 return false; 1187 1188 return true; 1189 } 1190 1191 /* 1192 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates: 1193 * - The Source shall suspend transmission of the TMDS clock and data 1194 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it 1195 * from a 0 to a 1 or from a 1 to a 0 1196 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from 1197 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming 1198 * transmission of TMDS clock and data 1199 * 1200 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio() 1201 * helper should called right before enabling the TMDS Clock and Data in 1202 * the PHY configuration callback. 1203 */ 1204 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi) 1205 { 1206 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1207 1208 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 1209 if (dw_hdmi_support_scdc(hdmi)) { 1210 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1211 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1); 1212 else 1213 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0); 1214 } 1215 } 1216 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio); 1217 1218 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 1219 { 1220 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 1221 HDMI_PHY_CONF0_PDZ_OFFSET, 1222 HDMI_PHY_CONF0_PDZ_MASK); 1223 } 1224 1225 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 1226 { 1227 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1228 HDMI_PHY_CONF0_ENTMDS_OFFSET, 1229 HDMI_PHY_CONF0_ENTMDS_MASK); 1230 } 1231 1232 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 1233 { 1234 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1235 HDMI_PHY_CONF0_SVSRET_OFFSET, 1236 HDMI_PHY_CONF0_SVSRET_MASK); 1237 } 1238 1239 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 1240 { 1241 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1242 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 1243 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 1244 } 1245 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq); 1246 1247 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 1248 { 1249 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1250 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 1251 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 1252 } 1253 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron); 1254 1255 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 1256 { 1257 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1258 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 1259 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 1260 } 1261 1262 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 1263 { 1264 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1265 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 1266 HDMI_PHY_CONF0_SELDIPIF_MASK); 1267 } 1268 1269 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi) 1270 { 1271 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 1272 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1273 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1274 } 1275 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset); 1276 1277 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) 1278 { 1279 hdmi_phy_test_clear(hdmi, 1); 1280 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR); 1281 hdmi_phy_test_clear(hdmi, 0); 1282 } 1283 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr); 1284 1285 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 1286 { 1287 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1288 unsigned int i; 1289 u16 val; 1290 1291 if (phy->gen == 1) { 1292 dw_hdmi_phy_enable_tmds(hdmi, 0); 1293 dw_hdmi_phy_enable_powerdown(hdmi, true); 1294 return; 1295 } 1296 1297 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 1298 1299 /* 1300 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 1301 * to low power mode. 1302 */ 1303 for (i = 0; i < 5; ++i) { 1304 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 1305 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 1306 break; 1307 1308 usleep_range(1000, 2000); 1309 } 1310 1311 if (val & HDMI_PHY_TX_PHY_LOCK) 1312 dev_warn(hdmi->dev, "PHY failed to power down\n"); 1313 else 1314 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); 1315 1316 dw_hdmi_phy_gen2_pddq(hdmi, 1); 1317 } 1318 1319 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 1320 { 1321 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1322 unsigned int i; 1323 u8 val; 1324 1325 if (phy->gen == 1) { 1326 dw_hdmi_phy_enable_powerdown(hdmi, false); 1327 1328 /* Toggle TMDS enable. */ 1329 dw_hdmi_phy_enable_tmds(hdmi, 0); 1330 dw_hdmi_phy_enable_tmds(hdmi, 1); 1331 return 0; 1332 } 1333 1334 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 1335 dw_hdmi_phy_gen2_pddq(hdmi, 0); 1336 1337 /* Wait for PHY PLL lock */ 1338 for (i = 0; i < 5; ++i) { 1339 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 1340 if (val) 1341 break; 1342 1343 usleep_range(1000, 2000); 1344 } 1345 1346 if (!val) { 1347 dev_err(hdmi->dev, "PHY PLL failed to lock\n"); 1348 return -ETIMEDOUT; 1349 } 1350 1351 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); 1352 return 0; 1353 } 1354 1355 /* 1356 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 1357 * information the DWC MHL PHY has the same register layout and is thus also 1358 * supported by this function. 1359 */ 1360 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 1361 const struct dw_hdmi_plat_data *pdata, 1362 unsigned long mpixelclock) 1363 { 1364 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 1365 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 1366 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 1367 1368 /* TOFIX Will need 420 specific PHY configuration tables */ 1369 1370 /* PLL/MPLL Cfg - always match on final entry */ 1371 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 1372 if (mpixelclock <= mpll_config->mpixelclock) 1373 break; 1374 1375 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 1376 if (mpixelclock <= curr_ctrl->mpixelclock) 1377 break; 1378 1379 for (; phy_config->mpixelclock != ~0UL; phy_config++) 1380 if (mpixelclock <= phy_config->mpixelclock) 1381 break; 1382 1383 if (mpll_config->mpixelclock == ~0UL || 1384 curr_ctrl->mpixelclock == ~0UL || 1385 phy_config->mpixelclock == ~0UL) 1386 return -EINVAL; 1387 1388 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 1389 HDMI_3D_TX_PHY_CPCE_CTRL); 1390 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 1391 HDMI_3D_TX_PHY_GMPCTRL); 1392 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 1393 HDMI_3D_TX_PHY_CURRCTRL); 1394 1395 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 1396 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 1397 HDMI_3D_TX_PHY_MSM_CTRL); 1398 1399 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 1400 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 1401 HDMI_3D_TX_PHY_CKSYMTXCTRL); 1402 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 1403 HDMI_3D_TX_PHY_VLEVCTRL); 1404 1405 /* Override and disable clock termination. */ 1406 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 1407 HDMI_3D_TX_PHY_CKCALCTRL); 1408 1409 return 0; 1410 } 1411 1412 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 1413 { 1414 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1415 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 1416 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 1417 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1418 int ret; 1419 1420 dw_hdmi_phy_power_off(hdmi); 1421 1422 dw_hdmi_set_high_tmds_clock_ratio(hdmi); 1423 1424 /* Leave low power consumption mode by asserting SVSRET. */ 1425 if (phy->has_svsret) 1426 dw_hdmi_phy_enable_svsret(hdmi, 1); 1427 1428 dw_hdmi_phy_reset(hdmi); 1429 1430 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 1431 1432 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); 1433 1434 /* Write to the PHY as configured by the platform */ 1435 if (pdata->configure_phy) 1436 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 1437 else 1438 ret = phy->configure(hdmi, pdata, mpixelclock); 1439 if (ret) { 1440 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", 1441 mpixelclock); 1442 return ret; 1443 } 1444 1445 /* Wait for resuming transmission of TMDS clock and data */ 1446 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1447 msleep(100); 1448 1449 return dw_hdmi_phy_power_on(hdmi); 1450 } 1451 1452 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 1453 struct drm_display_mode *mode) 1454 { 1455 int i, ret; 1456 1457 /* HDMI Phy spec says to do the phy initialization sequence twice */ 1458 for (i = 0; i < 2; i++) { 1459 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 1460 dw_hdmi_phy_sel_interface_control(hdmi, 0); 1461 1462 ret = hdmi_phy_configure(hdmi); 1463 if (ret) 1464 return ret; 1465 } 1466 1467 return 0; 1468 } 1469 1470 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 1471 { 1472 dw_hdmi_phy_power_off(hdmi); 1473 } 1474 1475 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 1476 void *data) 1477 { 1478 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 1479 connector_status_connected : connector_status_disconnected; 1480 } 1481 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); 1482 1483 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 1484 bool force, bool disabled, bool rxsense) 1485 { 1486 u8 old_mask = hdmi->phy_mask; 1487 1488 if (force || disabled || !rxsense) 1489 hdmi->phy_mask |= HDMI_PHY_RX_SENSE; 1490 else 1491 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; 1492 1493 if (old_mask != hdmi->phy_mask) 1494 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1495 } 1496 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd); 1497 1498 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) 1499 { 1500 /* 1501 * Configure the PHY RX SENSE and HPD interrupts polarities and clear 1502 * any pending interrupt. 1503 */ 1504 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); 1505 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1506 HDMI_IH_PHY_STAT0); 1507 1508 /* Enable cable hot plug irq. */ 1509 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1510 1511 /* Clear and unmute interrupts. */ 1512 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1513 HDMI_IH_PHY_STAT0); 1514 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 1515 HDMI_IH_MUTE_PHY_STAT0); 1516 } 1517 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd); 1518 1519 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 1520 .init = dw_hdmi_phy_init, 1521 .disable = dw_hdmi_phy_disable, 1522 .read_hpd = dw_hdmi_phy_read_hpd, 1523 .update_hpd = dw_hdmi_phy_update_hpd, 1524 .setup_hpd = dw_hdmi_phy_setup_hpd, 1525 }; 1526 1527 /* ----------------------------------------------------------------------------- 1528 * HDMI TX Setup 1529 */ 1530 1531 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) 1532 { 1533 u8 de; 1534 1535 if (hdmi->hdmi_data.video_mode.mdataenablepolarity) 1536 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1537 else 1538 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; 1539 1540 /* disable rx detect */ 1541 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, 1542 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 1543 1544 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); 1545 1546 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, 1547 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); 1548 } 1549 1550 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1551 { 1552 struct hdmi_avi_infoframe frame; 1553 u8 val; 1554 1555 /* Initialise info frame from DRM mode */ 1556 drm_hdmi_avi_infoframe_from_display_mode(&frame, 1557 &hdmi->connector, mode); 1558 1559 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1560 frame.colorspace = HDMI_COLORSPACE_YUV444; 1561 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1562 frame.colorspace = HDMI_COLORSPACE_YUV422; 1563 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1564 frame.colorspace = HDMI_COLORSPACE_YUV420; 1565 else 1566 frame.colorspace = HDMI_COLORSPACE_RGB; 1567 1568 /* Set up colorimetry */ 1569 switch (hdmi->hdmi_data.enc_out_encoding) { 1570 case V4L2_YCBCR_ENC_601: 1571 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1572 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1573 else 1574 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1575 frame.extended_colorimetry = 1576 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1577 break; 1578 case V4L2_YCBCR_ENC_709: 1579 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1580 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1581 else 1582 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1583 frame.extended_colorimetry = 1584 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1585 break; 1586 default: /* Carries no data */ 1587 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1588 frame.extended_colorimetry = 1589 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1590 break; 1591 } 1592 1593 frame.scan_mode = HDMI_SCAN_MODE_NONE; 1594 1595 /* 1596 * The Designware IP uses a different byte format from standard 1597 * AVI info frames, though generally the bits are in the correct 1598 * bytes. 1599 */ 1600 1601 /* 1602 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, 1603 * scan info in bits 4,5 rather than 0,1 and active aspect present in 1604 * bit 6 rather than 4. 1605 */ 1606 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); 1607 if (frame.active_aspect & 15) 1608 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1609 if (frame.top_bar || frame.bottom_bar) 1610 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1611 if (frame.left_bar || frame.right_bar) 1612 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1613 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1614 1615 /* AVI data byte 2 differences: none */ 1616 val = ((frame.colorimetry & 0x3) << 6) | 1617 ((frame.picture_aspect & 0x3) << 4) | 1618 (frame.active_aspect & 0xf); 1619 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1620 1621 /* AVI data byte 3 differences: none */ 1622 val = ((frame.extended_colorimetry & 0x7) << 4) | 1623 ((frame.quantization_range & 0x3) << 2) | 1624 (frame.nups & 0x3); 1625 if (frame.itc) 1626 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1627 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1628 1629 /* AVI data byte 4 differences: none */ 1630 val = frame.video_code & 0x7f; 1631 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1632 1633 /* AVI Data Byte 5- set up input and output pixel repetition */ 1634 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1635 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1636 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1637 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1638 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1639 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1640 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1641 1642 /* 1643 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1644 * ycc range in bits 2,3 rather than 6,7 1645 */ 1646 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1647 (frame.content_type & 0x3); 1648 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1649 1650 /* AVI Data Bytes 6-13 */ 1651 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1652 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1653 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1654 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1655 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1656 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1657 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1658 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1659 } 1660 1661 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1662 struct drm_display_mode *mode) 1663 { 1664 struct hdmi_vendor_infoframe frame; 1665 u8 buffer[10]; 1666 ssize_t err; 1667 1668 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, 1669 &hdmi->connector, 1670 mode); 1671 if (err < 0) 1672 /* 1673 * Going into that statement does not means vendor infoframe 1674 * fails. It just informed us that vendor infoframe is not 1675 * needed for the selected mode. Only 4k or stereoscopic 3D 1676 * mode requires vendor infoframe. So just simply return. 1677 */ 1678 return; 1679 1680 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1681 if (err < 0) { 1682 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1683 err); 1684 return; 1685 } 1686 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1687 HDMI_FC_DATAUTO0_VSD_MASK); 1688 1689 /* Set the length of HDMI vendor specific InfoFrame payload */ 1690 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1691 1692 /* Set 24bit IEEE Registration Identifier */ 1693 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1694 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1695 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1696 1697 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1698 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1699 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1700 1701 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1702 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1703 1704 /* Packet frame interpolation */ 1705 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1706 1707 /* Auto packets per frame and line spacing */ 1708 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1709 1710 /* Configures the Frame Composer On RDRB mode */ 1711 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1712 HDMI_FC_DATAUTO0_VSD_MASK); 1713 } 1714 1715 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1716 const struct drm_display_mode *mode) 1717 { 1718 u8 inv_val, bytes; 1719 struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi; 1720 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1721 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1722 unsigned int vdisplay, hdisplay; 1723 1724 vmode->mtmdsclock = vmode->mpixelclock = mode->clock * 1000; 1725 1726 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); 1727 1728 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1729 vmode->mtmdsclock /= 2; 1730 1731 /* Set up HDMI_FC_INVIDCONF */ 1732 inv_val = (hdmi->hdmi_data.hdcp_enable || 1733 (dw_hdmi_support_scdc(hdmi) && 1734 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 1735 hdmi_info->scdc.scrambling.low_rates)) ? 1736 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1737 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1738 1739 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1740 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1741 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1742 1743 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1744 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1745 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1746 1747 inv_val |= (vmode->mdataenablepolarity ? 1748 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1749 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1750 1751 if (hdmi->vic == 39) 1752 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1753 else 1754 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1755 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1756 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1757 1758 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1759 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1760 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1761 1762 inv_val |= hdmi->sink_is_hdmi ? 1763 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1764 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1765 1766 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1767 1768 hdisplay = mode->hdisplay; 1769 hblank = mode->htotal - mode->hdisplay; 1770 h_de_hs = mode->hsync_start - mode->hdisplay; 1771 hsync_len = mode->hsync_end - mode->hsync_start; 1772 1773 /* 1774 * When we're setting a YCbCr420 mode, we need 1775 * to adjust the horizontal timing to suit. 1776 */ 1777 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1778 hdisplay /= 2; 1779 hblank /= 2; 1780 h_de_hs /= 2; 1781 hsync_len /= 2; 1782 } 1783 1784 vdisplay = mode->vdisplay; 1785 vblank = mode->vtotal - mode->vdisplay; 1786 v_de_vs = mode->vsync_start - mode->vdisplay; 1787 vsync_len = mode->vsync_end - mode->vsync_start; 1788 1789 /* 1790 * When we're setting an interlaced mode, we need 1791 * to adjust the vertical timing to suit. 1792 */ 1793 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1794 vdisplay /= 2; 1795 vblank /= 2; 1796 v_de_vs /= 2; 1797 vsync_len /= 2; 1798 } 1799 1800 /* Scrambling Control */ 1801 if (dw_hdmi_support_scdc(hdmi)) { 1802 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 1803 hdmi_info->scdc.scrambling.low_rates) { 1804 /* 1805 * HDMI2.0 Specifies the following procedure: 1806 * After the Source Device has determined that 1807 * SCDC_Present is set (=1), the Source Device should 1808 * write the accurate Version of the Source Device 1809 * to the Source Version field in the SCDCS. 1810 * Source Devices compliant shall set the 1811 * Source Version = 1. 1812 */ 1813 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, 1814 &bytes); 1815 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, 1816 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); 1817 1818 /* Enabled Scrambling in the Sink */ 1819 drm_scdc_set_scrambling(hdmi->ddc, 1); 1820 1821 /* 1822 * To activate the scrambler feature, you must ensure 1823 * that the quasi-static configuration bit 1824 * fc_invidconf.HDCP_keepout is set at configuration 1825 * time, before the required mc_swrstzreq.tmdsswrst_req 1826 * reset request is issued. 1827 */ 1828 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 1829 HDMI_MC_SWRSTZ); 1830 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 1831 } else { 1832 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 1833 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 1834 HDMI_MC_SWRSTZ); 1835 drm_scdc_set_scrambling(hdmi->ddc, 0); 1836 } 1837 } 1838 1839 /* Set up horizontal active pixel width */ 1840 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 1841 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 1842 1843 /* Set up vertical active lines */ 1844 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1845 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1846 1847 /* Set up horizontal blanking pixel region width */ 1848 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 1849 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 1850 1851 /* Set up vertical blanking pixel region width */ 1852 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 1853 1854 /* Set up HSYNC active edge delay width (in pixel clks) */ 1855 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 1856 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 1857 1858 /* Set up VSYNC active edge delay (in lines) */ 1859 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 1860 1861 /* Set up HSYNC active pulse width (in pixel clks) */ 1862 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 1863 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 1864 1865 /* Set up VSYNC active edge delay (in lines) */ 1866 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 1867 } 1868 1869 /* HDMI Initialization Step B.4 */ 1870 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 1871 { 1872 /* control period minimum duration */ 1873 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 1874 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 1875 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 1876 1877 /* Set to fill TMDS data channels */ 1878 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 1879 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 1880 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 1881 1882 /* Enable pixel clock and tmds data path */ 1883 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE | 1884 HDMI_MC_CLKDIS_CSCCLK_DISABLE | 1885 HDMI_MC_CLKDIS_AUDCLK_DISABLE | 1886 HDMI_MC_CLKDIS_PREPCLK_DISABLE | 1887 HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1888 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 1889 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1890 1891 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1892 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1893 1894 /* Enable csc path */ 1895 if (is_color_space_conversion(hdmi)) { 1896 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 1897 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1898 } 1899 1900 /* Enable color space conversion if needed */ 1901 if (is_color_space_conversion(hdmi)) 1902 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 1903 HDMI_MC_FLOWCTRL); 1904 else 1905 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 1906 HDMI_MC_FLOWCTRL); 1907 } 1908 1909 /* Workaround to clear the overflow condition */ 1910 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 1911 { 1912 unsigned int count; 1913 unsigned int i; 1914 u8 val; 1915 1916 /* 1917 * Under some circumstances the Frame Composer arithmetic unit can miss 1918 * an FC register write due to being busy processing the previous one. 1919 * The issue can be worked around by issuing a TMDS software reset and 1920 * then write one of the FC registers several times. 1921 * 1922 * The number of iterations matters and depends on the HDMI TX revision 1923 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL 1924 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified 1925 * as needing the workaround, with 4 iterations for v1.30a and 1 1926 * iteration for others. 1927 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing 1928 * the workaround with a single iteration. 1929 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have 1930 * been identified as needing the workaround with a single iteration. 1931 */ 1932 1933 switch (hdmi->version) { 1934 case 0x130a: 1935 count = 4; 1936 break; 1937 case 0x131a: 1938 case 0x132a: 1939 case 0x200a: 1940 case 0x201a: 1941 case 0x211a: 1942 case 0x212a: 1943 count = 1; 1944 break; 1945 default: 1946 return; 1947 } 1948 1949 /* TMDS software reset */ 1950 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 1951 1952 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 1953 for (i = 0; i < count; i++) 1954 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 1955 } 1956 1957 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 1958 { 1959 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 1960 HDMI_IH_MUTE_FC_STAT2); 1961 } 1962 1963 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1964 { 1965 int ret; 1966 1967 hdmi_disable_overflow_interrupts(hdmi); 1968 1969 hdmi->vic = drm_match_cea_mode(mode); 1970 1971 if (!hdmi->vic) { 1972 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); 1973 } else { 1974 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); 1975 } 1976 1977 if ((hdmi->vic == 6) || (hdmi->vic == 7) || 1978 (hdmi->vic == 21) || (hdmi->vic == 22) || 1979 (hdmi->vic == 2) || (hdmi->vic == 3) || 1980 (hdmi->vic == 17) || (hdmi->vic == 18)) 1981 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 1982 else 1983 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 1984 1985 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 1986 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 1987 1988 /* TOFIX: Get input format from plat data or fallback to RGB888 */ 1989 if (hdmi->plat_data->input_bus_format) 1990 hdmi->hdmi_data.enc_in_bus_format = 1991 hdmi->plat_data->input_bus_format; 1992 else 1993 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1994 1995 /* TOFIX: Get input encoding from plat data or fallback to none */ 1996 if (hdmi->plat_data->input_bus_encoding) 1997 hdmi->hdmi_data.enc_in_encoding = 1998 hdmi->plat_data->input_bus_encoding; 1999 else 2000 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 2001 2002 /* TOFIX: Default to RGB888 output format */ 2003 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2004 2005 hdmi->hdmi_data.pix_repet_factor = 0; 2006 hdmi->hdmi_data.hdcp_enable = 0; 2007 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 2008 2009 /* HDMI Initialization Step B.1 */ 2010 hdmi_av_composer(hdmi, mode); 2011 2012 /* HDMI Initializateion Step B.2 */ 2013 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode); 2014 if (ret) 2015 return ret; 2016 hdmi->phy.enabled = true; 2017 2018 /* HDMI Initialization Step B.3 */ 2019 dw_hdmi_enable_video_path(hdmi); 2020 2021 if (hdmi->sink_has_audio) { 2022 dev_dbg(hdmi->dev, "sink has audio support\n"); 2023 2024 /* HDMI Initialization Step E - Configure audio */ 2025 hdmi_clk_regenerator_update_pixel_clock(hdmi); 2026 hdmi_enable_audio_clk(hdmi, true); 2027 } 2028 2029 /* not for DVI mode */ 2030 if (hdmi->sink_is_hdmi) { 2031 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); 2032 2033 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 2034 hdmi_config_AVI(hdmi, mode); 2035 hdmi_config_vendor_specific_infoframe(hdmi, mode); 2036 } else { 2037 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); 2038 } 2039 2040 hdmi_video_packetize(hdmi); 2041 hdmi_video_csc(hdmi); 2042 hdmi_video_sample(hdmi); 2043 hdmi_tx_hdcp_config(hdmi); 2044 2045 dw_hdmi_clear_overflow(hdmi); 2046 2047 return 0; 2048 } 2049 2050 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) 2051 { 2052 u8 ih_mute; 2053 2054 /* 2055 * Boot up defaults are: 2056 * HDMI_IH_MUTE = 0x03 (disabled) 2057 * HDMI_IH_MUTE_* = 0x00 (enabled) 2058 * 2059 * Disable top level interrupt bits in HDMI block 2060 */ 2061 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | 2062 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2063 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; 2064 2065 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2066 2067 /* by default mask all interrupts */ 2068 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); 2069 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 2070 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 2071 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 2072 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); 2073 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); 2074 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); 2075 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); 2076 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); 2077 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); 2078 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); 2079 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); 2080 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); 2081 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); 2082 2083 /* Disable interrupts in the IH_MUTE_* registers */ 2084 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2085 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2086 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2087 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2088 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); 2089 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2090 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2091 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2092 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2093 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2094 2095 /* Enable top level interrupt bits in HDMI block */ 2096 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2097 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); 2098 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2099 } 2100 2101 static void dw_hdmi_poweron(struct dw_hdmi *hdmi) 2102 { 2103 hdmi->bridge_is_on = true; 2104 dw_hdmi_setup(hdmi, &hdmi->previous_mode); 2105 } 2106 2107 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) 2108 { 2109 if (hdmi->phy.enabled) { 2110 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 2111 hdmi->phy.enabled = false; 2112 } 2113 2114 hdmi->bridge_is_on = false; 2115 } 2116 2117 static void dw_hdmi_update_power(struct dw_hdmi *hdmi) 2118 { 2119 int force = hdmi->force; 2120 2121 if (hdmi->disabled) { 2122 force = DRM_FORCE_OFF; 2123 } else if (force == DRM_FORCE_UNSPECIFIED) { 2124 if (hdmi->rxsense) 2125 force = DRM_FORCE_ON; 2126 else 2127 force = DRM_FORCE_OFF; 2128 } 2129 2130 if (force == DRM_FORCE_OFF) { 2131 if (hdmi->bridge_is_on) 2132 dw_hdmi_poweroff(hdmi); 2133 } else { 2134 if (!hdmi->bridge_is_on) 2135 dw_hdmi_poweron(hdmi); 2136 } 2137 } 2138 2139 /* 2140 * Adjust the detection of RXSENSE according to whether we have a forced 2141 * connection mode enabled, or whether we have been disabled. There is 2142 * no point processing RXSENSE interrupts if we have a forced connection 2143 * state, or DRM has us disabled. 2144 * 2145 * We also disable rxsense interrupts when we think we're disconnected 2146 * to avoid floating TDMS signals giving false rxsense interrupts. 2147 * 2148 * Note: we still need to listen for HPD interrupts even when DRM has us 2149 * disabled so that we can detect a connect event. 2150 */ 2151 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) 2152 { 2153 if (hdmi->phy.ops->update_hpd) 2154 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, 2155 hdmi->force, hdmi->disabled, 2156 hdmi->rxsense); 2157 } 2158 2159 static enum drm_connector_status 2160 dw_hdmi_connector_detect(struct drm_connector *connector, bool force) 2161 { 2162 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2163 connector); 2164 2165 mutex_lock(&hdmi->mutex); 2166 hdmi->force = DRM_FORCE_UNSPECIFIED; 2167 dw_hdmi_update_power(hdmi); 2168 dw_hdmi_update_phy_mask(hdmi); 2169 mutex_unlock(&hdmi->mutex); 2170 2171 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 2172 } 2173 2174 static int dw_hdmi_connector_get_modes(struct drm_connector *connector) 2175 { 2176 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2177 connector); 2178 struct edid *edid; 2179 int ret = 0; 2180 2181 if (!hdmi->ddc) 2182 return 0; 2183 2184 edid = drm_get_edid(connector, hdmi->ddc); 2185 if (edid) { 2186 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", 2187 edid->width_cm, edid->height_cm); 2188 2189 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); 2190 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2191 drm_connector_update_edid_property(connector, edid); 2192 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); 2193 ret = drm_add_edid_modes(connector, edid); 2194 kfree(edid); 2195 } else { 2196 dev_dbg(hdmi->dev, "failed to get edid\n"); 2197 } 2198 2199 return ret; 2200 } 2201 2202 static void dw_hdmi_connector_force(struct drm_connector *connector) 2203 { 2204 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2205 connector); 2206 2207 mutex_lock(&hdmi->mutex); 2208 hdmi->force = connector->force; 2209 dw_hdmi_update_power(hdmi); 2210 dw_hdmi_update_phy_mask(hdmi); 2211 mutex_unlock(&hdmi->mutex); 2212 } 2213 2214 static const struct drm_connector_funcs dw_hdmi_connector_funcs = { 2215 .fill_modes = drm_helper_probe_single_connector_modes, 2216 .detect = dw_hdmi_connector_detect, 2217 .destroy = drm_connector_cleanup, 2218 .force = dw_hdmi_connector_force, 2219 .reset = drm_atomic_helper_connector_reset, 2220 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2221 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2222 }; 2223 2224 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { 2225 .get_modes = dw_hdmi_connector_get_modes, 2226 }; 2227 2228 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge) 2229 { 2230 struct dw_hdmi *hdmi = bridge->driver_private; 2231 struct drm_encoder *encoder = bridge->encoder; 2232 struct drm_connector *connector = &hdmi->connector; 2233 struct cec_connector_info conn_info; 2234 struct cec_notifier *notifier; 2235 2236 connector->interlace_allowed = 1; 2237 connector->polled = DRM_CONNECTOR_POLL_HPD; 2238 2239 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); 2240 2241 drm_connector_init_with_ddc(bridge->dev, connector, 2242 &dw_hdmi_connector_funcs, 2243 DRM_MODE_CONNECTOR_HDMIA, 2244 hdmi->ddc); 2245 2246 drm_connector_attach_encoder(connector, encoder); 2247 2248 cec_fill_conn_info_from_drm(&conn_info, connector); 2249 2250 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info); 2251 if (!notifier) 2252 return -ENOMEM; 2253 2254 mutex_lock(&hdmi->cec_notifier_mutex); 2255 hdmi->cec_notifier = notifier; 2256 mutex_unlock(&hdmi->cec_notifier_mutex); 2257 2258 return 0; 2259 } 2260 2261 static void dw_hdmi_bridge_detach(struct drm_bridge *bridge) 2262 { 2263 struct dw_hdmi *hdmi = bridge->driver_private; 2264 2265 mutex_lock(&hdmi->cec_notifier_mutex); 2266 cec_notifier_conn_unregister(hdmi->cec_notifier); 2267 hdmi->cec_notifier = NULL; 2268 mutex_unlock(&hdmi->cec_notifier_mutex); 2269 } 2270 2271 static enum drm_mode_status 2272 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 2273 const struct drm_display_mode *mode) 2274 { 2275 struct dw_hdmi *hdmi = bridge->driver_private; 2276 struct drm_connector *connector = &hdmi->connector; 2277 enum drm_mode_status mode_status = MODE_OK; 2278 2279 /* We don't support double-clocked modes */ 2280 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2281 return MODE_BAD; 2282 2283 if (hdmi->plat_data->mode_valid) 2284 mode_status = hdmi->plat_data->mode_valid(connector, mode); 2285 2286 return mode_status; 2287 } 2288 2289 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, 2290 const struct drm_display_mode *orig_mode, 2291 const struct drm_display_mode *mode) 2292 { 2293 struct dw_hdmi *hdmi = bridge->driver_private; 2294 2295 mutex_lock(&hdmi->mutex); 2296 2297 /* Store the display mode for plugin/DKMS poweron events */ 2298 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 2299 2300 mutex_unlock(&hdmi->mutex); 2301 } 2302 2303 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge) 2304 { 2305 struct dw_hdmi *hdmi = bridge->driver_private; 2306 2307 mutex_lock(&hdmi->mutex); 2308 hdmi->disabled = true; 2309 dw_hdmi_update_power(hdmi); 2310 dw_hdmi_update_phy_mask(hdmi); 2311 mutex_unlock(&hdmi->mutex); 2312 } 2313 2314 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge) 2315 { 2316 struct dw_hdmi *hdmi = bridge->driver_private; 2317 2318 mutex_lock(&hdmi->mutex); 2319 hdmi->disabled = false; 2320 dw_hdmi_update_power(hdmi); 2321 dw_hdmi_update_phy_mask(hdmi); 2322 mutex_unlock(&hdmi->mutex); 2323 } 2324 2325 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { 2326 .attach = dw_hdmi_bridge_attach, 2327 .detach = dw_hdmi_bridge_detach, 2328 .enable = dw_hdmi_bridge_enable, 2329 .disable = dw_hdmi_bridge_disable, 2330 .mode_set = dw_hdmi_bridge_mode_set, 2331 .mode_valid = dw_hdmi_bridge_mode_valid, 2332 }; 2333 2334 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) 2335 { 2336 struct dw_hdmi_i2c *i2c = hdmi->i2c; 2337 unsigned int stat; 2338 2339 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 2340 if (!stat) 2341 return IRQ_NONE; 2342 2343 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0); 2344 2345 i2c->stat = stat; 2346 2347 complete(&i2c->cmp); 2348 2349 return IRQ_HANDLED; 2350 } 2351 2352 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) 2353 { 2354 struct dw_hdmi *hdmi = dev_id; 2355 u8 intr_stat; 2356 irqreturn_t ret = IRQ_NONE; 2357 2358 if (hdmi->i2c) 2359 ret = dw_hdmi_i2c_irq(hdmi); 2360 2361 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2362 if (intr_stat) { 2363 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2364 return IRQ_WAKE_THREAD; 2365 } 2366 2367 return ret; 2368 } 2369 2370 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) 2371 { 2372 mutex_lock(&hdmi->mutex); 2373 2374 if (!hdmi->force) { 2375 /* 2376 * If the RX sense status indicates we're disconnected, 2377 * clear the software rxsense status. 2378 */ 2379 if (!rx_sense) 2380 hdmi->rxsense = false; 2381 2382 /* 2383 * Only set the software rxsense status when both 2384 * rxsense and hpd indicates we're connected. 2385 * This avoids what seems to be bad behaviour in 2386 * at least iMX6S versions of the phy. 2387 */ 2388 if (hpd) 2389 hdmi->rxsense = true; 2390 2391 dw_hdmi_update_power(hdmi); 2392 dw_hdmi_update_phy_mask(hdmi); 2393 } 2394 mutex_unlock(&hdmi->mutex); 2395 } 2396 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); 2397 2398 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) 2399 { 2400 struct dw_hdmi *hdmi = dev_id; 2401 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; 2402 2403 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2404 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); 2405 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); 2406 2407 phy_pol_mask = 0; 2408 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) 2409 phy_pol_mask |= HDMI_PHY_HPD; 2410 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) 2411 phy_pol_mask |= HDMI_PHY_RX_SENSE0; 2412 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) 2413 phy_pol_mask |= HDMI_PHY_RX_SENSE1; 2414 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) 2415 phy_pol_mask |= HDMI_PHY_RX_SENSE2; 2416 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) 2417 phy_pol_mask |= HDMI_PHY_RX_SENSE3; 2418 2419 if (phy_pol_mask) 2420 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); 2421 2422 /* 2423 * RX sense tells us whether the TDMS transmitters are detecting 2424 * load - in other words, there's something listening on the 2425 * other end of the link. Use this to decide whether we should 2426 * power on the phy as HPD may be toggled by the sink to merely 2427 * ask the source to re-read the EDID. 2428 */ 2429 if (intr_stat & 2430 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { 2431 dw_hdmi_setup_rx_sense(hdmi, 2432 phy_stat & HDMI_PHY_HPD, 2433 phy_stat & HDMI_PHY_RX_SENSE); 2434 2435 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) { 2436 mutex_lock(&hdmi->cec_notifier_mutex); 2437 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); 2438 mutex_unlock(&hdmi->cec_notifier_mutex); 2439 } 2440 } 2441 2442 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { 2443 dev_dbg(hdmi->dev, "EVENT=%s\n", 2444 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout"); 2445 if (hdmi->bridge.dev) 2446 drm_helper_hpd_irq_event(hdmi->bridge.dev); 2447 } 2448 2449 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); 2450 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 2451 HDMI_IH_MUTE_PHY_STAT0); 2452 2453 return IRQ_HANDLED; 2454 } 2455 2456 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 2457 { 2458 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 2459 .name = "DWC HDMI TX PHY", 2460 .gen = 1, 2461 }, { 2462 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 2463 .name = "DWC MHL PHY + HEAC PHY", 2464 .gen = 2, 2465 .has_svsret = true, 2466 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2467 }, { 2468 .type = DW_HDMI_PHY_DWC_MHL_PHY, 2469 .name = "DWC MHL PHY", 2470 .gen = 2, 2471 .has_svsret = true, 2472 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2473 }, { 2474 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 2475 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 2476 .gen = 2, 2477 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2478 }, { 2479 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 2480 .name = "DWC HDMI 3D TX PHY", 2481 .gen = 2, 2482 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2483 }, { 2484 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 2485 .name = "DWC HDMI 2.0 TX PHY", 2486 .gen = 2, 2487 .has_svsret = true, 2488 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2489 }, { 2490 .type = DW_HDMI_PHY_VENDOR_PHY, 2491 .name = "Vendor PHY", 2492 } 2493 }; 2494 2495 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 2496 { 2497 unsigned int i; 2498 u8 phy_type; 2499 2500 phy_type = hdmi->plat_data->phy_force_vendor ? 2501 DW_HDMI_PHY_VENDOR_PHY : 2502 hdmi_readb(hdmi, HDMI_CONFIG2_ID); 2503 2504 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { 2505 /* Vendor PHYs require support from the glue layer. */ 2506 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 2507 dev_err(hdmi->dev, 2508 "Vendor HDMI PHY not supported by glue layer\n"); 2509 return -ENODEV; 2510 } 2511 2512 hdmi->phy.ops = hdmi->plat_data->phy_ops; 2513 hdmi->phy.data = hdmi->plat_data->phy_data; 2514 hdmi->phy.name = hdmi->plat_data->phy_name; 2515 return 0; 2516 } 2517 2518 /* Synopsys PHYs are handled internally. */ 2519 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 2520 if (dw_hdmi_phys[i].type == phy_type) { 2521 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 2522 hdmi->phy.name = dw_hdmi_phys[i].name; 2523 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 2524 2525 if (!dw_hdmi_phys[i].configure && 2526 !hdmi->plat_data->configure_phy) { 2527 dev_err(hdmi->dev, "%s requires platform support\n", 2528 hdmi->phy.name); 2529 return -ENODEV; 2530 } 2531 2532 return 0; 2533 } 2534 } 2535 2536 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); 2537 return -ENODEV; 2538 } 2539 2540 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi) 2541 { 2542 mutex_lock(&hdmi->mutex); 2543 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE; 2544 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2545 mutex_unlock(&hdmi->mutex); 2546 } 2547 2548 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi) 2549 { 2550 mutex_lock(&hdmi->mutex); 2551 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE; 2552 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2553 mutex_unlock(&hdmi->mutex); 2554 } 2555 2556 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = { 2557 .write = hdmi_writeb, 2558 .read = hdmi_readb, 2559 .enable = dw_hdmi_cec_enable, 2560 .disable = dw_hdmi_cec_disable, 2561 }; 2562 2563 static const struct regmap_config hdmi_regmap_8bit_config = { 2564 .reg_bits = 32, 2565 .val_bits = 8, 2566 .reg_stride = 1, 2567 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, 2568 }; 2569 2570 static const struct regmap_config hdmi_regmap_32bit_config = { 2571 .reg_bits = 32, 2572 .val_bits = 32, 2573 .reg_stride = 4, 2574 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, 2575 }; 2576 2577 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi) 2578 { 2579 initialize_hdmi_ih_mutes(hdmi); 2580 2581 /* 2582 * Reset HDMI DDC I2C master controller and mute I2CM interrupts. 2583 * Even if we are using a separate i2c adapter doing this doesn't 2584 * hurt. 2585 */ 2586 dw_hdmi_i2c_init(hdmi); 2587 2588 if (hdmi->phy.ops->setup_hpd) 2589 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 2590 } 2591 2592 static struct dw_hdmi * 2593 __dw_hdmi_probe(struct platform_device *pdev, 2594 const struct dw_hdmi_plat_data *plat_data) 2595 { 2596 struct device *dev = &pdev->dev; 2597 struct device_node *np = dev->of_node; 2598 struct platform_device_info pdevinfo; 2599 struct device_node *ddc_node; 2600 struct dw_hdmi_cec_data cec; 2601 struct dw_hdmi *hdmi; 2602 struct resource *iores = NULL; 2603 int irq; 2604 int ret; 2605 u32 val = 1; 2606 u8 prod_id0; 2607 u8 prod_id1; 2608 u8 config0; 2609 u8 config3; 2610 2611 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 2612 if (!hdmi) 2613 return ERR_PTR(-ENOMEM); 2614 2615 hdmi->plat_data = plat_data; 2616 hdmi->dev = dev; 2617 hdmi->sample_rate = 48000; 2618 hdmi->disabled = true; 2619 hdmi->rxsense = true; 2620 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); 2621 hdmi->mc_clkdis = 0x7f; 2622 2623 mutex_init(&hdmi->mutex); 2624 mutex_init(&hdmi->audio_mutex); 2625 mutex_init(&hdmi->cec_notifier_mutex); 2626 spin_lock_init(&hdmi->audio_lock); 2627 2628 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 2629 if (ddc_node) { 2630 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); 2631 of_node_put(ddc_node); 2632 if (!hdmi->ddc) { 2633 dev_dbg(hdmi->dev, "failed to read ddc node\n"); 2634 return ERR_PTR(-EPROBE_DEFER); 2635 } 2636 2637 } else { 2638 dev_dbg(hdmi->dev, "no ddc property found\n"); 2639 } 2640 2641 if (!plat_data->regm) { 2642 const struct regmap_config *reg_config; 2643 2644 of_property_read_u32(np, "reg-io-width", &val); 2645 switch (val) { 2646 case 4: 2647 reg_config = &hdmi_regmap_32bit_config; 2648 hdmi->reg_shift = 2; 2649 break; 2650 case 1: 2651 reg_config = &hdmi_regmap_8bit_config; 2652 break; 2653 default: 2654 dev_err(dev, "reg-io-width must be 1 or 4\n"); 2655 return ERR_PTR(-EINVAL); 2656 } 2657 2658 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2659 hdmi->regs = devm_ioremap_resource(dev, iores); 2660 if (IS_ERR(hdmi->regs)) { 2661 ret = PTR_ERR(hdmi->regs); 2662 goto err_res; 2663 } 2664 2665 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); 2666 if (IS_ERR(hdmi->regm)) { 2667 dev_err(dev, "Failed to configure regmap\n"); 2668 ret = PTR_ERR(hdmi->regm); 2669 goto err_res; 2670 } 2671 } else { 2672 hdmi->regm = plat_data->regm; 2673 } 2674 2675 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); 2676 if (IS_ERR(hdmi->isfr_clk)) { 2677 ret = PTR_ERR(hdmi->isfr_clk); 2678 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); 2679 goto err_res; 2680 } 2681 2682 ret = clk_prepare_enable(hdmi->isfr_clk); 2683 if (ret) { 2684 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret); 2685 goto err_res; 2686 } 2687 2688 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); 2689 if (IS_ERR(hdmi->iahb_clk)) { 2690 ret = PTR_ERR(hdmi->iahb_clk); 2691 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); 2692 goto err_isfr; 2693 } 2694 2695 ret = clk_prepare_enable(hdmi->iahb_clk); 2696 if (ret) { 2697 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret); 2698 goto err_isfr; 2699 } 2700 2701 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec"); 2702 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) { 2703 hdmi->cec_clk = NULL; 2704 } else if (IS_ERR(hdmi->cec_clk)) { 2705 ret = PTR_ERR(hdmi->cec_clk); 2706 if (ret != -EPROBE_DEFER) 2707 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n", 2708 ret); 2709 2710 hdmi->cec_clk = NULL; 2711 goto err_iahb; 2712 } else { 2713 ret = clk_prepare_enable(hdmi->cec_clk); 2714 if (ret) { 2715 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n", 2716 ret); 2717 goto err_iahb; 2718 } 2719 } 2720 2721 /* Product and revision IDs */ 2722 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 2723 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 2724 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); 2725 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); 2726 2727 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || 2728 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { 2729 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", 2730 hdmi->version, prod_id0, prod_id1); 2731 ret = -ENODEV; 2732 goto err_iahb; 2733 } 2734 2735 ret = dw_hdmi_detect_phy(hdmi); 2736 if (ret < 0) 2737 goto err_iahb; 2738 2739 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", 2740 hdmi->version >> 12, hdmi->version & 0xfff, 2741 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", 2742 hdmi->phy.name); 2743 2744 dw_hdmi_init_hw(hdmi); 2745 2746 irq = platform_get_irq(pdev, 0); 2747 if (irq < 0) { 2748 ret = irq; 2749 goto err_iahb; 2750 } 2751 2752 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, 2753 dw_hdmi_irq, IRQF_SHARED, 2754 dev_name(dev), hdmi); 2755 if (ret) 2756 goto err_iahb; 2757 2758 /* 2759 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator 2760 * N and cts values before enabling phy 2761 */ 2762 hdmi_init_clk_regenerator(hdmi); 2763 2764 /* If DDC bus is not specified, try to register HDMI I2C bus */ 2765 if (!hdmi->ddc) { 2766 /* Look for (optional) stuff related to unwedging */ 2767 hdmi->pinctrl = devm_pinctrl_get(dev); 2768 if (!IS_ERR(hdmi->pinctrl)) { 2769 hdmi->unwedge_state = 2770 pinctrl_lookup_state(hdmi->pinctrl, "unwedge"); 2771 hdmi->default_state = 2772 pinctrl_lookup_state(hdmi->pinctrl, "default"); 2773 2774 if (IS_ERR(hdmi->default_state) || 2775 IS_ERR(hdmi->unwedge_state)) { 2776 if (!IS_ERR(hdmi->unwedge_state)) 2777 dev_warn(dev, 2778 "Unwedge requires default pinctrl\n"); 2779 hdmi->default_state = NULL; 2780 hdmi->unwedge_state = NULL; 2781 } 2782 } 2783 2784 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); 2785 if (IS_ERR(hdmi->ddc)) 2786 hdmi->ddc = NULL; 2787 } 2788 2789 hdmi->bridge.driver_private = hdmi; 2790 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; 2791 #ifdef CONFIG_OF 2792 hdmi->bridge.of_node = pdev->dev.of_node; 2793 #endif 2794 2795 memset(&pdevinfo, 0, sizeof(pdevinfo)); 2796 pdevinfo.parent = dev; 2797 pdevinfo.id = PLATFORM_DEVID_AUTO; 2798 2799 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); 2800 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 2801 2802 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { 2803 struct dw_hdmi_audio_data audio; 2804 2805 audio.phys = iores->start; 2806 audio.base = hdmi->regs; 2807 audio.irq = irq; 2808 audio.hdmi = hdmi; 2809 audio.eld = hdmi->connector.eld; 2810 hdmi->enable_audio = dw_hdmi_ahb_audio_enable; 2811 hdmi->disable_audio = dw_hdmi_ahb_audio_disable; 2812 2813 pdevinfo.name = "dw-hdmi-ahb-audio"; 2814 pdevinfo.data = &audio; 2815 pdevinfo.size_data = sizeof(audio); 2816 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2817 hdmi->audio = platform_device_register_full(&pdevinfo); 2818 } else if (config0 & HDMI_CONFIG0_I2S) { 2819 struct dw_hdmi_i2s_audio_data audio; 2820 2821 audio.hdmi = hdmi; 2822 audio.eld = hdmi->connector.eld; 2823 audio.write = hdmi_writeb; 2824 audio.read = hdmi_readb; 2825 hdmi->enable_audio = dw_hdmi_i2s_audio_enable; 2826 hdmi->disable_audio = dw_hdmi_i2s_audio_disable; 2827 2828 pdevinfo.name = "dw-hdmi-i2s-audio"; 2829 pdevinfo.data = &audio; 2830 pdevinfo.size_data = sizeof(audio); 2831 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2832 hdmi->audio = platform_device_register_full(&pdevinfo); 2833 } 2834 2835 if (config0 & HDMI_CONFIG0_CEC) { 2836 cec.hdmi = hdmi; 2837 cec.ops = &dw_hdmi_cec_ops; 2838 cec.irq = irq; 2839 2840 pdevinfo.name = "dw-hdmi-cec"; 2841 pdevinfo.data = &cec; 2842 pdevinfo.size_data = sizeof(cec); 2843 pdevinfo.dma_mask = 0; 2844 2845 hdmi->cec = platform_device_register_full(&pdevinfo); 2846 } 2847 2848 return hdmi; 2849 2850 err_iahb: 2851 if (hdmi->i2c) { 2852 i2c_del_adapter(&hdmi->i2c->adap); 2853 hdmi->ddc = NULL; 2854 } 2855 2856 clk_disable_unprepare(hdmi->iahb_clk); 2857 if (hdmi->cec_clk) 2858 clk_disable_unprepare(hdmi->cec_clk); 2859 err_isfr: 2860 clk_disable_unprepare(hdmi->isfr_clk); 2861 err_res: 2862 i2c_put_adapter(hdmi->ddc); 2863 2864 return ERR_PTR(ret); 2865 } 2866 2867 static void __dw_hdmi_remove(struct dw_hdmi *hdmi) 2868 { 2869 if (hdmi->audio && !IS_ERR(hdmi->audio)) 2870 platform_device_unregister(hdmi->audio); 2871 if (!IS_ERR(hdmi->cec)) 2872 platform_device_unregister(hdmi->cec); 2873 2874 /* Disable all interrupts */ 2875 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2876 2877 clk_disable_unprepare(hdmi->iahb_clk); 2878 clk_disable_unprepare(hdmi->isfr_clk); 2879 if (hdmi->cec_clk) 2880 clk_disable_unprepare(hdmi->cec_clk); 2881 2882 if (hdmi->i2c) 2883 i2c_del_adapter(&hdmi->i2c->adap); 2884 else 2885 i2c_put_adapter(hdmi->ddc); 2886 } 2887 2888 /* ----------------------------------------------------------------------------- 2889 * Probe/remove API, used from platforms based on the DRM bridge API. 2890 */ 2891 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, 2892 const struct dw_hdmi_plat_data *plat_data) 2893 { 2894 struct dw_hdmi *hdmi; 2895 2896 hdmi = __dw_hdmi_probe(pdev, plat_data); 2897 if (IS_ERR(hdmi)) 2898 return hdmi; 2899 2900 drm_bridge_add(&hdmi->bridge); 2901 2902 return hdmi; 2903 } 2904 EXPORT_SYMBOL_GPL(dw_hdmi_probe); 2905 2906 void dw_hdmi_remove(struct dw_hdmi *hdmi) 2907 { 2908 drm_bridge_remove(&hdmi->bridge); 2909 2910 __dw_hdmi_remove(hdmi); 2911 } 2912 EXPORT_SYMBOL_GPL(dw_hdmi_remove); 2913 2914 /* ----------------------------------------------------------------------------- 2915 * Bind/unbind API, used from platforms based on the component framework. 2916 */ 2917 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, 2918 struct drm_encoder *encoder, 2919 const struct dw_hdmi_plat_data *plat_data) 2920 { 2921 struct dw_hdmi *hdmi; 2922 int ret; 2923 2924 hdmi = __dw_hdmi_probe(pdev, plat_data); 2925 if (IS_ERR(hdmi)) 2926 return hdmi; 2927 2928 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL); 2929 if (ret) { 2930 dw_hdmi_remove(hdmi); 2931 DRM_ERROR("Failed to initialize bridge with drm\n"); 2932 return ERR_PTR(ret); 2933 } 2934 2935 return hdmi; 2936 } 2937 EXPORT_SYMBOL_GPL(dw_hdmi_bind); 2938 2939 void dw_hdmi_unbind(struct dw_hdmi *hdmi) 2940 { 2941 __dw_hdmi_remove(hdmi); 2942 } 2943 EXPORT_SYMBOL_GPL(dw_hdmi_unbind); 2944 2945 void dw_hdmi_resume(struct dw_hdmi *hdmi) 2946 { 2947 dw_hdmi_init_hw(hdmi); 2948 } 2949 EXPORT_SYMBOL_GPL(dw_hdmi_resume); 2950 2951 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 2952 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); 2953 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); 2954 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>"); 2955 MODULE_DESCRIPTION("DW HDMI transmitter driver"); 2956 MODULE_LICENSE("GPL"); 2957 MODULE_ALIAS("platform:dw-hdmi"); 2958