1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DesignWare High-Definition Multimedia Interface (HDMI) driver 4 * 5 * Copyright (C) 2013-2015 Mentor Graphics Inc. 6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 8 */ 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/hdmi.h> 13 #include <linux/irq.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of_device.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/regmap.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/spinlock.h> 21 22 #include <media/cec-notifier.h> 23 24 #include <uapi/linux/media-bus-format.h> 25 #include <uapi/linux/videodev2.h> 26 27 #include <drm/bridge/dw_hdmi.h> 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_encoder_slave.h> 31 #include <drm/drm_of.h> 32 #include <drm/drm_print.h> 33 #include <drm/drm_probe_helper.h> 34 #include <drm/drm_scdc_helper.h> 35 36 #include "dw-hdmi-audio.h" 37 #include "dw-hdmi-cec.h" 38 #include "dw-hdmi.h" 39 40 #define DDC_SEGMENT_ADDR 0x30 41 42 #define HDMI_EDID_LEN 512 43 44 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ 45 #define SCDC_MIN_SOURCE_VERSION 0x1 46 47 #define HDMI14_MAX_TMDSCLK 340000000 48 49 enum hdmi_datamap { 50 RGB444_8B = 0x01, 51 RGB444_10B = 0x03, 52 RGB444_12B = 0x05, 53 RGB444_16B = 0x07, 54 YCbCr444_8B = 0x09, 55 YCbCr444_10B = 0x0B, 56 YCbCr444_12B = 0x0D, 57 YCbCr444_16B = 0x0F, 58 YCbCr422_8B = 0x16, 59 YCbCr422_10B = 0x14, 60 YCbCr422_12B = 0x12, 61 }; 62 63 static const u16 csc_coeff_default[3][4] = { 64 { 0x2000, 0x0000, 0x0000, 0x0000 }, 65 { 0x0000, 0x2000, 0x0000, 0x0000 }, 66 { 0x0000, 0x0000, 0x2000, 0x0000 } 67 }; 68 69 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 70 { 0x2000, 0x6926, 0x74fd, 0x010e }, 71 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 72 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 73 }; 74 75 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 76 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 77 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 78 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 79 }; 80 81 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 82 { 0x2591, 0x1322, 0x074b, 0x0000 }, 83 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 84 { 0x6acd, 0x7534, 0x2000, 0x0200 } 85 }; 86 87 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 88 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 89 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 90 { 0x6756, 0x78ab, 0x2000, 0x0200 } 91 }; 92 93 struct hdmi_vmode { 94 bool mdataenablepolarity; 95 96 unsigned int mpixelclock; 97 unsigned int mpixelrepetitioninput; 98 unsigned int mpixelrepetitionoutput; 99 unsigned int mtmdsclock; 100 }; 101 102 struct hdmi_data_info { 103 unsigned int enc_in_bus_format; 104 unsigned int enc_out_bus_format; 105 unsigned int enc_in_encoding; 106 unsigned int enc_out_encoding; 107 unsigned int pix_repet_factor; 108 unsigned int hdcp_enable; 109 struct hdmi_vmode video_mode; 110 }; 111 112 struct dw_hdmi_i2c { 113 struct i2c_adapter adap; 114 115 struct mutex lock; /* used to serialize data transfers */ 116 struct completion cmp; 117 u8 stat; 118 119 u8 slave_reg; 120 bool is_regaddr; 121 bool is_segment; 122 }; 123 124 struct dw_hdmi_phy_data { 125 enum dw_hdmi_phy_type type; 126 const char *name; 127 unsigned int gen; 128 bool has_svsret; 129 int (*configure)(struct dw_hdmi *hdmi, 130 const struct dw_hdmi_plat_data *pdata, 131 unsigned long mpixelclock); 132 }; 133 134 struct dw_hdmi { 135 struct drm_connector connector; 136 struct drm_bridge bridge; 137 138 unsigned int version; 139 140 struct platform_device *audio; 141 struct platform_device *cec; 142 struct device *dev; 143 struct clk *isfr_clk; 144 struct clk *iahb_clk; 145 struct clk *cec_clk; 146 struct dw_hdmi_i2c *i2c; 147 148 struct hdmi_data_info hdmi_data; 149 const struct dw_hdmi_plat_data *plat_data; 150 151 int vic; 152 153 u8 edid[HDMI_EDID_LEN]; 154 155 struct { 156 const struct dw_hdmi_phy_ops *ops; 157 const char *name; 158 void *data; 159 bool enabled; 160 } phy; 161 162 struct drm_display_mode previous_mode; 163 164 struct i2c_adapter *ddc; 165 void __iomem *regs; 166 bool sink_is_hdmi; 167 bool sink_has_audio; 168 169 struct pinctrl *pinctrl; 170 struct pinctrl_state *default_state; 171 struct pinctrl_state *unwedge_state; 172 173 struct mutex mutex; /* for state below and previous_mode */ 174 enum drm_connector_force force; /* mutex-protected force state */ 175 bool disabled; /* DRM has disabled our bridge */ 176 bool bridge_is_on; /* indicates the bridge is on */ 177 bool rxsense; /* rxsense state */ 178 u8 phy_mask; /* desired phy int mask settings */ 179 u8 mc_clkdis; /* clock disable register */ 180 181 spinlock_t audio_lock; 182 struct mutex audio_mutex; 183 unsigned int sample_rate; 184 unsigned int audio_cts; 185 unsigned int audio_n; 186 bool audio_enable; 187 188 unsigned int reg_shift; 189 struct regmap *regm; 190 void (*enable_audio)(struct dw_hdmi *hdmi); 191 void (*disable_audio)(struct dw_hdmi *hdmi); 192 193 struct cec_notifier *cec_notifier; 194 }; 195 196 #define HDMI_IH_PHY_STAT0_RX_SENSE \ 197 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ 198 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) 199 200 #define HDMI_PHY_RX_SENSE \ 201 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ 202 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) 203 204 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 205 { 206 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); 207 } 208 209 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 210 { 211 unsigned int val = 0; 212 213 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); 214 215 return val; 216 } 217 218 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 219 { 220 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); 221 } 222 223 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 224 u8 shift, u8 mask) 225 { 226 hdmi_modb(hdmi, data << shift, mask, reg); 227 } 228 229 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 230 { 231 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, 232 HDMI_PHY_I2CM_INT_ADDR); 233 234 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | 235 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, 236 HDMI_PHY_I2CM_CTLINT_ADDR); 237 238 /* Software reset */ 239 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 240 241 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ 242 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); 243 244 /* Set done, not acknowledged and arbitration interrupt polarities */ 245 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 246 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 247 HDMI_I2CM_CTLINT); 248 249 /* Clear DONE and ERROR interrupts */ 250 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 251 HDMI_IH_I2CM_STAT0); 252 253 /* Mute DONE and ERROR interrupts */ 254 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 255 HDMI_IH_MUTE_I2CM_STAT0); 256 } 257 258 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi) 259 { 260 /* If no unwedge state then give up */ 261 if (!hdmi->unwedge_state) 262 return false; 263 264 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n"); 265 266 /* 267 * This is a huge hack to workaround a problem where the dw_hdmi i2c 268 * bus could sometimes get wedged. Once wedged there doesn't appear 269 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ) 270 * other than pulsing the SDA line. 271 * 272 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi) 273 * by: 274 * 1. Remux the pin as a GPIO output, driven low. 275 * 2. Wait a little while. 1 ms seems to work, but we'll do 10. 276 * 3. Immediately jump to remux the pin as dw_hdmi i2c again. 277 * 278 * At the moment of remuxing, the line will still be low due to its 279 * recent stint as an output, but then it will be pulled high by the 280 * (presumed) external pullup. dw_hdmi seems to see this as a rising 281 * edge and that seems to get it out of its jam. 282 * 283 * This wedging was only ever seen on one TV, and only on one of 284 * its HDMI ports. It happened when the TV was powered on while the 285 * device was plugged in. A scope trace shows the TV bringing both SDA 286 * and SCL low, then bringing them both back up at roughly the same 287 * time. Presumably this confuses dw_hdmi because it saw activity but 288 * no real STOP (maybe it thinks there's another master on the bus?). 289 * Giving it a clean rising edge of SDA while SCL is already high 290 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out 291 * of its stupor. 292 * 293 * Note that after coming back alive, transfers seem to immediately 294 * resume, so if we unwedge due to a timeout we should wait a little 295 * longer for our transfer to finish, since it might have just started 296 * now. 297 */ 298 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state); 299 msleep(10); 300 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state); 301 302 return true; 303 } 304 305 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi) 306 { 307 struct dw_hdmi_i2c *i2c = hdmi->i2c; 308 int stat; 309 310 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 311 if (!stat) { 312 /* If we can't unwedge, return timeout */ 313 if (!dw_hdmi_i2c_unwedge(hdmi)) 314 return -EAGAIN; 315 316 /* We tried to unwedge; give it another chance */ 317 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 318 if (!stat) 319 return -EAGAIN; 320 } 321 322 /* Check for error condition on the bus */ 323 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 324 return -EIO; 325 326 return 0; 327 } 328 329 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 330 unsigned char *buf, unsigned int length) 331 { 332 struct dw_hdmi_i2c *i2c = hdmi->i2c; 333 int ret; 334 335 if (!i2c->is_regaddr) { 336 dev_dbg(hdmi->dev, "set read register address to 0\n"); 337 i2c->slave_reg = 0x00; 338 i2c->is_regaddr = true; 339 } 340 341 while (length--) { 342 reinit_completion(&i2c->cmp); 343 344 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 345 if (i2c->is_segment) 346 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 347 HDMI_I2CM_OPERATION); 348 else 349 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 350 HDMI_I2CM_OPERATION); 351 352 ret = dw_hdmi_i2c_wait(hdmi); 353 if (ret) 354 return ret; 355 356 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 357 } 358 i2c->is_segment = false; 359 360 return 0; 361 } 362 363 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 364 unsigned char *buf, unsigned int length) 365 { 366 struct dw_hdmi_i2c *i2c = hdmi->i2c; 367 int ret; 368 369 if (!i2c->is_regaddr) { 370 /* Use the first write byte as register address */ 371 i2c->slave_reg = buf[0]; 372 length--; 373 buf++; 374 i2c->is_regaddr = true; 375 } 376 377 while (length--) { 378 reinit_completion(&i2c->cmp); 379 380 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 381 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 382 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 383 HDMI_I2CM_OPERATION); 384 385 ret = dw_hdmi_i2c_wait(hdmi); 386 if (ret) 387 return ret; 388 } 389 390 return 0; 391 } 392 393 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, 394 struct i2c_msg *msgs, int num) 395 { 396 struct dw_hdmi *hdmi = i2c_get_adapdata(adap); 397 struct dw_hdmi_i2c *i2c = hdmi->i2c; 398 u8 addr = msgs[0].addr; 399 int i, ret = 0; 400 401 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); 402 403 for (i = 0; i < num; i++) { 404 if (msgs[i].len == 0) { 405 dev_dbg(hdmi->dev, 406 "unsupported transfer %d/%d, no data\n", 407 i + 1, num); 408 return -EOPNOTSUPP; 409 } 410 } 411 412 mutex_lock(&i2c->lock); 413 414 /* Unmute DONE and ERROR interrupts */ 415 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 416 417 /* Set slave device address taken from the first I2C message */ 418 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 419 420 /* Set slave device register address on transfer */ 421 i2c->is_regaddr = false; 422 423 /* Set segment pointer for I2C extended read mode operation */ 424 i2c->is_segment = false; 425 426 for (i = 0; i < num; i++) { 427 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", 428 i + 1, num, msgs[i].len, msgs[i].flags); 429 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 430 i2c->is_segment = true; 431 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 432 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 433 } else { 434 if (msgs[i].flags & I2C_M_RD) 435 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 436 msgs[i].len); 437 else 438 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 439 msgs[i].len); 440 } 441 if (ret < 0) 442 break; 443 } 444 445 if (!ret) 446 ret = num; 447 448 /* Mute DONE and ERROR interrupts */ 449 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 450 HDMI_IH_MUTE_I2CM_STAT0); 451 452 mutex_unlock(&i2c->lock); 453 454 return ret; 455 } 456 457 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) 458 { 459 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 460 } 461 462 static const struct i2c_algorithm dw_hdmi_algorithm = { 463 .master_xfer = dw_hdmi_i2c_xfer, 464 .functionality = dw_hdmi_i2c_func, 465 }; 466 467 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) 468 { 469 struct i2c_adapter *adap; 470 struct dw_hdmi_i2c *i2c; 471 int ret; 472 473 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 474 if (!i2c) 475 return ERR_PTR(-ENOMEM); 476 477 mutex_init(&i2c->lock); 478 init_completion(&i2c->cmp); 479 480 adap = &i2c->adap; 481 adap->class = I2C_CLASS_DDC; 482 adap->owner = THIS_MODULE; 483 adap->dev.parent = hdmi->dev; 484 adap->algo = &dw_hdmi_algorithm; 485 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name)); 486 i2c_set_adapdata(adap, hdmi); 487 488 ret = i2c_add_adapter(adap); 489 if (ret) { 490 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 491 devm_kfree(hdmi->dev, i2c); 492 return ERR_PTR(ret); 493 } 494 495 hdmi->i2c = i2c; 496 497 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 498 499 return adap; 500 } 501 502 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 503 unsigned int n) 504 { 505 /* Must be set/cleared first */ 506 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 507 508 /* nshift factor = 0 */ 509 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 510 511 /* Use automatic CTS generation mode when CTS is not set */ 512 if (cts) 513 hdmi_writeb(hdmi, ((cts >> 16) & 514 HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 515 HDMI_AUD_CTS3_CTS_MANUAL, 516 HDMI_AUD_CTS3); 517 else 518 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3); 519 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 520 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 521 522 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 523 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 524 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 525 } 526 527 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) 528 { 529 unsigned int n = (128 * freq) / 1000; 530 unsigned int mult = 1; 531 532 while (freq > 48000) { 533 mult *= 2; 534 freq /= 2; 535 } 536 537 switch (freq) { 538 case 32000: 539 if (pixel_clk == 25175000) 540 n = 4576; 541 else if (pixel_clk == 27027000) 542 n = 4096; 543 else if (pixel_clk == 74176000 || pixel_clk == 148352000) 544 n = 11648; 545 else 546 n = 4096; 547 n *= mult; 548 break; 549 550 case 44100: 551 if (pixel_clk == 25175000) 552 n = 7007; 553 else if (pixel_clk == 74176000) 554 n = 17836; 555 else if (pixel_clk == 148352000) 556 n = 8918; 557 else 558 n = 6272; 559 n *= mult; 560 break; 561 562 case 48000: 563 if (pixel_clk == 25175000) 564 n = 6864; 565 else if (pixel_clk == 27027000) 566 n = 6144; 567 else if (pixel_clk == 74176000) 568 n = 11648; 569 else if (pixel_clk == 148352000) 570 n = 5824; 571 else 572 n = 6144; 573 n *= mult; 574 break; 575 576 default: 577 break; 578 } 579 580 return n; 581 } 582 583 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, 584 unsigned long pixel_clk, unsigned int sample_rate) 585 { 586 unsigned long ftdms = pixel_clk; 587 unsigned int n, cts; 588 u8 config3; 589 u64 tmp; 590 591 n = hdmi_compute_n(sample_rate, pixel_clk); 592 593 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 594 595 /* Only compute CTS when using internal AHB audio */ 596 if (config3 & HDMI_CONFIG3_AHBAUDDMA) { 597 /* 598 * Compute the CTS value from the N value. Note that CTS and N 599 * can be up to 20 bits in total, so we need 64-bit math. Also 600 * note that our TDMS clock is not fully accurate; it is 601 * accurate to kHz. This can introduce an unnecessary remainder 602 * in the calculation below, so we don't try to warn about that. 603 */ 604 tmp = (u64)ftdms * n; 605 do_div(tmp, 128 * sample_rate); 606 cts = tmp; 607 608 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", 609 __func__, sample_rate, 610 ftdms / 1000000, (ftdms / 1000) % 1000, 611 n, cts); 612 } else { 613 cts = 0; 614 } 615 616 spin_lock_irq(&hdmi->audio_lock); 617 hdmi->audio_n = n; 618 hdmi->audio_cts = cts; 619 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 620 spin_unlock_irq(&hdmi->audio_lock); 621 } 622 623 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) 624 { 625 mutex_lock(&hdmi->audio_mutex); 626 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); 627 mutex_unlock(&hdmi->audio_mutex); 628 } 629 630 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 631 { 632 mutex_lock(&hdmi->audio_mutex); 633 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 634 hdmi->sample_rate); 635 mutex_unlock(&hdmi->audio_mutex); 636 } 637 638 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 639 { 640 mutex_lock(&hdmi->audio_mutex); 641 hdmi->sample_rate = rate; 642 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 643 hdmi->sample_rate); 644 mutex_unlock(&hdmi->audio_mutex); 645 } 646 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); 647 648 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) 649 { 650 if (enable) 651 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; 652 else 653 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; 654 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 655 } 656 657 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi) 658 { 659 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 660 } 661 662 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi) 663 { 664 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 665 } 666 667 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi) 668 { 669 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 670 hdmi_enable_audio_clk(hdmi, true); 671 } 672 673 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi) 674 { 675 hdmi_enable_audio_clk(hdmi, false); 676 } 677 678 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 679 { 680 unsigned long flags; 681 682 spin_lock_irqsave(&hdmi->audio_lock, flags); 683 hdmi->audio_enable = true; 684 if (hdmi->enable_audio) 685 hdmi->enable_audio(hdmi); 686 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 687 } 688 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); 689 690 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 691 { 692 unsigned long flags; 693 694 spin_lock_irqsave(&hdmi->audio_lock, flags); 695 hdmi->audio_enable = false; 696 if (hdmi->disable_audio) 697 hdmi->disable_audio(hdmi); 698 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 699 } 700 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); 701 702 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 703 { 704 switch (bus_format) { 705 case MEDIA_BUS_FMT_RGB888_1X24: 706 case MEDIA_BUS_FMT_RGB101010_1X30: 707 case MEDIA_BUS_FMT_RGB121212_1X36: 708 case MEDIA_BUS_FMT_RGB161616_1X48: 709 return true; 710 711 default: 712 return false; 713 } 714 } 715 716 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 717 { 718 switch (bus_format) { 719 case MEDIA_BUS_FMT_YUV8_1X24: 720 case MEDIA_BUS_FMT_YUV10_1X30: 721 case MEDIA_BUS_FMT_YUV12_1X36: 722 case MEDIA_BUS_FMT_YUV16_1X48: 723 return true; 724 725 default: 726 return false; 727 } 728 } 729 730 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 731 { 732 switch (bus_format) { 733 case MEDIA_BUS_FMT_UYVY8_1X16: 734 case MEDIA_BUS_FMT_UYVY10_1X20: 735 case MEDIA_BUS_FMT_UYVY12_1X24: 736 return true; 737 738 default: 739 return false; 740 } 741 } 742 743 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 744 { 745 switch (bus_format) { 746 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 747 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 748 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 749 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 750 return true; 751 752 default: 753 return false; 754 } 755 } 756 757 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 758 { 759 switch (bus_format) { 760 case MEDIA_BUS_FMT_RGB888_1X24: 761 case MEDIA_BUS_FMT_YUV8_1X24: 762 case MEDIA_BUS_FMT_UYVY8_1X16: 763 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 764 return 8; 765 766 case MEDIA_BUS_FMT_RGB101010_1X30: 767 case MEDIA_BUS_FMT_YUV10_1X30: 768 case MEDIA_BUS_FMT_UYVY10_1X20: 769 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 770 return 10; 771 772 case MEDIA_BUS_FMT_RGB121212_1X36: 773 case MEDIA_BUS_FMT_YUV12_1X36: 774 case MEDIA_BUS_FMT_UYVY12_1X24: 775 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 776 return 12; 777 778 case MEDIA_BUS_FMT_RGB161616_1X48: 779 case MEDIA_BUS_FMT_YUV16_1X48: 780 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 781 return 16; 782 783 default: 784 return 0; 785 } 786 } 787 788 /* 789 * this submodule is responsible for the video data synchronization. 790 * for example, for RGB 4:4:4 input, the data map is defined as 791 * pin{47~40} <==> R[7:0] 792 * pin{31~24} <==> G[7:0] 793 * pin{15~8} <==> B[7:0] 794 */ 795 static void hdmi_video_sample(struct dw_hdmi *hdmi) 796 { 797 int color_format = 0; 798 u8 val; 799 800 switch (hdmi->hdmi_data.enc_in_bus_format) { 801 case MEDIA_BUS_FMT_RGB888_1X24: 802 color_format = 0x01; 803 break; 804 case MEDIA_BUS_FMT_RGB101010_1X30: 805 color_format = 0x03; 806 break; 807 case MEDIA_BUS_FMT_RGB121212_1X36: 808 color_format = 0x05; 809 break; 810 case MEDIA_BUS_FMT_RGB161616_1X48: 811 color_format = 0x07; 812 break; 813 814 case MEDIA_BUS_FMT_YUV8_1X24: 815 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 816 color_format = 0x09; 817 break; 818 case MEDIA_BUS_FMT_YUV10_1X30: 819 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 820 color_format = 0x0B; 821 break; 822 case MEDIA_BUS_FMT_YUV12_1X36: 823 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 824 color_format = 0x0D; 825 break; 826 case MEDIA_BUS_FMT_YUV16_1X48: 827 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 828 color_format = 0x0F; 829 break; 830 831 case MEDIA_BUS_FMT_UYVY8_1X16: 832 color_format = 0x16; 833 break; 834 case MEDIA_BUS_FMT_UYVY10_1X20: 835 color_format = 0x14; 836 break; 837 case MEDIA_BUS_FMT_UYVY12_1X24: 838 color_format = 0x12; 839 break; 840 841 default: 842 return; 843 } 844 845 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 846 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 847 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 848 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 849 850 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 851 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 852 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 853 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 854 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 855 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 856 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 857 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 858 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 859 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 860 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 861 } 862 863 static int is_color_space_conversion(struct dw_hdmi *hdmi) 864 { 865 return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format; 866 } 867 868 static int is_color_space_decimation(struct dw_hdmi *hdmi) 869 { 870 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 871 return 0; 872 873 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 874 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 875 return 1; 876 877 return 0; 878 } 879 880 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 881 { 882 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 883 return 0; 884 885 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 886 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 887 return 1; 888 889 return 0; 890 } 891 892 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 893 { 894 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 895 unsigned i; 896 u32 csc_scale = 1; 897 898 if (is_color_space_conversion(hdmi)) { 899 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 900 if (hdmi->hdmi_data.enc_out_encoding == 901 V4L2_YCBCR_ENC_601) 902 csc_coeff = &csc_coeff_rgb_out_eitu601; 903 else 904 csc_coeff = &csc_coeff_rgb_out_eitu709; 905 } else if (hdmi_bus_fmt_is_rgb( 906 hdmi->hdmi_data.enc_in_bus_format)) { 907 if (hdmi->hdmi_data.enc_out_encoding == 908 V4L2_YCBCR_ENC_601) 909 csc_coeff = &csc_coeff_rgb_in_eitu601; 910 else 911 csc_coeff = &csc_coeff_rgb_in_eitu709; 912 csc_scale = 0; 913 } 914 } 915 916 /* The CSC registers are sequential, alternating MSB then LSB */ 917 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 918 u16 coeff_a = (*csc_coeff)[0][i]; 919 u16 coeff_b = (*csc_coeff)[1][i]; 920 u16 coeff_c = (*csc_coeff)[2][i]; 921 922 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 923 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 924 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 925 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 926 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 927 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 928 } 929 930 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 931 HDMI_CSC_SCALE); 932 } 933 934 static void hdmi_video_csc(struct dw_hdmi *hdmi) 935 { 936 int color_depth = 0; 937 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 938 int decimation = 0; 939 940 /* YCC422 interpolation to 444 mode */ 941 if (is_color_space_interpolation(hdmi)) 942 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 943 else if (is_color_space_decimation(hdmi)) 944 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 945 946 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 947 case 8: 948 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 949 break; 950 case 10: 951 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 952 break; 953 case 12: 954 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 955 break; 956 case 16: 957 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 958 break; 959 960 default: 961 return; 962 } 963 964 /* Configure the CSC registers */ 965 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 966 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 967 HDMI_CSC_SCALE); 968 969 dw_hdmi_update_csc_coeffs(hdmi); 970 } 971 972 /* 973 * HDMI video packetizer is used to packetize the data. 974 * for example, if input is YCC422 mode or repeater is used, 975 * data should be repacked this module can be bypassed. 976 */ 977 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 978 { 979 unsigned int color_depth = 0; 980 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 981 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 982 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 983 u8 val, vp_conf; 984 985 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 986 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 987 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 988 switch (hdmi_bus_fmt_color_depth( 989 hdmi->hdmi_data.enc_out_bus_format)) { 990 case 8: 991 color_depth = 4; 992 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 993 break; 994 case 10: 995 color_depth = 5; 996 break; 997 case 12: 998 color_depth = 6; 999 break; 1000 case 16: 1001 color_depth = 7; 1002 break; 1003 default: 1004 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1005 } 1006 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1007 switch (hdmi_bus_fmt_color_depth( 1008 hdmi->hdmi_data.enc_out_bus_format)) { 1009 case 0: 1010 case 8: 1011 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1012 break; 1013 case 10: 1014 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1015 break; 1016 case 12: 1017 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1018 break; 1019 1020 default: 1021 return; 1022 } 1023 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1024 } else { 1025 return; 1026 } 1027 1028 /* set the packetizer registers */ 1029 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1030 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | 1031 ((hdmi_data->pix_repet_factor << 1032 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & 1033 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); 1034 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1035 1036 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1037 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1038 1039 /* Data from pixel repeater block */ 1040 if (hdmi_data->pix_repet_factor > 1) { 1041 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1042 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1043 } else { /* data from packetizer block */ 1044 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1045 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1046 } 1047 1048 hdmi_modb(hdmi, vp_conf, 1049 HDMI_VP_CONF_PR_EN_MASK | 1050 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1051 1052 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 1053 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 1054 1055 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1056 1057 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1058 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1059 HDMI_VP_CONF_PP_EN_ENABLE | 1060 HDMI_VP_CONF_YCC422_EN_DISABLE; 1061 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1062 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1063 HDMI_VP_CONF_PP_EN_DISABLE | 1064 HDMI_VP_CONF_YCC422_EN_ENABLE; 1065 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1066 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1067 HDMI_VP_CONF_PP_EN_DISABLE | 1068 HDMI_VP_CONF_YCC422_EN_DISABLE; 1069 } else { 1070 return; 1071 } 1072 1073 hdmi_modb(hdmi, vp_conf, 1074 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1075 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1076 1077 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1078 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1079 HDMI_VP_STUFF_PP_STUFFING_MASK | 1080 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1081 1082 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1083 HDMI_VP_CONF); 1084 } 1085 1086 /* ----------------------------------------------------------------------------- 1087 * Synopsys PHY Handling 1088 */ 1089 1090 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 1091 unsigned char bit) 1092 { 1093 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 1094 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 1095 } 1096 1097 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 1098 { 1099 u32 val; 1100 1101 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 1102 if (msec-- == 0) 1103 return false; 1104 udelay(1000); 1105 } 1106 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 1107 1108 return true; 1109 } 1110 1111 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 1112 unsigned char addr) 1113 { 1114 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 1115 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 1116 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 1117 HDMI_PHY_I2CM_DATAO_1_ADDR); 1118 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 1119 HDMI_PHY_I2CM_DATAO_0_ADDR); 1120 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 1121 HDMI_PHY_I2CM_OPERATION_ADDR); 1122 hdmi_phy_wait_i2c_done(hdmi, 1000); 1123 } 1124 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); 1125 1126 /* Filter out invalid setups to avoid configuring SCDC and scrambling */ 1127 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi) 1128 { 1129 struct drm_display_info *display = &hdmi->connector.display_info; 1130 1131 /* Completely disable SCDC support for older controllers */ 1132 if (hdmi->version < 0x200a) 1133 return false; 1134 1135 /* Disable if no DDC bus */ 1136 if (!hdmi->ddc) 1137 return false; 1138 1139 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */ 1140 if (!display->hdmi.scdc.supported || 1141 !display->hdmi.scdc.scrambling.supported) 1142 return false; 1143 1144 /* 1145 * Disable if display only support low TMDS rates and scrambling 1146 * for low rates is not supported either 1147 */ 1148 if (!display->hdmi.scdc.scrambling.low_rates && 1149 display->max_tmds_clock <= 340000) 1150 return false; 1151 1152 return true; 1153 } 1154 1155 /* 1156 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates: 1157 * - The Source shall suspend transmission of the TMDS clock and data 1158 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it 1159 * from a 0 to a 1 or from a 1 to a 0 1160 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from 1161 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming 1162 * transmission of TMDS clock and data 1163 * 1164 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio() 1165 * helper should called right before enabling the TMDS Clock and Data in 1166 * the PHY configuration callback. 1167 */ 1168 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi) 1169 { 1170 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1171 1172 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 1173 if (dw_hdmi_support_scdc(hdmi)) { 1174 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1175 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1); 1176 else 1177 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0); 1178 } 1179 } 1180 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio); 1181 1182 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 1183 { 1184 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 1185 HDMI_PHY_CONF0_PDZ_OFFSET, 1186 HDMI_PHY_CONF0_PDZ_MASK); 1187 } 1188 1189 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 1190 { 1191 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1192 HDMI_PHY_CONF0_ENTMDS_OFFSET, 1193 HDMI_PHY_CONF0_ENTMDS_MASK); 1194 } 1195 1196 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 1197 { 1198 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1199 HDMI_PHY_CONF0_SVSRET_OFFSET, 1200 HDMI_PHY_CONF0_SVSRET_MASK); 1201 } 1202 1203 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 1204 { 1205 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1206 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 1207 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 1208 } 1209 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq); 1210 1211 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 1212 { 1213 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1214 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 1215 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 1216 } 1217 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron); 1218 1219 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 1220 { 1221 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1222 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 1223 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 1224 } 1225 1226 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 1227 { 1228 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1229 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 1230 HDMI_PHY_CONF0_SELDIPIF_MASK); 1231 } 1232 1233 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi) 1234 { 1235 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 1236 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1237 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1238 } 1239 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset); 1240 1241 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) 1242 { 1243 hdmi_phy_test_clear(hdmi, 1); 1244 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR); 1245 hdmi_phy_test_clear(hdmi, 0); 1246 } 1247 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr); 1248 1249 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 1250 { 1251 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1252 unsigned int i; 1253 u16 val; 1254 1255 if (phy->gen == 1) { 1256 dw_hdmi_phy_enable_tmds(hdmi, 0); 1257 dw_hdmi_phy_enable_powerdown(hdmi, true); 1258 return; 1259 } 1260 1261 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 1262 1263 /* 1264 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 1265 * to low power mode. 1266 */ 1267 for (i = 0; i < 5; ++i) { 1268 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 1269 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 1270 break; 1271 1272 usleep_range(1000, 2000); 1273 } 1274 1275 if (val & HDMI_PHY_TX_PHY_LOCK) 1276 dev_warn(hdmi->dev, "PHY failed to power down\n"); 1277 else 1278 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); 1279 1280 dw_hdmi_phy_gen2_pddq(hdmi, 1); 1281 } 1282 1283 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 1284 { 1285 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1286 unsigned int i; 1287 u8 val; 1288 1289 if (phy->gen == 1) { 1290 dw_hdmi_phy_enable_powerdown(hdmi, false); 1291 1292 /* Toggle TMDS enable. */ 1293 dw_hdmi_phy_enable_tmds(hdmi, 0); 1294 dw_hdmi_phy_enable_tmds(hdmi, 1); 1295 return 0; 1296 } 1297 1298 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 1299 dw_hdmi_phy_gen2_pddq(hdmi, 0); 1300 1301 /* Wait for PHY PLL lock */ 1302 for (i = 0; i < 5; ++i) { 1303 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 1304 if (val) 1305 break; 1306 1307 usleep_range(1000, 2000); 1308 } 1309 1310 if (!val) { 1311 dev_err(hdmi->dev, "PHY PLL failed to lock\n"); 1312 return -ETIMEDOUT; 1313 } 1314 1315 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); 1316 return 0; 1317 } 1318 1319 /* 1320 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 1321 * information the DWC MHL PHY has the same register layout and is thus also 1322 * supported by this function. 1323 */ 1324 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 1325 const struct dw_hdmi_plat_data *pdata, 1326 unsigned long mpixelclock) 1327 { 1328 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 1329 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 1330 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 1331 1332 /* TOFIX Will need 420 specific PHY configuration tables */ 1333 1334 /* PLL/MPLL Cfg - always match on final entry */ 1335 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 1336 if (mpixelclock <= mpll_config->mpixelclock) 1337 break; 1338 1339 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 1340 if (mpixelclock <= curr_ctrl->mpixelclock) 1341 break; 1342 1343 for (; phy_config->mpixelclock != ~0UL; phy_config++) 1344 if (mpixelclock <= phy_config->mpixelclock) 1345 break; 1346 1347 if (mpll_config->mpixelclock == ~0UL || 1348 curr_ctrl->mpixelclock == ~0UL || 1349 phy_config->mpixelclock == ~0UL) 1350 return -EINVAL; 1351 1352 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 1353 HDMI_3D_TX_PHY_CPCE_CTRL); 1354 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 1355 HDMI_3D_TX_PHY_GMPCTRL); 1356 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 1357 HDMI_3D_TX_PHY_CURRCTRL); 1358 1359 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 1360 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 1361 HDMI_3D_TX_PHY_MSM_CTRL); 1362 1363 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 1364 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 1365 HDMI_3D_TX_PHY_CKSYMTXCTRL); 1366 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 1367 HDMI_3D_TX_PHY_VLEVCTRL); 1368 1369 /* Override and disable clock termination. */ 1370 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 1371 HDMI_3D_TX_PHY_CKCALCTRL); 1372 1373 return 0; 1374 } 1375 1376 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 1377 { 1378 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1379 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 1380 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 1381 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1382 int ret; 1383 1384 dw_hdmi_phy_power_off(hdmi); 1385 1386 dw_hdmi_set_high_tmds_clock_ratio(hdmi); 1387 1388 /* Leave low power consumption mode by asserting SVSRET. */ 1389 if (phy->has_svsret) 1390 dw_hdmi_phy_enable_svsret(hdmi, 1); 1391 1392 dw_hdmi_phy_reset(hdmi); 1393 1394 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 1395 1396 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); 1397 1398 /* Write to the PHY as configured by the platform */ 1399 if (pdata->configure_phy) 1400 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 1401 else 1402 ret = phy->configure(hdmi, pdata, mpixelclock); 1403 if (ret) { 1404 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", 1405 mpixelclock); 1406 return ret; 1407 } 1408 1409 /* Wait for resuming transmission of TMDS clock and data */ 1410 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1411 msleep(100); 1412 1413 return dw_hdmi_phy_power_on(hdmi); 1414 } 1415 1416 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 1417 struct drm_display_mode *mode) 1418 { 1419 int i, ret; 1420 1421 /* HDMI Phy spec says to do the phy initialization sequence twice */ 1422 for (i = 0; i < 2; i++) { 1423 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 1424 dw_hdmi_phy_sel_interface_control(hdmi, 0); 1425 1426 ret = hdmi_phy_configure(hdmi); 1427 if (ret) 1428 return ret; 1429 } 1430 1431 return 0; 1432 } 1433 1434 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 1435 { 1436 dw_hdmi_phy_power_off(hdmi); 1437 } 1438 1439 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 1440 void *data) 1441 { 1442 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 1443 connector_status_connected : connector_status_disconnected; 1444 } 1445 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); 1446 1447 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 1448 bool force, bool disabled, bool rxsense) 1449 { 1450 u8 old_mask = hdmi->phy_mask; 1451 1452 if (force || disabled || !rxsense) 1453 hdmi->phy_mask |= HDMI_PHY_RX_SENSE; 1454 else 1455 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; 1456 1457 if (old_mask != hdmi->phy_mask) 1458 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1459 } 1460 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd); 1461 1462 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) 1463 { 1464 /* 1465 * Configure the PHY RX SENSE and HPD interrupts polarities and clear 1466 * any pending interrupt. 1467 */ 1468 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); 1469 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1470 HDMI_IH_PHY_STAT0); 1471 1472 /* Enable cable hot plug irq. */ 1473 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1474 1475 /* Clear and unmute interrupts. */ 1476 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1477 HDMI_IH_PHY_STAT0); 1478 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 1479 HDMI_IH_MUTE_PHY_STAT0); 1480 } 1481 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd); 1482 1483 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 1484 .init = dw_hdmi_phy_init, 1485 .disable = dw_hdmi_phy_disable, 1486 .read_hpd = dw_hdmi_phy_read_hpd, 1487 .update_hpd = dw_hdmi_phy_update_hpd, 1488 .setup_hpd = dw_hdmi_phy_setup_hpd, 1489 }; 1490 1491 /* ----------------------------------------------------------------------------- 1492 * HDMI TX Setup 1493 */ 1494 1495 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) 1496 { 1497 u8 de; 1498 1499 if (hdmi->hdmi_data.video_mode.mdataenablepolarity) 1500 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1501 else 1502 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; 1503 1504 /* disable rx detect */ 1505 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, 1506 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 1507 1508 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); 1509 1510 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, 1511 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); 1512 } 1513 1514 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1515 { 1516 struct hdmi_avi_infoframe frame; 1517 u8 val; 1518 1519 /* Initialise info frame from DRM mode */ 1520 drm_hdmi_avi_infoframe_from_display_mode(&frame, 1521 &hdmi->connector, mode); 1522 1523 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1524 frame.colorspace = HDMI_COLORSPACE_YUV444; 1525 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1526 frame.colorspace = HDMI_COLORSPACE_YUV422; 1527 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1528 frame.colorspace = HDMI_COLORSPACE_YUV420; 1529 else 1530 frame.colorspace = HDMI_COLORSPACE_RGB; 1531 1532 /* Set up colorimetry */ 1533 switch (hdmi->hdmi_data.enc_out_encoding) { 1534 case V4L2_YCBCR_ENC_601: 1535 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1536 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1537 else 1538 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1539 frame.extended_colorimetry = 1540 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1541 break; 1542 case V4L2_YCBCR_ENC_709: 1543 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1544 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1545 else 1546 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1547 frame.extended_colorimetry = 1548 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1549 break; 1550 default: /* Carries no data */ 1551 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1552 frame.extended_colorimetry = 1553 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1554 break; 1555 } 1556 1557 frame.scan_mode = HDMI_SCAN_MODE_NONE; 1558 1559 /* 1560 * The Designware IP uses a different byte format from standard 1561 * AVI info frames, though generally the bits are in the correct 1562 * bytes. 1563 */ 1564 1565 /* 1566 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, 1567 * scan info in bits 4,5 rather than 0,1 and active aspect present in 1568 * bit 6 rather than 4. 1569 */ 1570 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); 1571 if (frame.active_aspect & 15) 1572 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1573 if (frame.top_bar || frame.bottom_bar) 1574 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1575 if (frame.left_bar || frame.right_bar) 1576 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1577 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1578 1579 /* AVI data byte 2 differences: none */ 1580 val = ((frame.colorimetry & 0x3) << 6) | 1581 ((frame.picture_aspect & 0x3) << 4) | 1582 (frame.active_aspect & 0xf); 1583 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1584 1585 /* AVI data byte 3 differences: none */ 1586 val = ((frame.extended_colorimetry & 0x7) << 4) | 1587 ((frame.quantization_range & 0x3) << 2) | 1588 (frame.nups & 0x3); 1589 if (frame.itc) 1590 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1591 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1592 1593 /* AVI data byte 4 differences: none */ 1594 val = frame.video_code & 0x7f; 1595 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1596 1597 /* AVI Data Byte 5- set up input and output pixel repetition */ 1598 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1599 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1600 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1601 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1602 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1603 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1604 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1605 1606 /* 1607 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1608 * ycc range in bits 2,3 rather than 6,7 1609 */ 1610 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1611 (frame.content_type & 0x3); 1612 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1613 1614 /* AVI Data Bytes 6-13 */ 1615 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1616 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1617 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1618 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1619 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1620 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1621 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1622 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1623 } 1624 1625 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1626 struct drm_display_mode *mode) 1627 { 1628 struct hdmi_vendor_infoframe frame; 1629 u8 buffer[10]; 1630 ssize_t err; 1631 1632 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, 1633 &hdmi->connector, 1634 mode); 1635 if (err < 0) 1636 /* 1637 * Going into that statement does not means vendor infoframe 1638 * fails. It just informed us that vendor infoframe is not 1639 * needed for the selected mode. Only 4k or stereoscopic 3D 1640 * mode requires vendor infoframe. So just simply return. 1641 */ 1642 return; 1643 1644 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1645 if (err < 0) { 1646 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1647 err); 1648 return; 1649 } 1650 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1651 HDMI_FC_DATAUTO0_VSD_MASK); 1652 1653 /* Set the length of HDMI vendor specific InfoFrame payload */ 1654 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1655 1656 /* Set 24bit IEEE Registration Identifier */ 1657 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1658 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1659 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1660 1661 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1662 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1663 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1664 1665 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1666 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1667 1668 /* Packet frame interpolation */ 1669 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1670 1671 /* Auto packets per frame and line spacing */ 1672 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1673 1674 /* Configures the Frame Composer On RDRB mode */ 1675 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1676 HDMI_FC_DATAUTO0_VSD_MASK); 1677 } 1678 1679 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1680 const struct drm_display_mode *mode) 1681 { 1682 u8 inv_val, bytes; 1683 struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi; 1684 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1685 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1686 unsigned int vdisplay, hdisplay; 1687 1688 vmode->mtmdsclock = vmode->mpixelclock = mode->clock * 1000; 1689 1690 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); 1691 1692 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1693 vmode->mtmdsclock /= 2; 1694 1695 /* Set up HDMI_FC_INVIDCONF */ 1696 inv_val = (hdmi->hdmi_data.hdcp_enable || 1697 (dw_hdmi_support_scdc(hdmi) && 1698 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 1699 hdmi_info->scdc.scrambling.low_rates)) ? 1700 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1701 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1702 1703 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1704 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1705 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1706 1707 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1708 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1709 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1710 1711 inv_val |= (vmode->mdataenablepolarity ? 1712 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1713 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1714 1715 if (hdmi->vic == 39) 1716 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1717 else 1718 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1719 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1720 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1721 1722 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1723 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1724 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1725 1726 inv_val |= hdmi->sink_is_hdmi ? 1727 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1728 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1729 1730 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1731 1732 hdisplay = mode->hdisplay; 1733 hblank = mode->htotal - mode->hdisplay; 1734 h_de_hs = mode->hsync_start - mode->hdisplay; 1735 hsync_len = mode->hsync_end - mode->hsync_start; 1736 1737 /* 1738 * When we're setting a YCbCr420 mode, we need 1739 * to adjust the horizontal timing to suit. 1740 */ 1741 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1742 hdisplay /= 2; 1743 hblank /= 2; 1744 h_de_hs /= 2; 1745 hsync_len /= 2; 1746 } 1747 1748 vdisplay = mode->vdisplay; 1749 vblank = mode->vtotal - mode->vdisplay; 1750 v_de_vs = mode->vsync_start - mode->vdisplay; 1751 vsync_len = mode->vsync_end - mode->vsync_start; 1752 1753 /* 1754 * When we're setting an interlaced mode, we need 1755 * to adjust the vertical timing to suit. 1756 */ 1757 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1758 vdisplay /= 2; 1759 vblank /= 2; 1760 v_de_vs /= 2; 1761 vsync_len /= 2; 1762 } 1763 1764 /* Scrambling Control */ 1765 if (dw_hdmi_support_scdc(hdmi)) { 1766 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 1767 hdmi_info->scdc.scrambling.low_rates) { 1768 /* 1769 * HDMI2.0 Specifies the following procedure: 1770 * After the Source Device has determined that 1771 * SCDC_Present is set (=1), the Source Device should 1772 * write the accurate Version of the Source Device 1773 * to the Source Version field in the SCDCS. 1774 * Source Devices compliant shall set the 1775 * Source Version = 1. 1776 */ 1777 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, 1778 &bytes); 1779 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, 1780 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); 1781 1782 /* Enabled Scrambling in the Sink */ 1783 drm_scdc_set_scrambling(hdmi->ddc, 1); 1784 1785 /* 1786 * To activate the scrambler feature, you must ensure 1787 * that the quasi-static configuration bit 1788 * fc_invidconf.HDCP_keepout is set at configuration 1789 * time, before the required mc_swrstzreq.tmdsswrst_req 1790 * reset request is issued. 1791 */ 1792 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 1793 HDMI_MC_SWRSTZ); 1794 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 1795 } else { 1796 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 1797 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 1798 HDMI_MC_SWRSTZ); 1799 drm_scdc_set_scrambling(hdmi->ddc, 0); 1800 } 1801 } 1802 1803 /* Set up horizontal active pixel width */ 1804 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 1805 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 1806 1807 /* Set up vertical active lines */ 1808 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1809 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1810 1811 /* Set up horizontal blanking pixel region width */ 1812 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 1813 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 1814 1815 /* Set up vertical blanking pixel region width */ 1816 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 1817 1818 /* Set up HSYNC active edge delay width (in pixel clks) */ 1819 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 1820 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 1821 1822 /* Set up VSYNC active edge delay (in lines) */ 1823 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 1824 1825 /* Set up HSYNC active pulse width (in pixel clks) */ 1826 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 1827 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 1828 1829 /* Set up VSYNC active edge delay (in lines) */ 1830 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 1831 } 1832 1833 /* HDMI Initialization Step B.4 */ 1834 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 1835 { 1836 /* control period minimum duration */ 1837 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 1838 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 1839 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 1840 1841 /* Set to fill TMDS data channels */ 1842 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 1843 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 1844 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 1845 1846 /* Enable pixel clock and tmds data path */ 1847 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE | 1848 HDMI_MC_CLKDIS_CSCCLK_DISABLE | 1849 HDMI_MC_CLKDIS_AUDCLK_DISABLE | 1850 HDMI_MC_CLKDIS_PREPCLK_DISABLE | 1851 HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1852 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 1853 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1854 1855 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1856 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1857 1858 /* Enable csc path */ 1859 if (is_color_space_conversion(hdmi)) { 1860 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 1861 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1862 } 1863 1864 /* Enable color space conversion if needed */ 1865 if (is_color_space_conversion(hdmi)) 1866 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 1867 HDMI_MC_FLOWCTRL); 1868 else 1869 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 1870 HDMI_MC_FLOWCTRL); 1871 } 1872 1873 /* Workaround to clear the overflow condition */ 1874 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 1875 { 1876 unsigned int count; 1877 unsigned int i; 1878 u8 val; 1879 1880 /* 1881 * Under some circumstances the Frame Composer arithmetic unit can miss 1882 * an FC register write due to being busy processing the previous one. 1883 * The issue can be worked around by issuing a TMDS software reset and 1884 * then write one of the FC registers several times. 1885 * 1886 * The number of iterations matters and depends on the HDMI TX revision 1887 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL 1888 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified 1889 * as needing the workaround, with 4 iterations for v1.30a and 1 1890 * iteration for others. 1891 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing 1892 * the workaround with a single iteration. 1893 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have 1894 * been identified as needing the workaround with a single iteration. 1895 */ 1896 1897 switch (hdmi->version) { 1898 case 0x130a: 1899 count = 4; 1900 break; 1901 case 0x131a: 1902 case 0x132a: 1903 case 0x200a: 1904 case 0x201a: 1905 case 0x211a: 1906 case 0x212a: 1907 count = 1; 1908 break; 1909 default: 1910 return; 1911 } 1912 1913 /* TMDS software reset */ 1914 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 1915 1916 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 1917 for (i = 0; i < count; i++) 1918 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 1919 } 1920 1921 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 1922 { 1923 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 1924 HDMI_IH_MUTE_FC_STAT2); 1925 } 1926 1927 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1928 { 1929 int ret; 1930 1931 hdmi_disable_overflow_interrupts(hdmi); 1932 1933 hdmi->vic = drm_match_cea_mode(mode); 1934 1935 if (!hdmi->vic) { 1936 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); 1937 } else { 1938 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); 1939 } 1940 1941 if ((hdmi->vic == 6) || (hdmi->vic == 7) || 1942 (hdmi->vic == 21) || (hdmi->vic == 22) || 1943 (hdmi->vic == 2) || (hdmi->vic == 3) || 1944 (hdmi->vic == 17) || (hdmi->vic == 18)) 1945 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 1946 else 1947 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 1948 1949 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 1950 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 1951 1952 /* TOFIX: Get input format from plat data or fallback to RGB888 */ 1953 if (hdmi->plat_data->input_bus_format) 1954 hdmi->hdmi_data.enc_in_bus_format = 1955 hdmi->plat_data->input_bus_format; 1956 else 1957 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1958 1959 /* TOFIX: Get input encoding from plat data or fallback to none */ 1960 if (hdmi->plat_data->input_bus_encoding) 1961 hdmi->hdmi_data.enc_in_encoding = 1962 hdmi->plat_data->input_bus_encoding; 1963 else 1964 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 1965 1966 /* TOFIX: Default to RGB888 output format */ 1967 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1968 1969 hdmi->hdmi_data.pix_repet_factor = 0; 1970 hdmi->hdmi_data.hdcp_enable = 0; 1971 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 1972 1973 /* HDMI Initialization Step B.1 */ 1974 hdmi_av_composer(hdmi, mode); 1975 1976 /* HDMI Initializateion Step B.2 */ 1977 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode); 1978 if (ret) 1979 return ret; 1980 hdmi->phy.enabled = true; 1981 1982 /* HDMI Initialization Step B.3 */ 1983 dw_hdmi_enable_video_path(hdmi); 1984 1985 if (hdmi->sink_has_audio) { 1986 dev_dbg(hdmi->dev, "sink has audio support\n"); 1987 1988 /* HDMI Initialization Step E - Configure audio */ 1989 hdmi_clk_regenerator_update_pixel_clock(hdmi); 1990 hdmi_enable_audio_clk(hdmi, true); 1991 } 1992 1993 /* not for DVI mode */ 1994 if (hdmi->sink_is_hdmi) { 1995 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); 1996 1997 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 1998 hdmi_config_AVI(hdmi, mode); 1999 hdmi_config_vendor_specific_infoframe(hdmi, mode); 2000 } else { 2001 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); 2002 } 2003 2004 hdmi_video_packetize(hdmi); 2005 hdmi_video_csc(hdmi); 2006 hdmi_video_sample(hdmi); 2007 hdmi_tx_hdcp_config(hdmi); 2008 2009 dw_hdmi_clear_overflow(hdmi); 2010 2011 return 0; 2012 } 2013 2014 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) 2015 { 2016 u8 ih_mute; 2017 2018 /* 2019 * Boot up defaults are: 2020 * HDMI_IH_MUTE = 0x03 (disabled) 2021 * HDMI_IH_MUTE_* = 0x00 (enabled) 2022 * 2023 * Disable top level interrupt bits in HDMI block 2024 */ 2025 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | 2026 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2027 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; 2028 2029 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2030 2031 /* by default mask all interrupts */ 2032 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); 2033 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 2034 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 2035 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 2036 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); 2037 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); 2038 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); 2039 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); 2040 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); 2041 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); 2042 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); 2043 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); 2044 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); 2045 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); 2046 2047 /* Disable interrupts in the IH_MUTE_* registers */ 2048 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2049 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2050 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2051 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2052 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); 2053 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2054 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2055 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2056 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2057 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2058 2059 /* Enable top level interrupt bits in HDMI block */ 2060 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2061 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); 2062 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2063 } 2064 2065 static void dw_hdmi_poweron(struct dw_hdmi *hdmi) 2066 { 2067 hdmi->bridge_is_on = true; 2068 dw_hdmi_setup(hdmi, &hdmi->previous_mode); 2069 } 2070 2071 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) 2072 { 2073 if (hdmi->phy.enabled) { 2074 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 2075 hdmi->phy.enabled = false; 2076 } 2077 2078 hdmi->bridge_is_on = false; 2079 } 2080 2081 static void dw_hdmi_update_power(struct dw_hdmi *hdmi) 2082 { 2083 int force = hdmi->force; 2084 2085 if (hdmi->disabled) { 2086 force = DRM_FORCE_OFF; 2087 } else if (force == DRM_FORCE_UNSPECIFIED) { 2088 if (hdmi->rxsense) 2089 force = DRM_FORCE_ON; 2090 else 2091 force = DRM_FORCE_OFF; 2092 } 2093 2094 if (force == DRM_FORCE_OFF) { 2095 if (hdmi->bridge_is_on) 2096 dw_hdmi_poweroff(hdmi); 2097 } else { 2098 if (!hdmi->bridge_is_on) 2099 dw_hdmi_poweron(hdmi); 2100 } 2101 } 2102 2103 /* 2104 * Adjust the detection of RXSENSE according to whether we have a forced 2105 * connection mode enabled, or whether we have been disabled. There is 2106 * no point processing RXSENSE interrupts if we have a forced connection 2107 * state, or DRM has us disabled. 2108 * 2109 * We also disable rxsense interrupts when we think we're disconnected 2110 * to avoid floating TDMS signals giving false rxsense interrupts. 2111 * 2112 * Note: we still need to listen for HPD interrupts even when DRM has us 2113 * disabled so that we can detect a connect event. 2114 */ 2115 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) 2116 { 2117 if (hdmi->phy.ops->update_hpd) 2118 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, 2119 hdmi->force, hdmi->disabled, 2120 hdmi->rxsense); 2121 } 2122 2123 static enum drm_connector_status 2124 dw_hdmi_connector_detect(struct drm_connector *connector, bool force) 2125 { 2126 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2127 connector); 2128 2129 mutex_lock(&hdmi->mutex); 2130 hdmi->force = DRM_FORCE_UNSPECIFIED; 2131 dw_hdmi_update_power(hdmi); 2132 dw_hdmi_update_phy_mask(hdmi); 2133 mutex_unlock(&hdmi->mutex); 2134 2135 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 2136 } 2137 2138 static int dw_hdmi_connector_get_modes(struct drm_connector *connector) 2139 { 2140 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2141 connector); 2142 struct edid *edid; 2143 int ret = 0; 2144 2145 if (!hdmi->ddc) 2146 return 0; 2147 2148 edid = drm_get_edid(connector, hdmi->ddc); 2149 if (edid) { 2150 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", 2151 edid->width_cm, edid->height_cm); 2152 2153 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); 2154 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2155 drm_connector_update_edid_property(connector, edid); 2156 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); 2157 ret = drm_add_edid_modes(connector, edid); 2158 kfree(edid); 2159 } else { 2160 dev_dbg(hdmi->dev, "failed to get edid\n"); 2161 } 2162 2163 return ret; 2164 } 2165 2166 static void dw_hdmi_connector_force(struct drm_connector *connector) 2167 { 2168 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2169 connector); 2170 2171 mutex_lock(&hdmi->mutex); 2172 hdmi->force = connector->force; 2173 dw_hdmi_update_power(hdmi); 2174 dw_hdmi_update_phy_mask(hdmi); 2175 mutex_unlock(&hdmi->mutex); 2176 } 2177 2178 static const struct drm_connector_funcs dw_hdmi_connector_funcs = { 2179 .fill_modes = drm_helper_probe_single_connector_modes, 2180 .detect = dw_hdmi_connector_detect, 2181 .destroy = drm_connector_cleanup, 2182 .force = dw_hdmi_connector_force, 2183 .reset = drm_atomic_helper_connector_reset, 2184 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2185 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2186 }; 2187 2188 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { 2189 .get_modes = dw_hdmi_connector_get_modes, 2190 }; 2191 2192 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge) 2193 { 2194 struct dw_hdmi *hdmi = bridge->driver_private; 2195 struct drm_encoder *encoder = bridge->encoder; 2196 struct drm_connector *connector = &hdmi->connector; 2197 2198 connector->interlace_allowed = 1; 2199 connector->polled = DRM_CONNECTOR_POLL_HPD; 2200 2201 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); 2202 2203 drm_connector_init_with_ddc(bridge->dev, connector, 2204 &dw_hdmi_connector_funcs, 2205 DRM_MODE_CONNECTOR_HDMIA, 2206 hdmi->ddc); 2207 2208 drm_connector_attach_encoder(connector, encoder); 2209 2210 return 0; 2211 } 2212 2213 static enum drm_mode_status 2214 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 2215 const struct drm_display_mode *mode) 2216 { 2217 struct dw_hdmi *hdmi = bridge->driver_private; 2218 struct drm_connector *connector = &hdmi->connector; 2219 enum drm_mode_status mode_status = MODE_OK; 2220 2221 /* We don't support double-clocked modes */ 2222 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2223 return MODE_BAD; 2224 2225 if (hdmi->plat_data->mode_valid) 2226 mode_status = hdmi->plat_data->mode_valid(connector, mode); 2227 2228 return mode_status; 2229 } 2230 2231 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, 2232 const struct drm_display_mode *orig_mode, 2233 const struct drm_display_mode *mode) 2234 { 2235 struct dw_hdmi *hdmi = bridge->driver_private; 2236 2237 mutex_lock(&hdmi->mutex); 2238 2239 /* Store the display mode for plugin/DKMS poweron events */ 2240 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 2241 2242 mutex_unlock(&hdmi->mutex); 2243 } 2244 2245 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge) 2246 { 2247 struct dw_hdmi *hdmi = bridge->driver_private; 2248 2249 mutex_lock(&hdmi->mutex); 2250 hdmi->disabled = true; 2251 dw_hdmi_update_power(hdmi); 2252 dw_hdmi_update_phy_mask(hdmi); 2253 mutex_unlock(&hdmi->mutex); 2254 } 2255 2256 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge) 2257 { 2258 struct dw_hdmi *hdmi = bridge->driver_private; 2259 2260 mutex_lock(&hdmi->mutex); 2261 hdmi->disabled = false; 2262 dw_hdmi_update_power(hdmi); 2263 dw_hdmi_update_phy_mask(hdmi); 2264 mutex_unlock(&hdmi->mutex); 2265 } 2266 2267 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { 2268 .attach = dw_hdmi_bridge_attach, 2269 .enable = dw_hdmi_bridge_enable, 2270 .disable = dw_hdmi_bridge_disable, 2271 .mode_set = dw_hdmi_bridge_mode_set, 2272 .mode_valid = dw_hdmi_bridge_mode_valid, 2273 }; 2274 2275 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) 2276 { 2277 struct dw_hdmi_i2c *i2c = hdmi->i2c; 2278 unsigned int stat; 2279 2280 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 2281 if (!stat) 2282 return IRQ_NONE; 2283 2284 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0); 2285 2286 i2c->stat = stat; 2287 2288 complete(&i2c->cmp); 2289 2290 return IRQ_HANDLED; 2291 } 2292 2293 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) 2294 { 2295 struct dw_hdmi *hdmi = dev_id; 2296 u8 intr_stat; 2297 irqreturn_t ret = IRQ_NONE; 2298 2299 if (hdmi->i2c) 2300 ret = dw_hdmi_i2c_irq(hdmi); 2301 2302 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2303 if (intr_stat) { 2304 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2305 return IRQ_WAKE_THREAD; 2306 } 2307 2308 return ret; 2309 } 2310 2311 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) 2312 { 2313 mutex_lock(&hdmi->mutex); 2314 2315 if (!hdmi->force) { 2316 /* 2317 * If the RX sense status indicates we're disconnected, 2318 * clear the software rxsense status. 2319 */ 2320 if (!rx_sense) 2321 hdmi->rxsense = false; 2322 2323 /* 2324 * Only set the software rxsense status when both 2325 * rxsense and hpd indicates we're connected. 2326 * This avoids what seems to be bad behaviour in 2327 * at least iMX6S versions of the phy. 2328 */ 2329 if (hpd) 2330 hdmi->rxsense = true; 2331 2332 dw_hdmi_update_power(hdmi); 2333 dw_hdmi_update_phy_mask(hdmi); 2334 } 2335 mutex_unlock(&hdmi->mutex); 2336 } 2337 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); 2338 2339 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) 2340 { 2341 struct dw_hdmi *hdmi = dev_id; 2342 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; 2343 2344 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2345 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); 2346 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); 2347 2348 phy_pol_mask = 0; 2349 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) 2350 phy_pol_mask |= HDMI_PHY_HPD; 2351 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) 2352 phy_pol_mask |= HDMI_PHY_RX_SENSE0; 2353 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) 2354 phy_pol_mask |= HDMI_PHY_RX_SENSE1; 2355 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) 2356 phy_pol_mask |= HDMI_PHY_RX_SENSE2; 2357 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) 2358 phy_pol_mask |= HDMI_PHY_RX_SENSE3; 2359 2360 if (phy_pol_mask) 2361 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); 2362 2363 /* 2364 * RX sense tells us whether the TDMS transmitters are detecting 2365 * load - in other words, there's something listening on the 2366 * other end of the link. Use this to decide whether we should 2367 * power on the phy as HPD may be toggled by the sink to merely 2368 * ask the source to re-read the EDID. 2369 */ 2370 if (intr_stat & 2371 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { 2372 dw_hdmi_setup_rx_sense(hdmi, 2373 phy_stat & HDMI_PHY_HPD, 2374 phy_stat & HDMI_PHY_RX_SENSE); 2375 2376 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) 2377 cec_notifier_set_phys_addr(hdmi->cec_notifier, 2378 CEC_PHYS_ADDR_INVALID); 2379 } 2380 2381 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { 2382 dev_dbg(hdmi->dev, "EVENT=%s\n", 2383 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout"); 2384 if (hdmi->bridge.dev) 2385 drm_helper_hpd_irq_event(hdmi->bridge.dev); 2386 } 2387 2388 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); 2389 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 2390 HDMI_IH_MUTE_PHY_STAT0); 2391 2392 return IRQ_HANDLED; 2393 } 2394 2395 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 2396 { 2397 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 2398 .name = "DWC HDMI TX PHY", 2399 .gen = 1, 2400 }, { 2401 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 2402 .name = "DWC MHL PHY + HEAC PHY", 2403 .gen = 2, 2404 .has_svsret = true, 2405 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2406 }, { 2407 .type = DW_HDMI_PHY_DWC_MHL_PHY, 2408 .name = "DWC MHL PHY", 2409 .gen = 2, 2410 .has_svsret = true, 2411 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2412 }, { 2413 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 2414 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 2415 .gen = 2, 2416 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2417 }, { 2418 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 2419 .name = "DWC HDMI 3D TX PHY", 2420 .gen = 2, 2421 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2422 }, { 2423 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 2424 .name = "DWC HDMI 2.0 TX PHY", 2425 .gen = 2, 2426 .has_svsret = true, 2427 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2428 }, { 2429 .type = DW_HDMI_PHY_VENDOR_PHY, 2430 .name = "Vendor PHY", 2431 } 2432 }; 2433 2434 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 2435 { 2436 unsigned int i; 2437 u8 phy_type; 2438 2439 phy_type = hdmi->plat_data->phy_force_vendor ? 2440 DW_HDMI_PHY_VENDOR_PHY : 2441 hdmi_readb(hdmi, HDMI_CONFIG2_ID); 2442 2443 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { 2444 /* Vendor PHYs require support from the glue layer. */ 2445 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 2446 dev_err(hdmi->dev, 2447 "Vendor HDMI PHY not supported by glue layer\n"); 2448 return -ENODEV; 2449 } 2450 2451 hdmi->phy.ops = hdmi->plat_data->phy_ops; 2452 hdmi->phy.data = hdmi->plat_data->phy_data; 2453 hdmi->phy.name = hdmi->plat_data->phy_name; 2454 return 0; 2455 } 2456 2457 /* Synopsys PHYs are handled internally. */ 2458 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 2459 if (dw_hdmi_phys[i].type == phy_type) { 2460 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 2461 hdmi->phy.name = dw_hdmi_phys[i].name; 2462 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 2463 2464 if (!dw_hdmi_phys[i].configure && 2465 !hdmi->plat_data->configure_phy) { 2466 dev_err(hdmi->dev, "%s requires platform support\n", 2467 hdmi->phy.name); 2468 return -ENODEV; 2469 } 2470 2471 return 0; 2472 } 2473 } 2474 2475 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); 2476 return -ENODEV; 2477 } 2478 2479 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi) 2480 { 2481 mutex_lock(&hdmi->mutex); 2482 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE; 2483 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2484 mutex_unlock(&hdmi->mutex); 2485 } 2486 2487 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi) 2488 { 2489 mutex_lock(&hdmi->mutex); 2490 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE; 2491 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2492 mutex_unlock(&hdmi->mutex); 2493 } 2494 2495 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = { 2496 .write = hdmi_writeb, 2497 .read = hdmi_readb, 2498 .enable = dw_hdmi_cec_enable, 2499 .disable = dw_hdmi_cec_disable, 2500 }; 2501 2502 static const struct regmap_config hdmi_regmap_8bit_config = { 2503 .reg_bits = 32, 2504 .val_bits = 8, 2505 .reg_stride = 1, 2506 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, 2507 }; 2508 2509 static const struct regmap_config hdmi_regmap_32bit_config = { 2510 .reg_bits = 32, 2511 .val_bits = 32, 2512 .reg_stride = 4, 2513 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, 2514 }; 2515 2516 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi) 2517 { 2518 initialize_hdmi_ih_mutes(hdmi); 2519 2520 /* 2521 * Reset HDMI DDC I2C master controller and mute I2CM interrupts. 2522 * Even if we are using a separate i2c adapter doing this doesn't 2523 * hurt. 2524 */ 2525 dw_hdmi_i2c_init(hdmi); 2526 2527 if (hdmi->phy.ops->setup_hpd) 2528 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 2529 } 2530 2531 static struct dw_hdmi * 2532 __dw_hdmi_probe(struct platform_device *pdev, 2533 const struct dw_hdmi_plat_data *plat_data) 2534 { 2535 struct device *dev = &pdev->dev; 2536 struct device_node *np = dev->of_node; 2537 struct platform_device_info pdevinfo; 2538 struct device_node *ddc_node; 2539 struct dw_hdmi_cec_data cec; 2540 struct dw_hdmi *hdmi; 2541 struct resource *iores = NULL; 2542 int irq; 2543 int ret; 2544 u32 val = 1; 2545 u8 prod_id0; 2546 u8 prod_id1; 2547 u8 config0; 2548 u8 config3; 2549 2550 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 2551 if (!hdmi) 2552 return ERR_PTR(-ENOMEM); 2553 2554 hdmi->plat_data = plat_data; 2555 hdmi->dev = dev; 2556 hdmi->sample_rate = 48000; 2557 hdmi->disabled = true; 2558 hdmi->rxsense = true; 2559 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); 2560 hdmi->mc_clkdis = 0x7f; 2561 2562 mutex_init(&hdmi->mutex); 2563 mutex_init(&hdmi->audio_mutex); 2564 spin_lock_init(&hdmi->audio_lock); 2565 2566 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 2567 if (ddc_node) { 2568 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); 2569 of_node_put(ddc_node); 2570 if (!hdmi->ddc) { 2571 dev_dbg(hdmi->dev, "failed to read ddc node\n"); 2572 return ERR_PTR(-EPROBE_DEFER); 2573 } 2574 2575 } else { 2576 dev_dbg(hdmi->dev, "no ddc property found\n"); 2577 } 2578 2579 if (!plat_data->regm) { 2580 const struct regmap_config *reg_config; 2581 2582 of_property_read_u32(np, "reg-io-width", &val); 2583 switch (val) { 2584 case 4: 2585 reg_config = &hdmi_regmap_32bit_config; 2586 hdmi->reg_shift = 2; 2587 break; 2588 case 1: 2589 reg_config = &hdmi_regmap_8bit_config; 2590 break; 2591 default: 2592 dev_err(dev, "reg-io-width must be 1 or 4\n"); 2593 return ERR_PTR(-EINVAL); 2594 } 2595 2596 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2597 hdmi->regs = devm_ioremap_resource(dev, iores); 2598 if (IS_ERR(hdmi->regs)) { 2599 ret = PTR_ERR(hdmi->regs); 2600 goto err_res; 2601 } 2602 2603 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); 2604 if (IS_ERR(hdmi->regm)) { 2605 dev_err(dev, "Failed to configure regmap\n"); 2606 ret = PTR_ERR(hdmi->regm); 2607 goto err_res; 2608 } 2609 } else { 2610 hdmi->regm = plat_data->regm; 2611 } 2612 2613 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); 2614 if (IS_ERR(hdmi->isfr_clk)) { 2615 ret = PTR_ERR(hdmi->isfr_clk); 2616 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); 2617 goto err_res; 2618 } 2619 2620 ret = clk_prepare_enable(hdmi->isfr_clk); 2621 if (ret) { 2622 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret); 2623 goto err_res; 2624 } 2625 2626 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); 2627 if (IS_ERR(hdmi->iahb_clk)) { 2628 ret = PTR_ERR(hdmi->iahb_clk); 2629 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); 2630 goto err_isfr; 2631 } 2632 2633 ret = clk_prepare_enable(hdmi->iahb_clk); 2634 if (ret) { 2635 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret); 2636 goto err_isfr; 2637 } 2638 2639 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec"); 2640 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) { 2641 hdmi->cec_clk = NULL; 2642 } else if (IS_ERR(hdmi->cec_clk)) { 2643 ret = PTR_ERR(hdmi->cec_clk); 2644 if (ret != -EPROBE_DEFER) 2645 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n", 2646 ret); 2647 2648 hdmi->cec_clk = NULL; 2649 goto err_iahb; 2650 } else { 2651 ret = clk_prepare_enable(hdmi->cec_clk); 2652 if (ret) { 2653 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n", 2654 ret); 2655 goto err_iahb; 2656 } 2657 } 2658 2659 /* Product and revision IDs */ 2660 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 2661 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 2662 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); 2663 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); 2664 2665 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || 2666 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { 2667 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", 2668 hdmi->version, prod_id0, prod_id1); 2669 ret = -ENODEV; 2670 goto err_iahb; 2671 } 2672 2673 ret = dw_hdmi_detect_phy(hdmi); 2674 if (ret < 0) 2675 goto err_iahb; 2676 2677 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", 2678 hdmi->version >> 12, hdmi->version & 0xfff, 2679 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", 2680 hdmi->phy.name); 2681 2682 dw_hdmi_init_hw(hdmi); 2683 2684 irq = platform_get_irq(pdev, 0); 2685 if (irq < 0) { 2686 ret = irq; 2687 goto err_iahb; 2688 } 2689 2690 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, 2691 dw_hdmi_irq, IRQF_SHARED, 2692 dev_name(dev), hdmi); 2693 if (ret) 2694 goto err_iahb; 2695 2696 hdmi->cec_notifier = cec_notifier_get(dev); 2697 if (!hdmi->cec_notifier) { 2698 ret = -ENOMEM; 2699 goto err_iahb; 2700 } 2701 2702 /* 2703 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator 2704 * N and cts values before enabling phy 2705 */ 2706 hdmi_init_clk_regenerator(hdmi); 2707 2708 /* If DDC bus is not specified, try to register HDMI I2C bus */ 2709 if (!hdmi->ddc) { 2710 /* Look for (optional) stuff related to unwedging */ 2711 hdmi->pinctrl = devm_pinctrl_get(dev); 2712 if (!IS_ERR(hdmi->pinctrl)) { 2713 hdmi->unwedge_state = 2714 pinctrl_lookup_state(hdmi->pinctrl, "unwedge"); 2715 hdmi->default_state = 2716 pinctrl_lookup_state(hdmi->pinctrl, "default"); 2717 2718 if (IS_ERR(hdmi->default_state) || 2719 IS_ERR(hdmi->unwedge_state)) { 2720 if (!IS_ERR(hdmi->unwedge_state)) 2721 dev_warn(dev, 2722 "Unwedge requires default pinctrl\n"); 2723 hdmi->default_state = NULL; 2724 hdmi->unwedge_state = NULL; 2725 } 2726 } 2727 2728 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); 2729 if (IS_ERR(hdmi->ddc)) 2730 hdmi->ddc = NULL; 2731 } 2732 2733 hdmi->bridge.driver_private = hdmi; 2734 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; 2735 #ifdef CONFIG_OF 2736 hdmi->bridge.of_node = pdev->dev.of_node; 2737 #endif 2738 2739 memset(&pdevinfo, 0, sizeof(pdevinfo)); 2740 pdevinfo.parent = dev; 2741 pdevinfo.id = PLATFORM_DEVID_AUTO; 2742 2743 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); 2744 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 2745 2746 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { 2747 struct dw_hdmi_audio_data audio; 2748 2749 audio.phys = iores->start; 2750 audio.base = hdmi->regs; 2751 audio.irq = irq; 2752 audio.hdmi = hdmi; 2753 audio.eld = hdmi->connector.eld; 2754 hdmi->enable_audio = dw_hdmi_ahb_audio_enable; 2755 hdmi->disable_audio = dw_hdmi_ahb_audio_disable; 2756 2757 pdevinfo.name = "dw-hdmi-ahb-audio"; 2758 pdevinfo.data = &audio; 2759 pdevinfo.size_data = sizeof(audio); 2760 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2761 hdmi->audio = platform_device_register_full(&pdevinfo); 2762 } else if (config0 & HDMI_CONFIG0_I2S) { 2763 struct dw_hdmi_i2s_audio_data audio; 2764 2765 audio.hdmi = hdmi; 2766 audio.write = hdmi_writeb; 2767 audio.read = hdmi_readb; 2768 hdmi->enable_audio = dw_hdmi_i2s_audio_enable; 2769 hdmi->disable_audio = dw_hdmi_i2s_audio_disable; 2770 2771 pdevinfo.name = "dw-hdmi-i2s-audio"; 2772 pdevinfo.data = &audio; 2773 pdevinfo.size_data = sizeof(audio); 2774 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2775 hdmi->audio = platform_device_register_full(&pdevinfo); 2776 } 2777 2778 if (config0 & HDMI_CONFIG0_CEC) { 2779 cec.hdmi = hdmi; 2780 cec.ops = &dw_hdmi_cec_ops; 2781 cec.irq = irq; 2782 2783 pdevinfo.name = "dw-hdmi-cec"; 2784 pdevinfo.data = &cec; 2785 pdevinfo.size_data = sizeof(cec); 2786 pdevinfo.dma_mask = 0; 2787 2788 hdmi->cec = platform_device_register_full(&pdevinfo); 2789 } 2790 2791 return hdmi; 2792 2793 err_iahb: 2794 if (hdmi->i2c) { 2795 i2c_del_adapter(&hdmi->i2c->adap); 2796 hdmi->ddc = NULL; 2797 } 2798 2799 if (hdmi->cec_notifier) 2800 cec_notifier_put(hdmi->cec_notifier); 2801 2802 clk_disable_unprepare(hdmi->iahb_clk); 2803 if (hdmi->cec_clk) 2804 clk_disable_unprepare(hdmi->cec_clk); 2805 err_isfr: 2806 clk_disable_unprepare(hdmi->isfr_clk); 2807 err_res: 2808 i2c_put_adapter(hdmi->ddc); 2809 2810 return ERR_PTR(ret); 2811 } 2812 2813 static void __dw_hdmi_remove(struct dw_hdmi *hdmi) 2814 { 2815 if (hdmi->audio && !IS_ERR(hdmi->audio)) 2816 platform_device_unregister(hdmi->audio); 2817 if (!IS_ERR(hdmi->cec)) 2818 platform_device_unregister(hdmi->cec); 2819 2820 /* Disable all interrupts */ 2821 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2822 2823 if (hdmi->cec_notifier) 2824 cec_notifier_put(hdmi->cec_notifier); 2825 2826 clk_disable_unprepare(hdmi->iahb_clk); 2827 clk_disable_unprepare(hdmi->isfr_clk); 2828 if (hdmi->cec_clk) 2829 clk_disable_unprepare(hdmi->cec_clk); 2830 2831 if (hdmi->i2c) 2832 i2c_del_adapter(&hdmi->i2c->adap); 2833 else 2834 i2c_put_adapter(hdmi->ddc); 2835 } 2836 2837 /* ----------------------------------------------------------------------------- 2838 * Probe/remove API, used from platforms based on the DRM bridge API. 2839 */ 2840 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, 2841 const struct dw_hdmi_plat_data *plat_data) 2842 { 2843 struct dw_hdmi *hdmi; 2844 2845 hdmi = __dw_hdmi_probe(pdev, plat_data); 2846 if (IS_ERR(hdmi)) 2847 return hdmi; 2848 2849 drm_bridge_add(&hdmi->bridge); 2850 2851 return hdmi; 2852 } 2853 EXPORT_SYMBOL_GPL(dw_hdmi_probe); 2854 2855 void dw_hdmi_remove(struct dw_hdmi *hdmi) 2856 { 2857 drm_bridge_remove(&hdmi->bridge); 2858 2859 __dw_hdmi_remove(hdmi); 2860 } 2861 EXPORT_SYMBOL_GPL(dw_hdmi_remove); 2862 2863 /* ----------------------------------------------------------------------------- 2864 * Bind/unbind API, used from platforms based on the component framework. 2865 */ 2866 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, 2867 struct drm_encoder *encoder, 2868 const struct dw_hdmi_plat_data *plat_data) 2869 { 2870 struct dw_hdmi *hdmi; 2871 int ret; 2872 2873 hdmi = __dw_hdmi_probe(pdev, plat_data); 2874 if (IS_ERR(hdmi)) 2875 return hdmi; 2876 2877 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL); 2878 if (ret) { 2879 dw_hdmi_remove(hdmi); 2880 DRM_ERROR("Failed to initialize bridge with drm\n"); 2881 return ERR_PTR(ret); 2882 } 2883 2884 return hdmi; 2885 } 2886 EXPORT_SYMBOL_GPL(dw_hdmi_bind); 2887 2888 void dw_hdmi_unbind(struct dw_hdmi *hdmi) 2889 { 2890 __dw_hdmi_remove(hdmi); 2891 } 2892 EXPORT_SYMBOL_GPL(dw_hdmi_unbind); 2893 2894 void dw_hdmi_resume(struct dw_hdmi *hdmi) 2895 { 2896 dw_hdmi_init_hw(hdmi); 2897 } 2898 EXPORT_SYMBOL_GPL(dw_hdmi_resume); 2899 2900 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 2901 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); 2902 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); 2903 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>"); 2904 MODULE_DESCRIPTION("DW HDMI transmitter driver"); 2905 MODULE_LICENSE("GPL"); 2906 MODULE_ALIAS("platform:dw-hdmi"); 2907