1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DesignWare High-Definition Multimedia Interface (HDMI) driver 4 * 5 * Copyright (C) 2013-2015 Mentor Graphics Inc. 6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 8 */ 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/hdmi.h> 13 #include <linux/irq.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of_device.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/regmap.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/spinlock.h> 21 22 #include <media/cec-notifier.h> 23 24 #include <uapi/linux/media-bus-format.h> 25 #include <uapi/linux/videodev2.h> 26 27 #include <drm/bridge/dw_hdmi.h> 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_bridge.h> 30 #include <drm/drm_edid.h> 31 #include <drm/drm_of.h> 32 #include <drm/drm_print.h> 33 #include <drm/drm_probe_helper.h> 34 #include <drm/drm_scdc_helper.h> 35 36 #include "dw-hdmi-audio.h" 37 #include "dw-hdmi-cec.h" 38 #include "dw-hdmi.h" 39 40 #define DDC_CI_ADDR 0x37 41 #define DDC_SEGMENT_ADDR 0x30 42 43 #define HDMI_EDID_LEN 512 44 45 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ 46 #define SCDC_MIN_SOURCE_VERSION 0x1 47 48 #define HDMI14_MAX_TMDSCLK 340000000 49 50 enum hdmi_datamap { 51 RGB444_8B = 0x01, 52 RGB444_10B = 0x03, 53 RGB444_12B = 0x05, 54 RGB444_16B = 0x07, 55 YCbCr444_8B = 0x09, 56 YCbCr444_10B = 0x0B, 57 YCbCr444_12B = 0x0D, 58 YCbCr444_16B = 0x0F, 59 YCbCr422_8B = 0x16, 60 YCbCr422_10B = 0x14, 61 YCbCr422_12B = 0x12, 62 }; 63 64 static const u16 csc_coeff_default[3][4] = { 65 { 0x2000, 0x0000, 0x0000, 0x0000 }, 66 { 0x0000, 0x2000, 0x0000, 0x0000 }, 67 { 0x0000, 0x0000, 0x2000, 0x0000 } 68 }; 69 70 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 71 { 0x2000, 0x6926, 0x74fd, 0x010e }, 72 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 73 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 74 }; 75 76 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 77 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 78 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 79 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 80 }; 81 82 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 83 { 0x2591, 0x1322, 0x074b, 0x0000 }, 84 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 85 { 0x6acd, 0x7534, 0x2000, 0x0200 } 86 }; 87 88 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 89 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 90 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 91 { 0x6756, 0x78ab, 0x2000, 0x0200 } 92 }; 93 94 struct hdmi_vmode { 95 bool mdataenablepolarity; 96 97 unsigned int mpixelclock; 98 unsigned int mpixelrepetitioninput; 99 unsigned int mpixelrepetitionoutput; 100 unsigned int mtmdsclock; 101 }; 102 103 struct hdmi_data_info { 104 unsigned int enc_in_bus_format; 105 unsigned int enc_out_bus_format; 106 unsigned int enc_in_encoding; 107 unsigned int enc_out_encoding; 108 unsigned int pix_repet_factor; 109 unsigned int hdcp_enable; 110 struct hdmi_vmode video_mode; 111 }; 112 113 struct dw_hdmi_i2c { 114 struct i2c_adapter adap; 115 116 struct mutex lock; /* used to serialize data transfers */ 117 struct completion cmp; 118 u8 stat; 119 120 u8 slave_reg; 121 bool is_regaddr; 122 bool is_segment; 123 }; 124 125 struct dw_hdmi_phy_data { 126 enum dw_hdmi_phy_type type; 127 const char *name; 128 unsigned int gen; 129 bool has_svsret; 130 int (*configure)(struct dw_hdmi *hdmi, 131 const struct dw_hdmi_plat_data *pdata, 132 unsigned long mpixelclock); 133 }; 134 135 struct dw_hdmi { 136 struct drm_connector connector; 137 struct drm_bridge bridge; 138 139 unsigned int version; 140 141 struct platform_device *audio; 142 struct platform_device *cec; 143 struct device *dev; 144 struct clk *isfr_clk; 145 struct clk *iahb_clk; 146 struct clk *cec_clk; 147 struct dw_hdmi_i2c *i2c; 148 149 struct hdmi_data_info hdmi_data; 150 const struct dw_hdmi_plat_data *plat_data; 151 152 int vic; 153 154 u8 edid[HDMI_EDID_LEN]; 155 156 struct { 157 const struct dw_hdmi_phy_ops *ops; 158 const char *name; 159 void *data; 160 bool enabled; 161 } phy; 162 163 struct drm_display_mode previous_mode; 164 165 struct i2c_adapter *ddc; 166 void __iomem *regs; 167 bool sink_is_hdmi; 168 bool sink_has_audio; 169 170 struct pinctrl *pinctrl; 171 struct pinctrl_state *default_state; 172 struct pinctrl_state *unwedge_state; 173 174 struct mutex mutex; /* for state below and previous_mode */ 175 enum drm_connector_force force; /* mutex-protected force state */ 176 bool disabled; /* DRM has disabled our bridge */ 177 bool bridge_is_on; /* indicates the bridge is on */ 178 bool rxsense; /* rxsense state */ 179 u8 phy_mask; /* desired phy int mask settings */ 180 u8 mc_clkdis; /* clock disable register */ 181 182 spinlock_t audio_lock; 183 struct mutex audio_mutex; 184 unsigned int sample_rate; 185 unsigned int audio_cts; 186 unsigned int audio_n; 187 bool audio_enable; 188 189 unsigned int reg_shift; 190 struct regmap *regm; 191 void (*enable_audio)(struct dw_hdmi *hdmi); 192 void (*disable_audio)(struct dw_hdmi *hdmi); 193 194 struct mutex cec_notifier_mutex; 195 struct cec_notifier *cec_notifier; 196 }; 197 198 #define HDMI_IH_PHY_STAT0_RX_SENSE \ 199 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ 200 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) 201 202 #define HDMI_PHY_RX_SENSE \ 203 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ 204 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) 205 206 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 207 { 208 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); 209 } 210 211 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 212 { 213 unsigned int val = 0; 214 215 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); 216 217 return val; 218 } 219 220 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 221 { 222 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); 223 } 224 225 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 226 u8 shift, u8 mask) 227 { 228 hdmi_modb(hdmi, data << shift, mask, reg); 229 } 230 231 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 232 { 233 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, 234 HDMI_PHY_I2CM_INT_ADDR); 235 236 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | 237 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, 238 HDMI_PHY_I2CM_CTLINT_ADDR); 239 240 /* Software reset */ 241 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 242 243 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ 244 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); 245 246 /* Set done, not acknowledged and arbitration interrupt polarities */ 247 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 248 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 249 HDMI_I2CM_CTLINT); 250 251 /* Clear DONE and ERROR interrupts */ 252 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 253 HDMI_IH_I2CM_STAT0); 254 255 /* Mute DONE and ERROR interrupts */ 256 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 257 HDMI_IH_MUTE_I2CM_STAT0); 258 } 259 260 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi) 261 { 262 /* If no unwedge state then give up */ 263 if (!hdmi->unwedge_state) 264 return false; 265 266 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n"); 267 268 /* 269 * This is a huge hack to workaround a problem where the dw_hdmi i2c 270 * bus could sometimes get wedged. Once wedged there doesn't appear 271 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ) 272 * other than pulsing the SDA line. 273 * 274 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi) 275 * by: 276 * 1. Remux the pin as a GPIO output, driven low. 277 * 2. Wait a little while. 1 ms seems to work, but we'll do 10. 278 * 3. Immediately jump to remux the pin as dw_hdmi i2c again. 279 * 280 * At the moment of remuxing, the line will still be low due to its 281 * recent stint as an output, but then it will be pulled high by the 282 * (presumed) external pullup. dw_hdmi seems to see this as a rising 283 * edge and that seems to get it out of its jam. 284 * 285 * This wedging was only ever seen on one TV, and only on one of 286 * its HDMI ports. It happened when the TV was powered on while the 287 * device was plugged in. A scope trace shows the TV bringing both SDA 288 * and SCL low, then bringing them both back up at roughly the same 289 * time. Presumably this confuses dw_hdmi because it saw activity but 290 * no real STOP (maybe it thinks there's another master on the bus?). 291 * Giving it a clean rising edge of SDA while SCL is already high 292 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out 293 * of its stupor. 294 * 295 * Note that after coming back alive, transfers seem to immediately 296 * resume, so if we unwedge due to a timeout we should wait a little 297 * longer for our transfer to finish, since it might have just started 298 * now. 299 */ 300 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state); 301 msleep(10); 302 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state); 303 304 return true; 305 } 306 307 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi) 308 { 309 struct dw_hdmi_i2c *i2c = hdmi->i2c; 310 int stat; 311 312 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 313 if (!stat) { 314 /* If we can't unwedge, return timeout */ 315 if (!dw_hdmi_i2c_unwedge(hdmi)) 316 return -EAGAIN; 317 318 /* We tried to unwedge; give it another chance */ 319 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 320 if (!stat) 321 return -EAGAIN; 322 } 323 324 /* Check for error condition on the bus */ 325 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 326 return -EIO; 327 328 return 0; 329 } 330 331 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 332 unsigned char *buf, unsigned int length) 333 { 334 struct dw_hdmi_i2c *i2c = hdmi->i2c; 335 int ret; 336 337 if (!i2c->is_regaddr) { 338 dev_dbg(hdmi->dev, "set read register address to 0\n"); 339 i2c->slave_reg = 0x00; 340 i2c->is_regaddr = true; 341 } 342 343 while (length--) { 344 reinit_completion(&i2c->cmp); 345 346 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 347 if (i2c->is_segment) 348 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 349 HDMI_I2CM_OPERATION); 350 else 351 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 352 HDMI_I2CM_OPERATION); 353 354 ret = dw_hdmi_i2c_wait(hdmi); 355 if (ret) 356 return ret; 357 358 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 359 } 360 i2c->is_segment = false; 361 362 return 0; 363 } 364 365 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 366 unsigned char *buf, unsigned int length) 367 { 368 struct dw_hdmi_i2c *i2c = hdmi->i2c; 369 int ret; 370 371 if (!i2c->is_regaddr) { 372 /* Use the first write byte as register address */ 373 i2c->slave_reg = buf[0]; 374 length--; 375 buf++; 376 i2c->is_regaddr = true; 377 } 378 379 while (length--) { 380 reinit_completion(&i2c->cmp); 381 382 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 383 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 384 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 385 HDMI_I2CM_OPERATION); 386 387 ret = dw_hdmi_i2c_wait(hdmi); 388 if (ret) 389 return ret; 390 } 391 392 return 0; 393 } 394 395 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, 396 struct i2c_msg *msgs, int num) 397 { 398 struct dw_hdmi *hdmi = i2c_get_adapdata(adap); 399 struct dw_hdmi_i2c *i2c = hdmi->i2c; 400 u8 addr = msgs[0].addr; 401 int i, ret = 0; 402 403 if (addr == DDC_CI_ADDR) 404 /* 405 * The internal I2C controller does not support the multi-byte 406 * read and write operations needed for DDC/CI. 407 * TOFIX: Blacklist the DDC/CI address until we filter out 408 * unsupported I2C operations. 409 */ 410 return -EOPNOTSUPP; 411 412 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); 413 414 for (i = 0; i < num; i++) { 415 if (msgs[i].len == 0) { 416 dev_dbg(hdmi->dev, 417 "unsupported transfer %d/%d, no data\n", 418 i + 1, num); 419 return -EOPNOTSUPP; 420 } 421 } 422 423 mutex_lock(&i2c->lock); 424 425 /* Unmute DONE and ERROR interrupts */ 426 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 427 428 /* Set slave device address taken from the first I2C message */ 429 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 430 431 /* Set slave device register address on transfer */ 432 i2c->is_regaddr = false; 433 434 /* Set segment pointer for I2C extended read mode operation */ 435 i2c->is_segment = false; 436 437 for (i = 0; i < num; i++) { 438 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", 439 i + 1, num, msgs[i].len, msgs[i].flags); 440 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 441 i2c->is_segment = true; 442 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 443 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 444 } else { 445 if (msgs[i].flags & I2C_M_RD) 446 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 447 msgs[i].len); 448 else 449 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 450 msgs[i].len); 451 } 452 if (ret < 0) 453 break; 454 } 455 456 if (!ret) 457 ret = num; 458 459 /* Mute DONE and ERROR interrupts */ 460 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 461 HDMI_IH_MUTE_I2CM_STAT0); 462 463 mutex_unlock(&i2c->lock); 464 465 return ret; 466 } 467 468 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) 469 { 470 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 471 } 472 473 static const struct i2c_algorithm dw_hdmi_algorithm = { 474 .master_xfer = dw_hdmi_i2c_xfer, 475 .functionality = dw_hdmi_i2c_func, 476 }; 477 478 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) 479 { 480 struct i2c_adapter *adap; 481 struct dw_hdmi_i2c *i2c; 482 int ret; 483 484 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 485 if (!i2c) 486 return ERR_PTR(-ENOMEM); 487 488 mutex_init(&i2c->lock); 489 init_completion(&i2c->cmp); 490 491 adap = &i2c->adap; 492 adap->class = I2C_CLASS_DDC; 493 adap->owner = THIS_MODULE; 494 adap->dev.parent = hdmi->dev; 495 adap->algo = &dw_hdmi_algorithm; 496 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name)); 497 i2c_set_adapdata(adap, hdmi); 498 499 ret = i2c_add_adapter(adap); 500 if (ret) { 501 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 502 devm_kfree(hdmi->dev, i2c); 503 return ERR_PTR(ret); 504 } 505 506 hdmi->i2c = i2c; 507 508 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 509 510 return adap; 511 } 512 513 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 514 unsigned int n) 515 { 516 /* Must be set/cleared first */ 517 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 518 519 /* nshift factor = 0 */ 520 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 521 522 /* Use automatic CTS generation mode when CTS is not set */ 523 if (cts) 524 hdmi_writeb(hdmi, ((cts >> 16) & 525 HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 526 HDMI_AUD_CTS3_CTS_MANUAL, 527 HDMI_AUD_CTS3); 528 else 529 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3); 530 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 531 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 532 533 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 534 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 535 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 536 } 537 538 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) 539 { 540 unsigned int n = (128 * freq) / 1000; 541 unsigned int mult = 1; 542 543 while (freq > 48000) { 544 mult *= 2; 545 freq /= 2; 546 } 547 548 switch (freq) { 549 case 32000: 550 if (pixel_clk == 25175000) 551 n = 4576; 552 else if (pixel_clk == 27027000) 553 n = 4096; 554 else if (pixel_clk == 74176000 || pixel_clk == 148352000) 555 n = 11648; 556 else 557 n = 4096; 558 n *= mult; 559 break; 560 561 case 44100: 562 if (pixel_clk == 25175000) 563 n = 7007; 564 else if (pixel_clk == 74176000) 565 n = 17836; 566 else if (pixel_clk == 148352000) 567 n = 8918; 568 else 569 n = 6272; 570 n *= mult; 571 break; 572 573 case 48000: 574 if (pixel_clk == 25175000) 575 n = 6864; 576 else if (pixel_clk == 27027000) 577 n = 6144; 578 else if (pixel_clk == 74176000) 579 n = 11648; 580 else if (pixel_clk == 148352000) 581 n = 5824; 582 else 583 n = 6144; 584 n *= mult; 585 break; 586 587 default: 588 break; 589 } 590 591 return n; 592 } 593 594 /* 595 * When transmitting IEC60958 linear PCM audio, these registers allow to 596 * configure the channel status information of all the channel status 597 * bits in the IEC60958 frame. For the moment this configuration is only 598 * used when the I2S audio interface, General Purpose Audio (GPA), 599 * or AHB audio DMA (AHBAUDDMA) interface is active 600 * (for S/PDIF interface this information comes from the stream). 601 */ 602 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, 603 u8 *channel_status) 604 { 605 /* 606 * Set channel status register for frequency and word length. 607 * Use default values for other registers. 608 */ 609 hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7); 610 hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8); 611 } 612 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status); 613 614 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, 615 unsigned long pixel_clk, unsigned int sample_rate) 616 { 617 unsigned long ftdms = pixel_clk; 618 unsigned int n, cts; 619 u8 config3; 620 u64 tmp; 621 622 n = hdmi_compute_n(sample_rate, pixel_clk); 623 624 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 625 626 /* Only compute CTS when using internal AHB audio */ 627 if (config3 & HDMI_CONFIG3_AHBAUDDMA) { 628 /* 629 * Compute the CTS value from the N value. Note that CTS and N 630 * can be up to 20 bits in total, so we need 64-bit math. Also 631 * note that our TDMS clock is not fully accurate; it is 632 * accurate to kHz. This can introduce an unnecessary remainder 633 * in the calculation below, so we don't try to warn about that. 634 */ 635 tmp = (u64)ftdms * n; 636 do_div(tmp, 128 * sample_rate); 637 cts = tmp; 638 639 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", 640 __func__, sample_rate, 641 ftdms / 1000000, (ftdms / 1000) % 1000, 642 n, cts); 643 } else { 644 cts = 0; 645 } 646 647 spin_lock_irq(&hdmi->audio_lock); 648 hdmi->audio_n = n; 649 hdmi->audio_cts = cts; 650 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 651 spin_unlock_irq(&hdmi->audio_lock); 652 } 653 654 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) 655 { 656 mutex_lock(&hdmi->audio_mutex); 657 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); 658 mutex_unlock(&hdmi->audio_mutex); 659 } 660 661 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 662 { 663 mutex_lock(&hdmi->audio_mutex); 664 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 665 hdmi->sample_rate); 666 mutex_unlock(&hdmi->audio_mutex); 667 } 668 669 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 670 { 671 mutex_lock(&hdmi->audio_mutex); 672 hdmi->sample_rate = rate; 673 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 674 hdmi->sample_rate); 675 mutex_unlock(&hdmi->audio_mutex); 676 } 677 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); 678 679 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt) 680 { 681 u8 layout; 682 683 mutex_lock(&hdmi->audio_mutex); 684 685 /* 686 * For >2 channel PCM audio, we need to select layout 1 687 * and set an appropriate channel map. 688 */ 689 if (cnt > 2) 690 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1; 691 else 692 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0; 693 694 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK, 695 HDMI_FC_AUDSCONF); 696 697 /* Set the audio infoframes channel count */ 698 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET, 699 HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0); 700 701 mutex_unlock(&hdmi->audio_mutex); 702 } 703 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count); 704 705 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca) 706 { 707 mutex_lock(&hdmi->audio_mutex); 708 709 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2); 710 711 mutex_unlock(&hdmi->audio_mutex); 712 } 713 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation); 714 715 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) 716 { 717 if (enable) 718 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; 719 else 720 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; 721 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 722 } 723 724 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi) 725 { 726 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 727 } 728 729 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi) 730 { 731 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 732 } 733 734 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi) 735 { 736 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 737 hdmi_enable_audio_clk(hdmi, true); 738 } 739 740 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi) 741 { 742 hdmi_enable_audio_clk(hdmi, false); 743 } 744 745 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 746 { 747 unsigned long flags; 748 749 spin_lock_irqsave(&hdmi->audio_lock, flags); 750 hdmi->audio_enable = true; 751 if (hdmi->enable_audio) 752 hdmi->enable_audio(hdmi); 753 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 754 } 755 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); 756 757 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 758 { 759 unsigned long flags; 760 761 spin_lock_irqsave(&hdmi->audio_lock, flags); 762 hdmi->audio_enable = false; 763 if (hdmi->disable_audio) 764 hdmi->disable_audio(hdmi); 765 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 766 } 767 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); 768 769 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 770 { 771 switch (bus_format) { 772 case MEDIA_BUS_FMT_RGB888_1X24: 773 case MEDIA_BUS_FMT_RGB101010_1X30: 774 case MEDIA_BUS_FMT_RGB121212_1X36: 775 case MEDIA_BUS_FMT_RGB161616_1X48: 776 return true; 777 778 default: 779 return false; 780 } 781 } 782 783 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 784 { 785 switch (bus_format) { 786 case MEDIA_BUS_FMT_YUV8_1X24: 787 case MEDIA_BUS_FMT_YUV10_1X30: 788 case MEDIA_BUS_FMT_YUV12_1X36: 789 case MEDIA_BUS_FMT_YUV16_1X48: 790 return true; 791 792 default: 793 return false; 794 } 795 } 796 797 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 798 { 799 switch (bus_format) { 800 case MEDIA_BUS_FMT_UYVY8_1X16: 801 case MEDIA_BUS_FMT_UYVY10_1X20: 802 case MEDIA_BUS_FMT_UYVY12_1X24: 803 return true; 804 805 default: 806 return false; 807 } 808 } 809 810 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 811 { 812 switch (bus_format) { 813 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 814 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 815 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 816 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 817 return true; 818 819 default: 820 return false; 821 } 822 } 823 824 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 825 { 826 switch (bus_format) { 827 case MEDIA_BUS_FMT_RGB888_1X24: 828 case MEDIA_BUS_FMT_YUV8_1X24: 829 case MEDIA_BUS_FMT_UYVY8_1X16: 830 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 831 return 8; 832 833 case MEDIA_BUS_FMT_RGB101010_1X30: 834 case MEDIA_BUS_FMT_YUV10_1X30: 835 case MEDIA_BUS_FMT_UYVY10_1X20: 836 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 837 return 10; 838 839 case MEDIA_BUS_FMT_RGB121212_1X36: 840 case MEDIA_BUS_FMT_YUV12_1X36: 841 case MEDIA_BUS_FMT_UYVY12_1X24: 842 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 843 return 12; 844 845 case MEDIA_BUS_FMT_RGB161616_1X48: 846 case MEDIA_BUS_FMT_YUV16_1X48: 847 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 848 return 16; 849 850 default: 851 return 0; 852 } 853 } 854 855 /* 856 * this submodule is responsible for the video data synchronization. 857 * for example, for RGB 4:4:4 input, the data map is defined as 858 * pin{47~40} <==> R[7:0] 859 * pin{31~24} <==> G[7:0] 860 * pin{15~8} <==> B[7:0] 861 */ 862 static void hdmi_video_sample(struct dw_hdmi *hdmi) 863 { 864 int color_format = 0; 865 u8 val; 866 867 switch (hdmi->hdmi_data.enc_in_bus_format) { 868 case MEDIA_BUS_FMT_RGB888_1X24: 869 color_format = 0x01; 870 break; 871 case MEDIA_BUS_FMT_RGB101010_1X30: 872 color_format = 0x03; 873 break; 874 case MEDIA_BUS_FMT_RGB121212_1X36: 875 color_format = 0x05; 876 break; 877 case MEDIA_BUS_FMT_RGB161616_1X48: 878 color_format = 0x07; 879 break; 880 881 case MEDIA_BUS_FMT_YUV8_1X24: 882 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 883 color_format = 0x09; 884 break; 885 case MEDIA_BUS_FMT_YUV10_1X30: 886 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 887 color_format = 0x0B; 888 break; 889 case MEDIA_BUS_FMT_YUV12_1X36: 890 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 891 color_format = 0x0D; 892 break; 893 case MEDIA_BUS_FMT_YUV16_1X48: 894 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 895 color_format = 0x0F; 896 break; 897 898 case MEDIA_BUS_FMT_UYVY8_1X16: 899 color_format = 0x16; 900 break; 901 case MEDIA_BUS_FMT_UYVY10_1X20: 902 color_format = 0x14; 903 break; 904 case MEDIA_BUS_FMT_UYVY12_1X24: 905 color_format = 0x12; 906 break; 907 908 default: 909 return; 910 } 911 912 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 913 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 914 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 915 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 916 917 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 918 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 919 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 920 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 921 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 922 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 923 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 924 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 925 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 926 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 927 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 928 } 929 930 static int is_color_space_conversion(struct dw_hdmi *hdmi) 931 { 932 return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format; 933 } 934 935 static int is_color_space_decimation(struct dw_hdmi *hdmi) 936 { 937 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 938 return 0; 939 940 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 941 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 942 return 1; 943 944 return 0; 945 } 946 947 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 948 { 949 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 950 return 0; 951 952 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 953 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 954 return 1; 955 956 return 0; 957 } 958 959 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 960 { 961 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 962 unsigned i; 963 u32 csc_scale = 1; 964 965 if (is_color_space_conversion(hdmi)) { 966 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 967 if (hdmi->hdmi_data.enc_out_encoding == 968 V4L2_YCBCR_ENC_601) 969 csc_coeff = &csc_coeff_rgb_out_eitu601; 970 else 971 csc_coeff = &csc_coeff_rgb_out_eitu709; 972 } else if (hdmi_bus_fmt_is_rgb( 973 hdmi->hdmi_data.enc_in_bus_format)) { 974 if (hdmi->hdmi_data.enc_out_encoding == 975 V4L2_YCBCR_ENC_601) 976 csc_coeff = &csc_coeff_rgb_in_eitu601; 977 else 978 csc_coeff = &csc_coeff_rgb_in_eitu709; 979 csc_scale = 0; 980 } 981 } 982 983 /* The CSC registers are sequential, alternating MSB then LSB */ 984 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 985 u16 coeff_a = (*csc_coeff)[0][i]; 986 u16 coeff_b = (*csc_coeff)[1][i]; 987 u16 coeff_c = (*csc_coeff)[2][i]; 988 989 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 990 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 991 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 992 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 993 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 994 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 995 } 996 997 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 998 HDMI_CSC_SCALE); 999 } 1000 1001 static void hdmi_video_csc(struct dw_hdmi *hdmi) 1002 { 1003 int color_depth = 0; 1004 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 1005 int decimation = 0; 1006 1007 /* YCC422 interpolation to 444 mode */ 1008 if (is_color_space_interpolation(hdmi)) 1009 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 1010 else if (is_color_space_decimation(hdmi)) 1011 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 1012 1013 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 1014 case 8: 1015 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 1016 break; 1017 case 10: 1018 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 1019 break; 1020 case 12: 1021 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 1022 break; 1023 case 16: 1024 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 1025 break; 1026 1027 default: 1028 return; 1029 } 1030 1031 /* Configure the CSC registers */ 1032 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 1033 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 1034 HDMI_CSC_SCALE); 1035 1036 dw_hdmi_update_csc_coeffs(hdmi); 1037 } 1038 1039 /* 1040 * HDMI video packetizer is used to packetize the data. 1041 * for example, if input is YCC422 mode or repeater is used, 1042 * data should be repacked this module can be bypassed. 1043 */ 1044 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 1045 { 1046 unsigned int color_depth = 0; 1047 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 1048 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 1049 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1050 u8 val, vp_conf; 1051 1052 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1053 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 1054 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1055 switch (hdmi_bus_fmt_color_depth( 1056 hdmi->hdmi_data.enc_out_bus_format)) { 1057 case 8: 1058 color_depth = 4; 1059 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1060 break; 1061 case 10: 1062 color_depth = 5; 1063 break; 1064 case 12: 1065 color_depth = 6; 1066 break; 1067 case 16: 1068 color_depth = 7; 1069 break; 1070 default: 1071 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1072 } 1073 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1074 switch (hdmi_bus_fmt_color_depth( 1075 hdmi->hdmi_data.enc_out_bus_format)) { 1076 case 0: 1077 case 8: 1078 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1079 break; 1080 case 10: 1081 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1082 break; 1083 case 12: 1084 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1085 break; 1086 1087 default: 1088 return; 1089 } 1090 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1091 } else { 1092 return; 1093 } 1094 1095 /* set the packetizer registers */ 1096 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1097 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | 1098 ((hdmi_data->pix_repet_factor << 1099 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & 1100 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); 1101 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1102 1103 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1104 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1105 1106 /* Data from pixel repeater block */ 1107 if (hdmi_data->pix_repet_factor > 1) { 1108 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1109 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1110 } else { /* data from packetizer block */ 1111 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1112 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1113 } 1114 1115 hdmi_modb(hdmi, vp_conf, 1116 HDMI_VP_CONF_PR_EN_MASK | 1117 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1118 1119 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 1120 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 1121 1122 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1123 1124 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1125 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1126 HDMI_VP_CONF_PP_EN_ENABLE | 1127 HDMI_VP_CONF_YCC422_EN_DISABLE; 1128 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1129 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1130 HDMI_VP_CONF_PP_EN_DISABLE | 1131 HDMI_VP_CONF_YCC422_EN_ENABLE; 1132 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1133 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1134 HDMI_VP_CONF_PP_EN_DISABLE | 1135 HDMI_VP_CONF_YCC422_EN_DISABLE; 1136 } else { 1137 return; 1138 } 1139 1140 hdmi_modb(hdmi, vp_conf, 1141 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1142 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1143 1144 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1145 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1146 HDMI_VP_STUFF_PP_STUFFING_MASK | 1147 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1148 1149 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1150 HDMI_VP_CONF); 1151 } 1152 1153 /* ----------------------------------------------------------------------------- 1154 * Synopsys PHY Handling 1155 */ 1156 1157 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 1158 unsigned char bit) 1159 { 1160 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 1161 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 1162 } 1163 1164 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 1165 { 1166 u32 val; 1167 1168 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 1169 if (msec-- == 0) 1170 return false; 1171 udelay(1000); 1172 } 1173 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 1174 1175 return true; 1176 } 1177 1178 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 1179 unsigned char addr) 1180 { 1181 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 1182 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 1183 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 1184 HDMI_PHY_I2CM_DATAO_1_ADDR); 1185 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 1186 HDMI_PHY_I2CM_DATAO_0_ADDR); 1187 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 1188 HDMI_PHY_I2CM_OPERATION_ADDR); 1189 hdmi_phy_wait_i2c_done(hdmi, 1000); 1190 } 1191 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); 1192 1193 /* Filter out invalid setups to avoid configuring SCDC and scrambling */ 1194 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi) 1195 { 1196 struct drm_display_info *display = &hdmi->connector.display_info; 1197 1198 /* Completely disable SCDC support for older controllers */ 1199 if (hdmi->version < 0x200a) 1200 return false; 1201 1202 /* Disable if no DDC bus */ 1203 if (!hdmi->ddc) 1204 return false; 1205 1206 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */ 1207 if (!display->hdmi.scdc.supported || 1208 !display->hdmi.scdc.scrambling.supported) 1209 return false; 1210 1211 /* 1212 * Disable if display only support low TMDS rates and scrambling 1213 * for low rates is not supported either 1214 */ 1215 if (!display->hdmi.scdc.scrambling.low_rates && 1216 display->max_tmds_clock <= 340000) 1217 return false; 1218 1219 return true; 1220 } 1221 1222 /* 1223 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates: 1224 * - The Source shall suspend transmission of the TMDS clock and data 1225 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it 1226 * from a 0 to a 1 or from a 1 to a 0 1227 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from 1228 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming 1229 * transmission of TMDS clock and data 1230 * 1231 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio() 1232 * helper should called right before enabling the TMDS Clock and Data in 1233 * the PHY configuration callback. 1234 */ 1235 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi) 1236 { 1237 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1238 1239 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 1240 if (dw_hdmi_support_scdc(hdmi)) { 1241 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1242 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1); 1243 else 1244 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0); 1245 } 1246 } 1247 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio); 1248 1249 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 1250 { 1251 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 1252 HDMI_PHY_CONF0_PDZ_OFFSET, 1253 HDMI_PHY_CONF0_PDZ_MASK); 1254 } 1255 1256 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 1257 { 1258 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1259 HDMI_PHY_CONF0_ENTMDS_OFFSET, 1260 HDMI_PHY_CONF0_ENTMDS_MASK); 1261 } 1262 1263 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 1264 { 1265 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1266 HDMI_PHY_CONF0_SVSRET_OFFSET, 1267 HDMI_PHY_CONF0_SVSRET_MASK); 1268 } 1269 1270 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 1271 { 1272 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1273 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 1274 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 1275 } 1276 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq); 1277 1278 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 1279 { 1280 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1281 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 1282 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 1283 } 1284 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron); 1285 1286 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 1287 { 1288 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1289 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 1290 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 1291 } 1292 1293 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 1294 { 1295 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1296 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 1297 HDMI_PHY_CONF0_SELDIPIF_MASK); 1298 } 1299 1300 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi) 1301 { 1302 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 1303 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1304 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1305 } 1306 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset); 1307 1308 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) 1309 { 1310 hdmi_phy_test_clear(hdmi, 1); 1311 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR); 1312 hdmi_phy_test_clear(hdmi, 0); 1313 } 1314 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr); 1315 1316 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 1317 { 1318 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1319 unsigned int i; 1320 u16 val; 1321 1322 if (phy->gen == 1) { 1323 dw_hdmi_phy_enable_tmds(hdmi, 0); 1324 dw_hdmi_phy_enable_powerdown(hdmi, true); 1325 return; 1326 } 1327 1328 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 1329 1330 /* 1331 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 1332 * to low power mode. 1333 */ 1334 for (i = 0; i < 5; ++i) { 1335 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 1336 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 1337 break; 1338 1339 usleep_range(1000, 2000); 1340 } 1341 1342 if (val & HDMI_PHY_TX_PHY_LOCK) 1343 dev_warn(hdmi->dev, "PHY failed to power down\n"); 1344 else 1345 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); 1346 1347 dw_hdmi_phy_gen2_pddq(hdmi, 1); 1348 } 1349 1350 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 1351 { 1352 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1353 unsigned int i; 1354 u8 val; 1355 1356 if (phy->gen == 1) { 1357 dw_hdmi_phy_enable_powerdown(hdmi, false); 1358 1359 /* Toggle TMDS enable. */ 1360 dw_hdmi_phy_enable_tmds(hdmi, 0); 1361 dw_hdmi_phy_enable_tmds(hdmi, 1); 1362 return 0; 1363 } 1364 1365 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 1366 dw_hdmi_phy_gen2_pddq(hdmi, 0); 1367 1368 /* Wait for PHY PLL lock */ 1369 for (i = 0; i < 5; ++i) { 1370 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 1371 if (val) 1372 break; 1373 1374 usleep_range(1000, 2000); 1375 } 1376 1377 if (!val) { 1378 dev_err(hdmi->dev, "PHY PLL failed to lock\n"); 1379 return -ETIMEDOUT; 1380 } 1381 1382 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); 1383 return 0; 1384 } 1385 1386 /* 1387 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 1388 * information the DWC MHL PHY has the same register layout and is thus also 1389 * supported by this function. 1390 */ 1391 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 1392 const struct dw_hdmi_plat_data *pdata, 1393 unsigned long mpixelclock) 1394 { 1395 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 1396 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 1397 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 1398 1399 /* TOFIX Will need 420 specific PHY configuration tables */ 1400 1401 /* PLL/MPLL Cfg - always match on final entry */ 1402 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 1403 if (mpixelclock <= mpll_config->mpixelclock) 1404 break; 1405 1406 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 1407 if (mpixelclock <= curr_ctrl->mpixelclock) 1408 break; 1409 1410 for (; phy_config->mpixelclock != ~0UL; phy_config++) 1411 if (mpixelclock <= phy_config->mpixelclock) 1412 break; 1413 1414 if (mpll_config->mpixelclock == ~0UL || 1415 curr_ctrl->mpixelclock == ~0UL || 1416 phy_config->mpixelclock == ~0UL) 1417 return -EINVAL; 1418 1419 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 1420 HDMI_3D_TX_PHY_CPCE_CTRL); 1421 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 1422 HDMI_3D_TX_PHY_GMPCTRL); 1423 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 1424 HDMI_3D_TX_PHY_CURRCTRL); 1425 1426 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 1427 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 1428 HDMI_3D_TX_PHY_MSM_CTRL); 1429 1430 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 1431 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 1432 HDMI_3D_TX_PHY_CKSYMTXCTRL); 1433 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 1434 HDMI_3D_TX_PHY_VLEVCTRL); 1435 1436 /* Override and disable clock termination. */ 1437 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 1438 HDMI_3D_TX_PHY_CKCALCTRL); 1439 1440 return 0; 1441 } 1442 1443 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 1444 { 1445 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1446 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 1447 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 1448 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1449 int ret; 1450 1451 dw_hdmi_phy_power_off(hdmi); 1452 1453 dw_hdmi_set_high_tmds_clock_ratio(hdmi); 1454 1455 /* Leave low power consumption mode by asserting SVSRET. */ 1456 if (phy->has_svsret) 1457 dw_hdmi_phy_enable_svsret(hdmi, 1); 1458 1459 dw_hdmi_phy_reset(hdmi); 1460 1461 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 1462 1463 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); 1464 1465 /* Write to the PHY as configured by the platform */ 1466 if (pdata->configure_phy) 1467 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 1468 else 1469 ret = phy->configure(hdmi, pdata, mpixelclock); 1470 if (ret) { 1471 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", 1472 mpixelclock); 1473 return ret; 1474 } 1475 1476 /* Wait for resuming transmission of TMDS clock and data */ 1477 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1478 msleep(100); 1479 1480 return dw_hdmi_phy_power_on(hdmi); 1481 } 1482 1483 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 1484 struct drm_display_mode *mode) 1485 { 1486 int i, ret; 1487 1488 /* HDMI Phy spec says to do the phy initialization sequence twice */ 1489 for (i = 0; i < 2; i++) { 1490 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 1491 dw_hdmi_phy_sel_interface_control(hdmi, 0); 1492 1493 ret = hdmi_phy_configure(hdmi); 1494 if (ret) 1495 return ret; 1496 } 1497 1498 return 0; 1499 } 1500 1501 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 1502 { 1503 dw_hdmi_phy_power_off(hdmi); 1504 } 1505 1506 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 1507 void *data) 1508 { 1509 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 1510 connector_status_connected : connector_status_disconnected; 1511 } 1512 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); 1513 1514 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 1515 bool force, bool disabled, bool rxsense) 1516 { 1517 u8 old_mask = hdmi->phy_mask; 1518 1519 if (force || disabled || !rxsense) 1520 hdmi->phy_mask |= HDMI_PHY_RX_SENSE; 1521 else 1522 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; 1523 1524 if (old_mask != hdmi->phy_mask) 1525 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1526 } 1527 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd); 1528 1529 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) 1530 { 1531 /* 1532 * Configure the PHY RX SENSE and HPD interrupts polarities and clear 1533 * any pending interrupt. 1534 */ 1535 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); 1536 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1537 HDMI_IH_PHY_STAT0); 1538 1539 /* Enable cable hot plug irq. */ 1540 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1541 1542 /* Clear and unmute interrupts. */ 1543 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1544 HDMI_IH_PHY_STAT0); 1545 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 1546 HDMI_IH_MUTE_PHY_STAT0); 1547 } 1548 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd); 1549 1550 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 1551 .init = dw_hdmi_phy_init, 1552 .disable = dw_hdmi_phy_disable, 1553 .read_hpd = dw_hdmi_phy_read_hpd, 1554 .update_hpd = dw_hdmi_phy_update_hpd, 1555 .setup_hpd = dw_hdmi_phy_setup_hpd, 1556 }; 1557 1558 /* ----------------------------------------------------------------------------- 1559 * HDMI TX Setup 1560 */ 1561 1562 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) 1563 { 1564 u8 de; 1565 1566 if (hdmi->hdmi_data.video_mode.mdataenablepolarity) 1567 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1568 else 1569 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; 1570 1571 /* disable rx detect */ 1572 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, 1573 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 1574 1575 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); 1576 1577 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, 1578 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); 1579 } 1580 1581 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1582 { 1583 struct hdmi_avi_infoframe frame; 1584 u8 val; 1585 1586 /* Initialise info frame from DRM mode */ 1587 drm_hdmi_avi_infoframe_from_display_mode(&frame, 1588 &hdmi->connector, mode); 1589 1590 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1591 frame.colorspace = HDMI_COLORSPACE_YUV444; 1592 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1593 frame.colorspace = HDMI_COLORSPACE_YUV422; 1594 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1595 frame.colorspace = HDMI_COLORSPACE_YUV420; 1596 else 1597 frame.colorspace = HDMI_COLORSPACE_RGB; 1598 1599 /* Set up colorimetry */ 1600 switch (hdmi->hdmi_data.enc_out_encoding) { 1601 case V4L2_YCBCR_ENC_601: 1602 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1603 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1604 else 1605 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1606 frame.extended_colorimetry = 1607 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1608 break; 1609 case V4L2_YCBCR_ENC_709: 1610 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1611 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1612 else 1613 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1614 frame.extended_colorimetry = 1615 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1616 break; 1617 default: /* Carries no data */ 1618 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1619 frame.extended_colorimetry = 1620 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1621 break; 1622 } 1623 1624 frame.scan_mode = HDMI_SCAN_MODE_NONE; 1625 1626 /* 1627 * The Designware IP uses a different byte format from standard 1628 * AVI info frames, though generally the bits are in the correct 1629 * bytes. 1630 */ 1631 1632 /* 1633 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, 1634 * scan info in bits 4,5 rather than 0,1 and active aspect present in 1635 * bit 6 rather than 4. 1636 */ 1637 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); 1638 if (frame.active_aspect & 15) 1639 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1640 if (frame.top_bar || frame.bottom_bar) 1641 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1642 if (frame.left_bar || frame.right_bar) 1643 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1644 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1645 1646 /* AVI data byte 2 differences: none */ 1647 val = ((frame.colorimetry & 0x3) << 6) | 1648 ((frame.picture_aspect & 0x3) << 4) | 1649 (frame.active_aspect & 0xf); 1650 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1651 1652 /* AVI data byte 3 differences: none */ 1653 val = ((frame.extended_colorimetry & 0x7) << 4) | 1654 ((frame.quantization_range & 0x3) << 2) | 1655 (frame.nups & 0x3); 1656 if (frame.itc) 1657 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1658 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1659 1660 /* AVI data byte 4 differences: none */ 1661 val = frame.video_code & 0x7f; 1662 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1663 1664 /* AVI Data Byte 5- set up input and output pixel repetition */ 1665 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1666 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1667 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1668 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1669 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1670 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1671 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1672 1673 /* 1674 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1675 * ycc range in bits 2,3 rather than 6,7 1676 */ 1677 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1678 (frame.content_type & 0x3); 1679 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1680 1681 /* AVI Data Bytes 6-13 */ 1682 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1683 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1684 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1685 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1686 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1687 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1688 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1689 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1690 } 1691 1692 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1693 struct drm_display_mode *mode) 1694 { 1695 struct hdmi_vendor_infoframe frame; 1696 u8 buffer[10]; 1697 ssize_t err; 1698 1699 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, 1700 &hdmi->connector, 1701 mode); 1702 if (err < 0) 1703 /* 1704 * Going into that statement does not means vendor infoframe 1705 * fails. It just informed us that vendor infoframe is not 1706 * needed for the selected mode. Only 4k or stereoscopic 3D 1707 * mode requires vendor infoframe. So just simply return. 1708 */ 1709 return; 1710 1711 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1712 if (err < 0) { 1713 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1714 err); 1715 return; 1716 } 1717 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1718 HDMI_FC_DATAUTO0_VSD_MASK); 1719 1720 /* Set the length of HDMI vendor specific InfoFrame payload */ 1721 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1722 1723 /* Set 24bit IEEE Registration Identifier */ 1724 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1725 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1726 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1727 1728 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1729 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1730 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1731 1732 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1733 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1734 1735 /* Packet frame interpolation */ 1736 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1737 1738 /* Auto packets per frame and line spacing */ 1739 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1740 1741 /* Configures the Frame Composer On RDRB mode */ 1742 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1743 HDMI_FC_DATAUTO0_VSD_MASK); 1744 } 1745 1746 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1747 const struct drm_display_mode *mode) 1748 { 1749 u8 inv_val, bytes; 1750 struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi; 1751 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1752 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1753 unsigned int vdisplay, hdisplay; 1754 1755 vmode->mtmdsclock = vmode->mpixelclock = mode->clock * 1000; 1756 1757 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); 1758 1759 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1760 vmode->mtmdsclock /= 2; 1761 1762 /* Set up HDMI_FC_INVIDCONF */ 1763 inv_val = (hdmi->hdmi_data.hdcp_enable || 1764 (dw_hdmi_support_scdc(hdmi) && 1765 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 1766 hdmi_info->scdc.scrambling.low_rates)) ? 1767 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1768 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1769 1770 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1771 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1772 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1773 1774 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1775 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1776 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1777 1778 inv_val |= (vmode->mdataenablepolarity ? 1779 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1780 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1781 1782 if (hdmi->vic == 39) 1783 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1784 else 1785 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1786 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1787 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1788 1789 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1790 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1791 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1792 1793 inv_val |= hdmi->sink_is_hdmi ? 1794 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1795 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1796 1797 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1798 1799 hdisplay = mode->hdisplay; 1800 hblank = mode->htotal - mode->hdisplay; 1801 h_de_hs = mode->hsync_start - mode->hdisplay; 1802 hsync_len = mode->hsync_end - mode->hsync_start; 1803 1804 /* 1805 * When we're setting a YCbCr420 mode, we need 1806 * to adjust the horizontal timing to suit. 1807 */ 1808 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1809 hdisplay /= 2; 1810 hblank /= 2; 1811 h_de_hs /= 2; 1812 hsync_len /= 2; 1813 } 1814 1815 vdisplay = mode->vdisplay; 1816 vblank = mode->vtotal - mode->vdisplay; 1817 v_de_vs = mode->vsync_start - mode->vdisplay; 1818 vsync_len = mode->vsync_end - mode->vsync_start; 1819 1820 /* 1821 * When we're setting an interlaced mode, we need 1822 * to adjust the vertical timing to suit. 1823 */ 1824 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1825 vdisplay /= 2; 1826 vblank /= 2; 1827 v_de_vs /= 2; 1828 vsync_len /= 2; 1829 } 1830 1831 /* Scrambling Control */ 1832 if (dw_hdmi_support_scdc(hdmi)) { 1833 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 1834 hdmi_info->scdc.scrambling.low_rates) { 1835 /* 1836 * HDMI2.0 Specifies the following procedure: 1837 * After the Source Device has determined that 1838 * SCDC_Present is set (=1), the Source Device should 1839 * write the accurate Version of the Source Device 1840 * to the Source Version field in the SCDCS. 1841 * Source Devices compliant shall set the 1842 * Source Version = 1. 1843 */ 1844 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, 1845 &bytes); 1846 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, 1847 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); 1848 1849 /* Enabled Scrambling in the Sink */ 1850 drm_scdc_set_scrambling(hdmi->ddc, 1); 1851 1852 /* 1853 * To activate the scrambler feature, you must ensure 1854 * that the quasi-static configuration bit 1855 * fc_invidconf.HDCP_keepout is set at configuration 1856 * time, before the required mc_swrstzreq.tmdsswrst_req 1857 * reset request is issued. 1858 */ 1859 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 1860 HDMI_MC_SWRSTZ); 1861 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 1862 } else { 1863 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 1864 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 1865 HDMI_MC_SWRSTZ); 1866 drm_scdc_set_scrambling(hdmi->ddc, 0); 1867 } 1868 } 1869 1870 /* Set up horizontal active pixel width */ 1871 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 1872 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 1873 1874 /* Set up vertical active lines */ 1875 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1876 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1877 1878 /* Set up horizontal blanking pixel region width */ 1879 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 1880 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 1881 1882 /* Set up vertical blanking pixel region width */ 1883 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 1884 1885 /* Set up HSYNC active edge delay width (in pixel clks) */ 1886 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 1887 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 1888 1889 /* Set up VSYNC active edge delay (in lines) */ 1890 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 1891 1892 /* Set up HSYNC active pulse width (in pixel clks) */ 1893 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 1894 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 1895 1896 /* Set up VSYNC active edge delay (in lines) */ 1897 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 1898 } 1899 1900 /* HDMI Initialization Step B.4 */ 1901 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 1902 { 1903 /* control period minimum duration */ 1904 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 1905 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 1906 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 1907 1908 /* Set to fill TMDS data channels */ 1909 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 1910 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 1911 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 1912 1913 /* Enable pixel clock and tmds data path */ 1914 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE | 1915 HDMI_MC_CLKDIS_CSCCLK_DISABLE | 1916 HDMI_MC_CLKDIS_AUDCLK_DISABLE | 1917 HDMI_MC_CLKDIS_PREPCLK_DISABLE | 1918 HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1919 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 1920 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1921 1922 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1923 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1924 1925 /* Enable csc path */ 1926 if (is_color_space_conversion(hdmi)) { 1927 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 1928 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1929 } 1930 1931 /* Enable color space conversion if needed */ 1932 if (is_color_space_conversion(hdmi)) 1933 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 1934 HDMI_MC_FLOWCTRL); 1935 else 1936 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 1937 HDMI_MC_FLOWCTRL); 1938 } 1939 1940 /* Workaround to clear the overflow condition */ 1941 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 1942 { 1943 unsigned int count; 1944 unsigned int i; 1945 u8 val; 1946 1947 /* 1948 * Under some circumstances the Frame Composer arithmetic unit can miss 1949 * an FC register write due to being busy processing the previous one. 1950 * The issue can be worked around by issuing a TMDS software reset and 1951 * then write one of the FC registers several times. 1952 * 1953 * The number of iterations matters and depends on the HDMI TX revision 1954 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL 1955 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified 1956 * as needing the workaround, with 4 iterations for v1.30a and 1 1957 * iteration for others. 1958 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing 1959 * the workaround with a single iteration. 1960 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have 1961 * been identified as needing the workaround with a single iteration. 1962 */ 1963 1964 switch (hdmi->version) { 1965 case 0x130a: 1966 count = 4; 1967 break; 1968 case 0x131a: 1969 case 0x132a: 1970 case 0x200a: 1971 case 0x201a: 1972 case 0x211a: 1973 case 0x212a: 1974 count = 1; 1975 break; 1976 default: 1977 return; 1978 } 1979 1980 /* TMDS software reset */ 1981 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 1982 1983 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 1984 for (i = 0; i < count; i++) 1985 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 1986 } 1987 1988 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 1989 { 1990 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 1991 HDMI_IH_MUTE_FC_STAT2); 1992 } 1993 1994 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1995 { 1996 int ret; 1997 1998 hdmi_disable_overflow_interrupts(hdmi); 1999 2000 hdmi->vic = drm_match_cea_mode(mode); 2001 2002 if (!hdmi->vic) { 2003 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); 2004 } else { 2005 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); 2006 } 2007 2008 if ((hdmi->vic == 6) || (hdmi->vic == 7) || 2009 (hdmi->vic == 21) || (hdmi->vic == 22) || 2010 (hdmi->vic == 2) || (hdmi->vic == 3) || 2011 (hdmi->vic == 17) || (hdmi->vic == 18)) 2012 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 2013 else 2014 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 2015 2016 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 2017 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 2018 2019 /* TOFIX: Get input format from plat data or fallback to RGB888 */ 2020 if (hdmi->plat_data->input_bus_format) 2021 hdmi->hdmi_data.enc_in_bus_format = 2022 hdmi->plat_data->input_bus_format; 2023 else 2024 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2025 2026 /* TOFIX: Get input encoding from plat data or fallback to none */ 2027 if (hdmi->plat_data->input_bus_encoding) 2028 hdmi->hdmi_data.enc_in_encoding = 2029 hdmi->plat_data->input_bus_encoding; 2030 else 2031 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 2032 2033 /* TOFIX: Default to RGB888 output format */ 2034 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2035 2036 hdmi->hdmi_data.pix_repet_factor = 0; 2037 hdmi->hdmi_data.hdcp_enable = 0; 2038 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 2039 2040 /* HDMI Initialization Step B.1 */ 2041 hdmi_av_composer(hdmi, mode); 2042 2043 /* HDMI Initializateion Step B.2 */ 2044 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode); 2045 if (ret) 2046 return ret; 2047 hdmi->phy.enabled = true; 2048 2049 /* HDMI Initialization Step B.3 */ 2050 dw_hdmi_enable_video_path(hdmi); 2051 2052 if (hdmi->sink_has_audio) { 2053 dev_dbg(hdmi->dev, "sink has audio support\n"); 2054 2055 /* HDMI Initialization Step E - Configure audio */ 2056 hdmi_clk_regenerator_update_pixel_clock(hdmi); 2057 hdmi_enable_audio_clk(hdmi, true); 2058 } 2059 2060 /* not for DVI mode */ 2061 if (hdmi->sink_is_hdmi) { 2062 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); 2063 2064 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 2065 hdmi_config_AVI(hdmi, mode); 2066 hdmi_config_vendor_specific_infoframe(hdmi, mode); 2067 } else { 2068 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); 2069 } 2070 2071 hdmi_video_packetize(hdmi); 2072 hdmi_video_csc(hdmi); 2073 hdmi_video_sample(hdmi); 2074 hdmi_tx_hdcp_config(hdmi); 2075 2076 dw_hdmi_clear_overflow(hdmi); 2077 2078 return 0; 2079 } 2080 2081 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) 2082 { 2083 u8 ih_mute; 2084 2085 /* 2086 * Boot up defaults are: 2087 * HDMI_IH_MUTE = 0x03 (disabled) 2088 * HDMI_IH_MUTE_* = 0x00 (enabled) 2089 * 2090 * Disable top level interrupt bits in HDMI block 2091 */ 2092 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | 2093 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2094 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; 2095 2096 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2097 2098 /* by default mask all interrupts */ 2099 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); 2100 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 2101 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 2102 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 2103 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); 2104 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); 2105 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); 2106 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); 2107 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); 2108 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); 2109 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); 2110 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); 2111 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); 2112 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); 2113 2114 /* Disable interrupts in the IH_MUTE_* registers */ 2115 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2116 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2117 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2118 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2119 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); 2120 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2121 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2122 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2123 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2124 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2125 2126 /* Enable top level interrupt bits in HDMI block */ 2127 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2128 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); 2129 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2130 } 2131 2132 static void dw_hdmi_poweron(struct dw_hdmi *hdmi) 2133 { 2134 hdmi->bridge_is_on = true; 2135 dw_hdmi_setup(hdmi, &hdmi->previous_mode); 2136 } 2137 2138 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) 2139 { 2140 if (hdmi->phy.enabled) { 2141 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 2142 hdmi->phy.enabled = false; 2143 } 2144 2145 hdmi->bridge_is_on = false; 2146 } 2147 2148 static void dw_hdmi_update_power(struct dw_hdmi *hdmi) 2149 { 2150 int force = hdmi->force; 2151 2152 if (hdmi->disabled) { 2153 force = DRM_FORCE_OFF; 2154 } else if (force == DRM_FORCE_UNSPECIFIED) { 2155 if (hdmi->rxsense) 2156 force = DRM_FORCE_ON; 2157 else 2158 force = DRM_FORCE_OFF; 2159 } 2160 2161 if (force == DRM_FORCE_OFF) { 2162 if (hdmi->bridge_is_on) 2163 dw_hdmi_poweroff(hdmi); 2164 } else { 2165 if (!hdmi->bridge_is_on) 2166 dw_hdmi_poweron(hdmi); 2167 } 2168 } 2169 2170 /* 2171 * Adjust the detection of RXSENSE according to whether we have a forced 2172 * connection mode enabled, or whether we have been disabled. There is 2173 * no point processing RXSENSE interrupts if we have a forced connection 2174 * state, or DRM has us disabled. 2175 * 2176 * We also disable rxsense interrupts when we think we're disconnected 2177 * to avoid floating TDMS signals giving false rxsense interrupts. 2178 * 2179 * Note: we still need to listen for HPD interrupts even when DRM has us 2180 * disabled so that we can detect a connect event. 2181 */ 2182 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) 2183 { 2184 if (hdmi->phy.ops->update_hpd) 2185 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, 2186 hdmi->force, hdmi->disabled, 2187 hdmi->rxsense); 2188 } 2189 2190 static enum drm_connector_status 2191 dw_hdmi_connector_detect(struct drm_connector *connector, bool force) 2192 { 2193 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2194 connector); 2195 2196 mutex_lock(&hdmi->mutex); 2197 hdmi->force = DRM_FORCE_UNSPECIFIED; 2198 dw_hdmi_update_power(hdmi); 2199 dw_hdmi_update_phy_mask(hdmi); 2200 mutex_unlock(&hdmi->mutex); 2201 2202 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 2203 } 2204 2205 static int dw_hdmi_connector_get_modes(struct drm_connector *connector) 2206 { 2207 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2208 connector); 2209 struct edid *edid; 2210 int ret = 0; 2211 2212 if (!hdmi->ddc) 2213 return 0; 2214 2215 edid = drm_get_edid(connector, hdmi->ddc); 2216 if (edid) { 2217 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", 2218 edid->width_cm, edid->height_cm); 2219 2220 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); 2221 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2222 drm_connector_update_edid_property(connector, edid); 2223 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); 2224 ret = drm_add_edid_modes(connector, edid); 2225 kfree(edid); 2226 } else { 2227 dev_dbg(hdmi->dev, "failed to get edid\n"); 2228 } 2229 2230 return ret; 2231 } 2232 2233 static void dw_hdmi_connector_force(struct drm_connector *connector) 2234 { 2235 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2236 connector); 2237 2238 mutex_lock(&hdmi->mutex); 2239 hdmi->force = connector->force; 2240 dw_hdmi_update_power(hdmi); 2241 dw_hdmi_update_phy_mask(hdmi); 2242 mutex_unlock(&hdmi->mutex); 2243 } 2244 2245 static const struct drm_connector_funcs dw_hdmi_connector_funcs = { 2246 .fill_modes = drm_helper_probe_single_connector_modes, 2247 .detect = dw_hdmi_connector_detect, 2248 .destroy = drm_connector_cleanup, 2249 .force = dw_hdmi_connector_force, 2250 .reset = drm_atomic_helper_connector_reset, 2251 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2252 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2253 }; 2254 2255 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { 2256 .get_modes = dw_hdmi_connector_get_modes, 2257 }; 2258 2259 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge) 2260 { 2261 struct dw_hdmi *hdmi = bridge->driver_private; 2262 struct drm_encoder *encoder = bridge->encoder; 2263 struct drm_connector *connector = &hdmi->connector; 2264 struct cec_connector_info conn_info; 2265 struct cec_notifier *notifier; 2266 2267 connector->interlace_allowed = 1; 2268 connector->polled = DRM_CONNECTOR_POLL_HPD; 2269 2270 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); 2271 2272 drm_connector_init_with_ddc(bridge->dev, connector, 2273 &dw_hdmi_connector_funcs, 2274 DRM_MODE_CONNECTOR_HDMIA, 2275 hdmi->ddc); 2276 2277 drm_connector_attach_encoder(connector, encoder); 2278 2279 cec_fill_conn_info_from_drm(&conn_info, connector); 2280 2281 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info); 2282 if (!notifier) 2283 return -ENOMEM; 2284 2285 mutex_lock(&hdmi->cec_notifier_mutex); 2286 hdmi->cec_notifier = notifier; 2287 mutex_unlock(&hdmi->cec_notifier_mutex); 2288 2289 return 0; 2290 } 2291 2292 static void dw_hdmi_bridge_detach(struct drm_bridge *bridge) 2293 { 2294 struct dw_hdmi *hdmi = bridge->driver_private; 2295 2296 mutex_lock(&hdmi->cec_notifier_mutex); 2297 cec_notifier_conn_unregister(hdmi->cec_notifier); 2298 hdmi->cec_notifier = NULL; 2299 mutex_unlock(&hdmi->cec_notifier_mutex); 2300 } 2301 2302 static enum drm_mode_status 2303 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 2304 const struct drm_display_mode *mode) 2305 { 2306 struct dw_hdmi *hdmi = bridge->driver_private; 2307 struct drm_connector *connector = &hdmi->connector; 2308 enum drm_mode_status mode_status = MODE_OK; 2309 2310 /* We don't support double-clocked modes */ 2311 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2312 return MODE_BAD; 2313 2314 if (hdmi->plat_data->mode_valid) 2315 mode_status = hdmi->plat_data->mode_valid(connector, mode); 2316 2317 return mode_status; 2318 } 2319 2320 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, 2321 const struct drm_display_mode *orig_mode, 2322 const struct drm_display_mode *mode) 2323 { 2324 struct dw_hdmi *hdmi = bridge->driver_private; 2325 2326 mutex_lock(&hdmi->mutex); 2327 2328 /* Store the display mode for plugin/DKMS poweron events */ 2329 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 2330 2331 mutex_unlock(&hdmi->mutex); 2332 } 2333 2334 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge) 2335 { 2336 struct dw_hdmi *hdmi = bridge->driver_private; 2337 2338 mutex_lock(&hdmi->mutex); 2339 hdmi->disabled = true; 2340 dw_hdmi_update_power(hdmi); 2341 dw_hdmi_update_phy_mask(hdmi); 2342 mutex_unlock(&hdmi->mutex); 2343 } 2344 2345 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge) 2346 { 2347 struct dw_hdmi *hdmi = bridge->driver_private; 2348 2349 mutex_lock(&hdmi->mutex); 2350 hdmi->disabled = false; 2351 dw_hdmi_update_power(hdmi); 2352 dw_hdmi_update_phy_mask(hdmi); 2353 mutex_unlock(&hdmi->mutex); 2354 } 2355 2356 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { 2357 .attach = dw_hdmi_bridge_attach, 2358 .detach = dw_hdmi_bridge_detach, 2359 .enable = dw_hdmi_bridge_enable, 2360 .disable = dw_hdmi_bridge_disable, 2361 .mode_set = dw_hdmi_bridge_mode_set, 2362 .mode_valid = dw_hdmi_bridge_mode_valid, 2363 }; 2364 2365 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) 2366 { 2367 struct dw_hdmi_i2c *i2c = hdmi->i2c; 2368 unsigned int stat; 2369 2370 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 2371 if (!stat) 2372 return IRQ_NONE; 2373 2374 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0); 2375 2376 i2c->stat = stat; 2377 2378 complete(&i2c->cmp); 2379 2380 return IRQ_HANDLED; 2381 } 2382 2383 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) 2384 { 2385 struct dw_hdmi *hdmi = dev_id; 2386 u8 intr_stat; 2387 irqreturn_t ret = IRQ_NONE; 2388 2389 if (hdmi->i2c) 2390 ret = dw_hdmi_i2c_irq(hdmi); 2391 2392 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2393 if (intr_stat) { 2394 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2395 return IRQ_WAKE_THREAD; 2396 } 2397 2398 return ret; 2399 } 2400 2401 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) 2402 { 2403 mutex_lock(&hdmi->mutex); 2404 2405 if (!hdmi->force) { 2406 /* 2407 * If the RX sense status indicates we're disconnected, 2408 * clear the software rxsense status. 2409 */ 2410 if (!rx_sense) 2411 hdmi->rxsense = false; 2412 2413 /* 2414 * Only set the software rxsense status when both 2415 * rxsense and hpd indicates we're connected. 2416 * This avoids what seems to be bad behaviour in 2417 * at least iMX6S versions of the phy. 2418 */ 2419 if (hpd) 2420 hdmi->rxsense = true; 2421 2422 dw_hdmi_update_power(hdmi); 2423 dw_hdmi_update_phy_mask(hdmi); 2424 } 2425 mutex_unlock(&hdmi->mutex); 2426 } 2427 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); 2428 2429 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) 2430 { 2431 struct dw_hdmi *hdmi = dev_id; 2432 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; 2433 2434 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2435 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); 2436 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); 2437 2438 phy_pol_mask = 0; 2439 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) 2440 phy_pol_mask |= HDMI_PHY_HPD; 2441 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) 2442 phy_pol_mask |= HDMI_PHY_RX_SENSE0; 2443 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) 2444 phy_pol_mask |= HDMI_PHY_RX_SENSE1; 2445 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) 2446 phy_pol_mask |= HDMI_PHY_RX_SENSE2; 2447 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) 2448 phy_pol_mask |= HDMI_PHY_RX_SENSE3; 2449 2450 if (phy_pol_mask) 2451 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); 2452 2453 /* 2454 * RX sense tells us whether the TDMS transmitters are detecting 2455 * load - in other words, there's something listening on the 2456 * other end of the link. Use this to decide whether we should 2457 * power on the phy as HPD may be toggled by the sink to merely 2458 * ask the source to re-read the EDID. 2459 */ 2460 if (intr_stat & 2461 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { 2462 dw_hdmi_setup_rx_sense(hdmi, 2463 phy_stat & HDMI_PHY_HPD, 2464 phy_stat & HDMI_PHY_RX_SENSE); 2465 2466 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) { 2467 mutex_lock(&hdmi->cec_notifier_mutex); 2468 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); 2469 mutex_unlock(&hdmi->cec_notifier_mutex); 2470 } 2471 } 2472 2473 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { 2474 dev_dbg(hdmi->dev, "EVENT=%s\n", 2475 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout"); 2476 if (hdmi->bridge.dev) 2477 drm_helper_hpd_irq_event(hdmi->bridge.dev); 2478 } 2479 2480 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); 2481 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 2482 HDMI_IH_MUTE_PHY_STAT0); 2483 2484 return IRQ_HANDLED; 2485 } 2486 2487 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 2488 { 2489 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 2490 .name = "DWC HDMI TX PHY", 2491 .gen = 1, 2492 }, { 2493 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 2494 .name = "DWC MHL PHY + HEAC PHY", 2495 .gen = 2, 2496 .has_svsret = true, 2497 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2498 }, { 2499 .type = DW_HDMI_PHY_DWC_MHL_PHY, 2500 .name = "DWC MHL PHY", 2501 .gen = 2, 2502 .has_svsret = true, 2503 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2504 }, { 2505 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 2506 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 2507 .gen = 2, 2508 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2509 }, { 2510 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 2511 .name = "DWC HDMI 3D TX PHY", 2512 .gen = 2, 2513 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2514 }, { 2515 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 2516 .name = "DWC HDMI 2.0 TX PHY", 2517 .gen = 2, 2518 .has_svsret = true, 2519 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2520 }, { 2521 .type = DW_HDMI_PHY_VENDOR_PHY, 2522 .name = "Vendor PHY", 2523 } 2524 }; 2525 2526 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 2527 { 2528 unsigned int i; 2529 u8 phy_type; 2530 2531 phy_type = hdmi->plat_data->phy_force_vendor ? 2532 DW_HDMI_PHY_VENDOR_PHY : 2533 hdmi_readb(hdmi, HDMI_CONFIG2_ID); 2534 2535 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { 2536 /* Vendor PHYs require support from the glue layer. */ 2537 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 2538 dev_err(hdmi->dev, 2539 "Vendor HDMI PHY not supported by glue layer\n"); 2540 return -ENODEV; 2541 } 2542 2543 hdmi->phy.ops = hdmi->plat_data->phy_ops; 2544 hdmi->phy.data = hdmi->plat_data->phy_data; 2545 hdmi->phy.name = hdmi->plat_data->phy_name; 2546 return 0; 2547 } 2548 2549 /* Synopsys PHYs are handled internally. */ 2550 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 2551 if (dw_hdmi_phys[i].type == phy_type) { 2552 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 2553 hdmi->phy.name = dw_hdmi_phys[i].name; 2554 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 2555 2556 if (!dw_hdmi_phys[i].configure && 2557 !hdmi->plat_data->configure_phy) { 2558 dev_err(hdmi->dev, "%s requires platform support\n", 2559 hdmi->phy.name); 2560 return -ENODEV; 2561 } 2562 2563 return 0; 2564 } 2565 } 2566 2567 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); 2568 return -ENODEV; 2569 } 2570 2571 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi) 2572 { 2573 mutex_lock(&hdmi->mutex); 2574 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE; 2575 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2576 mutex_unlock(&hdmi->mutex); 2577 } 2578 2579 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi) 2580 { 2581 mutex_lock(&hdmi->mutex); 2582 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE; 2583 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2584 mutex_unlock(&hdmi->mutex); 2585 } 2586 2587 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = { 2588 .write = hdmi_writeb, 2589 .read = hdmi_readb, 2590 .enable = dw_hdmi_cec_enable, 2591 .disable = dw_hdmi_cec_disable, 2592 }; 2593 2594 static const struct regmap_config hdmi_regmap_8bit_config = { 2595 .reg_bits = 32, 2596 .val_bits = 8, 2597 .reg_stride = 1, 2598 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, 2599 }; 2600 2601 static const struct regmap_config hdmi_regmap_32bit_config = { 2602 .reg_bits = 32, 2603 .val_bits = 32, 2604 .reg_stride = 4, 2605 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, 2606 }; 2607 2608 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi) 2609 { 2610 initialize_hdmi_ih_mutes(hdmi); 2611 2612 /* 2613 * Reset HDMI DDC I2C master controller and mute I2CM interrupts. 2614 * Even if we are using a separate i2c adapter doing this doesn't 2615 * hurt. 2616 */ 2617 dw_hdmi_i2c_init(hdmi); 2618 2619 if (hdmi->phy.ops->setup_hpd) 2620 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 2621 } 2622 2623 static struct dw_hdmi * 2624 __dw_hdmi_probe(struct platform_device *pdev, 2625 const struct dw_hdmi_plat_data *plat_data) 2626 { 2627 struct device *dev = &pdev->dev; 2628 struct device_node *np = dev->of_node; 2629 struct platform_device_info pdevinfo; 2630 struct device_node *ddc_node; 2631 struct dw_hdmi_cec_data cec; 2632 struct dw_hdmi *hdmi; 2633 struct resource *iores = NULL; 2634 int irq; 2635 int ret; 2636 u32 val = 1; 2637 u8 prod_id0; 2638 u8 prod_id1; 2639 u8 config0; 2640 u8 config3; 2641 2642 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 2643 if (!hdmi) 2644 return ERR_PTR(-ENOMEM); 2645 2646 hdmi->plat_data = plat_data; 2647 hdmi->dev = dev; 2648 hdmi->sample_rate = 48000; 2649 hdmi->disabled = true; 2650 hdmi->rxsense = true; 2651 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); 2652 hdmi->mc_clkdis = 0x7f; 2653 2654 mutex_init(&hdmi->mutex); 2655 mutex_init(&hdmi->audio_mutex); 2656 mutex_init(&hdmi->cec_notifier_mutex); 2657 spin_lock_init(&hdmi->audio_lock); 2658 2659 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 2660 if (ddc_node) { 2661 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); 2662 of_node_put(ddc_node); 2663 if (!hdmi->ddc) { 2664 dev_dbg(hdmi->dev, "failed to read ddc node\n"); 2665 return ERR_PTR(-EPROBE_DEFER); 2666 } 2667 2668 } else { 2669 dev_dbg(hdmi->dev, "no ddc property found\n"); 2670 } 2671 2672 if (!plat_data->regm) { 2673 const struct regmap_config *reg_config; 2674 2675 of_property_read_u32(np, "reg-io-width", &val); 2676 switch (val) { 2677 case 4: 2678 reg_config = &hdmi_regmap_32bit_config; 2679 hdmi->reg_shift = 2; 2680 break; 2681 case 1: 2682 reg_config = &hdmi_regmap_8bit_config; 2683 break; 2684 default: 2685 dev_err(dev, "reg-io-width must be 1 or 4\n"); 2686 return ERR_PTR(-EINVAL); 2687 } 2688 2689 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2690 hdmi->regs = devm_ioremap_resource(dev, iores); 2691 if (IS_ERR(hdmi->regs)) { 2692 ret = PTR_ERR(hdmi->regs); 2693 goto err_res; 2694 } 2695 2696 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); 2697 if (IS_ERR(hdmi->regm)) { 2698 dev_err(dev, "Failed to configure regmap\n"); 2699 ret = PTR_ERR(hdmi->regm); 2700 goto err_res; 2701 } 2702 } else { 2703 hdmi->regm = plat_data->regm; 2704 } 2705 2706 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); 2707 if (IS_ERR(hdmi->isfr_clk)) { 2708 ret = PTR_ERR(hdmi->isfr_clk); 2709 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); 2710 goto err_res; 2711 } 2712 2713 ret = clk_prepare_enable(hdmi->isfr_clk); 2714 if (ret) { 2715 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret); 2716 goto err_res; 2717 } 2718 2719 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); 2720 if (IS_ERR(hdmi->iahb_clk)) { 2721 ret = PTR_ERR(hdmi->iahb_clk); 2722 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); 2723 goto err_isfr; 2724 } 2725 2726 ret = clk_prepare_enable(hdmi->iahb_clk); 2727 if (ret) { 2728 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret); 2729 goto err_isfr; 2730 } 2731 2732 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec"); 2733 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) { 2734 hdmi->cec_clk = NULL; 2735 } else if (IS_ERR(hdmi->cec_clk)) { 2736 ret = PTR_ERR(hdmi->cec_clk); 2737 if (ret != -EPROBE_DEFER) 2738 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n", 2739 ret); 2740 2741 hdmi->cec_clk = NULL; 2742 goto err_iahb; 2743 } else { 2744 ret = clk_prepare_enable(hdmi->cec_clk); 2745 if (ret) { 2746 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n", 2747 ret); 2748 goto err_iahb; 2749 } 2750 } 2751 2752 /* Product and revision IDs */ 2753 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 2754 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 2755 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); 2756 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); 2757 2758 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || 2759 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { 2760 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", 2761 hdmi->version, prod_id0, prod_id1); 2762 ret = -ENODEV; 2763 goto err_iahb; 2764 } 2765 2766 ret = dw_hdmi_detect_phy(hdmi); 2767 if (ret < 0) 2768 goto err_iahb; 2769 2770 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", 2771 hdmi->version >> 12, hdmi->version & 0xfff, 2772 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", 2773 hdmi->phy.name); 2774 2775 dw_hdmi_init_hw(hdmi); 2776 2777 irq = platform_get_irq(pdev, 0); 2778 if (irq < 0) { 2779 ret = irq; 2780 goto err_iahb; 2781 } 2782 2783 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, 2784 dw_hdmi_irq, IRQF_SHARED, 2785 dev_name(dev), hdmi); 2786 if (ret) 2787 goto err_iahb; 2788 2789 /* 2790 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator 2791 * N and cts values before enabling phy 2792 */ 2793 hdmi_init_clk_regenerator(hdmi); 2794 2795 /* If DDC bus is not specified, try to register HDMI I2C bus */ 2796 if (!hdmi->ddc) { 2797 /* Look for (optional) stuff related to unwedging */ 2798 hdmi->pinctrl = devm_pinctrl_get(dev); 2799 if (!IS_ERR(hdmi->pinctrl)) { 2800 hdmi->unwedge_state = 2801 pinctrl_lookup_state(hdmi->pinctrl, "unwedge"); 2802 hdmi->default_state = 2803 pinctrl_lookup_state(hdmi->pinctrl, "default"); 2804 2805 if (IS_ERR(hdmi->default_state) || 2806 IS_ERR(hdmi->unwedge_state)) { 2807 if (!IS_ERR(hdmi->unwedge_state)) 2808 dev_warn(dev, 2809 "Unwedge requires default pinctrl\n"); 2810 hdmi->default_state = NULL; 2811 hdmi->unwedge_state = NULL; 2812 } 2813 } 2814 2815 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); 2816 if (IS_ERR(hdmi->ddc)) 2817 hdmi->ddc = NULL; 2818 } 2819 2820 hdmi->bridge.driver_private = hdmi; 2821 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; 2822 #ifdef CONFIG_OF 2823 hdmi->bridge.of_node = pdev->dev.of_node; 2824 #endif 2825 2826 memset(&pdevinfo, 0, sizeof(pdevinfo)); 2827 pdevinfo.parent = dev; 2828 pdevinfo.id = PLATFORM_DEVID_AUTO; 2829 2830 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); 2831 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 2832 2833 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { 2834 struct dw_hdmi_audio_data audio; 2835 2836 audio.phys = iores->start; 2837 audio.base = hdmi->regs; 2838 audio.irq = irq; 2839 audio.hdmi = hdmi; 2840 audio.eld = hdmi->connector.eld; 2841 hdmi->enable_audio = dw_hdmi_ahb_audio_enable; 2842 hdmi->disable_audio = dw_hdmi_ahb_audio_disable; 2843 2844 pdevinfo.name = "dw-hdmi-ahb-audio"; 2845 pdevinfo.data = &audio; 2846 pdevinfo.size_data = sizeof(audio); 2847 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2848 hdmi->audio = platform_device_register_full(&pdevinfo); 2849 } else if (config0 & HDMI_CONFIG0_I2S) { 2850 struct dw_hdmi_i2s_audio_data audio; 2851 2852 audio.hdmi = hdmi; 2853 audio.eld = hdmi->connector.eld; 2854 audio.write = hdmi_writeb; 2855 audio.read = hdmi_readb; 2856 hdmi->enable_audio = dw_hdmi_i2s_audio_enable; 2857 hdmi->disable_audio = dw_hdmi_i2s_audio_disable; 2858 2859 pdevinfo.name = "dw-hdmi-i2s-audio"; 2860 pdevinfo.data = &audio; 2861 pdevinfo.size_data = sizeof(audio); 2862 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2863 hdmi->audio = platform_device_register_full(&pdevinfo); 2864 } 2865 2866 if (config0 & HDMI_CONFIG0_CEC) { 2867 cec.hdmi = hdmi; 2868 cec.ops = &dw_hdmi_cec_ops; 2869 cec.irq = irq; 2870 2871 pdevinfo.name = "dw-hdmi-cec"; 2872 pdevinfo.data = &cec; 2873 pdevinfo.size_data = sizeof(cec); 2874 pdevinfo.dma_mask = 0; 2875 2876 hdmi->cec = platform_device_register_full(&pdevinfo); 2877 } 2878 2879 return hdmi; 2880 2881 err_iahb: 2882 if (hdmi->i2c) { 2883 i2c_del_adapter(&hdmi->i2c->adap); 2884 hdmi->ddc = NULL; 2885 } 2886 2887 clk_disable_unprepare(hdmi->iahb_clk); 2888 if (hdmi->cec_clk) 2889 clk_disable_unprepare(hdmi->cec_clk); 2890 err_isfr: 2891 clk_disable_unprepare(hdmi->isfr_clk); 2892 err_res: 2893 i2c_put_adapter(hdmi->ddc); 2894 2895 return ERR_PTR(ret); 2896 } 2897 2898 static void __dw_hdmi_remove(struct dw_hdmi *hdmi) 2899 { 2900 if (hdmi->audio && !IS_ERR(hdmi->audio)) 2901 platform_device_unregister(hdmi->audio); 2902 if (!IS_ERR(hdmi->cec)) 2903 platform_device_unregister(hdmi->cec); 2904 2905 /* Disable all interrupts */ 2906 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2907 2908 clk_disable_unprepare(hdmi->iahb_clk); 2909 clk_disable_unprepare(hdmi->isfr_clk); 2910 if (hdmi->cec_clk) 2911 clk_disable_unprepare(hdmi->cec_clk); 2912 2913 if (hdmi->i2c) 2914 i2c_del_adapter(&hdmi->i2c->adap); 2915 else 2916 i2c_put_adapter(hdmi->ddc); 2917 } 2918 2919 /* ----------------------------------------------------------------------------- 2920 * Probe/remove API, used from platforms based on the DRM bridge API. 2921 */ 2922 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, 2923 const struct dw_hdmi_plat_data *plat_data) 2924 { 2925 struct dw_hdmi *hdmi; 2926 2927 hdmi = __dw_hdmi_probe(pdev, plat_data); 2928 if (IS_ERR(hdmi)) 2929 return hdmi; 2930 2931 drm_bridge_add(&hdmi->bridge); 2932 2933 return hdmi; 2934 } 2935 EXPORT_SYMBOL_GPL(dw_hdmi_probe); 2936 2937 void dw_hdmi_remove(struct dw_hdmi *hdmi) 2938 { 2939 drm_bridge_remove(&hdmi->bridge); 2940 2941 __dw_hdmi_remove(hdmi); 2942 } 2943 EXPORT_SYMBOL_GPL(dw_hdmi_remove); 2944 2945 /* ----------------------------------------------------------------------------- 2946 * Bind/unbind API, used from platforms based on the component framework. 2947 */ 2948 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, 2949 struct drm_encoder *encoder, 2950 const struct dw_hdmi_plat_data *plat_data) 2951 { 2952 struct dw_hdmi *hdmi; 2953 int ret; 2954 2955 hdmi = __dw_hdmi_probe(pdev, plat_data); 2956 if (IS_ERR(hdmi)) 2957 return hdmi; 2958 2959 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL); 2960 if (ret) { 2961 dw_hdmi_remove(hdmi); 2962 DRM_ERROR("Failed to initialize bridge with drm\n"); 2963 return ERR_PTR(ret); 2964 } 2965 2966 return hdmi; 2967 } 2968 EXPORT_SYMBOL_GPL(dw_hdmi_bind); 2969 2970 void dw_hdmi_unbind(struct dw_hdmi *hdmi) 2971 { 2972 __dw_hdmi_remove(hdmi); 2973 } 2974 EXPORT_SYMBOL_GPL(dw_hdmi_unbind); 2975 2976 void dw_hdmi_resume(struct dw_hdmi *hdmi) 2977 { 2978 dw_hdmi_init_hw(hdmi); 2979 } 2980 EXPORT_SYMBOL_GPL(dw_hdmi_resume); 2981 2982 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 2983 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); 2984 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); 2985 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>"); 2986 MODULE_DESCRIPTION("DW HDMI transmitter driver"); 2987 MODULE_LICENSE("GPL"); 2988 MODULE_ALIAS("platform:dw-hdmi"); 2989