1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DesignWare High-Definition Multimedia Interface (HDMI) driver 4 * 5 * Copyright (C) 2013-2015 Mentor Graphics Inc. 6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 8 */ 9 #include <linux/module.h> 10 #include <linux/irq.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/clk.h> 14 #include <linux/hdmi.h> 15 #include <linux/mutex.h> 16 #include <linux/of_device.h> 17 #include <linux/regmap.h> 18 #include <linux/spinlock.h> 19 20 #include <drm/drm_of.h> 21 #include <drm/drmP.h> 22 #include <drm/drm_atomic_helper.h> 23 #include <drm/drm_edid.h> 24 #include <drm/drm_encoder_slave.h> 25 #include <drm/drm_scdc_helper.h> 26 #include <drm/drm_probe_helper.h> 27 #include <drm/bridge/dw_hdmi.h> 28 29 #include <uapi/linux/media-bus-format.h> 30 #include <uapi/linux/videodev2.h> 31 32 #include "dw-hdmi.h" 33 #include "dw-hdmi-audio.h" 34 #include "dw-hdmi-cec.h" 35 36 #include <media/cec-notifier.h> 37 38 #define DDC_SEGMENT_ADDR 0x30 39 40 #define HDMI_EDID_LEN 512 41 42 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ 43 #define SCDC_MIN_SOURCE_VERSION 0x1 44 45 #define HDMI14_MAX_TMDSCLK 340000000 46 47 enum hdmi_datamap { 48 RGB444_8B = 0x01, 49 RGB444_10B = 0x03, 50 RGB444_12B = 0x05, 51 RGB444_16B = 0x07, 52 YCbCr444_8B = 0x09, 53 YCbCr444_10B = 0x0B, 54 YCbCr444_12B = 0x0D, 55 YCbCr444_16B = 0x0F, 56 YCbCr422_8B = 0x16, 57 YCbCr422_10B = 0x14, 58 YCbCr422_12B = 0x12, 59 }; 60 61 static const u16 csc_coeff_default[3][4] = { 62 { 0x2000, 0x0000, 0x0000, 0x0000 }, 63 { 0x0000, 0x2000, 0x0000, 0x0000 }, 64 { 0x0000, 0x0000, 0x2000, 0x0000 } 65 }; 66 67 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 68 { 0x2000, 0x6926, 0x74fd, 0x010e }, 69 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 70 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 71 }; 72 73 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 74 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 75 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 76 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 77 }; 78 79 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 80 { 0x2591, 0x1322, 0x074b, 0x0000 }, 81 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 82 { 0x6acd, 0x7534, 0x2000, 0x0200 } 83 }; 84 85 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 86 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 87 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 88 { 0x6756, 0x78ab, 0x2000, 0x0200 } 89 }; 90 91 struct hdmi_vmode { 92 bool mdataenablepolarity; 93 94 unsigned int mpixelclock; 95 unsigned int mpixelrepetitioninput; 96 unsigned int mpixelrepetitionoutput; 97 unsigned int mtmdsclock; 98 }; 99 100 struct hdmi_data_info { 101 unsigned int enc_in_bus_format; 102 unsigned int enc_out_bus_format; 103 unsigned int enc_in_encoding; 104 unsigned int enc_out_encoding; 105 unsigned int pix_repet_factor; 106 unsigned int hdcp_enable; 107 struct hdmi_vmode video_mode; 108 }; 109 110 struct dw_hdmi_i2c { 111 struct i2c_adapter adap; 112 113 struct mutex lock; /* used to serialize data transfers */ 114 struct completion cmp; 115 u8 stat; 116 117 u8 slave_reg; 118 bool is_regaddr; 119 bool is_segment; 120 }; 121 122 struct dw_hdmi_phy_data { 123 enum dw_hdmi_phy_type type; 124 const char *name; 125 unsigned int gen; 126 bool has_svsret; 127 int (*configure)(struct dw_hdmi *hdmi, 128 const struct dw_hdmi_plat_data *pdata, 129 unsigned long mpixelclock); 130 }; 131 132 struct dw_hdmi { 133 struct drm_connector connector; 134 struct drm_bridge bridge; 135 136 unsigned int version; 137 138 struct platform_device *audio; 139 struct platform_device *cec; 140 struct device *dev; 141 struct clk *isfr_clk; 142 struct clk *iahb_clk; 143 struct clk *cec_clk; 144 struct dw_hdmi_i2c *i2c; 145 146 struct hdmi_data_info hdmi_data; 147 const struct dw_hdmi_plat_data *plat_data; 148 149 int vic; 150 151 u8 edid[HDMI_EDID_LEN]; 152 153 struct { 154 const struct dw_hdmi_phy_ops *ops; 155 const char *name; 156 void *data; 157 bool enabled; 158 } phy; 159 160 struct drm_display_mode previous_mode; 161 162 struct i2c_adapter *ddc; 163 void __iomem *regs; 164 bool sink_is_hdmi; 165 bool sink_has_audio; 166 167 struct mutex mutex; /* for state below and previous_mode */ 168 enum drm_connector_force force; /* mutex-protected force state */ 169 bool disabled; /* DRM has disabled our bridge */ 170 bool bridge_is_on; /* indicates the bridge is on */ 171 bool rxsense; /* rxsense state */ 172 u8 phy_mask; /* desired phy int mask settings */ 173 u8 mc_clkdis; /* clock disable register */ 174 175 spinlock_t audio_lock; 176 struct mutex audio_mutex; 177 unsigned int sample_rate; 178 unsigned int audio_cts; 179 unsigned int audio_n; 180 bool audio_enable; 181 182 unsigned int reg_shift; 183 struct regmap *regm; 184 void (*enable_audio)(struct dw_hdmi *hdmi); 185 void (*disable_audio)(struct dw_hdmi *hdmi); 186 187 struct cec_notifier *cec_notifier; 188 }; 189 190 #define HDMI_IH_PHY_STAT0_RX_SENSE \ 191 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ 192 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) 193 194 #define HDMI_PHY_RX_SENSE \ 195 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ 196 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) 197 198 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 199 { 200 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); 201 } 202 203 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 204 { 205 unsigned int val = 0; 206 207 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); 208 209 return val; 210 } 211 212 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 213 { 214 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); 215 } 216 217 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 218 u8 shift, u8 mask) 219 { 220 hdmi_modb(hdmi, data << shift, mask, reg); 221 } 222 223 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 224 { 225 /* Software reset */ 226 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 227 228 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ 229 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); 230 231 /* Set done, not acknowledged and arbitration interrupt polarities */ 232 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 233 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 234 HDMI_I2CM_CTLINT); 235 236 /* Clear DONE and ERROR interrupts */ 237 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 238 HDMI_IH_I2CM_STAT0); 239 240 /* Mute DONE and ERROR interrupts */ 241 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 242 HDMI_IH_MUTE_I2CM_STAT0); 243 } 244 245 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 246 unsigned char *buf, unsigned int length) 247 { 248 struct dw_hdmi_i2c *i2c = hdmi->i2c; 249 int stat; 250 251 if (!i2c->is_regaddr) { 252 dev_dbg(hdmi->dev, "set read register address to 0\n"); 253 i2c->slave_reg = 0x00; 254 i2c->is_regaddr = true; 255 } 256 257 while (length--) { 258 reinit_completion(&i2c->cmp); 259 260 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 261 if (i2c->is_segment) 262 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 263 HDMI_I2CM_OPERATION); 264 else 265 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 266 HDMI_I2CM_OPERATION); 267 268 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 269 if (!stat) 270 return -EAGAIN; 271 272 /* Check for error condition on the bus */ 273 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 274 return -EIO; 275 276 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 277 } 278 i2c->is_segment = false; 279 280 return 0; 281 } 282 283 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 284 unsigned char *buf, unsigned int length) 285 { 286 struct dw_hdmi_i2c *i2c = hdmi->i2c; 287 int stat; 288 289 if (!i2c->is_regaddr) { 290 /* Use the first write byte as register address */ 291 i2c->slave_reg = buf[0]; 292 length--; 293 buf++; 294 i2c->is_regaddr = true; 295 } 296 297 while (length--) { 298 reinit_completion(&i2c->cmp); 299 300 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 301 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 302 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 303 HDMI_I2CM_OPERATION); 304 305 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 306 if (!stat) 307 return -EAGAIN; 308 309 /* Check for error condition on the bus */ 310 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 311 return -EIO; 312 } 313 314 return 0; 315 } 316 317 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, 318 struct i2c_msg *msgs, int num) 319 { 320 struct dw_hdmi *hdmi = i2c_get_adapdata(adap); 321 struct dw_hdmi_i2c *i2c = hdmi->i2c; 322 u8 addr = msgs[0].addr; 323 int i, ret = 0; 324 325 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); 326 327 for (i = 0; i < num; i++) { 328 if (msgs[i].len == 0) { 329 dev_dbg(hdmi->dev, 330 "unsupported transfer %d/%d, no data\n", 331 i + 1, num); 332 return -EOPNOTSUPP; 333 } 334 } 335 336 mutex_lock(&i2c->lock); 337 338 /* Unmute DONE and ERROR interrupts */ 339 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 340 341 /* Set slave device address taken from the first I2C message */ 342 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 343 344 /* Set slave device register address on transfer */ 345 i2c->is_regaddr = false; 346 347 /* Set segment pointer for I2C extended read mode operation */ 348 i2c->is_segment = false; 349 350 for (i = 0; i < num; i++) { 351 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", 352 i + 1, num, msgs[i].len, msgs[i].flags); 353 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 354 i2c->is_segment = true; 355 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 356 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 357 } else { 358 if (msgs[i].flags & I2C_M_RD) 359 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 360 msgs[i].len); 361 else 362 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 363 msgs[i].len); 364 } 365 if (ret < 0) 366 break; 367 } 368 369 if (!ret) 370 ret = num; 371 372 /* Mute DONE and ERROR interrupts */ 373 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 374 HDMI_IH_MUTE_I2CM_STAT0); 375 376 mutex_unlock(&i2c->lock); 377 378 return ret; 379 } 380 381 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) 382 { 383 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 384 } 385 386 static const struct i2c_algorithm dw_hdmi_algorithm = { 387 .master_xfer = dw_hdmi_i2c_xfer, 388 .functionality = dw_hdmi_i2c_func, 389 }; 390 391 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) 392 { 393 struct i2c_adapter *adap; 394 struct dw_hdmi_i2c *i2c; 395 int ret; 396 397 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 398 if (!i2c) 399 return ERR_PTR(-ENOMEM); 400 401 mutex_init(&i2c->lock); 402 init_completion(&i2c->cmp); 403 404 adap = &i2c->adap; 405 adap->class = I2C_CLASS_DDC; 406 adap->owner = THIS_MODULE; 407 adap->dev.parent = hdmi->dev; 408 adap->algo = &dw_hdmi_algorithm; 409 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name)); 410 i2c_set_adapdata(adap, hdmi); 411 412 ret = i2c_add_adapter(adap); 413 if (ret) { 414 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 415 devm_kfree(hdmi->dev, i2c); 416 return ERR_PTR(ret); 417 } 418 419 hdmi->i2c = i2c; 420 421 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 422 423 return adap; 424 } 425 426 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 427 unsigned int n) 428 { 429 /* Must be set/cleared first */ 430 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 431 432 /* nshift factor = 0 */ 433 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 434 435 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 436 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 437 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 438 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 439 440 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 441 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 442 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 443 } 444 445 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) 446 { 447 unsigned int n = (128 * freq) / 1000; 448 unsigned int mult = 1; 449 450 while (freq > 48000) { 451 mult *= 2; 452 freq /= 2; 453 } 454 455 switch (freq) { 456 case 32000: 457 if (pixel_clk == 25175000) 458 n = 4576; 459 else if (pixel_clk == 27027000) 460 n = 4096; 461 else if (pixel_clk == 74176000 || pixel_clk == 148352000) 462 n = 11648; 463 else 464 n = 4096; 465 n *= mult; 466 break; 467 468 case 44100: 469 if (pixel_clk == 25175000) 470 n = 7007; 471 else if (pixel_clk == 74176000) 472 n = 17836; 473 else if (pixel_clk == 148352000) 474 n = 8918; 475 else 476 n = 6272; 477 n *= mult; 478 break; 479 480 case 48000: 481 if (pixel_clk == 25175000) 482 n = 6864; 483 else if (pixel_clk == 27027000) 484 n = 6144; 485 else if (pixel_clk == 74176000) 486 n = 11648; 487 else if (pixel_clk == 148352000) 488 n = 5824; 489 else 490 n = 6144; 491 n *= mult; 492 break; 493 494 default: 495 break; 496 } 497 498 return n; 499 } 500 501 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, 502 unsigned long pixel_clk, unsigned int sample_rate) 503 { 504 unsigned long ftdms = pixel_clk; 505 unsigned int n, cts; 506 u64 tmp; 507 508 n = hdmi_compute_n(sample_rate, pixel_clk); 509 510 /* 511 * Compute the CTS value from the N value. Note that CTS and N 512 * can be up to 20 bits in total, so we need 64-bit math. Also 513 * note that our TDMS clock is not fully accurate; it is accurate 514 * to kHz. This can introduce an unnecessary remainder in the 515 * calculation below, so we don't try to warn about that. 516 */ 517 tmp = (u64)ftdms * n; 518 do_div(tmp, 128 * sample_rate); 519 cts = tmp; 520 521 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", 522 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, 523 n, cts); 524 525 spin_lock_irq(&hdmi->audio_lock); 526 hdmi->audio_n = n; 527 hdmi->audio_cts = cts; 528 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 529 spin_unlock_irq(&hdmi->audio_lock); 530 } 531 532 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) 533 { 534 mutex_lock(&hdmi->audio_mutex); 535 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); 536 mutex_unlock(&hdmi->audio_mutex); 537 } 538 539 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 540 { 541 mutex_lock(&hdmi->audio_mutex); 542 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 543 hdmi->sample_rate); 544 mutex_unlock(&hdmi->audio_mutex); 545 } 546 547 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 548 { 549 mutex_lock(&hdmi->audio_mutex); 550 hdmi->sample_rate = rate; 551 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 552 hdmi->sample_rate); 553 mutex_unlock(&hdmi->audio_mutex); 554 } 555 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); 556 557 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) 558 { 559 if (enable) 560 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; 561 else 562 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; 563 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 564 } 565 566 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi) 567 { 568 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 569 } 570 571 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi) 572 { 573 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 574 } 575 576 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi) 577 { 578 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 579 hdmi_enable_audio_clk(hdmi, true); 580 } 581 582 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi) 583 { 584 hdmi_enable_audio_clk(hdmi, false); 585 } 586 587 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 588 { 589 unsigned long flags; 590 591 spin_lock_irqsave(&hdmi->audio_lock, flags); 592 hdmi->audio_enable = true; 593 if (hdmi->enable_audio) 594 hdmi->enable_audio(hdmi); 595 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 596 } 597 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); 598 599 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 600 { 601 unsigned long flags; 602 603 spin_lock_irqsave(&hdmi->audio_lock, flags); 604 hdmi->audio_enable = false; 605 if (hdmi->disable_audio) 606 hdmi->disable_audio(hdmi); 607 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 608 } 609 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); 610 611 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 612 { 613 switch (bus_format) { 614 case MEDIA_BUS_FMT_RGB888_1X24: 615 case MEDIA_BUS_FMT_RGB101010_1X30: 616 case MEDIA_BUS_FMT_RGB121212_1X36: 617 case MEDIA_BUS_FMT_RGB161616_1X48: 618 return true; 619 620 default: 621 return false; 622 } 623 } 624 625 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 626 { 627 switch (bus_format) { 628 case MEDIA_BUS_FMT_YUV8_1X24: 629 case MEDIA_BUS_FMT_YUV10_1X30: 630 case MEDIA_BUS_FMT_YUV12_1X36: 631 case MEDIA_BUS_FMT_YUV16_1X48: 632 return true; 633 634 default: 635 return false; 636 } 637 } 638 639 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 640 { 641 switch (bus_format) { 642 case MEDIA_BUS_FMT_UYVY8_1X16: 643 case MEDIA_BUS_FMT_UYVY10_1X20: 644 case MEDIA_BUS_FMT_UYVY12_1X24: 645 return true; 646 647 default: 648 return false; 649 } 650 } 651 652 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 653 { 654 switch (bus_format) { 655 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 656 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 657 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 658 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 659 return true; 660 661 default: 662 return false; 663 } 664 } 665 666 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 667 { 668 switch (bus_format) { 669 case MEDIA_BUS_FMT_RGB888_1X24: 670 case MEDIA_BUS_FMT_YUV8_1X24: 671 case MEDIA_BUS_FMT_UYVY8_1X16: 672 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 673 return 8; 674 675 case MEDIA_BUS_FMT_RGB101010_1X30: 676 case MEDIA_BUS_FMT_YUV10_1X30: 677 case MEDIA_BUS_FMT_UYVY10_1X20: 678 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 679 return 10; 680 681 case MEDIA_BUS_FMT_RGB121212_1X36: 682 case MEDIA_BUS_FMT_YUV12_1X36: 683 case MEDIA_BUS_FMT_UYVY12_1X24: 684 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 685 return 12; 686 687 case MEDIA_BUS_FMT_RGB161616_1X48: 688 case MEDIA_BUS_FMT_YUV16_1X48: 689 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 690 return 16; 691 692 default: 693 return 0; 694 } 695 } 696 697 /* 698 * this submodule is responsible for the video data synchronization. 699 * for example, for RGB 4:4:4 input, the data map is defined as 700 * pin{47~40} <==> R[7:0] 701 * pin{31~24} <==> G[7:0] 702 * pin{15~8} <==> B[7:0] 703 */ 704 static void hdmi_video_sample(struct dw_hdmi *hdmi) 705 { 706 int color_format = 0; 707 u8 val; 708 709 switch (hdmi->hdmi_data.enc_in_bus_format) { 710 case MEDIA_BUS_FMT_RGB888_1X24: 711 color_format = 0x01; 712 break; 713 case MEDIA_BUS_FMT_RGB101010_1X30: 714 color_format = 0x03; 715 break; 716 case MEDIA_BUS_FMT_RGB121212_1X36: 717 color_format = 0x05; 718 break; 719 case MEDIA_BUS_FMT_RGB161616_1X48: 720 color_format = 0x07; 721 break; 722 723 case MEDIA_BUS_FMT_YUV8_1X24: 724 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 725 color_format = 0x09; 726 break; 727 case MEDIA_BUS_FMT_YUV10_1X30: 728 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 729 color_format = 0x0B; 730 break; 731 case MEDIA_BUS_FMT_YUV12_1X36: 732 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 733 color_format = 0x0D; 734 break; 735 case MEDIA_BUS_FMT_YUV16_1X48: 736 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 737 color_format = 0x0F; 738 break; 739 740 case MEDIA_BUS_FMT_UYVY8_1X16: 741 color_format = 0x16; 742 break; 743 case MEDIA_BUS_FMT_UYVY10_1X20: 744 color_format = 0x14; 745 break; 746 case MEDIA_BUS_FMT_UYVY12_1X24: 747 color_format = 0x12; 748 break; 749 750 default: 751 return; 752 } 753 754 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 755 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 756 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 757 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 758 759 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 760 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 761 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 762 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 763 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 764 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 765 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 766 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 767 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 768 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 769 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 770 } 771 772 static int is_color_space_conversion(struct dw_hdmi *hdmi) 773 { 774 return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format; 775 } 776 777 static int is_color_space_decimation(struct dw_hdmi *hdmi) 778 { 779 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 780 return 0; 781 782 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 783 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 784 return 1; 785 786 return 0; 787 } 788 789 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 790 { 791 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 792 return 0; 793 794 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 795 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 796 return 1; 797 798 return 0; 799 } 800 801 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 802 { 803 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 804 unsigned i; 805 u32 csc_scale = 1; 806 807 if (is_color_space_conversion(hdmi)) { 808 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 809 if (hdmi->hdmi_data.enc_out_encoding == 810 V4L2_YCBCR_ENC_601) 811 csc_coeff = &csc_coeff_rgb_out_eitu601; 812 else 813 csc_coeff = &csc_coeff_rgb_out_eitu709; 814 } else if (hdmi_bus_fmt_is_rgb( 815 hdmi->hdmi_data.enc_in_bus_format)) { 816 if (hdmi->hdmi_data.enc_out_encoding == 817 V4L2_YCBCR_ENC_601) 818 csc_coeff = &csc_coeff_rgb_in_eitu601; 819 else 820 csc_coeff = &csc_coeff_rgb_in_eitu709; 821 csc_scale = 0; 822 } 823 } 824 825 /* The CSC registers are sequential, alternating MSB then LSB */ 826 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 827 u16 coeff_a = (*csc_coeff)[0][i]; 828 u16 coeff_b = (*csc_coeff)[1][i]; 829 u16 coeff_c = (*csc_coeff)[2][i]; 830 831 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 832 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 833 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 834 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 835 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 836 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 837 } 838 839 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 840 HDMI_CSC_SCALE); 841 } 842 843 static void hdmi_video_csc(struct dw_hdmi *hdmi) 844 { 845 int color_depth = 0; 846 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 847 int decimation = 0; 848 849 /* YCC422 interpolation to 444 mode */ 850 if (is_color_space_interpolation(hdmi)) 851 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 852 else if (is_color_space_decimation(hdmi)) 853 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 854 855 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 856 case 8: 857 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 858 break; 859 case 10: 860 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 861 break; 862 case 12: 863 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 864 break; 865 case 16: 866 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 867 break; 868 869 default: 870 return; 871 } 872 873 /* Configure the CSC registers */ 874 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 875 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 876 HDMI_CSC_SCALE); 877 878 dw_hdmi_update_csc_coeffs(hdmi); 879 } 880 881 /* 882 * HDMI video packetizer is used to packetize the data. 883 * for example, if input is YCC422 mode or repeater is used, 884 * data should be repacked this module can be bypassed. 885 */ 886 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 887 { 888 unsigned int color_depth = 0; 889 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 890 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 891 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 892 u8 val, vp_conf; 893 894 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 895 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 896 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 897 switch (hdmi_bus_fmt_color_depth( 898 hdmi->hdmi_data.enc_out_bus_format)) { 899 case 8: 900 color_depth = 4; 901 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 902 break; 903 case 10: 904 color_depth = 5; 905 break; 906 case 12: 907 color_depth = 6; 908 break; 909 case 16: 910 color_depth = 7; 911 break; 912 default: 913 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 914 } 915 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 916 switch (hdmi_bus_fmt_color_depth( 917 hdmi->hdmi_data.enc_out_bus_format)) { 918 case 0: 919 case 8: 920 remap_size = HDMI_VP_REMAP_YCC422_16bit; 921 break; 922 case 10: 923 remap_size = HDMI_VP_REMAP_YCC422_20bit; 924 break; 925 case 12: 926 remap_size = HDMI_VP_REMAP_YCC422_24bit; 927 break; 928 929 default: 930 return; 931 } 932 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 933 } else { 934 return; 935 } 936 937 /* set the packetizer registers */ 938 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 939 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | 940 ((hdmi_data->pix_repet_factor << 941 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & 942 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); 943 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 944 945 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 946 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 947 948 /* Data from pixel repeater block */ 949 if (hdmi_data->pix_repet_factor > 1) { 950 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 951 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 952 } else { /* data from packetizer block */ 953 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 954 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 955 } 956 957 hdmi_modb(hdmi, vp_conf, 958 HDMI_VP_CONF_PR_EN_MASK | 959 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 960 961 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 962 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 963 964 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 965 966 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 967 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 968 HDMI_VP_CONF_PP_EN_ENABLE | 969 HDMI_VP_CONF_YCC422_EN_DISABLE; 970 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 971 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 972 HDMI_VP_CONF_PP_EN_DISABLE | 973 HDMI_VP_CONF_YCC422_EN_ENABLE; 974 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 975 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 976 HDMI_VP_CONF_PP_EN_DISABLE | 977 HDMI_VP_CONF_YCC422_EN_DISABLE; 978 } else { 979 return; 980 } 981 982 hdmi_modb(hdmi, vp_conf, 983 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 984 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 985 986 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 987 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 988 HDMI_VP_STUFF_PP_STUFFING_MASK | 989 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 990 991 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 992 HDMI_VP_CONF); 993 } 994 995 /* ----------------------------------------------------------------------------- 996 * Synopsys PHY Handling 997 */ 998 999 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 1000 unsigned char bit) 1001 { 1002 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 1003 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 1004 } 1005 1006 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 1007 { 1008 u32 val; 1009 1010 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 1011 if (msec-- == 0) 1012 return false; 1013 udelay(1000); 1014 } 1015 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 1016 1017 return true; 1018 } 1019 1020 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 1021 unsigned char addr) 1022 { 1023 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 1024 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 1025 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 1026 HDMI_PHY_I2CM_DATAO_1_ADDR); 1027 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 1028 HDMI_PHY_I2CM_DATAO_0_ADDR); 1029 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 1030 HDMI_PHY_I2CM_OPERATION_ADDR); 1031 hdmi_phy_wait_i2c_done(hdmi, 1000); 1032 } 1033 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); 1034 1035 /* Filter out invalid setups to avoid configuring SCDC and scrambling */ 1036 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi) 1037 { 1038 struct drm_display_info *display = &hdmi->connector.display_info; 1039 1040 /* Completely disable SCDC support for older controllers */ 1041 if (hdmi->version < 0x200a) 1042 return false; 1043 1044 /* Disable if no DDC bus */ 1045 if (!hdmi->ddc) 1046 return false; 1047 1048 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */ 1049 if (!display->hdmi.scdc.supported || 1050 !display->hdmi.scdc.scrambling.supported) 1051 return false; 1052 1053 /* 1054 * Disable if display only support low TMDS rates and scrambling 1055 * for low rates is not supported either 1056 */ 1057 if (!display->hdmi.scdc.scrambling.low_rates && 1058 display->max_tmds_clock <= 340000) 1059 return false; 1060 1061 return true; 1062 } 1063 1064 /* 1065 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates: 1066 * - The Source shall suspend transmission of the TMDS clock and data 1067 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it 1068 * from a 0 to a 1 or from a 1 to a 0 1069 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from 1070 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming 1071 * transmission of TMDS clock and data 1072 * 1073 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio() 1074 * helper should called right before enabling the TMDS Clock and Data in 1075 * the PHY configuration callback. 1076 */ 1077 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi) 1078 { 1079 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1080 1081 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 1082 if (dw_hdmi_support_scdc(hdmi)) { 1083 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1084 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1); 1085 else 1086 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0); 1087 } 1088 } 1089 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio); 1090 1091 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 1092 { 1093 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 1094 HDMI_PHY_CONF0_PDZ_OFFSET, 1095 HDMI_PHY_CONF0_PDZ_MASK); 1096 } 1097 1098 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 1099 { 1100 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1101 HDMI_PHY_CONF0_ENTMDS_OFFSET, 1102 HDMI_PHY_CONF0_ENTMDS_MASK); 1103 } 1104 1105 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 1106 { 1107 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1108 HDMI_PHY_CONF0_SVSRET_OFFSET, 1109 HDMI_PHY_CONF0_SVSRET_MASK); 1110 } 1111 1112 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 1113 { 1114 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1115 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 1116 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 1117 } 1118 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq); 1119 1120 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 1121 { 1122 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1123 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 1124 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 1125 } 1126 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron); 1127 1128 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 1129 { 1130 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1131 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 1132 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 1133 } 1134 1135 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 1136 { 1137 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1138 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 1139 HDMI_PHY_CONF0_SELDIPIF_MASK); 1140 } 1141 1142 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi) 1143 { 1144 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 1145 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1146 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1147 } 1148 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset); 1149 1150 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) 1151 { 1152 hdmi_phy_test_clear(hdmi, 1); 1153 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR); 1154 hdmi_phy_test_clear(hdmi, 0); 1155 } 1156 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr); 1157 1158 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 1159 { 1160 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1161 unsigned int i; 1162 u16 val; 1163 1164 if (phy->gen == 1) { 1165 dw_hdmi_phy_enable_tmds(hdmi, 0); 1166 dw_hdmi_phy_enable_powerdown(hdmi, true); 1167 return; 1168 } 1169 1170 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 1171 1172 /* 1173 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 1174 * to low power mode. 1175 */ 1176 for (i = 0; i < 5; ++i) { 1177 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 1178 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 1179 break; 1180 1181 usleep_range(1000, 2000); 1182 } 1183 1184 if (val & HDMI_PHY_TX_PHY_LOCK) 1185 dev_warn(hdmi->dev, "PHY failed to power down\n"); 1186 else 1187 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); 1188 1189 dw_hdmi_phy_gen2_pddq(hdmi, 1); 1190 } 1191 1192 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 1193 { 1194 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1195 unsigned int i; 1196 u8 val; 1197 1198 if (phy->gen == 1) { 1199 dw_hdmi_phy_enable_powerdown(hdmi, false); 1200 1201 /* Toggle TMDS enable. */ 1202 dw_hdmi_phy_enable_tmds(hdmi, 0); 1203 dw_hdmi_phy_enable_tmds(hdmi, 1); 1204 return 0; 1205 } 1206 1207 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 1208 dw_hdmi_phy_gen2_pddq(hdmi, 0); 1209 1210 /* Wait for PHY PLL lock */ 1211 for (i = 0; i < 5; ++i) { 1212 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 1213 if (val) 1214 break; 1215 1216 usleep_range(1000, 2000); 1217 } 1218 1219 if (!val) { 1220 dev_err(hdmi->dev, "PHY PLL failed to lock\n"); 1221 return -ETIMEDOUT; 1222 } 1223 1224 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); 1225 return 0; 1226 } 1227 1228 /* 1229 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 1230 * information the DWC MHL PHY has the same register layout and is thus also 1231 * supported by this function. 1232 */ 1233 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 1234 const struct dw_hdmi_plat_data *pdata, 1235 unsigned long mpixelclock) 1236 { 1237 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 1238 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 1239 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 1240 1241 /* TOFIX Will need 420 specific PHY configuration tables */ 1242 1243 /* PLL/MPLL Cfg - always match on final entry */ 1244 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 1245 if (mpixelclock <= mpll_config->mpixelclock) 1246 break; 1247 1248 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 1249 if (mpixelclock <= curr_ctrl->mpixelclock) 1250 break; 1251 1252 for (; phy_config->mpixelclock != ~0UL; phy_config++) 1253 if (mpixelclock <= phy_config->mpixelclock) 1254 break; 1255 1256 if (mpll_config->mpixelclock == ~0UL || 1257 curr_ctrl->mpixelclock == ~0UL || 1258 phy_config->mpixelclock == ~0UL) 1259 return -EINVAL; 1260 1261 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 1262 HDMI_3D_TX_PHY_CPCE_CTRL); 1263 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 1264 HDMI_3D_TX_PHY_GMPCTRL); 1265 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 1266 HDMI_3D_TX_PHY_CURRCTRL); 1267 1268 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 1269 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 1270 HDMI_3D_TX_PHY_MSM_CTRL); 1271 1272 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 1273 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 1274 HDMI_3D_TX_PHY_CKSYMTXCTRL); 1275 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 1276 HDMI_3D_TX_PHY_VLEVCTRL); 1277 1278 /* Override and disable clock termination. */ 1279 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 1280 HDMI_3D_TX_PHY_CKCALCTRL); 1281 1282 return 0; 1283 } 1284 1285 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 1286 { 1287 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1288 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 1289 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 1290 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1291 int ret; 1292 1293 dw_hdmi_phy_power_off(hdmi); 1294 1295 dw_hdmi_set_high_tmds_clock_ratio(hdmi); 1296 1297 /* Leave low power consumption mode by asserting SVSRET. */ 1298 if (phy->has_svsret) 1299 dw_hdmi_phy_enable_svsret(hdmi, 1); 1300 1301 dw_hdmi_phy_reset(hdmi); 1302 1303 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 1304 1305 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); 1306 1307 /* Write to the PHY as configured by the platform */ 1308 if (pdata->configure_phy) 1309 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 1310 else 1311 ret = phy->configure(hdmi, pdata, mpixelclock); 1312 if (ret) { 1313 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", 1314 mpixelclock); 1315 return ret; 1316 } 1317 1318 /* Wait for resuming transmission of TMDS clock and data */ 1319 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1320 msleep(100); 1321 1322 return dw_hdmi_phy_power_on(hdmi); 1323 } 1324 1325 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 1326 struct drm_display_mode *mode) 1327 { 1328 int i, ret; 1329 1330 /* HDMI Phy spec says to do the phy initialization sequence twice */ 1331 for (i = 0; i < 2; i++) { 1332 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 1333 dw_hdmi_phy_sel_interface_control(hdmi, 0); 1334 1335 ret = hdmi_phy_configure(hdmi); 1336 if (ret) 1337 return ret; 1338 } 1339 1340 return 0; 1341 } 1342 1343 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 1344 { 1345 dw_hdmi_phy_power_off(hdmi); 1346 } 1347 1348 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 1349 void *data) 1350 { 1351 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 1352 connector_status_connected : connector_status_disconnected; 1353 } 1354 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); 1355 1356 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 1357 bool force, bool disabled, bool rxsense) 1358 { 1359 u8 old_mask = hdmi->phy_mask; 1360 1361 if (force || disabled || !rxsense) 1362 hdmi->phy_mask |= HDMI_PHY_RX_SENSE; 1363 else 1364 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; 1365 1366 if (old_mask != hdmi->phy_mask) 1367 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1368 } 1369 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd); 1370 1371 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) 1372 { 1373 /* 1374 * Configure the PHY RX SENSE and HPD interrupts polarities and clear 1375 * any pending interrupt. 1376 */ 1377 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); 1378 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1379 HDMI_IH_PHY_STAT0); 1380 1381 /* Enable cable hot plug irq. */ 1382 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1383 1384 /* Clear and unmute interrupts. */ 1385 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1386 HDMI_IH_PHY_STAT0); 1387 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 1388 HDMI_IH_MUTE_PHY_STAT0); 1389 } 1390 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd); 1391 1392 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 1393 .init = dw_hdmi_phy_init, 1394 .disable = dw_hdmi_phy_disable, 1395 .read_hpd = dw_hdmi_phy_read_hpd, 1396 .update_hpd = dw_hdmi_phy_update_hpd, 1397 .setup_hpd = dw_hdmi_phy_setup_hpd, 1398 }; 1399 1400 /* ----------------------------------------------------------------------------- 1401 * HDMI TX Setup 1402 */ 1403 1404 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) 1405 { 1406 u8 de; 1407 1408 if (hdmi->hdmi_data.video_mode.mdataenablepolarity) 1409 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1410 else 1411 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; 1412 1413 /* disable rx detect */ 1414 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, 1415 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 1416 1417 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); 1418 1419 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, 1420 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); 1421 } 1422 1423 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1424 { 1425 struct hdmi_avi_infoframe frame; 1426 u8 val; 1427 1428 /* Initialise info frame from DRM mode */ 1429 drm_hdmi_avi_infoframe_from_display_mode(&frame, 1430 &hdmi->connector, mode); 1431 1432 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1433 frame.colorspace = HDMI_COLORSPACE_YUV444; 1434 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1435 frame.colorspace = HDMI_COLORSPACE_YUV422; 1436 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1437 frame.colorspace = HDMI_COLORSPACE_YUV420; 1438 else 1439 frame.colorspace = HDMI_COLORSPACE_RGB; 1440 1441 /* Set up colorimetry */ 1442 switch (hdmi->hdmi_data.enc_out_encoding) { 1443 case V4L2_YCBCR_ENC_601: 1444 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1445 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1446 else 1447 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1448 frame.extended_colorimetry = 1449 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1450 break; 1451 case V4L2_YCBCR_ENC_709: 1452 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1453 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1454 else 1455 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1456 frame.extended_colorimetry = 1457 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1458 break; 1459 default: /* Carries no data */ 1460 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1461 frame.extended_colorimetry = 1462 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1463 break; 1464 } 1465 1466 frame.scan_mode = HDMI_SCAN_MODE_NONE; 1467 1468 /* 1469 * The Designware IP uses a different byte format from standard 1470 * AVI info frames, though generally the bits are in the correct 1471 * bytes. 1472 */ 1473 1474 /* 1475 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, 1476 * scan info in bits 4,5 rather than 0,1 and active aspect present in 1477 * bit 6 rather than 4. 1478 */ 1479 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); 1480 if (frame.active_aspect & 15) 1481 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1482 if (frame.top_bar || frame.bottom_bar) 1483 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1484 if (frame.left_bar || frame.right_bar) 1485 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1486 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1487 1488 /* AVI data byte 2 differences: none */ 1489 val = ((frame.colorimetry & 0x3) << 6) | 1490 ((frame.picture_aspect & 0x3) << 4) | 1491 (frame.active_aspect & 0xf); 1492 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1493 1494 /* AVI data byte 3 differences: none */ 1495 val = ((frame.extended_colorimetry & 0x7) << 4) | 1496 ((frame.quantization_range & 0x3) << 2) | 1497 (frame.nups & 0x3); 1498 if (frame.itc) 1499 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1500 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1501 1502 /* AVI data byte 4 differences: none */ 1503 val = frame.video_code & 0x7f; 1504 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1505 1506 /* AVI Data Byte 5- set up input and output pixel repetition */ 1507 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1508 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1509 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1510 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1511 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1512 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1513 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1514 1515 /* 1516 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1517 * ycc range in bits 2,3 rather than 6,7 1518 */ 1519 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1520 (frame.content_type & 0x3); 1521 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1522 1523 /* AVI Data Bytes 6-13 */ 1524 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1525 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1526 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1527 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1528 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1529 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1530 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1531 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1532 } 1533 1534 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1535 struct drm_display_mode *mode) 1536 { 1537 struct hdmi_vendor_infoframe frame; 1538 u8 buffer[10]; 1539 ssize_t err; 1540 1541 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, 1542 &hdmi->connector, 1543 mode); 1544 if (err < 0) 1545 /* 1546 * Going into that statement does not means vendor infoframe 1547 * fails. It just informed us that vendor infoframe is not 1548 * needed for the selected mode. Only 4k or stereoscopic 3D 1549 * mode requires vendor infoframe. So just simply return. 1550 */ 1551 return; 1552 1553 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1554 if (err < 0) { 1555 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1556 err); 1557 return; 1558 } 1559 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1560 HDMI_FC_DATAUTO0_VSD_MASK); 1561 1562 /* Set the length of HDMI vendor specific InfoFrame payload */ 1563 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1564 1565 /* Set 24bit IEEE Registration Identifier */ 1566 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1567 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1568 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1569 1570 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1571 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1572 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1573 1574 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1575 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1576 1577 /* Packet frame interpolation */ 1578 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1579 1580 /* Auto packets per frame and line spacing */ 1581 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1582 1583 /* Configures the Frame Composer On RDRB mode */ 1584 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1585 HDMI_FC_DATAUTO0_VSD_MASK); 1586 } 1587 1588 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1589 const struct drm_display_mode *mode) 1590 { 1591 u8 inv_val, bytes; 1592 struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi; 1593 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1594 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1595 unsigned int vdisplay, hdisplay; 1596 1597 vmode->mtmdsclock = vmode->mpixelclock = mode->clock * 1000; 1598 1599 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); 1600 1601 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1602 vmode->mtmdsclock /= 2; 1603 1604 /* Set up HDMI_FC_INVIDCONF */ 1605 inv_val = (hdmi->hdmi_data.hdcp_enable || 1606 (dw_hdmi_support_scdc(hdmi) && 1607 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 1608 hdmi_info->scdc.scrambling.low_rates)) ? 1609 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1610 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1611 1612 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1613 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1614 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1615 1616 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1617 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1618 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1619 1620 inv_val |= (vmode->mdataenablepolarity ? 1621 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1622 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1623 1624 if (hdmi->vic == 39) 1625 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1626 else 1627 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1628 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1629 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1630 1631 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1632 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1633 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1634 1635 inv_val |= hdmi->sink_is_hdmi ? 1636 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1637 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1638 1639 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1640 1641 hdisplay = mode->hdisplay; 1642 hblank = mode->htotal - mode->hdisplay; 1643 h_de_hs = mode->hsync_start - mode->hdisplay; 1644 hsync_len = mode->hsync_end - mode->hsync_start; 1645 1646 /* 1647 * When we're setting a YCbCr420 mode, we need 1648 * to adjust the horizontal timing to suit. 1649 */ 1650 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1651 hdisplay /= 2; 1652 hblank /= 2; 1653 h_de_hs /= 2; 1654 hsync_len /= 2; 1655 } 1656 1657 vdisplay = mode->vdisplay; 1658 vblank = mode->vtotal - mode->vdisplay; 1659 v_de_vs = mode->vsync_start - mode->vdisplay; 1660 vsync_len = mode->vsync_end - mode->vsync_start; 1661 1662 /* 1663 * When we're setting an interlaced mode, we need 1664 * to adjust the vertical timing to suit. 1665 */ 1666 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1667 vdisplay /= 2; 1668 vblank /= 2; 1669 v_de_vs /= 2; 1670 vsync_len /= 2; 1671 } 1672 1673 /* Scrambling Control */ 1674 if (dw_hdmi_support_scdc(hdmi)) { 1675 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 1676 hdmi_info->scdc.scrambling.low_rates) { 1677 /* 1678 * HDMI2.0 Specifies the following procedure: 1679 * After the Source Device has determined that 1680 * SCDC_Present is set (=1), the Source Device should 1681 * write the accurate Version of the Source Device 1682 * to the Source Version field in the SCDCS. 1683 * Source Devices compliant shall set the 1684 * Source Version = 1. 1685 */ 1686 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, 1687 &bytes); 1688 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, 1689 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); 1690 1691 /* Enabled Scrambling in the Sink */ 1692 drm_scdc_set_scrambling(hdmi->ddc, 1); 1693 1694 /* 1695 * To activate the scrambler feature, you must ensure 1696 * that the quasi-static configuration bit 1697 * fc_invidconf.HDCP_keepout is set at configuration 1698 * time, before the required mc_swrstzreq.tmdsswrst_req 1699 * reset request is issued. 1700 */ 1701 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 1702 HDMI_MC_SWRSTZ); 1703 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 1704 } else { 1705 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 1706 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 1707 HDMI_MC_SWRSTZ); 1708 drm_scdc_set_scrambling(hdmi->ddc, 0); 1709 } 1710 } 1711 1712 /* Set up horizontal active pixel width */ 1713 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 1714 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 1715 1716 /* Set up vertical active lines */ 1717 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1718 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1719 1720 /* Set up horizontal blanking pixel region width */ 1721 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 1722 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 1723 1724 /* Set up vertical blanking pixel region width */ 1725 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 1726 1727 /* Set up HSYNC active edge delay width (in pixel clks) */ 1728 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 1729 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 1730 1731 /* Set up VSYNC active edge delay (in lines) */ 1732 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 1733 1734 /* Set up HSYNC active pulse width (in pixel clks) */ 1735 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 1736 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 1737 1738 /* Set up VSYNC active edge delay (in lines) */ 1739 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 1740 } 1741 1742 /* HDMI Initialization Step B.4 */ 1743 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 1744 { 1745 /* control period minimum duration */ 1746 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 1747 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 1748 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 1749 1750 /* Set to fill TMDS data channels */ 1751 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 1752 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 1753 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 1754 1755 /* Enable pixel clock and tmds data path */ 1756 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE | 1757 HDMI_MC_CLKDIS_CSCCLK_DISABLE | 1758 HDMI_MC_CLKDIS_AUDCLK_DISABLE | 1759 HDMI_MC_CLKDIS_PREPCLK_DISABLE | 1760 HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1761 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 1762 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1763 1764 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1765 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1766 1767 /* Enable csc path */ 1768 if (is_color_space_conversion(hdmi)) { 1769 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 1770 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1771 } 1772 1773 /* Enable color space conversion if needed */ 1774 if (is_color_space_conversion(hdmi)) 1775 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 1776 HDMI_MC_FLOWCTRL); 1777 else 1778 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 1779 HDMI_MC_FLOWCTRL); 1780 } 1781 1782 /* Workaround to clear the overflow condition */ 1783 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 1784 { 1785 unsigned int count; 1786 unsigned int i; 1787 u8 val; 1788 1789 /* 1790 * Under some circumstances the Frame Composer arithmetic unit can miss 1791 * an FC register write due to being busy processing the previous one. 1792 * The issue can be worked around by issuing a TMDS software reset and 1793 * then write one of the FC registers several times. 1794 * 1795 * The number of iterations matters and depends on the HDMI TX revision 1796 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL 1797 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified 1798 * as needing the workaround, with 4 iterations for v1.30a and 1 1799 * iteration for others. 1800 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing 1801 * the workaround with a single iteration. 1802 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have 1803 * been identified as needing the workaround with a single iteration. 1804 */ 1805 1806 switch (hdmi->version) { 1807 case 0x130a: 1808 count = 4; 1809 break; 1810 case 0x131a: 1811 case 0x132a: 1812 case 0x200a: 1813 case 0x201a: 1814 case 0x211a: 1815 case 0x212a: 1816 count = 1; 1817 break; 1818 default: 1819 return; 1820 } 1821 1822 /* TMDS software reset */ 1823 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 1824 1825 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 1826 for (i = 0; i < count; i++) 1827 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 1828 } 1829 1830 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 1831 { 1832 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 1833 HDMI_IH_MUTE_FC_STAT2); 1834 } 1835 1836 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1837 { 1838 int ret; 1839 1840 hdmi_disable_overflow_interrupts(hdmi); 1841 1842 hdmi->vic = drm_match_cea_mode(mode); 1843 1844 if (!hdmi->vic) { 1845 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); 1846 } else { 1847 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); 1848 } 1849 1850 if ((hdmi->vic == 6) || (hdmi->vic == 7) || 1851 (hdmi->vic == 21) || (hdmi->vic == 22) || 1852 (hdmi->vic == 2) || (hdmi->vic == 3) || 1853 (hdmi->vic == 17) || (hdmi->vic == 18)) 1854 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 1855 else 1856 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 1857 1858 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 1859 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 1860 1861 /* TOFIX: Get input format from plat data or fallback to RGB888 */ 1862 if (hdmi->plat_data->input_bus_format) 1863 hdmi->hdmi_data.enc_in_bus_format = 1864 hdmi->plat_data->input_bus_format; 1865 else 1866 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1867 1868 /* TOFIX: Get input encoding from plat data or fallback to none */ 1869 if (hdmi->plat_data->input_bus_encoding) 1870 hdmi->hdmi_data.enc_in_encoding = 1871 hdmi->plat_data->input_bus_encoding; 1872 else 1873 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 1874 1875 /* TOFIX: Default to RGB888 output format */ 1876 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1877 1878 hdmi->hdmi_data.pix_repet_factor = 0; 1879 hdmi->hdmi_data.hdcp_enable = 0; 1880 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 1881 1882 /* HDMI Initialization Step B.1 */ 1883 hdmi_av_composer(hdmi, mode); 1884 1885 /* HDMI Initializateion Step B.2 */ 1886 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode); 1887 if (ret) 1888 return ret; 1889 hdmi->phy.enabled = true; 1890 1891 /* HDMI Initialization Step B.3 */ 1892 dw_hdmi_enable_video_path(hdmi); 1893 1894 if (hdmi->sink_has_audio) { 1895 dev_dbg(hdmi->dev, "sink has audio support\n"); 1896 1897 /* HDMI Initialization Step E - Configure audio */ 1898 hdmi_clk_regenerator_update_pixel_clock(hdmi); 1899 hdmi_enable_audio_clk(hdmi, true); 1900 } 1901 1902 /* not for DVI mode */ 1903 if (hdmi->sink_is_hdmi) { 1904 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); 1905 1906 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 1907 hdmi_config_AVI(hdmi, mode); 1908 hdmi_config_vendor_specific_infoframe(hdmi, mode); 1909 } else { 1910 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); 1911 } 1912 1913 hdmi_video_packetize(hdmi); 1914 hdmi_video_csc(hdmi); 1915 hdmi_video_sample(hdmi); 1916 hdmi_tx_hdcp_config(hdmi); 1917 1918 dw_hdmi_clear_overflow(hdmi); 1919 1920 return 0; 1921 } 1922 1923 static void dw_hdmi_setup_i2c(struct dw_hdmi *hdmi) 1924 { 1925 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, 1926 HDMI_PHY_I2CM_INT_ADDR); 1927 1928 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | 1929 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, 1930 HDMI_PHY_I2CM_CTLINT_ADDR); 1931 } 1932 1933 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) 1934 { 1935 u8 ih_mute; 1936 1937 /* 1938 * Boot up defaults are: 1939 * HDMI_IH_MUTE = 0x03 (disabled) 1940 * HDMI_IH_MUTE_* = 0x00 (enabled) 1941 * 1942 * Disable top level interrupt bits in HDMI block 1943 */ 1944 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | 1945 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 1946 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; 1947 1948 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 1949 1950 /* by default mask all interrupts */ 1951 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); 1952 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 1953 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 1954 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 1955 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); 1956 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); 1957 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); 1958 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); 1959 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); 1960 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); 1961 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); 1962 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); 1963 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); 1964 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); 1965 1966 /* Disable interrupts in the IH_MUTE_* registers */ 1967 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 1968 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 1969 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 1970 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 1971 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); 1972 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 1973 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 1974 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 1975 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 1976 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 1977 1978 /* Enable top level interrupt bits in HDMI block */ 1979 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 1980 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); 1981 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 1982 } 1983 1984 static void dw_hdmi_poweron(struct dw_hdmi *hdmi) 1985 { 1986 hdmi->bridge_is_on = true; 1987 dw_hdmi_setup(hdmi, &hdmi->previous_mode); 1988 } 1989 1990 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) 1991 { 1992 if (hdmi->phy.enabled) { 1993 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 1994 hdmi->phy.enabled = false; 1995 } 1996 1997 hdmi->bridge_is_on = false; 1998 } 1999 2000 static void dw_hdmi_update_power(struct dw_hdmi *hdmi) 2001 { 2002 int force = hdmi->force; 2003 2004 if (hdmi->disabled) { 2005 force = DRM_FORCE_OFF; 2006 } else if (force == DRM_FORCE_UNSPECIFIED) { 2007 if (hdmi->rxsense) 2008 force = DRM_FORCE_ON; 2009 else 2010 force = DRM_FORCE_OFF; 2011 } 2012 2013 if (force == DRM_FORCE_OFF) { 2014 if (hdmi->bridge_is_on) 2015 dw_hdmi_poweroff(hdmi); 2016 } else { 2017 if (!hdmi->bridge_is_on) 2018 dw_hdmi_poweron(hdmi); 2019 } 2020 } 2021 2022 /* 2023 * Adjust the detection of RXSENSE according to whether we have a forced 2024 * connection mode enabled, or whether we have been disabled. There is 2025 * no point processing RXSENSE interrupts if we have a forced connection 2026 * state, or DRM has us disabled. 2027 * 2028 * We also disable rxsense interrupts when we think we're disconnected 2029 * to avoid floating TDMS signals giving false rxsense interrupts. 2030 * 2031 * Note: we still need to listen for HPD interrupts even when DRM has us 2032 * disabled so that we can detect a connect event. 2033 */ 2034 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) 2035 { 2036 if (hdmi->phy.ops->update_hpd) 2037 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, 2038 hdmi->force, hdmi->disabled, 2039 hdmi->rxsense); 2040 } 2041 2042 static enum drm_connector_status 2043 dw_hdmi_connector_detect(struct drm_connector *connector, bool force) 2044 { 2045 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2046 connector); 2047 2048 mutex_lock(&hdmi->mutex); 2049 hdmi->force = DRM_FORCE_UNSPECIFIED; 2050 dw_hdmi_update_power(hdmi); 2051 dw_hdmi_update_phy_mask(hdmi); 2052 mutex_unlock(&hdmi->mutex); 2053 2054 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 2055 } 2056 2057 static int dw_hdmi_connector_get_modes(struct drm_connector *connector) 2058 { 2059 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2060 connector); 2061 struct edid *edid; 2062 int ret = 0; 2063 2064 if (!hdmi->ddc) 2065 return 0; 2066 2067 edid = drm_get_edid(connector, hdmi->ddc); 2068 if (edid) { 2069 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", 2070 edid->width_cm, edid->height_cm); 2071 2072 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); 2073 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2074 drm_connector_update_edid_property(connector, edid); 2075 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); 2076 ret = drm_add_edid_modes(connector, edid); 2077 kfree(edid); 2078 } else { 2079 dev_dbg(hdmi->dev, "failed to get edid\n"); 2080 } 2081 2082 return ret; 2083 } 2084 2085 static void dw_hdmi_connector_force(struct drm_connector *connector) 2086 { 2087 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2088 connector); 2089 2090 mutex_lock(&hdmi->mutex); 2091 hdmi->force = connector->force; 2092 dw_hdmi_update_power(hdmi); 2093 dw_hdmi_update_phy_mask(hdmi); 2094 mutex_unlock(&hdmi->mutex); 2095 } 2096 2097 static const struct drm_connector_funcs dw_hdmi_connector_funcs = { 2098 .fill_modes = drm_helper_probe_single_connector_modes, 2099 .detect = dw_hdmi_connector_detect, 2100 .destroy = drm_connector_cleanup, 2101 .force = dw_hdmi_connector_force, 2102 .reset = drm_atomic_helper_connector_reset, 2103 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2104 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2105 }; 2106 2107 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { 2108 .get_modes = dw_hdmi_connector_get_modes, 2109 }; 2110 2111 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge) 2112 { 2113 struct dw_hdmi *hdmi = bridge->driver_private; 2114 struct drm_encoder *encoder = bridge->encoder; 2115 struct drm_connector *connector = &hdmi->connector; 2116 2117 connector->interlace_allowed = 1; 2118 connector->polled = DRM_CONNECTOR_POLL_HPD; 2119 2120 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); 2121 2122 drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs, 2123 DRM_MODE_CONNECTOR_HDMIA); 2124 2125 drm_connector_attach_encoder(connector, encoder); 2126 2127 return 0; 2128 } 2129 2130 static enum drm_mode_status 2131 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 2132 const struct drm_display_mode *mode) 2133 { 2134 struct dw_hdmi *hdmi = bridge->driver_private; 2135 struct drm_connector *connector = &hdmi->connector; 2136 enum drm_mode_status mode_status = MODE_OK; 2137 2138 /* We don't support double-clocked modes */ 2139 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2140 return MODE_BAD; 2141 2142 if (hdmi->plat_data->mode_valid) 2143 mode_status = hdmi->plat_data->mode_valid(connector, mode); 2144 2145 return mode_status; 2146 } 2147 2148 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, 2149 const struct drm_display_mode *orig_mode, 2150 const struct drm_display_mode *mode) 2151 { 2152 struct dw_hdmi *hdmi = bridge->driver_private; 2153 2154 mutex_lock(&hdmi->mutex); 2155 2156 /* Store the display mode for plugin/DKMS poweron events */ 2157 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 2158 2159 mutex_unlock(&hdmi->mutex); 2160 } 2161 2162 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge) 2163 { 2164 struct dw_hdmi *hdmi = bridge->driver_private; 2165 2166 mutex_lock(&hdmi->mutex); 2167 hdmi->disabled = true; 2168 dw_hdmi_update_power(hdmi); 2169 dw_hdmi_update_phy_mask(hdmi); 2170 mutex_unlock(&hdmi->mutex); 2171 } 2172 2173 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge) 2174 { 2175 struct dw_hdmi *hdmi = bridge->driver_private; 2176 2177 mutex_lock(&hdmi->mutex); 2178 hdmi->disabled = false; 2179 dw_hdmi_update_power(hdmi); 2180 dw_hdmi_update_phy_mask(hdmi); 2181 mutex_unlock(&hdmi->mutex); 2182 } 2183 2184 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { 2185 .attach = dw_hdmi_bridge_attach, 2186 .enable = dw_hdmi_bridge_enable, 2187 .disable = dw_hdmi_bridge_disable, 2188 .mode_set = dw_hdmi_bridge_mode_set, 2189 .mode_valid = dw_hdmi_bridge_mode_valid, 2190 }; 2191 2192 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) 2193 { 2194 struct dw_hdmi_i2c *i2c = hdmi->i2c; 2195 unsigned int stat; 2196 2197 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 2198 if (!stat) 2199 return IRQ_NONE; 2200 2201 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0); 2202 2203 i2c->stat = stat; 2204 2205 complete(&i2c->cmp); 2206 2207 return IRQ_HANDLED; 2208 } 2209 2210 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) 2211 { 2212 struct dw_hdmi *hdmi = dev_id; 2213 u8 intr_stat; 2214 irqreturn_t ret = IRQ_NONE; 2215 2216 if (hdmi->i2c) 2217 ret = dw_hdmi_i2c_irq(hdmi); 2218 2219 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2220 if (intr_stat) { 2221 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2222 return IRQ_WAKE_THREAD; 2223 } 2224 2225 return ret; 2226 } 2227 2228 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) 2229 { 2230 mutex_lock(&hdmi->mutex); 2231 2232 if (!hdmi->force) { 2233 /* 2234 * If the RX sense status indicates we're disconnected, 2235 * clear the software rxsense status. 2236 */ 2237 if (!rx_sense) 2238 hdmi->rxsense = false; 2239 2240 /* 2241 * Only set the software rxsense status when both 2242 * rxsense and hpd indicates we're connected. 2243 * This avoids what seems to be bad behaviour in 2244 * at least iMX6S versions of the phy. 2245 */ 2246 if (hpd) 2247 hdmi->rxsense = true; 2248 2249 dw_hdmi_update_power(hdmi); 2250 dw_hdmi_update_phy_mask(hdmi); 2251 } 2252 mutex_unlock(&hdmi->mutex); 2253 } 2254 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); 2255 2256 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) 2257 { 2258 struct dw_hdmi *hdmi = dev_id; 2259 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; 2260 2261 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2262 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); 2263 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); 2264 2265 phy_pol_mask = 0; 2266 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) 2267 phy_pol_mask |= HDMI_PHY_HPD; 2268 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) 2269 phy_pol_mask |= HDMI_PHY_RX_SENSE0; 2270 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) 2271 phy_pol_mask |= HDMI_PHY_RX_SENSE1; 2272 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) 2273 phy_pol_mask |= HDMI_PHY_RX_SENSE2; 2274 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) 2275 phy_pol_mask |= HDMI_PHY_RX_SENSE3; 2276 2277 if (phy_pol_mask) 2278 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); 2279 2280 /* 2281 * RX sense tells us whether the TDMS transmitters are detecting 2282 * load - in other words, there's something listening on the 2283 * other end of the link. Use this to decide whether we should 2284 * power on the phy as HPD may be toggled by the sink to merely 2285 * ask the source to re-read the EDID. 2286 */ 2287 if (intr_stat & 2288 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { 2289 dw_hdmi_setup_rx_sense(hdmi, 2290 phy_stat & HDMI_PHY_HPD, 2291 phy_stat & HDMI_PHY_RX_SENSE); 2292 2293 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) 2294 cec_notifier_set_phys_addr(hdmi->cec_notifier, 2295 CEC_PHYS_ADDR_INVALID); 2296 } 2297 2298 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { 2299 dev_dbg(hdmi->dev, "EVENT=%s\n", 2300 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout"); 2301 if (hdmi->bridge.dev) 2302 drm_helper_hpd_irq_event(hdmi->bridge.dev); 2303 } 2304 2305 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); 2306 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 2307 HDMI_IH_MUTE_PHY_STAT0); 2308 2309 return IRQ_HANDLED; 2310 } 2311 2312 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 2313 { 2314 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 2315 .name = "DWC HDMI TX PHY", 2316 .gen = 1, 2317 }, { 2318 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 2319 .name = "DWC MHL PHY + HEAC PHY", 2320 .gen = 2, 2321 .has_svsret = true, 2322 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2323 }, { 2324 .type = DW_HDMI_PHY_DWC_MHL_PHY, 2325 .name = "DWC MHL PHY", 2326 .gen = 2, 2327 .has_svsret = true, 2328 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2329 }, { 2330 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 2331 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 2332 .gen = 2, 2333 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2334 }, { 2335 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 2336 .name = "DWC HDMI 3D TX PHY", 2337 .gen = 2, 2338 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2339 }, { 2340 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 2341 .name = "DWC HDMI 2.0 TX PHY", 2342 .gen = 2, 2343 .has_svsret = true, 2344 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2345 }, { 2346 .type = DW_HDMI_PHY_VENDOR_PHY, 2347 .name = "Vendor PHY", 2348 } 2349 }; 2350 2351 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 2352 { 2353 unsigned int i; 2354 u8 phy_type; 2355 2356 phy_type = hdmi->plat_data->phy_force_vendor ? 2357 DW_HDMI_PHY_VENDOR_PHY : 2358 hdmi_readb(hdmi, HDMI_CONFIG2_ID); 2359 2360 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { 2361 /* Vendor PHYs require support from the glue layer. */ 2362 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 2363 dev_err(hdmi->dev, 2364 "Vendor HDMI PHY not supported by glue layer\n"); 2365 return -ENODEV; 2366 } 2367 2368 hdmi->phy.ops = hdmi->plat_data->phy_ops; 2369 hdmi->phy.data = hdmi->plat_data->phy_data; 2370 hdmi->phy.name = hdmi->plat_data->phy_name; 2371 return 0; 2372 } 2373 2374 /* Synopsys PHYs are handled internally. */ 2375 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 2376 if (dw_hdmi_phys[i].type == phy_type) { 2377 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 2378 hdmi->phy.name = dw_hdmi_phys[i].name; 2379 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 2380 2381 if (!dw_hdmi_phys[i].configure && 2382 !hdmi->plat_data->configure_phy) { 2383 dev_err(hdmi->dev, "%s requires platform support\n", 2384 hdmi->phy.name); 2385 return -ENODEV; 2386 } 2387 2388 return 0; 2389 } 2390 } 2391 2392 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); 2393 return -ENODEV; 2394 } 2395 2396 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi) 2397 { 2398 mutex_lock(&hdmi->mutex); 2399 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE; 2400 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2401 mutex_unlock(&hdmi->mutex); 2402 } 2403 2404 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi) 2405 { 2406 mutex_lock(&hdmi->mutex); 2407 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE; 2408 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2409 mutex_unlock(&hdmi->mutex); 2410 } 2411 2412 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = { 2413 .write = hdmi_writeb, 2414 .read = hdmi_readb, 2415 .enable = dw_hdmi_cec_enable, 2416 .disable = dw_hdmi_cec_disable, 2417 }; 2418 2419 static const struct regmap_config hdmi_regmap_8bit_config = { 2420 .reg_bits = 32, 2421 .val_bits = 8, 2422 .reg_stride = 1, 2423 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, 2424 }; 2425 2426 static const struct regmap_config hdmi_regmap_32bit_config = { 2427 .reg_bits = 32, 2428 .val_bits = 32, 2429 .reg_stride = 4, 2430 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, 2431 }; 2432 2433 static struct dw_hdmi * 2434 __dw_hdmi_probe(struct platform_device *pdev, 2435 const struct dw_hdmi_plat_data *plat_data) 2436 { 2437 struct device *dev = &pdev->dev; 2438 struct device_node *np = dev->of_node; 2439 struct platform_device_info pdevinfo; 2440 struct device_node *ddc_node; 2441 struct dw_hdmi_cec_data cec; 2442 struct dw_hdmi *hdmi; 2443 struct resource *iores = NULL; 2444 int irq; 2445 int ret; 2446 u32 val = 1; 2447 u8 prod_id0; 2448 u8 prod_id1; 2449 u8 config0; 2450 u8 config3; 2451 2452 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 2453 if (!hdmi) 2454 return ERR_PTR(-ENOMEM); 2455 2456 hdmi->plat_data = plat_data; 2457 hdmi->dev = dev; 2458 hdmi->sample_rate = 48000; 2459 hdmi->disabled = true; 2460 hdmi->rxsense = true; 2461 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); 2462 hdmi->mc_clkdis = 0x7f; 2463 2464 mutex_init(&hdmi->mutex); 2465 mutex_init(&hdmi->audio_mutex); 2466 spin_lock_init(&hdmi->audio_lock); 2467 2468 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 2469 if (ddc_node) { 2470 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); 2471 of_node_put(ddc_node); 2472 if (!hdmi->ddc) { 2473 dev_dbg(hdmi->dev, "failed to read ddc node\n"); 2474 return ERR_PTR(-EPROBE_DEFER); 2475 } 2476 2477 } else { 2478 dev_dbg(hdmi->dev, "no ddc property found\n"); 2479 } 2480 2481 if (!plat_data->regm) { 2482 const struct regmap_config *reg_config; 2483 2484 of_property_read_u32(np, "reg-io-width", &val); 2485 switch (val) { 2486 case 4: 2487 reg_config = &hdmi_regmap_32bit_config; 2488 hdmi->reg_shift = 2; 2489 break; 2490 case 1: 2491 reg_config = &hdmi_regmap_8bit_config; 2492 break; 2493 default: 2494 dev_err(dev, "reg-io-width must be 1 or 4\n"); 2495 return ERR_PTR(-EINVAL); 2496 } 2497 2498 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2499 hdmi->regs = devm_ioremap_resource(dev, iores); 2500 if (IS_ERR(hdmi->regs)) { 2501 ret = PTR_ERR(hdmi->regs); 2502 goto err_res; 2503 } 2504 2505 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); 2506 if (IS_ERR(hdmi->regm)) { 2507 dev_err(dev, "Failed to configure regmap\n"); 2508 ret = PTR_ERR(hdmi->regm); 2509 goto err_res; 2510 } 2511 } else { 2512 hdmi->regm = plat_data->regm; 2513 } 2514 2515 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); 2516 if (IS_ERR(hdmi->isfr_clk)) { 2517 ret = PTR_ERR(hdmi->isfr_clk); 2518 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); 2519 goto err_res; 2520 } 2521 2522 ret = clk_prepare_enable(hdmi->isfr_clk); 2523 if (ret) { 2524 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret); 2525 goto err_res; 2526 } 2527 2528 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); 2529 if (IS_ERR(hdmi->iahb_clk)) { 2530 ret = PTR_ERR(hdmi->iahb_clk); 2531 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); 2532 goto err_isfr; 2533 } 2534 2535 ret = clk_prepare_enable(hdmi->iahb_clk); 2536 if (ret) { 2537 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret); 2538 goto err_isfr; 2539 } 2540 2541 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec"); 2542 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) { 2543 hdmi->cec_clk = NULL; 2544 } else if (IS_ERR(hdmi->cec_clk)) { 2545 ret = PTR_ERR(hdmi->cec_clk); 2546 if (ret != -EPROBE_DEFER) 2547 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n", 2548 ret); 2549 2550 hdmi->cec_clk = NULL; 2551 goto err_iahb; 2552 } else { 2553 ret = clk_prepare_enable(hdmi->cec_clk); 2554 if (ret) { 2555 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n", 2556 ret); 2557 goto err_iahb; 2558 } 2559 } 2560 2561 /* Product and revision IDs */ 2562 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 2563 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 2564 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); 2565 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); 2566 2567 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || 2568 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { 2569 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", 2570 hdmi->version, prod_id0, prod_id1); 2571 ret = -ENODEV; 2572 goto err_iahb; 2573 } 2574 2575 ret = dw_hdmi_detect_phy(hdmi); 2576 if (ret < 0) 2577 goto err_iahb; 2578 2579 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", 2580 hdmi->version >> 12, hdmi->version & 0xfff, 2581 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", 2582 hdmi->phy.name); 2583 2584 initialize_hdmi_ih_mutes(hdmi); 2585 2586 irq = platform_get_irq(pdev, 0); 2587 if (irq < 0) { 2588 ret = irq; 2589 goto err_iahb; 2590 } 2591 2592 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, 2593 dw_hdmi_irq, IRQF_SHARED, 2594 dev_name(dev), hdmi); 2595 if (ret) 2596 goto err_iahb; 2597 2598 hdmi->cec_notifier = cec_notifier_get(dev); 2599 if (!hdmi->cec_notifier) { 2600 ret = -ENOMEM; 2601 goto err_iahb; 2602 } 2603 2604 /* 2605 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator 2606 * N and cts values before enabling phy 2607 */ 2608 hdmi_init_clk_regenerator(hdmi); 2609 2610 /* If DDC bus is not specified, try to register HDMI I2C bus */ 2611 if (!hdmi->ddc) { 2612 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); 2613 if (IS_ERR(hdmi->ddc)) 2614 hdmi->ddc = NULL; 2615 } 2616 2617 hdmi->bridge.driver_private = hdmi; 2618 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; 2619 #ifdef CONFIG_OF 2620 hdmi->bridge.of_node = pdev->dev.of_node; 2621 #endif 2622 2623 dw_hdmi_setup_i2c(hdmi); 2624 if (hdmi->phy.ops->setup_hpd) 2625 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 2626 2627 memset(&pdevinfo, 0, sizeof(pdevinfo)); 2628 pdevinfo.parent = dev; 2629 pdevinfo.id = PLATFORM_DEVID_AUTO; 2630 2631 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); 2632 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 2633 2634 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { 2635 struct dw_hdmi_audio_data audio; 2636 2637 audio.phys = iores->start; 2638 audio.base = hdmi->regs; 2639 audio.irq = irq; 2640 audio.hdmi = hdmi; 2641 audio.eld = hdmi->connector.eld; 2642 hdmi->enable_audio = dw_hdmi_ahb_audio_enable; 2643 hdmi->disable_audio = dw_hdmi_ahb_audio_disable; 2644 2645 pdevinfo.name = "dw-hdmi-ahb-audio"; 2646 pdevinfo.data = &audio; 2647 pdevinfo.size_data = sizeof(audio); 2648 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2649 hdmi->audio = platform_device_register_full(&pdevinfo); 2650 } else if (config0 & HDMI_CONFIG0_I2S) { 2651 struct dw_hdmi_i2s_audio_data audio; 2652 2653 audio.hdmi = hdmi; 2654 audio.write = hdmi_writeb; 2655 audio.read = hdmi_readb; 2656 hdmi->enable_audio = dw_hdmi_i2s_audio_enable; 2657 hdmi->disable_audio = dw_hdmi_i2s_audio_disable; 2658 2659 pdevinfo.name = "dw-hdmi-i2s-audio"; 2660 pdevinfo.data = &audio; 2661 pdevinfo.size_data = sizeof(audio); 2662 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2663 hdmi->audio = platform_device_register_full(&pdevinfo); 2664 } 2665 2666 if (config0 & HDMI_CONFIG0_CEC) { 2667 cec.hdmi = hdmi; 2668 cec.ops = &dw_hdmi_cec_ops; 2669 cec.irq = irq; 2670 2671 pdevinfo.name = "dw-hdmi-cec"; 2672 pdevinfo.data = &cec; 2673 pdevinfo.size_data = sizeof(cec); 2674 pdevinfo.dma_mask = 0; 2675 2676 hdmi->cec = platform_device_register_full(&pdevinfo); 2677 } 2678 2679 /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */ 2680 if (hdmi->i2c) 2681 dw_hdmi_i2c_init(hdmi); 2682 2683 return hdmi; 2684 2685 err_iahb: 2686 if (hdmi->i2c) { 2687 i2c_del_adapter(&hdmi->i2c->adap); 2688 hdmi->ddc = NULL; 2689 } 2690 2691 if (hdmi->cec_notifier) 2692 cec_notifier_put(hdmi->cec_notifier); 2693 2694 clk_disable_unprepare(hdmi->iahb_clk); 2695 if (hdmi->cec_clk) 2696 clk_disable_unprepare(hdmi->cec_clk); 2697 err_isfr: 2698 clk_disable_unprepare(hdmi->isfr_clk); 2699 err_res: 2700 i2c_put_adapter(hdmi->ddc); 2701 2702 return ERR_PTR(ret); 2703 } 2704 2705 static void __dw_hdmi_remove(struct dw_hdmi *hdmi) 2706 { 2707 if (hdmi->audio && !IS_ERR(hdmi->audio)) 2708 platform_device_unregister(hdmi->audio); 2709 if (!IS_ERR(hdmi->cec)) 2710 platform_device_unregister(hdmi->cec); 2711 2712 /* Disable all interrupts */ 2713 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2714 2715 if (hdmi->cec_notifier) 2716 cec_notifier_put(hdmi->cec_notifier); 2717 2718 clk_disable_unprepare(hdmi->iahb_clk); 2719 clk_disable_unprepare(hdmi->isfr_clk); 2720 if (hdmi->cec_clk) 2721 clk_disable_unprepare(hdmi->cec_clk); 2722 2723 if (hdmi->i2c) 2724 i2c_del_adapter(&hdmi->i2c->adap); 2725 else 2726 i2c_put_adapter(hdmi->ddc); 2727 } 2728 2729 /* ----------------------------------------------------------------------------- 2730 * Probe/remove API, used from platforms based on the DRM bridge API. 2731 */ 2732 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, 2733 const struct dw_hdmi_plat_data *plat_data) 2734 { 2735 struct dw_hdmi *hdmi; 2736 2737 hdmi = __dw_hdmi_probe(pdev, plat_data); 2738 if (IS_ERR(hdmi)) 2739 return hdmi; 2740 2741 drm_bridge_add(&hdmi->bridge); 2742 2743 return hdmi; 2744 } 2745 EXPORT_SYMBOL_GPL(dw_hdmi_probe); 2746 2747 void dw_hdmi_remove(struct dw_hdmi *hdmi) 2748 { 2749 drm_bridge_remove(&hdmi->bridge); 2750 2751 __dw_hdmi_remove(hdmi); 2752 } 2753 EXPORT_SYMBOL_GPL(dw_hdmi_remove); 2754 2755 /* ----------------------------------------------------------------------------- 2756 * Bind/unbind API, used from platforms based on the component framework. 2757 */ 2758 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, 2759 struct drm_encoder *encoder, 2760 const struct dw_hdmi_plat_data *plat_data) 2761 { 2762 struct dw_hdmi *hdmi; 2763 int ret; 2764 2765 hdmi = __dw_hdmi_probe(pdev, plat_data); 2766 if (IS_ERR(hdmi)) 2767 return hdmi; 2768 2769 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL); 2770 if (ret) { 2771 dw_hdmi_remove(hdmi); 2772 DRM_ERROR("Failed to initialize bridge with drm\n"); 2773 return ERR_PTR(ret); 2774 } 2775 2776 return hdmi; 2777 } 2778 EXPORT_SYMBOL_GPL(dw_hdmi_bind); 2779 2780 void dw_hdmi_unbind(struct dw_hdmi *hdmi) 2781 { 2782 __dw_hdmi_remove(hdmi); 2783 } 2784 EXPORT_SYMBOL_GPL(dw_hdmi_unbind); 2785 2786 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 2787 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); 2788 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); 2789 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>"); 2790 MODULE_DESCRIPTION("DW HDMI transmitter driver"); 2791 MODULE_LICENSE("GPL"); 2792 MODULE_ALIAS("platform:dw-hdmi"); 2793