1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DesignWare High-Definition Multimedia Interface (HDMI) driver 4 * 5 * Copyright (C) 2013-2015 Mentor Graphics Inc. 6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 8 */ 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/hdmi.h> 13 #include <linux/irq.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of_device.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/regmap.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/spinlock.h> 21 22 #include <media/cec-notifier.h> 23 24 #include <uapi/linux/media-bus-format.h> 25 #include <uapi/linux/videodev2.h> 26 27 #include <drm/bridge/dw_hdmi.h> 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_bridge.h> 30 #include <drm/drm_edid.h> 31 #include <drm/drm_encoder_slave.h> 32 #include <drm/drm_of.h> 33 #include <drm/drm_print.h> 34 #include <drm/drm_probe_helper.h> 35 #include <drm/drm_scdc_helper.h> 36 37 #include "dw-hdmi-audio.h" 38 #include "dw-hdmi-cec.h" 39 #include "dw-hdmi.h" 40 41 #define DDC_SEGMENT_ADDR 0x30 42 43 #define HDMI_EDID_LEN 512 44 45 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ 46 #define SCDC_MIN_SOURCE_VERSION 0x1 47 48 #define HDMI14_MAX_TMDSCLK 340000000 49 50 enum hdmi_datamap { 51 RGB444_8B = 0x01, 52 RGB444_10B = 0x03, 53 RGB444_12B = 0x05, 54 RGB444_16B = 0x07, 55 YCbCr444_8B = 0x09, 56 YCbCr444_10B = 0x0B, 57 YCbCr444_12B = 0x0D, 58 YCbCr444_16B = 0x0F, 59 YCbCr422_8B = 0x16, 60 YCbCr422_10B = 0x14, 61 YCbCr422_12B = 0x12, 62 }; 63 64 static const u16 csc_coeff_default[3][4] = { 65 { 0x2000, 0x0000, 0x0000, 0x0000 }, 66 { 0x0000, 0x2000, 0x0000, 0x0000 }, 67 { 0x0000, 0x0000, 0x2000, 0x0000 } 68 }; 69 70 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 71 { 0x2000, 0x6926, 0x74fd, 0x010e }, 72 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 73 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 74 }; 75 76 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 77 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 78 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 79 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 80 }; 81 82 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 83 { 0x2591, 0x1322, 0x074b, 0x0000 }, 84 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 85 { 0x6acd, 0x7534, 0x2000, 0x0200 } 86 }; 87 88 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 89 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 90 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 91 { 0x6756, 0x78ab, 0x2000, 0x0200 } 92 }; 93 94 struct hdmi_vmode { 95 bool mdataenablepolarity; 96 97 unsigned int mpixelclock; 98 unsigned int mpixelrepetitioninput; 99 unsigned int mpixelrepetitionoutput; 100 unsigned int mtmdsclock; 101 }; 102 103 struct hdmi_data_info { 104 unsigned int enc_in_bus_format; 105 unsigned int enc_out_bus_format; 106 unsigned int enc_in_encoding; 107 unsigned int enc_out_encoding; 108 unsigned int pix_repet_factor; 109 unsigned int hdcp_enable; 110 struct hdmi_vmode video_mode; 111 }; 112 113 struct dw_hdmi_i2c { 114 struct i2c_adapter adap; 115 116 struct mutex lock; /* used to serialize data transfers */ 117 struct completion cmp; 118 u8 stat; 119 120 u8 slave_reg; 121 bool is_regaddr; 122 bool is_segment; 123 }; 124 125 struct dw_hdmi_phy_data { 126 enum dw_hdmi_phy_type type; 127 const char *name; 128 unsigned int gen; 129 bool has_svsret; 130 int (*configure)(struct dw_hdmi *hdmi, 131 const struct dw_hdmi_plat_data *pdata, 132 unsigned long mpixelclock); 133 }; 134 135 struct dw_hdmi { 136 struct drm_connector connector; 137 struct drm_bridge bridge; 138 139 unsigned int version; 140 141 struct platform_device *audio; 142 struct platform_device *cec; 143 struct device *dev; 144 struct clk *isfr_clk; 145 struct clk *iahb_clk; 146 struct clk *cec_clk; 147 struct dw_hdmi_i2c *i2c; 148 149 struct hdmi_data_info hdmi_data; 150 const struct dw_hdmi_plat_data *plat_data; 151 152 int vic; 153 154 u8 edid[HDMI_EDID_LEN]; 155 156 struct { 157 const struct dw_hdmi_phy_ops *ops; 158 const char *name; 159 void *data; 160 bool enabled; 161 } phy; 162 163 struct drm_display_mode previous_mode; 164 165 struct i2c_adapter *ddc; 166 void __iomem *regs; 167 bool sink_is_hdmi; 168 bool sink_has_audio; 169 170 struct pinctrl *pinctrl; 171 struct pinctrl_state *default_state; 172 struct pinctrl_state *unwedge_state; 173 174 struct mutex mutex; /* for state below and previous_mode */ 175 enum drm_connector_force force; /* mutex-protected force state */ 176 bool disabled; /* DRM has disabled our bridge */ 177 bool bridge_is_on; /* indicates the bridge is on */ 178 bool rxsense; /* rxsense state */ 179 u8 phy_mask; /* desired phy int mask settings */ 180 u8 mc_clkdis; /* clock disable register */ 181 182 spinlock_t audio_lock; 183 struct mutex audio_mutex; 184 unsigned int sample_rate; 185 unsigned int audio_cts; 186 unsigned int audio_n; 187 bool audio_enable; 188 189 unsigned int reg_shift; 190 struct regmap *regm; 191 void (*enable_audio)(struct dw_hdmi *hdmi); 192 void (*disable_audio)(struct dw_hdmi *hdmi); 193 194 struct mutex cec_notifier_mutex; 195 struct cec_notifier *cec_notifier; 196 }; 197 198 #define HDMI_IH_PHY_STAT0_RX_SENSE \ 199 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ 200 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) 201 202 #define HDMI_PHY_RX_SENSE \ 203 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ 204 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) 205 206 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 207 { 208 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); 209 } 210 211 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 212 { 213 unsigned int val = 0; 214 215 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); 216 217 return val; 218 } 219 220 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 221 { 222 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); 223 } 224 225 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 226 u8 shift, u8 mask) 227 { 228 hdmi_modb(hdmi, data << shift, mask, reg); 229 } 230 231 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 232 { 233 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, 234 HDMI_PHY_I2CM_INT_ADDR); 235 236 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | 237 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, 238 HDMI_PHY_I2CM_CTLINT_ADDR); 239 240 /* Software reset */ 241 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 242 243 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ 244 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); 245 246 /* Set done, not acknowledged and arbitration interrupt polarities */ 247 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 248 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 249 HDMI_I2CM_CTLINT); 250 251 /* Clear DONE and ERROR interrupts */ 252 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 253 HDMI_IH_I2CM_STAT0); 254 255 /* Mute DONE and ERROR interrupts */ 256 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 257 HDMI_IH_MUTE_I2CM_STAT0); 258 } 259 260 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi) 261 { 262 /* If no unwedge state then give up */ 263 if (!hdmi->unwedge_state) 264 return false; 265 266 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n"); 267 268 /* 269 * This is a huge hack to workaround a problem where the dw_hdmi i2c 270 * bus could sometimes get wedged. Once wedged there doesn't appear 271 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ) 272 * other than pulsing the SDA line. 273 * 274 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi) 275 * by: 276 * 1. Remux the pin as a GPIO output, driven low. 277 * 2. Wait a little while. 1 ms seems to work, but we'll do 10. 278 * 3. Immediately jump to remux the pin as dw_hdmi i2c again. 279 * 280 * At the moment of remuxing, the line will still be low due to its 281 * recent stint as an output, but then it will be pulled high by the 282 * (presumed) external pullup. dw_hdmi seems to see this as a rising 283 * edge and that seems to get it out of its jam. 284 * 285 * This wedging was only ever seen on one TV, and only on one of 286 * its HDMI ports. It happened when the TV was powered on while the 287 * device was plugged in. A scope trace shows the TV bringing both SDA 288 * and SCL low, then bringing them both back up at roughly the same 289 * time. Presumably this confuses dw_hdmi because it saw activity but 290 * no real STOP (maybe it thinks there's another master on the bus?). 291 * Giving it a clean rising edge of SDA while SCL is already high 292 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out 293 * of its stupor. 294 * 295 * Note that after coming back alive, transfers seem to immediately 296 * resume, so if we unwedge due to a timeout we should wait a little 297 * longer for our transfer to finish, since it might have just started 298 * now. 299 */ 300 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state); 301 msleep(10); 302 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state); 303 304 return true; 305 } 306 307 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi) 308 { 309 struct dw_hdmi_i2c *i2c = hdmi->i2c; 310 int stat; 311 312 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 313 if (!stat) { 314 /* If we can't unwedge, return timeout */ 315 if (!dw_hdmi_i2c_unwedge(hdmi)) 316 return -EAGAIN; 317 318 /* We tried to unwedge; give it another chance */ 319 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 320 if (!stat) 321 return -EAGAIN; 322 } 323 324 /* Check for error condition on the bus */ 325 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 326 return -EIO; 327 328 return 0; 329 } 330 331 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 332 unsigned char *buf, unsigned int length) 333 { 334 struct dw_hdmi_i2c *i2c = hdmi->i2c; 335 int ret; 336 337 if (!i2c->is_regaddr) { 338 dev_dbg(hdmi->dev, "set read register address to 0\n"); 339 i2c->slave_reg = 0x00; 340 i2c->is_regaddr = true; 341 } 342 343 while (length--) { 344 reinit_completion(&i2c->cmp); 345 346 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 347 if (i2c->is_segment) 348 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 349 HDMI_I2CM_OPERATION); 350 else 351 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 352 HDMI_I2CM_OPERATION); 353 354 ret = dw_hdmi_i2c_wait(hdmi); 355 if (ret) 356 return ret; 357 358 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 359 } 360 i2c->is_segment = false; 361 362 return 0; 363 } 364 365 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 366 unsigned char *buf, unsigned int length) 367 { 368 struct dw_hdmi_i2c *i2c = hdmi->i2c; 369 int ret; 370 371 if (!i2c->is_regaddr) { 372 /* Use the first write byte as register address */ 373 i2c->slave_reg = buf[0]; 374 length--; 375 buf++; 376 i2c->is_regaddr = true; 377 } 378 379 while (length--) { 380 reinit_completion(&i2c->cmp); 381 382 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 383 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 384 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 385 HDMI_I2CM_OPERATION); 386 387 ret = dw_hdmi_i2c_wait(hdmi); 388 if (ret) 389 return ret; 390 } 391 392 return 0; 393 } 394 395 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, 396 struct i2c_msg *msgs, int num) 397 { 398 struct dw_hdmi *hdmi = i2c_get_adapdata(adap); 399 struct dw_hdmi_i2c *i2c = hdmi->i2c; 400 u8 addr = msgs[0].addr; 401 int i, ret = 0; 402 403 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); 404 405 for (i = 0; i < num; i++) { 406 if (msgs[i].len == 0) { 407 dev_dbg(hdmi->dev, 408 "unsupported transfer %d/%d, no data\n", 409 i + 1, num); 410 return -EOPNOTSUPP; 411 } 412 } 413 414 mutex_lock(&i2c->lock); 415 416 /* Unmute DONE and ERROR interrupts */ 417 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 418 419 /* Set slave device address taken from the first I2C message */ 420 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 421 422 /* Set slave device register address on transfer */ 423 i2c->is_regaddr = false; 424 425 /* Set segment pointer for I2C extended read mode operation */ 426 i2c->is_segment = false; 427 428 for (i = 0; i < num; i++) { 429 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", 430 i + 1, num, msgs[i].len, msgs[i].flags); 431 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 432 i2c->is_segment = true; 433 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 434 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 435 } else { 436 if (msgs[i].flags & I2C_M_RD) 437 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 438 msgs[i].len); 439 else 440 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 441 msgs[i].len); 442 } 443 if (ret < 0) 444 break; 445 } 446 447 if (!ret) 448 ret = num; 449 450 /* Mute DONE and ERROR interrupts */ 451 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 452 HDMI_IH_MUTE_I2CM_STAT0); 453 454 mutex_unlock(&i2c->lock); 455 456 return ret; 457 } 458 459 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) 460 { 461 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 462 } 463 464 static const struct i2c_algorithm dw_hdmi_algorithm = { 465 .master_xfer = dw_hdmi_i2c_xfer, 466 .functionality = dw_hdmi_i2c_func, 467 }; 468 469 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) 470 { 471 struct i2c_adapter *adap; 472 struct dw_hdmi_i2c *i2c; 473 int ret; 474 475 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 476 if (!i2c) 477 return ERR_PTR(-ENOMEM); 478 479 mutex_init(&i2c->lock); 480 init_completion(&i2c->cmp); 481 482 adap = &i2c->adap; 483 adap->class = I2C_CLASS_DDC; 484 adap->owner = THIS_MODULE; 485 adap->dev.parent = hdmi->dev; 486 adap->algo = &dw_hdmi_algorithm; 487 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name)); 488 i2c_set_adapdata(adap, hdmi); 489 490 ret = i2c_add_adapter(adap); 491 if (ret) { 492 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 493 devm_kfree(hdmi->dev, i2c); 494 return ERR_PTR(ret); 495 } 496 497 hdmi->i2c = i2c; 498 499 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 500 501 return adap; 502 } 503 504 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 505 unsigned int n) 506 { 507 /* Must be set/cleared first */ 508 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 509 510 /* nshift factor = 0 */ 511 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 512 513 /* Use automatic CTS generation mode when CTS is not set */ 514 if (cts) 515 hdmi_writeb(hdmi, ((cts >> 16) & 516 HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 517 HDMI_AUD_CTS3_CTS_MANUAL, 518 HDMI_AUD_CTS3); 519 else 520 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3); 521 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 522 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 523 524 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 525 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 526 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 527 } 528 529 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) 530 { 531 unsigned int n = (128 * freq) / 1000; 532 unsigned int mult = 1; 533 534 while (freq > 48000) { 535 mult *= 2; 536 freq /= 2; 537 } 538 539 switch (freq) { 540 case 32000: 541 if (pixel_clk == 25175000) 542 n = 4576; 543 else if (pixel_clk == 27027000) 544 n = 4096; 545 else if (pixel_clk == 74176000 || pixel_clk == 148352000) 546 n = 11648; 547 else 548 n = 4096; 549 n *= mult; 550 break; 551 552 case 44100: 553 if (pixel_clk == 25175000) 554 n = 7007; 555 else if (pixel_clk == 74176000) 556 n = 17836; 557 else if (pixel_clk == 148352000) 558 n = 8918; 559 else 560 n = 6272; 561 n *= mult; 562 break; 563 564 case 48000: 565 if (pixel_clk == 25175000) 566 n = 6864; 567 else if (pixel_clk == 27027000) 568 n = 6144; 569 else if (pixel_clk == 74176000) 570 n = 11648; 571 else if (pixel_clk == 148352000) 572 n = 5824; 573 else 574 n = 6144; 575 n *= mult; 576 break; 577 578 default: 579 break; 580 } 581 582 return n; 583 } 584 585 /* 586 * When transmitting IEC60958 linear PCM audio, these registers allow to 587 * configure the channel status information of all the channel status 588 * bits in the IEC60958 frame. For the moment this configuration is only 589 * used when the I2S audio interface, General Purpose Audio (GPA), 590 * or AHB audio DMA (AHBAUDDMA) interface is active 591 * (for S/PDIF interface this information comes from the stream). 592 */ 593 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, 594 u8 *channel_status) 595 { 596 /* 597 * Set channel status register for frequency and word length. 598 * Use default values for other registers. 599 */ 600 hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7); 601 hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8); 602 } 603 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status); 604 605 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, 606 unsigned long pixel_clk, unsigned int sample_rate) 607 { 608 unsigned long ftdms = pixel_clk; 609 unsigned int n, cts; 610 u8 config3; 611 u64 tmp; 612 613 n = hdmi_compute_n(sample_rate, pixel_clk); 614 615 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 616 617 /* Only compute CTS when using internal AHB audio */ 618 if (config3 & HDMI_CONFIG3_AHBAUDDMA) { 619 /* 620 * Compute the CTS value from the N value. Note that CTS and N 621 * can be up to 20 bits in total, so we need 64-bit math. Also 622 * note that our TDMS clock is not fully accurate; it is 623 * accurate to kHz. This can introduce an unnecessary remainder 624 * in the calculation below, so we don't try to warn about that. 625 */ 626 tmp = (u64)ftdms * n; 627 do_div(tmp, 128 * sample_rate); 628 cts = tmp; 629 630 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", 631 __func__, sample_rate, 632 ftdms / 1000000, (ftdms / 1000) % 1000, 633 n, cts); 634 } else { 635 cts = 0; 636 } 637 638 spin_lock_irq(&hdmi->audio_lock); 639 hdmi->audio_n = n; 640 hdmi->audio_cts = cts; 641 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 642 spin_unlock_irq(&hdmi->audio_lock); 643 } 644 645 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) 646 { 647 mutex_lock(&hdmi->audio_mutex); 648 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); 649 mutex_unlock(&hdmi->audio_mutex); 650 } 651 652 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 653 { 654 mutex_lock(&hdmi->audio_mutex); 655 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 656 hdmi->sample_rate); 657 mutex_unlock(&hdmi->audio_mutex); 658 } 659 660 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 661 { 662 mutex_lock(&hdmi->audio_mutex); 663 hdmi->sample_rate = rate; 664 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 665 hdmi->sample_rate); 666 mutex_unlock(&hdmi->audio_mutex); 667 } 668 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); 669 670 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt) 671 { 672 u8 layout; 673 674 mutex_lock(&hdmi->audio_mutex); 675 676 /* 677 * For >2 channel PCM audio, we need to select layout 1 678 * and set an appropriate channel map. 679 */ 680 if (cnt > 2) 681 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1; 682 else 683 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0; 684 685 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK, 686 HDMI_FC_AUDSCONF); 687 688 /* Set the audio infoframes channel count */ 689 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET, 690 HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0); 691 692 mutex_unlock(&hdmi->audio_mutex); 693 } 694 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count); 695 696 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca) 697 { 698 mutex_lock(&hdmi->audio_mutex); 699 700 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2); 701 702 mutex_unlock(&hdmi->audio_mutex); 703 } 704 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation); 705 706 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) 707 { 708 if (enable) 709 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; 710 else 711 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; 712 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 713 } 714 715 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi) 716 { 717 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 718 } 719 720 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi) 721 { 722 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 723 } 724 725 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi) 726 { 727 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 728 hdmi_enable_audio_clk(hdmi, true); 729 } 730 731 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi) 732 { 733 hdmi_enable_audio_clk(hdmi, false); 734 } 735 736 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 737 { 738 unsigned long flags; 739 740 spin_lock_irqsave(&hdmi->audio_lock, flags); 741 hdmi->audio_enable = true; 742 if (hdmi->enable_audio) 743 hdmi->enable_audio(hdmi); 744 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 745 } 746 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); 747 748 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 749 { 750 unsigned long flags; 751 752 spin_lock_irqsave(&hdmi->audio_lock, flags); 753 hdmi->audio_enable = false; 754 if (hdmi->disable_audio) 755 hdmi->disable_audio(hdmi); 756 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 757 } 758 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); 759 760 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 761 { 762 switch (bus_format) { 763 case MEDIA_BUS_FMT_RGB888_1X24: 764 case MEDIA_BUS_FMT_RGB101010_1X30: 765 case MEDIA_BUS_FMT_RGB121212_1X36: 766 case MEDIA_BUS_FMT_RGB161616_1X48: 767 return true; 768 769 default: 770 return false; 771 } 772 } 773 774 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 775 { 776 switch (bus_format) { 777 case MEDIA_BUS_FMT_YUV8_1X24: 778 case MEDIA_BUS_FMT_YUV10_1X30: 779 case MEDIA_BUS_FMT_YUV12_1X36: 780 case MEDIA_BUS_FMT_YUV16_1X48: 781 return true; 782 783 default: 784 return false; 785 } 786 } 787 788 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 789 { 790 switch (bus_format) { 791 case MEDIA_BUS_FMT_UYVY8_1X16: 792 case MEDIA_BUS_FMT_UYVY10_1X20: 793 case MEDIA_BUS_FMT_UYVY12_1X24: 794 return true; 795 796 default: 797 return false; 798 } 799 } 800 801 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 802 { 803 switch (bus_format) { 804 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 805 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 806 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 807 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 808 return true; 809 810 default: 811 return false; 812 } 813 } 814 815 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 816 { 817 switch (bus_format) { 818 case MEDIA_BUS_FMT_RGB888_1X24: 819 case MEDIA_BUS_FMT_YUV8_1X24: 820 case MEDIA_BUS_FMT_UYVY8_1X16: 821 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 822 return 8; 823 824 case MEDIA_BUS_FMT_RGB101010_1X30: 825 case MEDIA_BUS_FMT_YUV10_1X30: 826 case MEDIA_BUS_FMT_UYVY10_1X20: 827 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 828 return 10; 829 830 case MEDIA_BUS_FMT_RGB121212_1X36: 831 case MEDIA_BUS_FMT_YUV12_1X36: 832 case MEDIA_BUS_FMT_UYVY12_1X24: 833 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 834 return 12; 835 836 case MEDIA_BUS_FMT_RGB161616_1X48: 837 case MEDIA_BUS_FMT_YUV16_1X48: 838 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 839 return 16; 840 841 default: 842 return 0; 843 } 844 } 845 846 /* 847 * this submodule is responsible for the video data synchronization. 848 * for example, for RGB 4:4:4 input, the data map is defined as 849 * pin{47~40} <==> R[7:0] 850 * pin{31~24} <==> G[7:0] 851 * pin{15~8} <==> B[7:0] 852 */ 853 static void hdmi_video_sample(struct dw_hdmi *hdmi) 854 { 855 int color_format = 0; 856 u8 val; 857 858 switch (hdmi->hdmi_data.enc_in_bus_format) { 859 case MEDIA_BUS_FMT_RGB888_1X24: 860 color_format = 0x01; 861 break; 862 case MEDIA_BUS_FMT_RGB101010_1X30: 863 color_format = 0x03; 864 break; 865 case MEDIA_BUS_FMT_RGB121212_1X36: 866 color_format = 0x05; 867 break; 868 case MEDIA_BUS_FMT_RGB161616_1X48: 869 color_format = 0x07; 870 break; 871 872 case MEDIA_BUS_FMT_YUV8_1X24: 873 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 874 color_format = 0x09; 875 break; 876 case MEDIA_BUS_FMT_YUV10_1X30: 877 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 878 color_format = 0x0B; 879 break; 880 case MEDIA_BUS_FMT_YUV12_1X36: 881 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 882 color_format = 0x0D; 883 break; 884 case MEDIA_BUS_FMT_YUV16_1X48: 885 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 886 color_format = 0x0F; 887 break; 888 889 case MEDIA_BUS_FMT_UYVY8_1X16: 890 color_format = 0x16; 891 break; 892 case MEDIA_BUS_FMT_UYVY10_1X20: 893 color_format = 0x14; 894 break; 895 case MEDIA_BUS_FMT_UYVY12_1X24: 896 color_format = 0x12; 897 break; 898 899 default: 900 return; 901 } 902 903 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 904 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 905 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 906 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 907 908 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 909 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 910 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 911 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 912 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 913 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 914 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 915 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 916 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 917 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 918 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 919 } 920 921 static int is_color_space_conversion(struct dw_hdmi *hdmi) 922 { 923 return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format; 924 } 925 926 static int is_color_space_decimation(struct dw_hdmi *hdmi) 927 { 928 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 929 return 0; 930 931 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 932 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 933 return 1; 934 935 return 0; 936 } 937 938 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 939 { 940 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 941 return 0; 942 943 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 944 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 945 return 1; 946 947 return 0; 948 } 949 950 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 951 { 952 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 953 unsigned i; 954 u32 csc_scale = 1; 955 956 if (is_color_space_conversion(hdmi)) { 957 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 958 if (hdmi->hdmi_data.enc_out_encoding == 959 V4L2_YCBCR_ENC_601) 960 csc_coeff = &csc_coeff_rgb_out_eitu601; 961 else 962 csc_coeff = &csc_coeff_rgb_out_eitu709; 963 } else if (hdmi_bus_fmt_is_rgb( 964 hdmi->hdmi_data.enc_in_bus_format)) { 965 if (hdmi->hdmi_data.enc_out_encoding == 966 V4L2_YCBCR_ENC_601) 967 csc_coeff = &csc_coeff_rgb_in_eitu601; 968 else 969 csc_coeff = &csc_coeff_rgb_in_eitu709; 970 csc_scale = 0; 971 } 972 } 973 974 /* The CSC registers are sequential, alternating MSB then LSB */ 975 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 976 u16 coeff_a = (*csc_coeff)[0][i]; 977 u16 coeff_b = (*csc_coeff)[1][i]; 978 u16 coeff_c = (*csc_coeff)[2][i]; 979 980 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 981 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 982 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 983 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 984 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 985 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 986 } 987 988 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 989 HDMI_CSC_SCALE); 990 } 991 992 static void hdmi_video_csc(struct dw_hdmi *hdmi) 993 { 994 int color_depth = 0; 995 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 996 int decimation = 0; 997 998 /* YCC422 interpolation to 444 mode */ 999 if (is_color_space_interpolation(hdmi)) 1000 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 1001 else if (is_color_space_decimation(hdmi)) 1002 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 1003 1004 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 1005 case 8: 1006 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 1007 break; 1008 case 10: 1009 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 1010 break; 1011 case 12: 1012 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 1013 break; 1014 case 16: 1015 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 1016 break; 1017 1018 default: 1019 return; 1020 } 1021 1022 /* Configure the CSC registers */ 1023 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 1024 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 1025 HDMI_CSC_SCALE); 1026 1027 dw_hdmi_update_csc_coeffs(hdmi); 1028 } 1029 1030 /* 1031 * HDMI video packetizer is used to packetize the data. 1032 * for example, if input is YCC422 mode or repeater is used, 1033 * data should be repacked this module can be bypassed. 1034 */ 1035 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 1036 { 1037 unsigned int color_depth = 0; 1038 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 1039 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 1040 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1041 u8 val, vp_conf; 1042 1043 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1044 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 1045 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1046 switch (hdmi_bus_fmt_color_depth( 1047 hdmi->hdmi_data.enc_out_bus_format)) { 1048 case 8: 1049 color_depth = 4; 1050 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1051 break; 1052 case 10: 1053 color_depth = 5; 1054 break; 1055 case 12: 1056 color_depth = 6; 1057 break; 1058 case 16: 1059 color_depth = 7; 1060 break; 1061 default: 1062 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1063 } 1064 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1065 switch (hdmi_bus_fmt_color_depth( 1066 hdmi->hdmi_data.enc_out_bus_format)) { 1067 case 0: 1068 case 8: 1069 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1070 break; 1071 case 10: 1072 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1073 break; 1074 case 12: 1075 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1076 break; 1077 1078 default: 1079 return; 1080 } 1081 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1082 } else { 1083 return; 1084 } 1085 1086 /* set the packetizer registers */ 1087 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1088 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | 1089 ((hdmi_data->pix_repet_factor << 1090 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & 1091 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); 1092 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1093 1094 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1095 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1096 1097 /* Data from pixel repeater block */ 1098 if (hdmi_data->pix_repet_factor > 1) { 1099 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1100 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1101 } else { /* data from packetizer block */ 1102 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1103 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1104 } 1105 1106 hdmi_modb(hdmi, vp_conf, 1107 HDMI_VP_CONF_PR_EN_MASK | 1108 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1109 1110 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 1111 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 1112 1113 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1114 1115 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1116 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1117 HDMI_VP_CONF_PP_EN_ENABLE | 1118 HDMI_VP_CONF_YCC422_EN_DISABLE; 1119 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1120 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1121 HDMI_VP_CONF_PP_EN_DISABLE | 1122 HDMI_VP_CONF_YCC422_EN_ENABLE; 1123 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1124 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1125 HDMI_VP_CONF_PP_EN_DISABLE | 1126 HDMI_VP_CONF_YCC422_EN_DISABLE; 1127 } else { 1128 return; 1129 } 1130 1131 hdmi_modb(hdmi, vp_conf, 1132 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1133 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1134 1135 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1136 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1137 HDMI_VP_STUFF_PP_STUFFING_MASK | 1138 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1139 1140 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1141 HDMI_VP_CONF); 1142 } 1143 1144 /* ----------------------------------------------------------------------------- 1145 * Synopsys PHY Handling 1146 */ 1147 1148 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 1149 unsigned char bit) 1150 { 1151 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 1152 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 1153 } 1154 1155 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 1156 { 1157 u32 val; 1158 1159 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 1160 if (msec-- == 0) 1161 return false; 1162 udelay(1000); 1163 } 1164 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 1165 1166 return true; 1167 } 1168 1169 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 1170 unsigned char addr) 1171 { 1172 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 1173 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 1174 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 1175 HDMI_PHY_I2CM_DATAO_1_ADDR); 1176 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 1177 HDMI_PHY_I2CM_DATAO_0_ADDR); 1178 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 1179 HDMI_PHY_I2CM_OPERATION_ADDR); 1180 hdmi_phy_wait_i2c_done(hdmi, 1000); 1181 } 1182 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); 1183 1184 /* Filter out invalid setups to avoid configuring SCDC and scrambling */ 1185 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi) 1186 { 1187 struct drm_display_info *display = &hdmi->connector.display_info; 1188 1189 /* Completely disable SCDC support for older controllers */ 1190 if (hdmi->version < 0x200a) 1191 return false; 1192 1193 /* Disable if no DDC bus */ 1194 if (!hdmi->ddc) 1195 return false; 1196 1197 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */ 1198 if (!display->hdmi.scdc.supported || 1199 !display->hdmi.scdc.scrambling.supported) 1200 return false; 1201 1202 /* 1203 * Disable if display only support low TMDS rates and scrambling 1204 * for low rates is not supported either 1205 */ 1206 if (!display->hdmi.scdc.scrambling.low_rates && 1207 display->max_tmds_clock <= 340000) 1208 return false; 1209 1210 return true; 1211 } 1212 1213 /* 1214 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates: 1215 * - The Source shall suspend transmission of the TMDS clock and data 1216 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it 1217 * from a 0 to a 1 or from a 1 to a 0 1218 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from 1219 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming 1220 * transmission of TMDS clock and data 1221 * 1222 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio() 1223 * helper should called right before enabling the TMDS Clock and Data in 1224 * the PHY configuration callback. 1225 */ 1226 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi) 1227 { 1228 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1229 1230 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 1231 if (dw_hdmi_support_scdc(hdmi)) { 1232 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1233 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1); 1234 else 1235 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0); 1236 } 1237 } 1238 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio); 1239 1240 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 1241 { 1242 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 1243 HDMI_PHY_CONF0_PDZ_OFFSET, 1244 HDMI_PHY_CONF0_PDZ_MASK); 1245 } 1246 1247 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 1248 { 1249 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1250 HDMI_PHY_CONF0_ENTMDS_OFFSET, 1251 HDMI_PHY_CONF0_ENTMDS_MASK); 1252 } 1253 1254 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 1255 { 1256 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1257 HDMI_PHY_CONF0_SVSRET_OFFSET, 1258 HDMI_PHY_CONF0_SVSRET_MASK); 1259 } 1260 1261 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 1262 { 1263 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1264 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 1265 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 1266 } 1267 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq); 1268 1269 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 1270 { 1271 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1272 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 1273 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 1274 } 1275 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron); 1276 1277 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 1278 { 1279 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1280 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 1281 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 1282 } 1283 1284 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 1285 { 1286 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1287 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 1288 HDMI_PHY_CONF0_SELDIPIF_MASK); 1289 } 1290 1291 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi) 1292 { 1293 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 1294 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1295 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1296 } 1297 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset); 1298 1299 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) 1300 { 1301 hdmi_phy_test_clear(hdmi, 1); 1302 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR); 1303 hdmi_phy_test_clear(hdmi, 0); 1304 } 1305 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr); 1306 1307 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 1308 { 1309 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1310 unsigned int i; 1311 u16 val; 1312 1313 if (phy->gen == 1) { 1314 dw_hdmi_phy_enable_tmds(hdmi, 0); 1315 dw_hdmi_phy_enable_powerdown(hdmi, true); 1316 return; 1317 } 1318 1319 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 1320 1321 /* 1322 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 1323 * to low power mode. 1324 */ 1325 for (i = 0; i < 5; ++i) { 1326 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 1327 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 1328 break; 1329 1330 usleep_range(1000, 2000); 1331 } 1332 1333 if (val & HDMI_PHY_TX_PHY_LOCK) 1334 dev_warn(hdmi->dev, "PHY failed to power down\n"); 1335 else 1336 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); 1337 1338 dw_hdmi_phy_gen2_pddq(hdmi, 1); 1339 } 1340 1341 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 1342 { 1343 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1344 unsigned int i; 1345 u8 val; 1346 1347 if (phy->gen == 1) { 1348 dw_hdmi_phy_enable_powerdown(hdmi, false); 1349 1350 /* Toggle TMDS enable. */ 1351 dw_hdmi_phy_enable_tmds(hdmi, 0); 1352 dw_hdmi_phy_enable_tmds(hdmi, 1); 1353 return 0; 1354 } 1355 1356 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 1357 dw_hdmi_phy_gen2_pddq(hdmi, 0); 1358 1359 /* Wait for PHY PLL lock */ 1360 for (i = 0; i < 5; ++i) { 1361 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 1362 if (val) 1363 break; 1364 1365 usleep_range(1000, 2000); 1366 } 1367 1368 if (!val) { 1369 dev_err(hdmi->dev, "PHY PLL failed to lock\n"); 1370 return -ETIMEDOUT; 1371 } 1372 1373 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); 1374 return 0; 1375 } 1376 1377 /* 1378 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 1379 * information the DWC MHL PHY has the same register layout and is thus also 1380 * supported by this function. 1381 */ 1382 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 1383 const struct dw_hdmi_plat_data *pdata, 1384 unsigned long mpixelclock) 1385 { 1386 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 1387 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 1388 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 1389 1390 /* TOFIX Will need 420 specific PHY configuration tables */ 1391 1392 /* PLL/MPLL Cfg - always match on final entry */ 1393 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 1394 if (mpixelclock <= mpll_config->mpixelclock) 1395 break; 1396 1397 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 1398 if (mpixelclock <= curr_ctrl->mpixelclock) 1399 break; 1400 1401 for (; phy_config->mpixelclock != ~0UL; phy_config++) 1402 if (mpixelclock <= phy_config->mpixelclock) 1403 break; 1404 1405 if (mpll_config->mpixelclock == ~0UL || 1406 curr_ctrl->mpixelclock == ~0UL || 1407 phy_config->mpixelclock == ~0UL) 1408 return -EINVAL; 1409 1410 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 1411 HDMI_3D_TX_PHY_CPCE_CTRL); 1412 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 1413 HDMI_3D_TX_PHY_GMPCTRL); 1414 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 1415 HDMI_3D_TX_PHY_CURRCTRL); 1416 1417 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 1418 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 1419 HDMI_3D_TX_PHY_MSM_CTRL); 1420 1421 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 1422 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 1423 HDMI_3D_TX_PHY_CKSYMTXCTRL); 1424 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 1425 HDMI_3D_TX_PHY_VLEVCTRL); 1426 1427 /* Override and disable clock termination. */ 1428 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 1429 HDMI_3D_TX_PHY_CKCALCTRL); 1430 1431 return 0; 1432 } 1433 1434 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 1435 { 1436 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1437 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 1438 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 1439 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1440 int ret; 1441 1442 dw_hdmi_phy_power_off(hdmi); 1443 1444 dw_hdmi_set_high_tmds_clock_ratio(hdmi); 1445 1446 /* Leave low power consumption mode by asserting SVSRET. */ 1447 if (phy->has_svsret) 1448 dw_hdmi_phy_enable_svsret(hdmi, 1); 1449 1450 dw_hdmi_phy_reset(hdmi); 1451 1452 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 1453 1454 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); 1455 1456 /* Write to the PHY as configured by the platform */ 1457 if (pdata->configure_phy) 1458 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 1459 else 1460 ret = phy->configure(hdmi, pdata, mpixelclock); 1461 if (ret) { 1462 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", 1463 mpixelclock); 1464 return ret; 1465 } 1466 1467 /* Wait for resuming transmission of TMDS clock and data */ 1468 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1469 msleep(100); 1470 1471 return dw_hdmi_phy_power_on(hdmi); 1472 } 1473 1474 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 1475 struct drm_display_mode *mode) 1476 { 1477 int i, ret; 1478 1479 /* HDMI Phy spec says to do the phy initialization sequence twice */ 1480 for (i = 0; i < 2; i++) { 1481 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 1482 dw_hdmi_phy_sel_interface_control(hdmi, 0); 1483 1484 ret = hdmi_phy_configure(hdmi); 1485 if (ret) 1486 return ret; 1487 } 1488 1489 return 0; 1490 } 1491 1492 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 1493 { 1494 dw_hdmi_phy_power_off(hdmi); 1495 } 1496 1497 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 1498 void *data) 1499 { 1500 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 1501 connector_status_connected : connector_status_disconnected; 1502 } 1503 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); 1504 1505 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 1506 bool force, bool disabled, bool rxsense) 1507 { 1508 u8 old_mask = hdmi->phy_mask; 1509 1510 if (force || disabled || !rxsense) 1511 hdmi->phy_mask |= HDMI_PHY_RX_SENSE; 1512 else 1513 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; 1514 1515 if (old_mask != hdmi->phy_mask) 1516 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1517 } 1518 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd); 1519 1520 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) 1521 { 1522 /* 1523 * Configure the PHY RX SENSE and HPD interrupts polarities and clear 1524 * any pending interrupt. 1525 */ 1526 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); 1527 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1528 HDMI_IH_PHY_STAT0); 1529 1530 /* Enable cable hot plug irq. */ 1531 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1532 1533 /* Clear and unmute interrupts. */ 1534 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1535 HDMI_IH_PHY_STAT0); 1536 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 1537 HDMI_IH_MUTE_PHY_STAT0); 1538 } 1539 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd); 1540 1541 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 1542 .init = dw_hdmi_phy_init, 1543 .disable = dw_hdmi_phy_disable, 1544 .read_hpd = dw_hdmi_phy_read_hpd, 1545 .update_hpd = dw_hdmi_phy_update_hpd, 1546 .setup_hpd = dw_hdmi_phy_setup_hpd, 1547 }; 1548 1549 /* ----------------------------------------------------------------------------- 1550 * HDMI TX Setup 1551 */ 1552 1553 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) 1554 { 1555 u8 de; 1556 1557 if (hdmi->hdmi_data.video_mode.mdataenablepolarity) 1558 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1559 else 1560 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; 1561 1562 /* disable rx detect */ 1563 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, 1564 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 1565 1566 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); 1567 1568 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, 1569 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); 1570 } 1571 1572 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1573 { 1574 struct hdmi_avi_infoframe frame; 1575 u8 val; 1576 1577 /* Initialise info frame from DRM mode */ 1578 drm_hdmi_avi_infoframe_from_display_mode(&frame, 1579 &hdmi->connector, mode); 1580 1581 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1582 frame.colorspace = HDMI_COLORSPACE_YUV444; 1583 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1584 frame.colorspace = HDMI_COLORSPACE_YUV422; 1585 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1586 frame.colorspace = HDMI_COLORSPACE_YUV420; 1587 else 1588 frame.colorspace = HDMI_COLORSPACE_RGB; 1589 1590 /* Set up colorimetry */ 1591 switch (hdmi->hdmi_data.enc_out_encoding) { 1592 case V4L2_YCBCR_ENC_601: 1593 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1594 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1595 else 1596 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1597 frame.extended_colorimetry = 1598 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1599 break; 1600 case V4L2_YCBCR_ENC_709: 1601 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1602 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1603 else 1604 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1605 frame.extended_colorimetry = 1606 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1607 break; 1608 default: /* Carries no data */ 1609 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1610 frame.extended_colorimetry = 1611 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1612 break; 1613 } 1614 1615 frame.scan_mode = HDMI_SCAN_MODE_NONE; 1616 1617 /* 1618 * The Designware IP uses a different byte format from standard 1619 * AVI info frames, though generally the bits are in the correct 1620 * bytes. 1621 */ 1622 1623 /* 1624 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, 1625 * scan info in bits 4,5 rather than 0,1 and active aspect present in 1626 * bit 6 rather than 4. 1627 */ 1628 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); 1629 if (frame.active_aspect & 15) 1630 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1631 if (frame.top_bar || frame.bottom_bar) 1632 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1633 if (frame.left_bar || frame.right_bar) 1634 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1635 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1636 1637 /* AVI data byte 2 differences: none */ 1638 val = ((frame.colorimetry & 0x3) << 6) | 1639 ((frame.picture_aspect & 0x3) << 4) | 1640 (frame.active_aspect & 0xf); 1641 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1642 1643 /* AVI data byte 3 differences: none */ 1644 val = ((frame.extended_colorimetry & 0x7) << 4) | 1645 ((frame.quantization_range & 0x3) << 2) | 1646 (frame.nups & 0x3); 1647 if (frame.itc) 1648 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1649 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1650 1651 /* AVI data byte 4 differences: none */ 1652 val = frame.video_code & 0x7f; 1653 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1654 1655 /* AVI Data Byte 5- set up input and output pixel repetition */ 1656 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1657 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1658 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1659 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1660 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1661 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1662 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1663 1664 /* 1665 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1666 * ycc range in bits 2,3 rather than 6,7 1667 */ 1668 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1669 (frame.content_type & 0x3); 1670 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1671 1672 /* AVI Data Bytes 6-13 */ 1673 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1674 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1675 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1676 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1677 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1678 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1679 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1680 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1681 } 1682 1683 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1684 struct drm_display_mode *mode) 1685 { 1686 struct hdmi_vendor_infoframe frame; 1687 u8 buffer[10]; 1688 ssize_t err; 1689 1690 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, 1691 &hdmi->connector, 1692 mode); 1693 if (err < 0) 1694 /* 1695 * Going into that statement does not means vendor infoframe 1696 * fails. It just informed us that vendor infoframe is not 1697 * needed for the selected mode. Only 4k or stereoscopic 3D 1698 * mode requires vendor infoframe. So just simply return. 1699 */ 1700 return; 1701 1702 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1703 if (err < 0) { 1704 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1705 err); 1706 return; 1707 } 1708 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1709 HDMI_FC_DATAUTO0_VSD_MASK); 1710 1711 /* Set the length of HDMI vendor specific InfoFrame payload */ 1712 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1713 1714 /* Set 24bit IEEE Registration Identifier */ 1715 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1716 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1717 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1718 1719 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1720 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1721 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1722 1723 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1724 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1725 1726 /* Packet frame interpolation */ 1727 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1728 1729 /* Auto packets per frame and line spacing */ 1730 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1731 1732 /* Configures the Frame Composer On RDRB mode */ 1733 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1734 HDMI_FC_DATAUTO0_VSD_MASK); 1735 } 1736 1737 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1738 const struct drm_display_mode *mode) 1739 { 1740 u8 inv_val, bytes; 1741 struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi; 1742 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1743 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1744 unsigned int vdisplay, hdisplay; 1745 1746 vmode->mtmdsclock = vmode->mpixelclock = mode->clock * 1000; 1747 1748 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); 1749 1750 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1751 vmode->mtmdsclock /= 2; 1752 1753 /* Set up HDMI_FC_INVIDCONF */ 1754 inv_val = (hdmi->hdmi_data.hdcp_enable || 1755 (dw_hdmi_support_scdc(hdmi) && 1756 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 1757 hdmi_info->scdc.scrambling.low_rates)) ? 1758 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1759 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1760 1761 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1762 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1763 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1764 1765 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1766 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1767 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1768 1769 inv_val |= (vmode->mdataenablepolarity ? 1770 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1771 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1772 1773 if (hdmi->vic == 39) 1774 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1775 else 1776 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1777 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1778 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1779 1780 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1781 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1782 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1783 1784 inv_val |= hdmi->sink_is_hdmi ? 1785 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1786 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1787 1788 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1789 1790 hdisplay = mode->hdisplay; 1791 hblank = mode->htotal - mode->hdisplay; 1792 h_de_hs = mode->hsync_start - mode->hdisplay; 1793 hsync_len = mode->hsync_end - mode->hsync_start; 1794 1795 /* 1796 * When we're setting a YCbCr420 mode, we need 1797 * to adjust the horizontal timing to suit. 1798 */ 1799 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1800 hdisplay /= 2; 1801 hblank /= 2; 1802 h_de_hs /= 2; 1803 hsync_len /= 2; 1804 } 1805 1806 vdisplay = mode->vdisplay; 1807 vblank = mode->vtotal - mode->vdisplay; 1808 v_de_vs = mode->vsync_start - mode->vdisplay; 1809 vsync_len = mode->vsync_end - mode->vsync_start; 1810 1811 /* 1812 * When we're setting an interlaced mode, we need 1813 * to adjust the vertical timing to suit. 1814 */ 1815 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1816 vdisplay /= 2; 1817 vblank /= 2; 1818 v_de_vs /= 2; 1819 vsync_len /= 2; 1820 } 1821 1822 /* Scrambling Control */ 1823 if (dw_hdmi_support_scdc(hdmi)) { 1824 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 1825 hdmi_info->scdc.scrambling.low_rates) { 1826 /* 1827 * HDMI2.0 Specifies the following procedure: 1828 * After the Source Device has determined that 1829 * SCDC_Present is set (=1), the Source Device should 1830 * write the accurate Version of the Source Device 1831 * to the Source Version field in the SCDCS. 1832 * Source Devices compliant shall set the 1833 * Source Version = 1. 1834 */ 1835 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, 1836 &bytes); 1837 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, 1838 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); 1839 1840 /* Enabled Scrambling in the Sink */ 1841 drm_scdc_set_scrambling(hdmi->ddc, 1); 1842 1843 /* 1844 * To activate the scrambler feature, you must ensure 1845 * that the quasi-static configuration bit 1846 * fc_invidconf.HDCP_keepout is set at configuration 1847 * time, before the required mc_swrstzreq.tmdsswrst_req 1848 * reset request is issued. 1849 */ 1850 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 1851 HDMI_MC_SWRSTZ); 1852 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 1853 } else { 1854 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 1855 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 1856 HDMI_MC_SWRSTZ); 1857 drm_scdc_set_scrambling(hdmi->ddc, 0); 1858 } 1859 } 1860 1861 /* Set up horizontal active pixel width */ 1862 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 1863 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 1864 1865 /* Set up vertical active lines */ 1866 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1867 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1868 1869 /* Set up horizontal blanking pixel region width */ 1870 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 1871 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 1872 1873 /* Set up vertical blanking pixel region width */ 1874 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 1875 1876 /* Set up HSYNC active edge delay width (in pixel clks) */ 1877 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 1878 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 1879 1880 /* Set up VSYNC active edge delay (in lines) */ 1881 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 1882 1883 /* Set up HSYNC active pulse width (in pixel clks) */ 1884 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 1885 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 1886 1887 /* Set up VSYNC active edge delay (in lines) */ 1888 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 1889 } 1890 1891 /* HDMI Initialization Step B.4 */ 1892 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 1893 { 1894 /* control period minimum duration */ 1895 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 1896 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 1897 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 1898 1899 /* Set to fill TMDS data channels */ 1900 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 1901 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 1902 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 1903 1904 /* Enable pixel clock and tmds data path */ 1905 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE | 1906 HDMI_MC_CLKDIS_CSCCLK_DISABLE | 1907 HDMI_MC_CLKDIS_AUDCLK_DISABLE | 1908 HDMI_MC_CLKDIS_PREPCLK_DISABLE | 1909 HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1910 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 1911 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1912 1913 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1914 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1915 1916 /* Enable csc path */ 1917 if (is_color_space_conversion(hdmi)) { 1918 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 1919 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1920 } 1921 1922 /* Enable color space conversion if needed */ 1923 if (is_color_space_conversion(hdmi)) 1924 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 1925 HDMI_MC_FLOWCTRL); 1926 else 1927 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 1928 HDMI_MC_FLOWCTRL); 1929 } 1930 1931 /* Workaround to clear the overflow condition */ 1932 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 1933 { 1934 unsigned int count; 1935 unsigned int i; 1936 u8 val; 1937 1938 /* 1939 * Under some circumstances the Frame Composer arithmetic unit can miss 1940 * an FC register write due to being busy processing the previous one. 1941 * The issue can be worked around by issuing a TMDS software reset and 1942 * then write one of the FC registers several times. 1943 * 1944 * The number of iterations matters and depends on the HDMI TX revision 1945 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL 1946 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified 1947 * as needing the workaround, with 4 iterations for v1.30a and 1 1948 * iteration for others. 1949 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing 1950 * the workaround with a single iteration. 1951 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have 1952 * been identified as needing the workaround with a single iteration. 1953 */ 1954 1955 switch (hdmi->version) { 1956 case 0x130a: 1957 count = 4; 1958 break; 1959 case 0x131a: 1960 case 0x132a: 1961 case 0x200a: 1962 case 0x201a: 1963 case 0x211a: 1964 case 0x212a: 1965 count = 1; 1966 break; 1967 default: 1968 return; 1969 } 1970 1971 /* TMDS software reset */ 1972 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 1973 1974 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 1975 for (i = 0; i < count; i++) 1976 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 1977 } 1978 1979 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 1980 { 1981 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 1982 HDMI_IH_MUTE_FC_STAT2); 1983 } 1984 1985 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1986 { 1987 int ret; 1988 1989 hdmi_disable_overflow_interrupts(hdmi); 1990 1991 hdmi->vic = drm_match_cea_mode(mode); 1992 1993 if (!hdmi->vic) { 1994 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); 1995 } else { 1996 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); 1997 } 1998 1999 if ((hdmi->vic == 6) || (hdmi->vic == 7) || 2000 (hdmi->vic == 21) || (hdmi->vic == 22) || 2001 (hdmi->vic == 2) || (hdmi->vic == 3) || 2002 (hdmi->vic == 17) || (hdmi->vic == 18)) 2003 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 2004 else 2005 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 2006 2007 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 2008 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 2009 2010 /* TOFIX: Get input format from plat data or fallback to RGB888 */ 2011 if (hdmi->plat_data->input_bus_format) 2012 hdmi->hdmi_data.enc_in_bus_format = 2013 hdmi->plat_data->input_bus_format; 2014 else 2015 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2016 2017 /* TOFIX: Get input encoding from plat data or fallback to none */ 2018 if (hdmi->plat_data->input_bus_encoding) 2019 hdmi->hdmi_data.enc_in_encoding = 2020 hdmi->plat_data->input_bus_encoding; 2021 else 2022 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 2023 2024 /* TOFIX: Default to RGB888 output format */ 2025 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2026 2027 hdmi->hdmi_data.pix_repet_factor = 0; 2028 hdmi->hdmi_data.hdcp_enable = 0; 2029 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 2030 2031 /* HDMI Initialization Step B.1 */ 2032 hdmi_av_composer(hdmi, mode); 2033 2034 /* HDMI Initializateion Step B.2 */ 2035 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode); 2036 if (ret) 2037 return ret; 2038 hdmi->phy.enabled = true; 2039 2040 /* HDMI Initialization Step B.3 */ 2041 dw_hdmi_enable_video_path(hdmi); 2042 2043 if (hdmi->sink_has_audio) { 2044 dev_dbg(hdmi->dev, "sink has audio support\n"); 2045 2046 /* HDMI Initialization Step E - Configure audio */ 2047 hdmi_clk_regenerator_update_pixel_clock(hdmi); 2048 hdmi_enable_audio_clk(hdmi, true); 2049 } 2050 2051 /* not for DVI mode */ 2052 if (hdmi->sink_is_hdmi) { 2053 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); 2054 2055 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 2056 hdmi_config_AVI(hdmi, mode); 2057 hdmi_config_vendor_specific_infoframe(hdmi, mode); 2058 } else { 2059 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); 2060 } 2061 2062 hdmi_video_packetize(hdmi); 2063 hdmi_video_csc(hdmi); 2064 hdmi_video_sample(hdmi); 2065 hdmi_tx_hdcp_config(hdmi); 2066 2067 dw_hdmi_clear_overflow(hdmi); 2068 2069 return 0; 2070 } 2071 2072 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) 2073 { 2074 u8 ih_mute; 2075 2076 /* 2077 * Boot up defaults are: 2078 * HDMI_IH_MUTE = 0x03 (disabled) 2079 * HDMI_IH_MUTE_* = 0x00 (enabled) 2080 * 2081 * Disable top level interrupt bits in HDMI block 2082 */ 2083 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | 2084 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2085 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; 2086 2087 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2088 2089 /* by default mask all interrupts */ 2090 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); 2091 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 2092 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 2093 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 2094 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); 2095 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); 2096 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); 2097 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); 2098 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); 2099 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); 2100 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); 2101 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); 2102 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); 2103 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); 2104 2105 /* Disable interrupts in the IH_MUTE_* registers */ 2106 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2107 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2108 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2109 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2110 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); 2111 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2112 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2113 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2114 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2115 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2116 2117 /* Enable top level interrupt bits in HDMI block */ 2118 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2119 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); 2120 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2121 } 2122 2123 static void dw_hdmi_poweron(struct dw_hdmi *hdmi) 2124 { 2125 hdmi->bridge_is_on = true; 2126 dw_hdmi_setup(hdmi, &hdmi->previous_mode); 2127 } 2128 2129 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) 2130 { 2131 if (hdmi->phy.enabled) { 2132 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 2133 hdmi->phy.enabled = false; 2134 } 2135 2136 hdmi->bridge_is_on = false; 2137 } 2138 2139 static void dw_hdmi_update_power(struct dw_hdmi *hdmi) 2140 { 2141 int force = hdmi->force; 2142 2143 if (hdmi->disabled) { 2144 force = DRM_FORCE_OFF; 2145 } else if (force == DRM_FORCE_UNSPECIFIED) { 2146 if (hdmi->rxsense) 2147 force = DRM_FORCE_ON; 2148 else 2149 force = DRM_FORCE_OFF; 2150 } 2151 2152 if (force == DRM_FORCE_OFF) { 2153 if (hdmi->bridge_is_on) 2154 dw_hdmi_poweroff(hdmi); 2155 } else { 2156 if (!hdmi->bridge_is_on) 2157 dw_hdmi_poweron(hdmi); 2158 } 2159 } 2160 2161 /* 2162 * Adjust the detection of RXSENSE according to whether we have a forced 2163 * connection mode enabled, or whether we have been disabled. There is 2164 * no point processing RXSENSE interrupts if we have a forced connection 2165 * state, or DRM has us disabled. 2166 * 2167 * We also disable rxsense interrupts when we think we're disconnected 2168 * to avoid floating TDMS signals giving false rxsense interrupts. 2169 * 2170 * Note: we still need to listen for HPD interrupts even when DRM has us 2171 * disabled so that we can detect a connect event. 2172 */ 2173 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) 2174 { 2175 if (hdmi->phy.ops->update_hpd) 2176 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, 2177 hdmi->force, hdmi->disabled, 2178 hdmi->rxsense); 2179 } 2180 2181 static enum drm_connector_status 2182 dw_hdmi_connector_detect(struct drm_connector *connector, bool force) 2183 { 2184 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2185 connector); 2186 2187 mutex_lock(&hdmi->mutex); 2188 hdmi->force = DRM_FORCE_UNSPECIFIED; 2189 dw_hdmi_update_power(hdmi); 2190 dw_hdmi_update_phy_mask(hdmi); 2191 mutex_unlock(&hdmi->mutex); 2192 2193 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 2194 } 2195 2196 static int dw_hdmi_connector_get_modes(struct drm_connector *connector) 2197 { 2198 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2199 connector); 2200 struct edid *edid; 2201 int ret = 0; 2202 2203 if (!hdmi->ddc) 2204 return 0; 2205 2206 edid = drm_get_edid(connector, hdmi->ddc); 2207 if (edid) { 2208 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", 2209 edid->width_cm, edid->height_cm); 2210 2211 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); 2212 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2213 drm_connector_update_edid_property(connector, edid); 2214 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); 2215 ret = drm_add_edid_modes(connector, edid); 2216 kfree(edid); 2217 } else { 2218 dev_dbg(hdmi->dev, "failed to get edid\n"); 2219 } 2220 2221 return ret; 2222 } 2223 2224 static void dw_hdmi_connector_force(struct drm_connector *connector) 2225 { 2226 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2227 connector); 2228 2229 mutex_lock(&hdmi->mutex); 2230 hdmi->force = connector->force; 2231 dw_hdmi_update_power(hdmi); 2232 dw_hdmi_update_phy_mask(hdmi); 2233 mutex_unlock(&hdmi->mutex); 2234 } 2235 2236 static const struct drm_connector_funcs dw_hdmi_connector_funcs = { 2237 .fill_modes = drm_helper_probe_single_connector_modes, 2238 .detect = dw_hdmi_connector_detect, 2239 .destroy = drm_connector_cleanup, 2240 .force = dw_hdmi_connector_force, 2241 .reset = drm_atomic_helper_connector_reset, 2242 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2243 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2244 }; 2245 2246 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { 2247 .get_modes = dw_hdmi_connector_get_modes, 2248 }; 2249 2250 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge) 2251 { 2252 struct dw_hdmi *hdmi = bridge->driver_private; 2253 struct drm_encoder *encoder = bridge->encoder; 2254 struct drm_connector *connector = &hdmi->connector; 2255 struct cec_connector_info conn_info; 2256 struct cec_notifier *notifier; 2257 2258 connector->interlace_allowed = 1; 2259 connector->polled = DRM_CONNECTOR_POLL_HPD; 2260 2261 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); 2262 2263 drm_connector_init_with_ddc(bridge->dev, connector, 2264 &dw_hdmi_connector_funcs, 2265 DRM_MODE_CONNECTOR_HDMIA, 2266 hdmi->ddc); 2267 2268 drm_connector_attach_encoder(connector, encoder); 2269 2270 cec_fill_conn_info_from_drm(&conn_info, connector); 2271 2272 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info); 2273 if (!notifier) 2274 return -ENOMEM; 2275 2276 mutex_lock(&hdmi->cec_notifier_mutex); 2277 hdmi->cec_notifier = notifier; 2278 mutex_unlock(&hdmi->cec_notifier_mutex); 2279 2280 return 0; 2281 } 2282 2283 static void dw_hdmi_bridge_detach(struct drm_bridge *bridge) 2284 { 2285 struct dw_hdmi *hdmi = bridge->driver_private; 2286 2287 mutex_lock(&hdmi->cec_notifier_mutex); 2288 cec_notifier_conn_unregister(hdmi->cec_notifier); 2289 hdmi->cec_notifier = NULL; 2290 mutex_unlock(&hdmi->cec_notifier_mutex); 2291 } 2292 2293 static enum drm_mode_status 2294 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 2295 const struct drm_display_mode *mode) 2296 { 2297 struct dw_hdmi *hdmi = bridge->driver_private; 2298 struct drm_connector *connector = &hdmi->connector; 2299 enum drm_mode_status mode_status = MODE_OK; 2300 2301 /* We don't support double-clocked modes */ 2302 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2303 return MODE_BAD; 2304 2305 if (hdmi->plat_data->mode_valid) 2306 mode_status = hdmi->plat_data->mode_valid(connector, mode); 2307 2308 return mode_status; 2309 } 2310 2311 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, 2312 const struct drm_display_mode *orig_mode, 2313 const struct drm_display_mode *mode) 2314 { 2315 struct dw_hdmi *hdmi = bridge->driver_private; 2316 2317 mutex_lock(&hdmi->mutex); 2318 2319 /* Store the display mode for plugin/DKMS poweron events */ 2320 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 2321 2322 mutex_unlock(&hdmi->mutex); 2323 } 2324 2325 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge) 2326 { 2327 struct dw_hdmi *hdmi = bridge->driver_private; 2328 2329 mutex_lock(&hdmi->mutex); 2330 hdmi->disabled = true; 2331 dw_hdmi_update_power(hdmi); 2332 dw_hdmi_update_phy_mask(hdmi); 2333 mutex_unlock(&hdmi->mutex); 2334 } 2335 2336 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge) 2337 { 2338 struct dw_hdmi *hdmi = bridge->driver_private; 2339 2340 mutex_lock(&hdmi->mutex); 2341 hdmi->disabled = false; 2342 dw_hdmi_update_power(hdmi); 2343 dw_hdmi_update_phy_mask(hdmi); 2344 mutex_unlock(&hdmi->mutex); 2345 } 2346 2347 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { 2348 .attach = dw_hdmi_bridge_attach, 2349 .detach = dw_hdmi_bridge_detach, 2350 .enable = dw_hdmi_bridge_enable, 2351 .disable = dw_hdmi_bridge_disable, 2352 .mode_set = dw_hdmi_bridge_mode_set, 2353 .mode_valid = dw_hdmi_bridge_mode_valid, 2354 }; 2355 2356 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) 2357 { 2358 struct dw_hdmi_i2c *i2c = hdmi->i2c; 2359 unsigned int stat; 2360 2361 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 2362 if (!stat) 2363 return IRQ_NONE; 2364 2365 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0); 2366 2367 i2c->stat = stat; 2368 2369 complete(&i2c->cmp); 2370 2371 return IRQ_HANDLED; 2372 } 2373 2374 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) 2375 { 2376 struct dw_hdmi *hdmi = dev_id; 2377 u8 intr_stat; 2378 irqreturn_t ret = IRQ_NONE; 2379 2380 if (hdmi->i2c) 2381 ret = dw_hdmi_i2c_irq(hdmi); 2382 2383 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2384 if (intr_stat) { 2385 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2386 return IRQ_WAKE_THREAD; 2387 } 2388 2389 return ret; 2390 } 2391 2392 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) 2393 { 2394 mutex_lock(&hdmi->mutex); 2395 2396 if (!hdmi->force) { 2397 /* 2398 * If the RX sense status indicates we're disconnected, 2399 * clear the software rxsense status. 2400 */ 2401 if (!rx_sense) 2402 hdmi->rxsense = false; 2403 2404 /* 2405 * Only set the software rxsense status when both 2406 * rxsense and hpd indicates we're connected. 2407 * This avoids what seems to be bad behaviour in 2408 * at least iMX6S versions of the phy. 2409 */ 2410 if (hpd) 2411 hdmi->rxsense = true; 2412 2413 dw_hdmi_update_power(hdmi); 2414 dw_hdmi_update_phy_mask(hdmi); 2415 } 2416 mutex_unlock(&hdmi->mutex); 2417 } 2418 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); 2419 2420 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) 2421 { 2422 struct dw_hdmi *hdmi = dev_id; 2423 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; 2424 2425 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2426 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); 2427 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); 2428 2429 phy_pol_mask = 0; 2430 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) 2431 phy_pol_mask |= HDMI_PHY_HPD; 2432 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) 2433 phy_pol_mask |= HDMI_PHY_RX_SENSE0; 2434 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) 2435 phy_pol_mask |= HDMI_PHY_RX_SENSE1; 2436 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) 2437 phy_pol_mask |= HDMI_PHY_RX_SENSE2; 2438 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) 2439 phy_pol_mask |= HDMI_PHY_RX_SENSE3; 2440 2441 if (phy_pol_mask) 2442 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); 2443 2444 /* 2445 * RX sense tells us whether the TDMS transmitters are detecting 2446 * load - in other words, there's something listening on the 2447 * other end of the link. Use this to decide whether we should 2448 * power on the phy as HPD may be toggled by the sink to merely 2449 * ask the source to re-read the EDID. 2450 */ 2451 if (intr_stat & 2452 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { 2453 dw_hdmi_setup_rx_sense(hdmi, 2454 phy_stat & HDMI_PHY_HPD, 2455 phy_stat & HDMI_PHY_RX_SENSE); 2456 2457 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) { 2458 mutex_lock(&hdmi->cec_notifier_mutex); 2459 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); 2460 mutex_unlock(&hdmi->cec_notifier_mutex); 2461 } 2462 } 2463 2464 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { 2465 dev_dbg(hdmi->dev, "EVENT=%s\n", 2466 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout"); 2467 if (hdmi->bridge.dev) 2468 drm_helper_hpd_irq_event(hdmi->bridge.dev); 2469 } 2470 2471 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); 2472 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 2473 HDMI_IH_MUTE_PHY_STAT0); 2474 2475 return IRQ_HANDLED; 2476 } 2477 2478 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 2479 { 2480 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 2481 .name = "DWC HDMI TX PHY", 2482 .gen = 1, 2483 }, { 2484 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 2485 .name = "DWC MHL PHY + HEAC PHY", 2486 .gen = 2, 2487 .has_svsret = true, 2488 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2489 }, { 2490 .type = DW_HDMI_PHY_DWC_MHL_PHY, 2491 .name = "DWC MHL PHY", 2492 .gen = 2, 2493 .has_svsret = true, 2494 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2495 }, { 2496 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 2497 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 2498 .gen = 2, 2499 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2500 }, { 2501 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 2502 .name = "DWC HDMI 3D TX PHY", 2503 .gen = 2, 2504 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2505 }, { 2506 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 2507 .name = "DWC HDMI 2.0 TX PHY", 2508 .gen = 2, 2509 .has_svsret = true, 2510 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2511 }, { 2512 .type = DW_HDMI_PHY_VENDOR_PHY, 2513 .name = "Vendor PHY", 2514 } 2515 }; 2516 2517 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 2518 { 2519 unsigned int i; 2520 u8 phy_type; 2521 2522 phy_type = hdmi->plat_data->phy_force_vendor ? 2523 DW_HDMI_PHY_VENDOR_PHY : 2524 hdmi_readb(hdmi, HDMI_CONFIG2_ID); 2525 2526 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { 2527 /* Vendor PHYs require support from the glue layer. */ 2528 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 2529 dev_err(hdmi->dev, 2530 "Vendor HDMI PHY not supported by glue layer\n"); 2531 return -ENODEV; 2532 } 2533 2534 hdmi->phy.ops = hdmi->plat_data->phy_ops; 2535 hdmi->phy.data = hdmi->plat_data->phy_data; 2536 hdmi->phy.name = hdmi->plat_data->phy_name; 2537 return 0; 2538 } 2539 2540 /* Synopsys PHYs are handled internally. */ 2541 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 2542 if (dw_hdmi_phys[i].type == phy_type) { 2543 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 2544 hdmi->phy.name = dw_hdmi_phys[i].name; 2545 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 2546 2547 if (!dw_hdmi_phys[i].configure && 2548 !hdmi->plat_data->configure_phy) { 2549 dev_err(hdmi->dev, "%s requires platform support\n", 2550 hdmi->phy.name); 2551 return -ENODEV; 2552 } 2553 2554 return 0; 2555 } 2556 } 2557 2558 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); 2559 return -ENODEV; 2560 } 2561 2562 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi) 2563 { 2564 mutex_lock(&hdmi->mutex); 2565 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE; 2566 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2567 mutex_unlock(&hdmi->mutex); 2568 } 2569 2570 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi) 2571 { 2572 mutex_lock(&hdmi->mutex); 2573 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE; 2574 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2575 mutex_unlock(&hdmi->mutex); 2576 } 2577 2578 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = { 2579 .write = hdmi_writeb, 2580 .read = hdmi_readb, 2581 .enable = dw_hdmi_cec_enable, 2582 .disable = dw_hdmi_cec_disable, 2583 }; 2584 2585 static const struct regmap_config hdmi_regmap_8bit_config = { 2586 .reg_bits = 32, 2587 .val_bits = 8, 2588 .reg_stride = 1, 2589 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, 2590 }; 2591 2592 static const struct regmap_config hdmi_regmap_32bit_config = { 2593 .reg_bits = 32, 2594 .val_bits = 32, 2595 .reg_stride = 4, 2596 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, 2597 }; 2598 2599 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi) 2600 { 2601 initialize_hdmi_ih_mutes(hdmi); 2602 2603 /* 2604 * Reset HDMI DDC I2C master controller and mute I2CM interrupts. 2605 * Even if we are using a separate i2c adapter doing this doesn't 2606 * hurt. 2607 */ 2608 dw_hdmi_i2c_init(hdmi); 2609 2610 if (hdmi->phy.ops->setup_hpd) 2611 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 2612 } 2613 2614 static struct dw_hdmi * 2615 __dw_hdmi_probe(struct platform_device *pdev, 2616 const struct dw_hdmi_plat_data *plat_data) 2617 { 2618 struct device *dev = &pdev->dev; 2619 struct device_node *np = dev->of_node; 2620 struct platform_device_info pdevinfo; 2621 struct device_node *ddc_node; 2622 struct dw_hdmi_cec_data cec; 2623 struct dw_hdmi *hdmi; 2624 struct resource *iores = NULL; 2625 int irq; 2626 int ret; 2627 u32 val = 1; 2628 u8 prod_id0; 2629 u8 prod_id1; 2630 u8 config0; 2631 u8 config3; 2632 2633 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 2634 if (!hdmi) 2635 return ERR_PTR(-ENOMEM); 2636 2637 hdmi->plat_data = plat_data; 2638 hdmi->dev = dev; 2639 hdmi->sample_rate = 48000; 2640 hdmi->disabled = true; 2641 hdmi->rxsense = true; 2642 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); 2643 hdmi->mc_clkdis = 0x7f; 2644 2645 mutex_init(&hdmi->mutex); 2646 mutex_init(&hdmi->audio_mutex); 2647 mutex_init(&hdmi->cec_notifier_mutex); 2648 spin_lock_init(&hdmi->audio_lock); 2649 2650 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 2651 if (ddc_node) { 2652 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); 2653 of_node_put(ddc_node); 2654 if (!hdmi->ddc) { 2655 dev_dbg(hdmi->dev, "failed to read ddc node\n"); 2656 return ERR_PTR(-EPROBE_DEFER); 2657 } 2658 2659 } else { 2660 dev_dbg(hdmi->dev, "no ddc property found\n"); 2661 } 2662 2663 if (!plat_data->regm) { 2664 const struct regmap_config *reg_config; 2665 2666 of_property_read_u32(np, "reg-io-width", &val); 2667 switch (val) { 2668 case 4: 2669 reg_config = &hdmi_regmap_32bit_config; 2670 hdmi->reg_shift = 2; 2671 break; 2672 case 1: 2673 reg_config = &hdmi_regmap_8bit_config; 2674 break; 2675 default: 2676 dev_err(dev, "reg-io-width must be 1 or 4\n"); 2677 return ERR_PTR(-EINVAL); 2678 } 2679 2680 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2681 hdmi->regs = devm_ioremap_resource(dev, iores); 2682 if (IS_ERR(hdmi->regs)) { 2683 ret = PTR_ERR(hdmi->regs); 2684 goto err_res; 2685 } 2686 2687 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); 2688 if (IS_ERR(hdmi->regm)) { 2689 dev_err(dev, "Failed to configure regmap\n"); 2690 ret = PTR_ERR(hdmi->regm); 2691 goto err_res; 2692 } 2693 } else { 2694 hdmi->regm = plat_data->regm; 2695 } 2696 2697 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); 2698 if (IS_ERR(hdmi->isfr_clk)) { 2699 ret = PTR_ERR(hdmi->isfr_clk); 2700 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); 2701 goto err_res; 2702 } 2703 2704 ret = clk_prepare_enable(hdmi->isfr_clk); 2705 if (ret) { 2706 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret); 2707 goto err_res; 2708 } 2709 2710 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); 2711 if (IS_ERR(hdmi->iahb_clk)) { 2712 ret = PTR_ERR(hdmi->iahb_clk); 2713 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); 2714 goto err_isfr; 2715 } 2716 2717 ret = clk_prepare_enable(hdmi->iahb_clk); 2718 if (ret) { 2719 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret); 2720 goto err_isfr; 2721 } 2722 2723 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec"); 2724 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) { 2725 hdmi->cec_clk = NULL; 2726 } else if (IS_ERR(hdmi->cec_clk)) { 2727 ret = PTR_ERR(hdmi->cec_clk); 2728 if (ret != -EPROBE_DEFER) 2729 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n", 2730 ret); 2731 2732 hdmi->cec_clk = NULL; 2733 goto err_iahb; 2734 } else { 2735 ret = clk_prepare_enable(hdmi->cec_clk); 2736 if (ret) { 2737 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n", 2738 ret); 2739 goto err_iahb; 2740 } 2741 } 2742 2743 /* Product and revision IDs */ 2744 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 2745 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 2746 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); 2747 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); 2748 2749 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || 2750 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { 2751 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", 2752 hdmi->version, prod_id0, prod_id1); 2753 ret = -ENODEV; 2754 goto err_iahb; 2755 } 2756 2757 ret = dw_hdmi_detect_phy(hdmi); 2758 if (ret < 0) 2759 goto err_iahb; 2760 2761 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", 2762 hdmi->version >> 12, hdmi->version & 0xfff, 2763 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", 2764 hdmi->phy.name); 2765 2766 dw_hdmi_init_hw(hdmi); 2767 2768 irq = platform_get_irq(pdev, 0); 2769 if (irq < 0) { 2770 ret = irq; 2771 goto err_iahb; 2772 } 2773 2774 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, 2775 dw_hdmi_irq, IRQF_SHARED, 2776 dev_name(dev), hdmi); 2777 if (ret) 2778 goto err_iahb; 2779 2780 /* 2781 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator 2782 * N and cts values before enabling phy 2783 */ 2784 hdmi_init_clk_regenerator(hdmi); 2785 2786 /* If DDC bus is not specified, try to register HDMI I2C bus */ 2787 if (!hdmi->ddc) { 2788 /* Look for (optional) stuff related to unwedging */ 2789 hdmi->pinctrl = devm_pinctrl_get(dev); 2790 if (!IS_ERR(hdmi->pinctrl)) { 2791 hdmi->unwedge_state = 2792 pinctrl_lookup_state(hdmi->pinctrl, "unwedge"); 2793 hdmi->default_state = 2794 pinctrl_lookup_state(hdmi->pinctrl, "default"); 2795 2796 if (IS_ERR(hdmi->default_state) || 2797 IS_ERR(hdmi->unwedge_state)) { 2798 if (!IS_ERR(hdmi->unwedge_state)) 2799 dev_warn(dev, 2800 "Unwedge requires default pinctrl\n"); 2801 hdmi->default_state = NULL; 2802 hdmi->unwedge_state = NULL; 2803 } 2804 } 2805 2806 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); 2807 if (IS_ERR(hdmi->ddc)) 2808 hdmi->ddc = NULL; 2809 } 2810 2811 hdmi->bridge.driver_private = hdmi; 2812 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; 2813 #ifdef CONFIG_OF 2814 hdmi->bridge.of_node = pdev->dev.of_node; 2815 #endif 2816 2817 memset(&pdevinfo, 0, sizeof(pdevinfo)); 2818 pdevinfo.parent = dev; 2819 pdevinfo.id = PLATFORM_DEVID_AUTO; 2820 2821 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); 2822 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 2823 2824 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { 2825 struct dw_hdmi_audio_data audio; 2826 2827 audio.phys = iores->start; 2828 audio.base = hdmi->regs; 2829 audio.irq = irq; 2830 audio.hdmi = hdmi; 2831 audio.eld = hdmi->connector.eld; 2832 hdmi->enable_audio = dw_hdmi_ahb_audio_enable; 2833 hdmi->disable_audio = dw_hdmi_ahb_audio_disable; 2834 2835 pdevinfo.name = "dw-hdmi-ahb-audio"; 2836 pdevinfo.data = &audio; 2837 pdevinfo.size_data = sizeof(audio); 2838 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2839 hdmi->audio = platform_device_register_full(&pdevinfo); 2840 } else if (config0 & HDMI_CONFIG0_I2S) { 2841 struct dw_hdmi_i2s_audio_data audio; 2842 2843 audio.hdmi = hdmi; 2844 audio.eld = hdmi->connector.eld; 2845 audio.write = hdmi_writeb; 2846 audio.read = hdmi_readb; 2847 hdmi->enable_audio = dw_hdmi_i2s_audio_enable; 2848 hdmi->disable_audio = dw_hdmi_i2s_audio_disable; 2849 2850 pdevinfo.name = "dw-hdmi-i2s-audio"; 2851 pdevinfo.data = &audio; 2852 pdevinfo.size_data = sizeof(audio); 2853 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2854 hdmi->audio = platform_device_register_full(&pdevinfo); 2855 } 2856 2857 if (config0 & HDMI_CONFIG0_CEC) { 2858 cec.hdmi = hdmi; 2859 cec.ops = &dw_hdmi_cec_ops; 2860 cec.irq = irq; 2861 2862 pdevinfo.name = "dw-hdmi-cec"; 2863 pdevinfo.data = &cec; 2864 pdevinfo.size_data = sizeof(cec); 2865 pdevinfo.dma_mask = 0; 2866 2867 hdmi->cec = platform_device_register_full(&pdevinfo); 2868 } 2869 2870 return hdmi; 2871 2872 err_iahb: 2873 if (hdmi->i2c) { 2874 i2c_del_adapter(&hdmi->i2c->adap); 2875 hdmi->ddc = NULL; 2876 } 2877 2878 clk_disable_unprepare(hdmi->iahb_clk); 2879 if (hdmi->cec_clk) 2880 clk_disable_unprepare(hdmi->cec_clk); 2881 err_isfr: 2882 clk_disable_unprepare(hdmi->isfr_clk); 2883 err_res: 2884 i2c_put_adapter(hdmi->ddc); 2885 2886 return ERR_PTR(ret); 2887 } 2888 2889 static void __dw_hdmi_remove(struct dw_hdmi *hdmi) 2890 { 2891 if (hdmi->audio && !IS_ERR(hdmi->audio)) 2892 platform_device_unregister(hdmi->audio); 2893 if (!IS_ERR(hdmi->cec)) 2894 platform_device_unregister(hdmi->cec); 2895 2896 /* Disable all interrupts */ 2897 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2898 2899 clk_disable_unprepare(hdmi->iahb_clk); 2900 clk_disable_unprepare(hdmi->isfr_clk); 2901 if (hdmi->cec_clk) 2902 clk_disable_unprepare(hdmi->cec_clk); 2903 2904 if (hdmi->i2c) 2905 i2c_del_adapter(&hdmi->i2c->adap); 2906 else 2907 i2c_put_adapter(hdmi->ddc); 2908 } 2909 2910 /* ----------------------------------------------------------------------------- 2911 * Probe/remove API, used from platforms based on the DRM bridge API. 2912 */ 2913 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, 2914 const struct dw_hdmi_plat_data *plat_data) 2915 { 2916 struct dw_hdmi *hdmi; 2917 2918 hdmi = __dw_hdmi_probe(pdev, plat_data); 2919 if (IS_ERR(hdmi)) 2920 return hdmi; 2921 2922 drm_bridge_add(&hdmi->bridge); 2923 2924 return hdmi; 2925 } 2926 EXPORT_SYMBOL_GPL(dw_hdmi_probe); 2927 2928 void dw_hdmi_remove(struct dw_hdmi *hdmi) 2929 { 2930 drm_bridge_remove(&hdmi->bridge); 2931 2932 __dw_hdmi_remove(hdmi); 2933 } 2934 EXPORT_SYMBOL_GPL(dw_hdmi_remove); 2935 2936 /* ----------------------------------------------------------------------------- 2937 * Bind/unbind API, used from platforms based on the component framework. 2938 */ 2939 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, 2940 struct drm_encoder *encoder, 2941 const struct dw_hdmi_plat_data *plat_data) 2942 { 2943 struct dw_hdmi *hdmi; 2944 int ret; 2945 2946 hdmi = __dw_hdmi_probe(pdev, plat_data); 2947 if (IS_ERR(hdmi)) 2948 return hdmi; 2949 2950 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL); 2951 if (ret) { 2952 dw_hdmi_remove(hdmi); 2953 DRM_ERROR("Failed to initialize bridge with drm\n"); 2954 return ERR_PTR(ret); 2955 } 2956 2957 return hdmi; 2958 } 2959 EXPORT_SYMBOL_GPL(dw_hdmi_bind); 2960 2961 void dw_hdmi_unbind(struct dw_hdmi *hdmi) 2962 { 2963 __dw_hdmi_remove(hdmi); 2964 } 2965 EXPORT_SYMBOL_GPL(dw_hdmi_unbind); 2966 2967 void dw_hdmi_resume(struct dw_hdmi *hdmi) 2968 { 2969 dw_hdmi_init_hw(hdmi); 2970 } 2971 EXPORT_SYMBOL_GPL(dw_hdmi_resume); 2972 2973 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 2974 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); 2975 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); 2976 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>"); 2977 MODULE_DESCRIPTION("DW HDMI transmitter driver"); 2978 MODULE_LICENSE("GPL"); 2979 MODULE_ALIAS("platform:dw-hdmi"); 2980