1 /* 2 * DesignWare High-Definition Multimedia Interface (HDMI) driver 3 * 4 * Copyright (C) 2013-2015 Mentor Graphics Inc. 5 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 6 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 */ 14 #include <linux/module.h> 15 #include <linux/irq.h> 16 #include <linux/delay.h> 17 #include <linux/err.h> 18 #include <linux/clk.h> 19 #include <linux/hdmi.h> 20 #include <linux/mutex.h> 21 #include <linux/of_device.h> 22 #include <linux/regmap.h> 23 #include <linux/spinlock.h> 24 25 #include <drm/drm_of.h> 26 #include <drm/drmP.h> 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_encoder_slave.h> 31 #include <drm/bridge/dw_hdmi.h> 32 33 #include <uapi/linux/media-bus-format.h> 34 #include <uapi/linux/videodev2.h> 35 36 #include "dw-hdmi.h" 37 #include "dw-hdmi-audio.h" 38 #include "dw-hdmi-cec.h" 39 40 #include <media/cec-notifier.h> 41 42 #define DDC_SEGMENT_ADDR 0x30 43 44 #define HDMI_EDID_LEN 512 45 46 enum hdmi_datamap { 47 RGB444_8B = 0x01, 48 RGB444_10B = 0x03, 49 RGB444_12B = 0x05, 50 RGB444_16B = 0x07, 51 YCbCr444_8B = 0x09, 52 YCbCr444_10B = 0x0B, 53 YCbCr444_12B = 0x0D, 54 YCbCr444_16B = 0x0F, 55 YCbCr422_8B = 0x16, 56 YCbCr422_10B = 0x14, 57 YCbCr422_12B = 0x12, 58 }; 59 60 static const u16 csc_coeff_default[3][4] = { 61 { 0x2000, 0x0000, 0x0000, 0x0000 }, 62 { 0x0000, 0x2000, 0x0000, 0x0000 }, 63 { 0x0000, 0x0000, 0x2000, 0x0000 } 64 }; 65 66 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 67 { 0x2000, 0x6926, 0x74fd, 0x010e }, 68 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 69 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 70 }; 71 72 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 73 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 74 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 75 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 76 }; 77 78 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 79 { 0x2591, 0x1322, 0x074b, 0x0000 }, 80 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 81 { 0x6acd, 0x7534, 0x2000, 0x0200 } 82 }; 83 84 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 85 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 86 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 87 { 0x6756, 0x78ab, 0x2000, 0x0200 } 88 }; 89 90 struct hdmi_vmode { 91 bool mdataenablepolarity; 92 93 unsigned int mpixelclock; 94 unsigned int mpixelrepetitioninput; 95 unsigned int mpixelrepetitionoutput; 96 }; 97 98 struct hdmi_data_info { 99 unsigned int enc_in_bus_format; 100 unsigned int enc_out_bus_format; 101 unsigned int enc_in_encoding; 102 unsigned int enc_out_encoding; 103 unsigned int pix_repet_factor; 104 unsigned int hdcp_enable; 105 struct hdmi_vmode video_mode; 106 }; 107 108 struct dw_hdmi_i2c { 109 struct i2c_adapter adap; 110 111 struct mutex lock; /* used to serialize data transfers */ 112 struct completion cmp; 113 u8 stat; 114 115 u8 slave_reg; 116 bool is_regaddr; 117 bool is_segment; 118 }; 119 120 struct dw_hdmi_phy_data { 121 enum dw_hdmi_phy_type type; 122 const char *name; 123 unsigned int gen; 124 bool has_svsret; 125 int (*configure)(struct dw_hdmi *hdmi, 126 const struct dw_hdmi_plat_data *pdata, 127 unsigned long mpixelclock); 128 }; 129 130 struct dw_hdmi { 131 struct drm_connector connector; 132 struct drm_bridge bridge; 133 134 unsigned int version; 135 136 struct platform_device *audio; 137 struct platform_device *cec; 138 struct device *dev; 139 struct clk *isfr_clk; 140 struct clk *iahb_clk; 141 struct clk *cec_clk; 142 struct dw_hdmi_i2c *i2c; 143 144 struct hdmi_data_info hdmi_data; 145 const struct dw_hdmi_plat_data *plat_data; 146 147 int vic; 148 149 u8 edid[HDMI_EDID_LEN]; 150 151 struct { 152 const struct dw_hdmi_phy_ops *ops; 153 const char *name; 154 void *data; 155 bool enabled; 156 } phy; 157 158 struct drm_display_mode previous_mode; 159 160 struct i2c_adapter *ddc; 161 void __iomem *regs; 162 bool sink_is_hdmi; 163 bool sink_has_audio; 164 165 struct mutex mutex; /* for state below and previous_mode */ 166 enum drm_connector_force force; /* mutex-protected force state */ 167 bool disabled; /* DRM has disabled our bridge */ 168 bool bridge_is_on; /* indicates the bridge is on */ 169 bool rxsense; /* rxsense state */ 170 u8 phy_mask; /* desired phy int mask settings */ 171 u8 mc_clkdis; /* clock disable register */ 172 173 spinlock_t audio_lock; 174 struct mutex audio_mutex; 175 unsigned int sample_rate; 176 unsigned int audio_cts; 177 unsigned int audio_n; 178 bool audio_enable; 179 180 unsigned int reg_shift; 181 struct regmap *regm; 182 void (*enable_audio)(struct dw_hdmi *hdmi); 183 void (*disable_audio)(struct dw_hdmi *hdmi); 184 185 struct cec_notifier *cec_notifier; 186 }; 187 188 #define HDMI_IH_PHY_STAT0_RX_SENSE \ 189 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ 190 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) 191 192 #define HDMI_PHY_RX_SENSE \ 193 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ 194 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) 195 196 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 197 { 198 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); 199 } 200 201 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 202 { 203 unsigned int val = 0; 204 205 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); 206 207 return val; 208 } 209 210 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 211 { 212 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); 213 } 214 215 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 216 u8 shift, u8 mask) 217 { 218 hdmi_modb(hdmi, data << shift, mask, reg); 219 } 220 221 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 222 { 223 /* Software reset */ 224 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 225 226 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ 227 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); 228 229 /* Set done, not acknowledged and arbitration interrupt polarities */ 230 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 231 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 232 HDMI_I2CM_CTLINT); 233 234 /* Clear DONE and ERROR interrupts */ 235 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 236 HDMI_IH_I2CM_STAT0); 237 238 /* Mute DONE and ERROR interrupts */ 239 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 240 HDMI_IH_MUTE_I2CM_STAT0); 241 } 242 243 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 244 unsigned char *buf, unsigned int length) 245 { 246 struct dw_hdmi_i2c *i2c = hdmi->i2c; 247 int stat; 248 249 if (!i2c->is_regaddr) { 250 dev_dbg(hdmi->dev, "set read register address to 0\n"); 251 i2c->slave_reg = 0x00; 252 i2c->is_regaddr = true; 253 } 254 255 while (length--) { 256 reinit_completion(&i2c->cmp); 257 258 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 259 if (i2c->is_segment) 260 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 261 HDMI_I2CM_OPERATION); 262 else 263 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 264 HDMI_I2CM_OPERATION); 265 266 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 267 if (!stat) 268 return -EAGAIN; 269 270 /* Check for error condition on the bus */ 271 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 272 return -EIO; 273 274 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 275 } 276 i2c->is_segment = false; 277 278 return 0; 279 } 280 281 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 282 unsigned char *buf, unsigned int length) 283 { 284 struct dw_hdmi_i2c *i2c = hdmi->i2c; 285 int stat; 286 287 if (!i2c->is_regaddr) { 288 /* Use the first write byte as register address */ 289 i2c->slave_reg = buf[0]; 290 length--; 291 buf++; 292 i2c->is_regaddr = true; 293 } 294 295 while (length--) { 296 reinit_completion(&i2c->cmp); 297 298 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 299 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 300 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 301 HDMI_I2CM_OPERATION); 302 303 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 304 if (!stat) 305 return -EAGAIN; 306 307 /* Check for error condition on the bus */ 308 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 309 return -EIO; 310 } 311 312 return 0; 313 } 314 315 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, 316 struct i2c_msg *msgs, int num) 317 { 318 struct dw_hdmi *hdmi = i2c_get_adapdata(adap); 319 struct dw_hdmi_i2c *i2c = hdmi->i2c; 320 u8 addr = msgs[0].addr; 321 int i, ret = 0; 322 323 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); 324 325 for (i = 0; i < num; i++) { 326 if (msgs[i].len == 0) { 327 dev_dbg(hdmi->dev, 328 "unsupported transfer %d/%d, no data\n", 329 i + 1, num); 330 return -EOPNOTSUPP; 331 } 332 } 333 334 mutex_lock(&i2c->lock); 335 336 /* Unmute DONE and ERROR interrupts */ 337 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 338 339 /* Set slave device address taken from the first I2C message */ 340 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 341 342 /* Set slave device register address on transfer */ 343 i2c->is_regaddr = false; 344 345 /* Set segment pointer for I2C extended read mode operation */ 346 i2c->is_segment = false; 347 348 for (i = 0; i < num; i++) { 349 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", 350 i + 1, num, msgs[i].len, msgs[i].flags); 351 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 352 i2c->is_segment = true; 353 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 354 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 355 } else { 356 if (msgs[i].flags & I2C_M_RD) 357 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 358 msgs[i].len); 359 else 360 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 361 msgs[i].len); 362 } 363 if (ret < 0) 364 break; 365 } 366 367 if (!ret) 368 ret = num; 369 370 /* Mute DONE and ERROR interrupts */ 371 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 372 HDMI_IH_MUTE_I2CM_STAT0); 373 374 mutex_unlock(&i2c->lock); 375 376 return ret; 377 } 378 379 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) 380 { 381 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 382 } 383 384 static const struct i2c_algorithm dw_hdmi_algorithm = { 385 .master_xfer = dw_hdmi_i2c_xfer, 386 .functionality = dw_hdmi_i2c_func, 387 }; 388 389 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) 390 { 391 struct i2c_adapter *adap; 392 struct dw_hdmi_i2c *i2c; 393 int ret; 394 395 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 396 if (!i2c) 397 return ERR_PTR(-ENOMEM); 398 399 mutex_init(&i2c->lock); 400 init_completion(&i2c->cmp); 401 402 adap = &i2c->adap; 403 adap->class = I2C_CLASS_DDC; 404 adap->owner = THIS_MODULE; 405 adap->dev.parent = hdmi->dev; 406 adap->algo = &dw_hdmi_algorithm; 407 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name)); 408 i2c_set_adapdata(adap, hdmi); 409 410 ret = i2c_add_adapter(adap); 411 if (ret) { 412 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 413 devm_kfree(hdmi->dev, i2c); 414 return ERR_PTR(ret); 415 } 416 417 hdmi->i2c = i2c; 418 419 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 420 421 return adap; 422 } 423 424 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 425 unsigned int n) 426 { 427 /* Must be set/cleared first */ 428 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 429 430 /* nshift factor = 0 */ 431 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 432 433 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 434 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 435 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 436 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 437 438 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 439 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 440 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 441 } 442 443 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) 444 { 445 unsigned int n = (128 * freq) / 1000; 446 unsigned int mult = 1; 447 448 while (freq > 48000) { 449 mult *= 2; 450 freq /= 2; 451 } 452 453 switch (freq) { 454 case 32000: 455 if (pixel_clk == 25175000) 456 n = 4576; 457 else if (pixel_clk == 27027000) 458 n = 4096; 459 else if (pixel_clk == 74176000 || pixel_clk == 148352000) 460 n = 11648; 461 else 462 n = 4096; 463 n *= mult; 464 break; 465 466 case 44100: 467 if (pixel_clk == 25175000) 468 n = 7007; 469 else if (pixel_clk == 74176000) 470 n = 17836; 471 else if (pixel_clk == 148352000) 472 n = 8918; 473 else 474 n = 6272; 475 n *= mult; 476 break; 477 478 case 48000: 479 if (pixel_clk == 25175000) 480 n = 6864; 481 else if (pixel_clk == 27027000) 482 n = 6144; 483 else if (pixel_clk == 74176000) 484 n = 11648; 485 else if (pixel_clk == 148352000) 486 n = 5824; 487 else 488 n = 6144; 489 n *= mult; 490 break; 491 492 default: 493 break; 494 } 495 496 return n; 497 } 498 499 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, 500 unsigned long pixel_clk, unsigned int sample_rate) 501 { 502 unsigned long ftdms = pixel_clk; 503 unsigned int n, cts; 504 u64 tmp; 505 506 n = hdmi_compute_n(sample_rate, pixel_clk); 507 508 /* 509 * Compute the CTS value from the N value. Note that CTS and N 510 * can be up to 20 bits in total, so we need 64-bit math. Also 511 * note that our TDMS clock is not fully accurate; it is accurate 512 * to kHz. This can introduce an unnecessary remainder in the 513 * calculation below, so we don't try to warn about that. 514 */ 515 tmp = (u64)ftdms * n; 516 do_div(tmp, 128 * sample_rate); 517 cts = tmp; 518 519 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", 520 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, 521 n, cts); 522 523 spin_lock_irq(&hdmi->audio_lock); 524 hdmi->audio_n = n; 525 hdmi->audio_cts = cts; 526 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 527 spin_unlock_irq(&hdmi->audio_lock); 528 } 529 530 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) 531 { 532 mutex_lock(&hdmi->audio_mutex); 533 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); 534 mutex_unlock(&hdmi->audio_mutex); 535 } 536 537 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 538 { 539 mutex_lock(&hdmi->audio_mutex); 540 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock, 541 hdmi->sample_rate); 542 mutex_unlock(&hdmi->audio_mutex); 543 } 544 545 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 546 { 547 mutex_lock(&hdmi->audio_mutex); 548 hdmi->sample_rate = rate; 549 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock, 550 hdmi->sample_rate); 551 mutex_unlock(&hdmi->audio_mutex); 552 } 553 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); 554 555 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) 556 { 557 if (enable) 558 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; 559 else 560 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; 561 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 562 } 563 564 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi) 565 { 566 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 567 } 568 569 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi) 570 { 571 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 572 } 573 574 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi) 575 { 576 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 577 hdmi_enable_audio_clk(hdmi, true); 578 } 579 580 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi) 581 { 582 hdmi_enable_audio_clk(hdmi, false); 583 } 584 585 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 586 { 587 unsigned long flags; 588 589 spin_lock_irqsave(&hdmi->audio_lock, flags); 590 hdmi->audio_enable = true; 591 if (hdmi->enable_audio) 592 hdmi->enable_audio(hdmi); 593 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 594 } 595 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); 596 597 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 598 { 599 unsigned long flags; 600 601 spin_lock_irqsave(&hdmi->audio_lock, flags); 602 hdmi->audio_enable = false; 603 if (hdmi->disable_audio) 604 hdmi->disable_audio(hdmi); 605 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 606 } 607 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); 608 609 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 610 { 611 switch (bus_format) { 612 case MEDIA_BUS_FMT_RGB888_1X24: 613 case MEDIA_BUS_FMT_RGB101010_1X30: 614 case MEDIA_BUS_FMT_RGB121212_1X36: 615 case MEDIA_BUS_FMT_RGB161616_1X48: 616 return true; 617 618 default: 619 return false; 620 } 621 } 622 623 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 624 { 625 switch (bus_format) { 626 case MEDIA_BUS_FMT_YUV8_1X24: 627 case MEDIA_BUS_FMT_YUV10_1X30: 628 case MEDIA_BUS_FMT_YUV12_1X36: 629 case MEDIA_BUS_FMT_YUV16_1X48: 630 return true; 631 632 default: 633 return false; 634 } 635 } 636 637 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 638 { 639 switch (bus_format) { 640 case MEDIA_BUS_FMT_UYVY8_1X16: 641 case MEDIA_BUS_FMT_UYVY10_1X20: 642 case MEDIA_BUS_FMT_UYVY12_1X24: 643 return true; 644 645 default: 646 return false; 647 } 648 } 649 650 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 651 { 652 switch (bus_format) { 653 case MEDIA_BUS_FMT_RGB888_1X24: 654 case MEDIA_BUS_FMT_YUV8_1X24: 655 case MEDIA_BUS_FMT_UYVY8_1X16: 656 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 657 return 8; 658 659 case MEDIA_BUS_FMT_RGB101010_1X30: 660 case MEDIA_BUS_FMT_YUV10_1X30: 661 case MEDIA_BUS_FMT_UYVY10_1X20: 662 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 663 return 10; 664 665 case MEDIA_BUS_FMT_RGB121212_1X36: 666 case MEDIA_BUS_FMT_YUV12_1X36: 667 case MEDIA_BUS_FMT_UYVY12_1X24: 668 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 669 return 12; 670 671 case MEDIA_BUS_FMT_RGB161616_1X48: 672 case MEDIA_BUS_FMT_YUV16_1X48: 673 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 674 return 16; 675 676 default: 677 return 0; 678 } 679 } 680 681 /* 682 * this submodule is responsible for the video data synchronization. 683 * for example, for RGB 4:4:4 input, the data map is defined as 684 * pin{47~40} <==> R[7:0] 685 * pin{31~24} <==> G[7:0] 686 * pin{15~8} <==> B[7:0] 687 */ 688 static void hdmi_video_sample(struct dw_hdmi *hdmi) 689 { 690 int color_format = 0; 691 u8 val; 692 693 switch (hdmi->hdmi_data.enc_in_bus_format) { 694 case MEDIA_BUS_FMT_RGB888_1X24: 695 color_format = 0x01; 696 break; 697 case MEDIA_BUS_FMT_RGB101010_1X30: 698 color_format = 0x03; 699 break; 700 case MEDIA_BUS_FMT_RGB121212_1X36: 701 color_format = 0x05; 702 break; 703 case MEDIA_BUS_FMT_RGB161616_1X48: 704 color_format = 0x07; 705 break; 706 707 case MEDIA_BUS_FMT_YUV8_1X24: 708 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 709 color_format = 0x09; 710 break; 711 case MEDIA_BUS_FMT_YUV10_1X30: 712 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 713 color_format = 0x0B; 714 break; 715 case MEDIA_BUS_FMT_YUV12_1X36: 716 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 717 color_format = 0x0D; 718 break; 719 case MEDIA_BUS_FMT_YUV16_1X48: 720 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 721 color_format = 0x0F; 722 break; 723 724 case MEDIA_BUS_FMT_UYVY8_1X16: 725 color_format = 0x16; 726 break; 727 case MEDIA_BUS_FMT_UYVY10_1X20: 728 color_format = 0x14; 729 break; 730 case MEDIA_BUS_FMT_UYVY12_1X24: 731 color_format = 0x12; 732 break; 733 734 default: 735 return; 736 } 737 738 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 739 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 740 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 741 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 742 743 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 744 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 745 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 746 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 747 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 748 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 749 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 750 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 751 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 752 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 753 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 754 } 755 756 static int is_color_space_conversion(struct dw_hdmi *hdmi) 757 { 758 return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format; 759 } 760 761 static int is_color_space_decimation(struct dw_hdmi *hdmi) 762 { 763 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 764 return 0; 765 766 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 767 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 768 return 1; 769 770 return 0; 771 } 772 773 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 774 { 775 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 776 return 0; 777 778 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 779 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 780 return 1; 781 782 return 0; 783 } 784 785 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 786 { 787 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 788 unsigned i; 789 u32 csc_scale = 1; 790 791 if (is_color_space_conversion(hdmi)) { 792 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 793 if (hdmi->hdmi_data.enc_out_encoding == 794 V4L2_YCBCR_ENC_601) 795 csc_coeff = &csc_coeff_rgb_out_eitu601; 796 else 797 csc_coeff = &csc_coeff_rgb_out_eitu709; 798 } else if (hdmi_bus_fmt_is_rgb( 799 hdmi->hdmi_data.enc_in_bus_format)) { 800 if (hdmi->hdmi_data.enc_out_encoding == 801 V4L2_YCBCR_ENC_601) 802 csc_coeff = &csc_coeff_rgb_in_eitu601; 803 else 804 csc_coeff = &csc_coeff_rgb_in_eitu709; 805 csc_scale = 0; 806 } 807 } 808 809 /* The CSC registers are sequential, alternating MSB then LSB */ 810 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 811 u16 coeff_a = (*csc_coeff)[0][i]; 812 u16 coeff_b = (*csc_coeff)[1][i]; 813 u16 coeff_c = (*csc_coeff)[2][i]; 814 815 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 816 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 817 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 818 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 819 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 820 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 821 } 822 823 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 824 HDMI_CSC_SCALE); 825 } 826 827 static void hdmi_video_csc(struct dw_hdmi *hdmi) 828 { 829 int color_depth = 0; 830 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 831 int decimation = 0; 832 833 /* YCC422 interpolation to 444 mode */ 834 if (is_color_space_interpolation(hdmi)) 835 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 836 else if (is_color_space_decimation(hdmi)) 837 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 838 839 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 840 case 8: 841 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 842 break; 843 case 10: 844 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 845 break; 846 case 12: 847 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 848 break; 849 case 16: 850 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 851 break; 852 853 default: 854 return; 855 } 856 857 /* Configure the CSC registers */ 858 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 859 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 860 HDMI_CSC_SCALE); 861 862 dw_hdmi_update_csc_coeffs(hdmi); 863 } 864 865 /* 866 * HDMI video packetizer is used to packetize the data. 867 * for example, if input is YCC422 mode or repeater is used, 868 * data should be repacked this module can be bypassed. 869 */ 870 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 871 { 872 unsigned int color_depth = 0; 873 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 874 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 875 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 876 u8 val, vp_conf; 877 878 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 879 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) { 880 switch (hdmi_bus_fmt_color_depth( 881 hdmi->hdmi_data.enc_out_bus_format)) { 882 case 8: 883 color_depth = 4; 884 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 885 break; 886 case 10: 887 color_depth = 5; 888 break; 889 case 12: 890 color_depth = 6; 891 break; 892 case 16: 893 color_depth = 7; 894 break; 895 default: 896 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 897 } 898 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 899 switch (hdmi_bus_fmt_color_depth( 900 hdmi->hdmi_data.enc_out_bus_format)) { 901 case 0: 902 case 8: 903 remap_size = HDMI_VP_REMAP_YCC422_16bit; 904 break; 905 case 10: 906 remap_size = HDMI_VP_REMAP_YCC422_20bit; 907 break; 908 case 12: 909 remap_size = HDMI_VP_REMAP_YCC422_24bit; 910 break; 911 912 default: 913 return; 914 } 915 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 916 } else { 917 return; 918 } 919 920 /* set the packetizer registers */ 921 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 922 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | 923 ((hdmi_data->pix_repet_factor << 924 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & 925 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); 926 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 927 928 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 929 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 930 931 /* Data from pixel repeater block */ 932 if (hdmi_data->pix_repet_factor > 1) { 933 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 934 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 935 } else { /* data from packetizer block */ 936 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 937 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 938 } 939 940 hdmi_modb(hdmi, vp_conf, 941 HDMI_VP_CONF_PR_EN_MASK | 942 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 943 944 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 945 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 946 947 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 948 949 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 950 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 951 HDMI_VP_CONF_PP_EN_ENABLE | 952 HDMI_VP_CONF_YCC422_EN_DISABLE; 953 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 954 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 955 HDMI_VP_CONF_PP_EN_DISABLE | 956 HDMI_VP_CONF_YCC422_EN_ENABLE; 957 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 958 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 959 HDMI_VP_CONF_PP_EN_DISABLE | 960 HDMI_VP_CONF_YCC422_EN_DISABLE; 961 } else { 962 return; 963 } 964 965 hdmi_modb(hdmi, vp_conf, 966 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 967 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 968 969 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 970 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 971 HDMI_VP_STUFF_PP_STUFFING_MASK | 972 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 973 974 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 975 HDMI_VP_CONF); 976 } 977 978 /* ----------------------------------------------------------------------------- 979 * Synopsys PHY Handling 980 */ 981 982 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 983 unsigned char bit) 984 { 985 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 986 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 987 } 988 989 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 990 { 991 u32 val; 992 993 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 994 if (msec-- == 0) 995 return false; 996 udelay(1000); 997 } 998 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 999 1000 return true; 1001 } 1002 1003 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 1004 unsigned char addr) 1005 { 1006 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 1007 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 1008 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 1009 HDMI_PHY_I2CM_DATAO_1_ADDR); 1010 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 1011 HDMI_PHY_I2CM_DATAO_0_ADDR); 1012 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 1013 HDMI_PHY_I2CM_OPERATION_ADDR); 1014 hdmi_phy_wait_i2c_done(hdmi, 1000); 1015 } 1016 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); 1017 1018 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 1019 { 1020 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 1021 HDMI_PHY_CONF0_PDZ_OFFSET, 1022 HDMI_PHY_CONF0_PDZ_MASK); 1023 } 1024 1025 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 1026 { 1027 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1028 HDMI_PHY_CONF0_ENTMDS_OFFSET, 1029 HDMI_PHY_CONF0_ENTMDS_MASK); 1030 } 1031 1032 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 1033 { 1034 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1035 HDMI_PHY_CONF0_SVSRET_OFFSET, 1036 HDMI_PHY_CONF0_SVSRET_MASK); 1037 } 1038 1039 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 1040 { 1041 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1042 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 1043 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 1044 } 1045 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq); 1046 1047 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 1048 { 1049 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1050 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 1051 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 1052 } 1053 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron); 1054 1055 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 1056 { 1057 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1058 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 1059 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 1060 } 1061 1062 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 1063 { 1064 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1065 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 1066 HDMI_PHY_CONF0_SELDIPIF_MASK); 1067 } 1068 1069 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi) 1070 { 1071 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 1072 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1073 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1074 } 1075 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset); 1076 1077 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) 1078 { 1079 hdmi_phy_test_clear(hdmi, 1); 1080 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR); 1081 hdmi_phy_test_clear(hdmi, 0); 1082 } 1083 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr); 1084 1085 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 1086 { 1087 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1088 unsigned int i; 1089 u16 val; 1090 1091 if (phy->gen == 1) { 1092 dw_hdmi_phy_enable_tmds(hdmi, 0); 1093 dw_hdmi_phy_enable_powerdown(hdmi, true); 1094 return; 1095 } 1096 1097 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 1098 1099 /* 1100 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 1101 * to low power mode. 1102 */ 1103 for (i = 0; i < 5; ++i) { 1104 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 1105 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 1106 break; 1107 1108 usleep_range(1000, 2000); 1109 } 1110 1111 if (val & HDMI_PHY_TX_PHY_LOCK) 1112 dev_warn(hdmi->dev, "PHY failed to power down\n"); 1113 else 1114 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); 1115 1116 dw_hdmi_phy_gen2_pddq(hdmi, 1); 1117 } 1118 1119 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 1120 { 1121 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1122 unsigned int i; 1123 u8 val; 1124 1125 if (phy->gen == 1) { 1126 dw_hdmi_phy_enable_powerdown(hdmi, false); 1127 1128 /* Toggle TMDS enable. */ 1129 dw_hdmi_phy_enable_tmds(hdmi, 0); 1130 dw_hdmi_phy_enable_tmds(hdmi, 1); 1131 return 0; 1132 } 1133 1134 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 1135 dw_hdmi_phy_gen2_pddq(hdmi, 0); 1136 1137 /* Wait for PHY PLL lock */ 1138 for (i = 0; i < 5; ++i) { 1139 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 1140 if (val) 1141 break; 1142 1143 usleep_range(1000, 2000); 1144 } 1145 1146 if (!val) { 1147 dev_err(hdmi->dev, "PHY PLL failed to lock\n"); 1148 return -ETIMEDOUT; 1149 } 1150 1151 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); 1152 return 0; 1153 } 1154 1155 /* 1156 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 1157 * information the DWC MHL PHY has the same register layout and is thus also 1158 * supported by this function. 1159 */ 1160 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 1161 const struct dw_hdmi_plat_data *pdata, 1162 unsigned long mpixelclock) 1163 { 1164 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 1165 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 1166 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 1167 1168 /* PLL/MPLL Cfg - always match on final entry */ 1169 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 1170 if (mpixelclock <= mpll_config->mpixelclock) 1171 break; 1172 1173 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 1174 if (mpixelclock <= curr_ctrl->mpixelclock) 1175 break; 1176 1177 for (; phy_config->mpixelclock != ~0UL; phy_config++) 1178 if (mpixelclock <= phy_config->mpixelclock) 1179 break; 1180 1181 if (mpll_config->mpixelclock == ~0UL || 1182 curr_ctrl->mpixelclock == ~0UL || 1183 phy_config->mpixelclock == ~0UL) 1184 return -EINVAL; 1185 1186 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 1187 HDMI_3D_TX_PHY_CPCE_CTRL); 1188 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 1189 HDMI_3D_TX_PHY_GMPCTRL); 1190 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 1191 HDMI_3D_TX_PHY_CURRCTRL); 1192 1193 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 1194 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 1195 HDMI_3D_TX_PHY_MSM_CTRL); 1196 1197 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 1198 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 1199 HDMI_3D_TX_PHY_CKSYMTXCTRL); 1200 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 1201 HDMI_3D_TX_PHY_VLEVCTRL); 1202 1203 /* Override and disable clock termination. */ 1204 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 1205 HDMI_3D_TX_PHY_CKCALCTRL); 1206 1207 return 0; 1208 } 1209 1210 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 1211 { 1212 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1213 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 1214 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 1215 int ret; 1216 1217 dw_hdmi_phy_power_off(hdmi); 1218 1219 /* Leave low power consumption mode by asserting SVSRET. */ 1220 if (phy->has_svsret) 1221 dw_hdmi_phy_enable_svsret(hdmi, 1); 1222 1223 dw_hdmi_phy_reset(hdmi); 1224 1225 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 1226 1227 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); 1228 1229 /* Write to the PHY as configured by the platform */ 1230 if (pdata->configure_phy) 1231 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 1232 else 1233 ret = phy->configure(hdmi, pdata, mpixelclock); 1234 if (ret) { 1235 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", 1236 mpixelclock); 1237 return ret; 1238 } 1239 1240 return dw_hdmi_phy_power_on(hdmi); 1241 } 1242 1243 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 1244 struct drm_display_mode *mode) 1245 { 1246 int i, ret; 1247 1248 /* HDMI Phy spec says to do the phy initialization sequence twice */ 1249 for (i = 0; i < 2; i++) { 1250 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 1251 dw_hdmi_phy_sel_interface_control(hdmi, 0); 1252 1253 ret = hdmi_phy_configure(hdmi); 1254 if (ret) 1255 return ret; 1256 } 1257 1258 return 0; 1259 } 1260 1261 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 1262 { 1263 dw_hdmi_phy_power_off(hdmi); 1264 } 1265 1266 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 1267 void *data) 1268 { 1269 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 1270 connector_status_connected : connector_status_disconnected; 1271 } 1272 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); 1273 1274 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 1275 bool force, bool disabled, bool rxsense) 1276 { 1277 u8 old_mask = hdmi->phy_mask; 1278 1279 if (force || disabled || !rxsense) 1280 hdmi->phy_mask |= HDMI_PHY_RX_SENSE; 1281 else 1282 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; 1283 1284 if (old_mask != hdmi->phy_mask) 1285 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1286 } 1287 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd); 1288 1289 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) 1290 { 1291 /* 1292 * Configure the PHY RX SENSE and HPD interrupts polarities and clear 1293 * any pending interrupt. 1294 */ 1295 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); 1296 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1297 HDMI_IH_PHY_STAT0); 1298 1299 /* Enable cable hot plug irq. */ 1300 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1301 1302 /* Clear and unmute interrupts. */ 1303 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1304 HDMI_IH_PHY_STAT0); 1305 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 1306 HDMI_IH_MUTE_PHY_STAT0); 1307 } 1308 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd); 1309 1310 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 1311 .init = dw_hdmi_phy_init, 1312 .disable = dw_hdmi_phy_disable, 1313 .read_hpd = dw_hdmi_phy_read_hpd, 1314 .update_hpd = dw_hdmi_phy_update_hpd, 1315 .setup_hpd = dw_hdmi_phy_setup_hpd, 1316 }; 1317 1318 /* ----------------------------------------------------------------------------- 1319 * HDMI TX Setup 1320 */ 1321 1322 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) 1323 { 1324 u8 de; 1325 1326 if (hdmi->hdmi_data.video_mode.mdataenablepolarity) 1327 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1328 else 1329 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; 1330 1331 /* disable rx detect */ 1332 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, 1333 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 1334 1335 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); 1336 1337 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, 1338 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); 1339 } 1340 1341 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1342 { 1343 struct hdmi_avi_infoframe frame; 1344 u8 val; 1345 1346 /* Initialise info frame from DRM mode */ 1347 drm_hdmi_avi_infoframe_from_display_mode(&frame, 1348 &hdmi->connector, mode); 1349 1350 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1351 frame.colorspace = HDMI_COLORSPACE_YUV444; 1352 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1353 frame.colorspace = HDMI_COLORSPACE_YUV422; 1354 else 1355 frame.colorspace = HDMI_COLORSPACE_RGB; 1356 1357 /* Set up colorimetry */ 1358 switch (hdmi->hdmi_data.enc_out_encoding) { 1359 case V4L2_YCBCR_ENC_601: 1360 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1361 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1362 else 1363 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1364 frame.extended_colorimetry = 1365 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1366 break; 1367 case V4L2_YCBCR_ENC_709: 1368 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1369 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1370 else 1371 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1372 frame.extended_colorimetry = 1373 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1374 break; 1375 default: /* Carries no data */ 1376 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1377 frame.extended_colorimetry = 1378 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1379 break; 1380 } 1381 1382 frame.scan_mode = HDMI_SCAN_MODE_NONE; 1383 1384 /* 1385 * The Designware IP uses a different byte format from standard 1386 * AVI info frames, though generally the bits are in the correct 1387 * bytes. 1388 */ 1389 1390 /* 1391 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, 1392 * scan info in bits 4,5 rather than 0,1 and active aspect present in 1393 * bit 6 rather than 4. 1394 */ 1395 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); 1396 if (frame.active_aspect & 15) 1397 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1398 if (frame.top_bar || frame.bottom_bar) 1399 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1400 if (frame.left_bar || frame.right_bar) 1401 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1402 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1403 1404 /* AVI data byte 2 differences: none */ 1405 val = ((frame.colorimetry & 0x3) << 6) | 1406 ((frame.picture_aspect & 0x3) << 4) | 1407 (frame.active_aspect & 0xf); 1408 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1409 1410 /* AVI data byte 3 differences: none */ 1411 val = ((frame.extended_colorimetry & 0x7) << 4) | 1412 ((frame.quantization_range & 0x3) << 2) | 1413 (frame.nups & 0x3); 1414 if (frame.itc) 1415 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1416 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1417 1418 /* AVI data byte 4 differences: none */ 1419 val = frame.video_code & 0x7f; 1420 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1421 1422 /* AVI Data Byte 5- set up input and output pixel repetition */ 1423 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1424 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1425 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1426 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1427 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1428 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1429 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1430 1431 /* 1432 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1433 * ycc range in bits 2,3 rather than 6,7 1434 */ 1435 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1436 (frame.content_type & 0x3); 1437 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1438 1439 /* AVI Data Bytes 6-13 */ 1440 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1441 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1442 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1443 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1444 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1445 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1446 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1447 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1448 } 1449 1450 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1451 struct drm_display_mode *mode) 1452 { 1453 struct hdmi_vendor_infoframe frame; 1454 u8 buffer[10]; 1455 ssize_t err; 1456 1457 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, 1458 &hdmi->connector, 1459 mode); 1460 if (err < 0) 1461 /* 1462 * Going into that statement does not means vendor infoframe 1463 * fails. It just informed us that vendor infoframe is not 1464 * needed for the selected mode. Only 4k or stereoscopic 3D 1465 * mode requires vendor infoframe. So just simply return. 1466 */ 1467 return; 1468 1469 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1470 if (err < 0) { 1471 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1472 err); 1473 return; 1474 } 1475 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1476 HDMI_FC_DATAUTO0_VSD_MASK); 1477 1478 /* Set the length of HDMI vendor specific InfoFrame payload */ 1479 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1480 1481 /* Set 24bit IEEE Registration Identifier */ 1482 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1483 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1484 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1485 1486 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1487 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1488 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1489 1490 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1491 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1492 1493 /* Packet frame interpolation */ 1494 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1495 1496 /* Auto packets per frame and line spacing */ 1497 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1498 1499 /* Configures the Frame Composer On RDRB mode */ 1500 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1501 HDMI_FC_DATAUTO0_VSD_MASK); 1502 } 1503 1504 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1505 const struct drm_display_mode *mode) 1506 { 1507 u8 inv_val; 1508 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1509 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1510 unsigned int vdisplay; 1511 1512 vmode->mpixelclock = mode->clock * 1000; 1513 1514 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); 1515 1516 /* Set up HDMI_FC_INVIDCONF */ 1517 inv_val = (hdmi->hdmi_data.hdcp_enable ? 1518 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1519 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1520 1521 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1522 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1523 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1524 1525 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1526 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1527 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1528 1529 inv_val |= (vmode->mdataenablepolarity ? 1530 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1531 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1532 1533 if (hdmi->vic == 39) 1534 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1535 else 1536 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1537 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1538 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1539 1540 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1541 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1542 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1543 1544 inv_val |= hdmi->sink_is_hdmi ? 1545 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1546 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1547 1548 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1549 1550 vdisplay = mode->vdisplay; 1551 vblank = mode->vtotal - mode->vdisplay; 1552 v_de_vs = mode->vsync_start - mode->vdisplay; 1553 vsync_len = mode->vsync_end - mode->vsync_start; 1554 1555 /* 1556 * When we're setting an interlaced mode, we need 1557 * to adjust the vertical timing to suit. 1558 */ 1559 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1560 vdisplay /= 2; 1561 vblank /= 2; 1562 v_de_vs /= 2; 1563 vsync_len /= 2; 1564 } 1565 1566 /* Set up horizontal active pixel width */ 1567 hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1); 1568 hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0); 1569 1570 /* Set up vertical active lines */ 1571 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1572 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1573 1574 /* Set up horizontal blanking pixel region width */ 1575 hblank = mode->htotal - mode->hdisplay; 1576 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 1577 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 1578 1579 /* Set up vertical blanking pixel region width */ 1580 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 1581 1582 /* Set up HSYNC active edge delay width (in pixel clks) */ 1583 h_de_hs = mode->hsync_start - mode->hdisplay; 1584 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 1585 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 1586 1587 /* Set up VSYNC active edge delay (in lines) */ 1588 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 1589 1590 /* Set up HSYNC active pulse width (in pixel clks) */ 1591 hsync_len = mode->hsync_end - mode->hsync_start; 1592 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 1593 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 1594 1595 /* Set up VSYNC active edge delay (in lines) */ 1596 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 1597 } 1598 1599 /* HDMI Initialization Step B.4 */ 1600 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 1601 { 1602 /* control period minimum duration */ 1603 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 1604 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 1605 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 1606 1607 /* Set to fill TMDS data channels */ 1608 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 1609 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 1610 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 1611 1612 /* Enable pixel clock and tmds data path */ 1613 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE | 1614 HDMI_MC_CLKDIS_CSCCLK_DISABLE | 1615 HDMI_MC_CLKDIS_AUDCLK_DISABLE | 1616 HDMI_MC_CLKDIS_PREPCLK_DISABLE | 1617 HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1618 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 1619 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1620 1621 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1622 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1623 1624 /* Enable csc path */ 1625 if (is_color_space_conversion(hdmi)) { 1626 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 1627 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1628 } 1629 1630 /* Enable color space conversion if needed */ 1631 if (is_color_space_conversion(hdmi)) 1632 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 1633 HDMI_MC_FLOWCTRL); 1634 else 1635 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 1636 HDMI_MC_FLOWCTRL); 1637 } 1638 1639 /* Workaround to clear the overflow condition */ 1640 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 1641 { 1642 unsigned int count; 1643 unsigned int i; 1644 u8 val; 1645 1646 /* 1647 * Under some circumstances the Frame Composer arithmetic unit can miss 1648 * an FC register write due to being busy processing the previous one. 1649 * The issue can be worked around by issuing a TMDS software reset and 1650 * then write one of the FC registers several times. 1651 * 1652 * The number of iterations matters and depends on the HDMI TX revision 1653 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL 1654 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified 1655 * as needing the workaround, with 4 iterations for v1.30a and 1 1656 * iteration for others. 1657 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing 1658 * the workaround with a single iteration. 1659 */ 1660 1661 switch (hdmi->version) { 1662 case 0x130a: 1663 count = 4; 1664 break; 1665 case 0x131a: 1666 case 0x132a: 1667 case 0x201a: 1668 case 0x212a: 1669 count = 1; 1670 break; 1671 default: 1672 return; 1673 } 1674 1675 /* TMDS software reset */ 1676 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 1677 1678 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 1679 for (i = 0; i < count; i++) 1680 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 1681 } 1682 1683 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 1684 { 1685 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 1686 HDMI_IH_MUTE_FC_STAT2); 1687 } 1688 1689 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1690 { 1691 int ret; 1692 1693 hdmi_disable_overflow_interrupts(hdmi); 1694 1695 hdmi->vic = drm_match_cea_mode(mode); 1696 1697 if (!hdmi->vic) { 1698 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); 1699 } else { 1700 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); 1701 } 1702 1703 if ((hdmi->vic == 6) || (hdmi->vic == 7) || 1704 (hdmi->vic == 21) || (hdmi->vic == 22) || 1705 (hdmi->vic == 2) || (hdmi->vic == 3) || 1706 (hdmi->vic == 17) || (hdmi->vic == 18)) 1707 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 1708 else 1709 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 1710 1711 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 1712 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 1713 1714 /* TOFIX: Get input format from plat data or fallback to RGB888 */ 1715 if (hdmi->plat_data->input_bus_format) 1716 hdmi->hdmi_data.enc_in_bus_format = 1717 hdmi->plat_data->input_bus_format; 1718 else 1719 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1720 1721 /* TOFIX: Get input encoding from plat data or fallback to none */ 1722 if (hdmi->plat_data->input_bus_encoding) 1723 hdmi->hdmi_data.enc_in_encoding = 1724 hdmi->plat_data->input_bus_encoding; 1725 else 1726 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 1727 1728 /* TOFIX: Default to RGB888 output format */ 1729 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1730 1731 hdmi->hdmi_data.pix_repet_factor = 0; 1732 hdmi->hdmi_data.hdcp_enable = 0; 1733 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 1734 1735 /* HDMI Initialization Step B.1 */ 1736 hdmi_av_composer(hdmi, mode); 1737 1738 /* HDMI Initializateion Step B.2 */ 1739 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode); 1740 if (ret) 1741 return ret; 1742 hdmi->phy.enabled = true; 1743 1744 /* HDMI Initialization Step B.3 */ 1745 dw_hdmi_enable_video_path(hdmi); 1746 1747 if (hdmi->sink_has_audio) { 1748 dev_dbg(hdmi->dev, "sink has audio support\n"); 1749 1750 /* HDMI Initialization Step E - Configure audio */ 1751 hdmi_clk_regenerator_update_pixel_clock(hdmi); 1752 hdmi_enable_audio_clk(hdmi, true); 1753 } 1754 1755 /* not for DVI mode */ 1756 if (hdmi->sink_is_hdmi) { 1757 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); 1758 1759 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 1760 hdmi_config_AVI(hdmi, mode); 1761 hdmi_config_vendor_specific_infoframe(hdmi, mode); 1762 } else { 1763 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); 1764 } 1765 1766 hdmi_video_packetize(hdmi); 1767 hdmi_video_csc(hdmi); 1768 hdmi_video_sample(hdmi); 1769 hdmi_tx_hdcp_config(hdmi); 1770 1771 dw_hdmi_clear_overflow(hdmi); 1772 1773 return 0; 1774 } 1775 1776 static void dw_hdmi_setup_i2c(struct dw_hdmi *hdmi) 1777 { 1778 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, 1779 HDMI_PHY_I2CM_INT_ADDR); 1780 1781 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | 1782 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, 1783 HDMI_PHY_I2CM_CTLINT_ADDR); 1784 } 1785 1786 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) 1787 { 1788 u8 ih_mute; 1789 1790 /* 1791 * Boot up defaults are: 1792 * HDMI_IH_MUTE = 0x03 (disabled) 1793 * HDMI_IH_MUTE_* = 0x00 (enabled) 1794 * 1795 * Disable top level interrupt bits in HDMI block 1796 */ 1797 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | 1798 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 1799 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; 1800 1801 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 1802 1803 /* by default mask all interrupts */ 1804 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); 1805 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 1806 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 1807 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 1808 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); 1809 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); 1810 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); 1811 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); 1812 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); 1813 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); 1814 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); 1815 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); 1816 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); 1817 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); 1818 1819 /* Disable interrupts in the IH_MUTE_* registers */ 1820 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 1821 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 1822 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 1823 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 1824 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); 1825 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 1826 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 1827 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 1828 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 1829 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 1830 1831 /* Enable top level interrupt bits in HDMI block */ 1832 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 1833 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); 1834 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 1835 } 1836 1837 static void dw_hdmi_poweron(struct dw_hdmi *hdmi) 1838 { 1839 hdmi->bridge_is_on = true; 1840 dw_hdmi_setup(hdmi, &hdmi->previous_mode); 1841 } 1842 1843 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) 1844 { 1845 if (hdmi->phy.enabled) { 1846 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 1847 hdmi->phy.enabled = false; 1848 } 1849 1850 hdmi->bridge_is_on = false; 1851 } 1852 1853 static void dw_hdmi_update_power(struct dw_hdmi *hdmi) 1854 { 1855 int force = hdmi->force; 1856 1857 if (hdmi->disabled) { 1858 force = DRM_FORCE_OFF; 1859 } else if (force == DRM_FORCE_UNSPECIFIED) { 1860 if (hdmi->rxsense) 1861 force = DRM_FORCE_ON; 1862 else 1863 force = DRM_FORCE_OFF; 1864 } 1865 1866 if (force == DRM_FORCE_OFF) { 1867 if (hdmi->bridge_is_on) 1868 dw_hdmi_poweroff(hdmi); 1869 } else { 1870 if (!hdmi->bridge_is_on) 1871 dw_hdmi_poweron(hdmi); 1872 } 1873 } 1874 1875 /* 1876 * Adjust the detection of RXSENSE according to whether we have a forced 1877 * connection mode enabled, or whether we have been disabled. There is 1878 * no point processing RXSENSE interrupts if we have a forced connection 1879 * state, or DRM has us disabled. 1880 * 1881 * We also disable rxsense interrupts when we think we're disconnected 1882 * to avoid floating TDMS signals giving false rxsense interrupts. 1883 * 1884 * Note: we still need to listen for HPD interrupts even when DRM has us 1885 * disabled so that we can detect a connect event. 1886 */ 1887 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) 1888 { 1889 if (hdmi->phy.ops->update_hpd) 1890 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, 1891 hdmi->force, hdmi->disabled, 1892 hdmi->rxsense); 1893 } 1894 1895 static enum drm_connector_status 1896 dw_hdmi_connector_detect(struct drm_connector *connector, bool force) 1897 { 1898 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 1899 connector); 1900 1901 mutex_lock(&hdmi->mutex); 1902 hdmi->force = DRM_FORCE_UNSPECIFIED; 1903 dw_hdmi_update_power(hdmi); 1904 dw_hdmi_update_phy_mask(hdmi); 1905 mutex_unlock(&hdmi->mutex); 1906 1907 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 1908 } 1909 1910 static int dw_hdmi_connector_get_modes(struct drm_connector *connector) 1911 { 1912 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 1913 connector); 1914 struct edid *edid; 1915 int ret = 0; 1916 1917 if (!hdmi->ddc) 1918 return 0; 1919 1920 edid = drm_get_edid(connector, hdmi->ddc); 1921 if (edid) { 1922 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", 1923 edid->width_cm, edid->height_cm); 1924 1925 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); 1926 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 1927 drm_connector_update_edid_property(connector, edid); 1928 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); 1929 ret = drm_add_edid_modes(connector, edid); 1930 kfree(edid); 1931 } else { 1932 dev_dbg(hdmi->dev, "failed to get edid\n"); 1933 } 1934 1935 return ret; 1936 } 1937 1938 static void dw_hdmi_connector_force(struct drm_connector *connector) 1939 { 1940 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 1941 connector); 1942 1943 mutex_lock(&hdmi->mutex); 1944 hdmi->force = connector->force; 1945 dw_hdmi_update_power(hdmi); 1946 dw_hdmi_update_phy_mask(hdmi); 1947 mutex_unlock(&hdmi->mutex); 1948 } 1949 1950 static const struct drm_connector_funcs dw_hdmi_connector_funcs = { 1951 .fill_modes = drm_helper_probe_single_connector_modes, 1952 .detect = dw_hdmi_connector_detect, 1953 .destroy = drm_connector_cleanup, 1954 .force = dw_hdmi_connector_force, 1955 .reset = drm_atomic_helper_connector_reset, 1956 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1957 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1958 }; 1959 1960 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { 1961 .get_modes = dw_hdmi_connector_get_modes, 1962 }; 1963 1964 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge) 1965 { 1966 struct dw_hdmi *hdmi = bridge->driver_private; 1967 struct drm_encoder *encoder = bridge->encoder; 1968 struct drm_connector *connector = &hdmi->connector; 1969 1970 connector->interlace_allowed = 1; 1971 connector->polled = DRM_CONNECTOR_POLL_HPD; 1972 1973 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); 1974 1975 drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs, 1976 DRM_MODE_CONNECTOR_HDMIA); 1977 1978 drm_connector_attach_encoder(connector, encoder); 1979 1980 return 0; 1981 } 1982 1983 static enum drm_mode_status 1984 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 1985 const struct drm_display_mode *mode) 1986 { 1987 struct dw_hdmi *hdmi = bridge->driver_private; 1988 struct drm_connector *connector = &hdmi->connector; 1989 enum drm_mode_status mode_status = MODE_OK; 1990 1991 /* We don't support double-clocked modes */ 1992 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1993 return MODE_BAD; 1994 1995 if (hdmi->plat_data->mode_valid) 1996 mode_status = hdmi->plat_data->mode_valid(connector, mode); 1997 1998 return mode_status; 1999 } 2000 2001 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, 2002 struct drm_display_mode *orig_mode, 2003 struct drm_display_mode *mode) 2004 { 2005 struct dw_hdmi *hdmi = bridge->driver_private; 2006 2007 mutex_lock(&hdmi->mutex); 2008 2009 /* Store the display mode for plugin/DKMS poweron events */ 2010 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 2011 2012 mutex_unlock(&hdmi->mutex); 2013 } 2014 2015 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge) 2016 { 2017 struct dw_hdmi *hdmi = bridge->driver_private; 2018 2019 mutex_lock(&hdmi->mutex); 2020 hdmi->disabled = true; 2021 dw_hdmi_update_power(hdmi); 2022 dw_hdmi_update_phy_mask(hdmi); 2023 mutex_unlock(&hdmi->mutex); 2024 } 2025 2026 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge) 2027 { 2028 struct dw_hdmi *hdmi = bridge->driver_private; 2029 2030 mutex_lock(&hdmi->mutex); 2031 hdmi->disabled = false; 2032 dw_hdmi_update_power(hdmi); 2033 dw_hdmi_update_phy_mask(hdmi); 2034 mutex_unlock(&hdmi->mutex); 2035 } 2036 2037 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { 2038 .attach = dw_hdmi_bridge_attach, 2039 .enable = dw_hdmi_bridge_enable, 2040 .disable = dw_hdmi_bridge_disable, 2041 .mode_set = dw_hdmi_bridge_mode_set, 2042 .mode_valid = dw_hdmi_bridge_mode_valid, 2043 }; 2044 2045 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) 2046 { 2047 struct dw_hdmi_i2c *i2c = hdmi->i2c; 2048 unsigned int stat; 2049 2050 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 2051 if (!stat) 2052 return IRQ_NONE; 2053 2054 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0); 2055 2056 i2c->stat = stat; 2057 2058 complete(&i2c->cmp); 2059 2060 return IRQ_HANDLED; 2061 } 2062 2063 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) 2064 { 2065 struct dw_hdmi *hdmi = dev_id; 2066 u8 intr_stat; 2067 irqreturn_t ret = IRQ_NONE; 2068 2069 if (hdmi->i2c) 2070 ret = dw_hdmi_i2c_irq(hdmi); 2071 2072 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2073 if (intr_stat) { 2074 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2075 return IRQ_WAKE_THREAD; 2076 } 2077 2078 return ret; 2079 } 2080 2081 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) 2082 { 2083 mutex_lock(&hdmi->mutex); 2084 2085 if (!hdmi->force) { 2086 /* 2087 * If the RX sense status indicates we're disconnected, 2088 * clear the software rxsense status. 2089 */ 2090 if (!rx_sense) 2091 hdmi->rxsense = false; 2092 2093 /* 2094 * Only set the software rxsense status when both 2095 * rxsense and hpd indicates we're connected. 2096 * This avoids what seems to be bad behaviour in 2097 * at least iMX6S versions of the phy. 2098 */ 2099 if (hpd) 2100 hdmi->rxsense = true; 2101 2102 dw_hdmi_update_power(hdmi); 2103 dw_hdmi_update_phy_mask(hdmi); 2104 } 2105 mutex_unlock(&hdmi->mutex); 2106 } 2107 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); 2108 2109 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) 2110 { 2111 struct dw_hdmi *hdmi = dev_id; 2112 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; 2113 2114 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2115 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); 2116 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); 2117 2118 phy_pol_mask = 0; 2119 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) 2120 phy_pol_mask |= HDMI_PHY_HPD; 2121 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) 2122 phy_pol_mask |= HDMI_PHY_RX_SENSE0; 2123 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) 2124 phy_pol_mask |= HDMI_PHY_RX_SENSE1; 2125 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) 2126 phy_pol_mask |= HDMI_PHY_RX_SENSE2; 2127 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) 2128 phy_pol_mask |= HDMI_PHY_RX_SENSE3; 2129 2130 if (phy_pol_mask) 2131 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); 2132 2133 /* 2134 * RX sense tells us whether the TDMS transmitters are detecting 2135 * load - in other words, there's something listening on the 2136 * other end of the link. Use this to decide whether we should 2137 * power on the phy as HPD may be toggled by the sink to merely 2138 * ask the source to re-read the EDID. 2139 */ 2140 if (intr_stat & 2141 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { 2142 dw_hdmi_setup_rx_sense(hdmi, 2143 phy_stat & HDMI_PHY_HPD, 2144 phy_stat & HDMI_PHY_RX_SENSE); 2145 2146 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) 2147 cec_notifier_set_phys_addr(hdmi->cec_notifier, 2148 CEC_PHYS_ADDR_INVALID); 2149 } 2150 2151 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { 2152 dev_dbg(hdmi->dev, "EVENT=%s\n", 2153 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout"); 2154 if (hdmi->bridge.dev) 2155 drm_helper_hpd_irq_event(hdmi->bridge.dev); 2156 } 2157 2158 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); 2159 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 2160 HDMI_IH_MUTE_PHY_STAT0); 2161 2162 return IRQ_HANDLED; 2163 } 2164 2165 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 2166 { 2167 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 2168 .name = "DWC HDMI TX PHY", 2169 .gen = 1, 2170 }, { 2171 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 2172 .name = "DWC MHL PHY + HEAC PHY", 2173 .gen = 2, 2174 .has_svsret = true, 2175 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2176 }, { 2177 .type = DW_HDMI_PHY_DWC_MHL_PHY, 2178 .name = "DWC MHL PHY", 2179 .gen = 2, 2180 .has_svsret = true, 2181 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2182 }, { 2183 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 2184 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 2185 .gen = 2, 2186 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2187 }, { 2188 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 2189 .name = "DWC HDMI 3D TX PHY", 2190 .gen = 2, 2191 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2192 }, { 2193 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 2194 .name = "DWC HDMI 2.0 TX PHY", 2195 .gen = 2, 2196 .has_svsret = true, 2197 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2198 }, { 2199 .type = DW_HDMI_PHY_VENDOR_PHY, 2200 .name = "Vendor PHY", 2201 } 2202 }; 2203 2204 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 2205 { 2206 unsigned int i; 2207 u8 phy_type; 2208 2209 phy_type = hdmi->plat_data->phy_force_vendor ? 2210 DW_HDMI_PHY_VENDOR_PHY : 2211 hdmi_readb(hdmi, HDMI_CONFIG2_ID); 2212 2213 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { 2214 /* Vendor PHYs require support from the glue layer. */ 2215 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 2216 dev_err(hdmi->dev, 2217 "Vendor HDMI PHY not supported by glue layer\n"); 2218 return -ENODEV; 2219 } 2220 2221 hdmi->phy.ops = hdmi->plat_data->phy_ops; 2222 hdmi->phy.data = hdmi->plat_data->phy_data; 2223 hdmi->phy.name = hdmi->plat_data->phy_name; 2224 return 0; 2225 } 2226 2227 /* Synopsys PHYs are handled internally. */ 2228 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 2229 if (dw_hdmi_phys[i].type == phy_type) { 2230 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 2231 hdmi->phy.name = dw_hdmi_phys[i].name; 2232 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 2233 2234 if (!dw_hdmi_phys[i].configure && 2235 !hdmi->plat_data->configure_phy) { 2236 dev_err(hdmi->dev, "%s requires platform support\n", 2237 hdmi->phy.name); 2238 return -ENODEV; 2239 } 2240 2241 return 0; 2242 } 2243 } 2244 2245 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); 2246 return -ENODEV; 2247 } 2248 2249 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi) 2250 { 2251 mutex_lock(&hdmi->mutex); 2252 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE; 2253 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2254 mutex_unlock(&hdmi->mutex); 2255 } 2256 2257 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi) 2258 { 2259 mutex_lock(&hdmi->mutex); 2260 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE; 2261 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2262 mutex_unlock(&hdmi->mutex); 2263 } 2264 2265 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = { 2266 .write = hdmi_writeb, 2267 .read = hdmi_readb, 2268 .enable = dw_hdmi_cec_enable, 2269 .disable = dw_hdmi_cec_disable, 2270 }; 2271 2272 static const struct regmap_config hdmi_regmap_8bit_config = { 2273 .reg_bits = 32, 2274 .val_bits = 8, 2275 .reg_stride = 1, 2276 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, 2277 }; 2278 2279 static const struct regmap_config hdmi_regmap_32bit_config = { 2280 .reg_bits = 32, 2281 .val_bits = 32, 2282 .reg_stride = 4, 2283 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, 2284 }; 2285 2286 static struct dw_hdmi * 2287 __dw_hdmi_probe(struct platform_device *pdev, 2288 const struct dw_hdmi_plat_data *plat_data) 2289 { 2290 struct device *dev = &pdev->dev; 2291 struct device_node *np = dev->of_node; 2292 struct platform_device_info pdevinfo; 2293 struct device_node *ddc_node; 2294 struct dw_hdmi_cec_data cec; 2295 struct dw_hdmi *hdmi; 2296 struct resource *iores = NULL; 2297 int irq; 2298 int ret; 2299 u32 val = 1; 2300 u8 prod_id0; 2301 u8 prod_id1; 2302 u8 config0; 2303 u8 config3; 2304 2305 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 2306 if (!hdmi) 2307 return ERR_PTR(-ENOMEM); 2308 2309 hdmi->plat_data = plat_data; 2310 hdmi->dev = dev; 2311 hdmi->sample_rate = 48000; 2312 hdmi->disabled = true; 2313 hdmi->rxsense = true; 2314 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); 2315 hdmi->mc_clkdis = 0x7f; 2316 2317 mutex_init(&hdmi->mutex); 2318 mutex_init(&hdmi->audio_mutex); 2319 spin_lock_init(&hdmi->audio_lock); 2320 2321 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 2322 if (ddc_node) { 2323 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); 2324 of_node_put(ddc_node); 2325 if (!hdmi->ddc) { 2326 dev_dbg(hdmi->dev, "failed to read ddc node\n"); 2327 return ERR_PTR(-EPROBE_DEFER); 2328 } 2329 2330 } else { 2331 dev_dbg(hdmi->dev, "no ddc property found\n"); 2332 } 2333 2334 if (!plat_data->regm) { 2335 const struct regmap_config *reg_config; 2336 2337 of_property_read_u32(np, "reg-io-width", &val); 2338 switch (val) { 2339 case 4: 2340 reg_config = &hdmi_regmap_32bit_config; 2341 hdmi->reg_shift = 2; 2342 break; 2343 case 1: 2344 reg_config = &hdmi_regmap_8bit_config; 2345 break; 2346 default: 2347 dev_err(dev, "reg-io-width must be 1 or 4\n"); 2348 return ERR_PTR(-EINVAL); 2349 } 2350 2351 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2352 hdmi->regs = devm_ioremap_resource(dev, iores); 2353 if (IS_ERR(hdmi->regs)) { 2354 ret = PTR_ERR(hdmi->regs); 2355 goto err_res; 2356 } 2357 2358 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); 2359 if (IS_ERR(hdmi->regm)) { 2360 dev_err(dev, "Failed to configure regmap\n"); 2361 ret = PTR_ERR(hdmi->regm); 2362 goto err_res; 2363 } 2364 } else { 2365 hdmi->regm = plat_data->regm; 2366 } 2367 2368 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); 2369 if (IS_ERR(hdmi->isfr_clk)) { 2370 ret = PTR_ERR(hdmi->isfr_clk); 2371 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); 2372 goto err_res; 2373 } 2374 2375 ret = clk_prepare_enable(hdmi->isfr_clk); 2376 if (ret) { 2377 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret); 2378 goto err_res; 2379 } 2380 2381 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); 2382 if (IS_ERR(hdmi->iahb_clk)) { 2383 ret = PTR_ERR(hdmi->iahb_clk); 2384 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); 2385 goto err_isfr; 2386 } 2387 2388 ret = clk_prepare_enable(hdmi->iahb_clk); 2389 if (ret) { 2390 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret); 2391 goto err_isfr; 2392 } 2393 2394 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec"); 2395 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) { 2396 hdmi->cec_clk = NULL; 2397 } else if (IS_ERR(hdmi->cec_clk)) { 2398 ret = PTR_ERR(hdmi->cec_clk); 2399 if (ret != -EPROBE_DEFER) 2400 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n", 2401 ret); 2402 2403 hdmi->cec_clk = NULL; 2404 goto err_iahb; 2405 } else { 2406 ret = clk_prepare_enable(hdmi->cec_clk); 2407 if (ret) { 2408 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n", 2409 ret); 2410 goto err_iahb; 2411 } 2412 } 2413 2414 /* Product and revision IDs */ 2415 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 2416 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 2417 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); 2418 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); 2419 2420 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || 2421 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { 2422 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", 2423 hdmi->version, prod_id0, prod_id1); 2424 ret = -ENODEV; 2425 goto err_iahb; 2426 } 2427 2428 ret = dw_hdmi_detect_phy(hdmi); 2429 if (ret < 0) 2430 goto err_iahb; 2431 2432 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", 2433 hdmi->version >> 12, hdmi->version & 0xfff, 2434 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", 2435 hdmi->phy.name); 2436 2437 initialize_hdmi_ih_mutes(hdmi); 2438 2439 irq = platform_get_irq(pdev, 0); 2440 if (irq < 0) { 2441 ret = irq; 2442 goto err_iahb; 2443 } 2444 2445 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, 2446 dw_hdmi_irq, IRQF_SHARED, 2447 dev_name(dev), hdmi); 2448 if (ret) 2449 goto err_iahb; 2450 2451 hdmi->cec_notifier = cec_notifier_get(dev); 2452 if (!hdmi->cec_notifier) { 2453 ret = -ENOMEM; 2454 goto err_iahb; 2455 } 2456 2457 /* 2458 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator 2459 * N and cts values before enabling phy 2460 */ 2461 hdmi_init_clk_regenerator(hdmi); 2462 2463 /* If DDC bus is not specified, try to register HDMI I2C bus */ 2464 if (!hdmi->ddc) { 2465 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); 2466 if (IS_ERR(hdmi->ddc)) 2467 hdmi->ddc = NULL; 2468 } 2469 2470 hdmi->bridge.driver_private = hdmi; 2471 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; 2472 #ifdef CONFIG_OF 2473 hdmi->bridge.of_node = pdev->dev.of_node; 2474 #endif 2475 2476 dw_hdmi_setup_i2c(hdmi); 2477 if (hdmi->phy.ops->setup_hpd) 2478 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 2479 2480 memset(&pdevinfo, 0, sizeof(pdevinfo)); 2481 pdevinfo.parent = dev; 2482 pdevinfo.id = PLATFORM_DEVID_AUTO; 2483 2484 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); 2485 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 2486 2487 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { 2488 struct dw_hdmi_audio_data audio; 2489 2490 audio.phys = iores->start; 2491 audio.base = hdmi->regs; 2492 audio.irq = irq; 2493 audio.hdmi = hdmi; 2494 audio.eld = hdmi->connector.eld; 2495 hdmi->enable_audio = dw_hdmi_ahb_audio_enable; 2496 hdmi->disable_audio = dw_hdmi_ahb_audio_disable; 2497 2498 pdevinfo.name = "dw-hdmi-ahb-audio"; 2499 pdevinfo.data = &audio; 2500 pdevinfo.size_data = sizeof(audio); 2501 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2502 hdmi->audio = platform_device_register_full(&pdevinfo); 2503 } else if (config0 & HDMI_CONFIG0_I2S) { 2504 struct dw_hdmi_i2s_audio_data audio; 2505 2506 audio.hdmi = hdmi; 2507 audio.write = hdmi_writeb; 2508 audio.read = hdmi_readb; 2509 hdmi->enable_audio = dw_hdmi_i2s_audio_enable; 2510 hdmi->disable_audio = dw_hdmi_i2s_audio_disable; 2511 2512 pdevinfo.name = "dw-hdmi-i2s-audio"; 2513 pdevinfo.data = &audio; 2514 pdevinfo.size_data = sizeof(audio); 2515 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2516 hdmi->audio = platform_device_register_full(&pdevinfo); 2517 } 2518 2519 if (config0 & HDMI_CONFIG0_CEC) { 2520 cec.hdmi = hdmi; 2521 cec.ops = &dw_hdmi_cec_ops; 2522 cec.irq = irq; 2523 2524 pdevinfo.name = "dw-hdmi-cec"; 2525 pdevinfo.data = &cec; 2526 pdevinfo.size_data = sizeof(cec); 2527 pdevinfo.dma_mask = 0; 2528 2529 hdmi->cec = platform_device_register_full(&pdevinfo); 2530 } 2531 2532 /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */ 2533 if (hdmi->i2c) 2534 dw_hdmi_i2c_init(hdmi); 2535 2536 return hdmi; 2537 2538 err_iahb: 2539 if (hdmi->i2c) { 2540 i2c_del_adapter(&hdmi->i2c->adap); 2541 hdmi->ddc = NULL; 2542 } 2543 2544 if (hdmi->cec_notifier) 2545 cec_notifier_put(hdmi->cec_notifier); 2546 2547 clk_disable_unprepare(hdmi->iahb_clk); 2548 if (hdmi->cec_clk) 2549 clk_disable_unprepare(hdmi->cec_clk); 2550 err_isfr: 2551 clk_disable_unprepare(hdmi->isfr_clk); 2552 err_res: 2553 i2c_put_adapter(hdmi->ddc); 2554 2555 return ERR_PTR(ret); 2556 } 2557 2558 static void __dw_hdmi_remove(struct dw_hdmi *hdmi) 2559 { 2560 if (hdmi->audio && !IS_ERR(hdmi->audio)) 2561 platform_device_unregister(hdmi->audio); 2562 if (!IS_ERR(hdmi->cec)) 2563 platform_device_unregister(hdmi->cec); 2564 2565 /* Disable all interrupts */ 2566 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2567 2568 if (hdmi->cec_notifier) 2569 cec_notifier_put(hdmi->cec_notifier); 2570 2571 clk_disable_unprepare(hdmi->iahb_clk); 2572 clk_disable_unprepare(hdmi->isfr_clk); 2573 if (hdmi->cec_clk) 2574 clk_disable_unprepare(hdmi->cec_clk); 2575 2576 if (hdmi->i2c) 2577 i2c_del_adapter(&hdmi->i2c->adap); 2578 else 2579 i2c_put_adapter(hdmi->ddc); 2580 } 2581 2582 /* ----------------------------------------------------------------------------- 2583 * Probe/remove API, used from platforms based on the DRM bridge API. 2584 */ 2585 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, 2586 const struct dw_hdmi_plat_data *plat_data) 2587 { 2588 struct dw_hdmi *hdmi; 2589 2590 hdmi = __dw_hdmi_probe(pdev, plat_data); 2591 if (IS_ERR(hdmi)) 2592 return hdmi; 2593 2594 drm_bridge_add(&hdmi->bridge); 2595 2596 return hdmi; 2597 } 2598 EXPORT_SYMBOL_GPL(dw_hdmi_probe); 2599 2600 void dw_hdmi_remove(struct dw_hdmi *hdmi) 2601 { 2602 drm_bridge_remove(&hdmi->bridge); 2603 2604 __dw_hdmi_remove(hdmi); 2605 } 2606 EXPORT_SYMBOL_GPL(dw_hdmi_remove); 2607 2608 /* ----------------------------------------------------------------------------- 2609 * Bind/unbind API, used from platforms based on the component framework. 2610 */ 2611 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, 2612 struct drm_encoder *encoder, 2613 const struct dw_hdmi_plat_data *plat_data) 2614 { 2615 struct dw_hdmi *hdmi; 2616 int ret; 2617 2618 hdmi = __dw_hdmi_probe(pdev, plat_data); 2619 if (IS_ERR(hdmi)) 2620 return hdmi; 2621 2622 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL); 2623 if (ret) { 2624 dw_hdmi_remove(hdmi); 2625 DRM_ERROR("Failed to initialize bridge with drm\n"); 2626 return ERR_PTR(ret); 2627 } 2628 2629 return hdmi; 2630 } 2631 EXPORT_SYMBOL_GPL(dw_hdmi_bind); 2632 2633 void dw_hdmi_unbind(struct dw_hdmi *hdmi) 2634 { 2635 __dw_hdmi_remove(hdmi); 2636 } 2637 EXPORT_SYMBOL_GPL(dw_hdmi_unbind); 2638 2639 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 2640 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); 2641 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); 2642 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>"); 2643 MODULE_DESCRIPTION("DW HDMI transmitter driver"); 2644 MODULE_LICENSE("GPL"); 2645 MODULE_ALIAS("platform:dw-hdmi"); 2646