1 /* 2 * DesignWare High-Definition Multimedia Interface (HDMI) driver 3 * 4 * Copyright (C) 2013-2015 Mentor Graphics Inc. 5 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 6 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 */ 14 #include <linux/module.h> 15 #include <linux/irq.h> 16 #include <linux/delay.h> 17 #include <linux/err.h> 18 #include <linux/clk.h> 19 #include <linux/hdmi.h> 20 #include <linux/mutex.h> 21 #include <linux/of_device.h> 22 #include <linux/regmap.h> 23 #include <linux/spinlock.h> 24 25 #include <drm/drm_of.h> 26 #include <drm/drmP.h> 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_encoder_slave.h> 31 #include <drm/bridge/dw_hdmi.h> 32 33 #include <uapi/linux/media-bus-format.h> 34 #include <uapi/linux/videodev2.h> 35 36 #include "dw-hdmi.h" 37 #include "dw-hdmi-audio.h" 38 #include "dw-hdmi-cec.h" 39 40 #include <media/cec-notifier.h> 41 42 #define DDC_SEGMENT_ADDR 0x30 43 44 #define HDMI_EDID_LEN 512 45 46 enum hdmi_datamap { 47 RGB444_8B = 0x01, 48 RGB444_10B = 0x03, 49 RGB444_12B = 0x05, 50 RGB444_16B = 0x07, 51 YCbCr444_8B = 0x09, 52 YCbCr444_10B = 0x0B, 53 YCbCr444_12B = 0x0D, 54 YCbCr444_16B = 0x0F, 55 YCbCr422_8B = 0x16, 56 YCbCr422_10B = 0x14, 57 YCbCr422_12B = 0x12, 58 }; 59 60 static const u16 csc_coeff_default[3][4] = { 61 { 0x2000, 0x0000, 0x0000, 0x0000 }, 62 { 0x0000, 0x2000, 0x0000, 0x0000 }, 63 { 0x0000, 0x0000, 0x2000, 0x0000 } 64 }; 65 66 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 67 { 0x2000, 0x6926, 0x74fd, 0x010e }, 68 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 69 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 70 }; 71 72 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 73 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 74 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 75 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 76 }; 77 78 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 79 { 0x2591, 0x1322, 0x074b, 0x0000 }, 80 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 81 { 0x6acd, 0x7534, 0x2000, 0x0200 } 82 }; 83 84 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 85 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 86 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 87 { 0x6756, 0x78ab, 0x2000, 0x0200 } 88 }; 89 90 struct hdmi_vmode { 91 bool mdataenablepolarity; 92 93 unsigned int mpixelclock; 94 unsigned int mpixelrepetitioninput; 95 unsigned int mpixelrepetitionoutput; 96 }; 97 98 struct hdmi_data_info { 99 unsigned int enc_in_bus_format; 100 unsigned int enc_out_bus_format; 101 unsigned int enc_in_encoding; 102 unsigned int enc_out_encoding; 103 unsigned int pix_repet_factor; 104 unsigned int hdcp_enable; 105 struct hdmi_vmode video_mode; 106 }; 107 108 struct dw_hdmi_i2c { 109 struct i2c_adapter adap; 110 111 struct mutex lock; /* used to serialize data transfers */ 112 struct completion cmp; 113 u8 stat; 114 115 u8 slave_reg; 116 bool is_regaddr; 117 bool is_segment; 118 }; 119 120 struct dw_hdmi_phy_data { 121 enum dw_hdmi_phy_type type; 122 const char *name; 123 unsigned int gen; 124 bool has_svsret; 125 int (*configure)(struct dw_hdmi *hdmi, 126 const struct dw_hdmi_plat_data *pdata, 127 unsigned long mpixelclock); 128 }; 129 130 struct dw_hdmi { 131 struct drm_connector connector; 132 struct drm_bridge bridge; 133 134 unsigned int version; 135 136 struct platform_device *audio; 137 struct platform_device *cec; 138 struct device *dev; 139 struct clk *isfr_clk; 140 struct clk *iahb_clk; 141 struct clk *cec_clk; 142 struct dw_hdmi_i2c *i2c; 143 144 struct hdmi_data_info hdmi_data; 145 const struct dw_hdmi_plat_data *plat_data; 146 147 int vic; 148 149 u8 edid[HDMI_EDID_LEN]; 150 bool cable_plugin; 151 152 struct { 153 const struct dw_hdmi_phy_ops *ops; 154 const char *name; 155 void *data; 156 bool enabled; 157 } phy; 158 159 struct drm_display_mode previous_mode; 160 161 struct i2c_adapter *ddc; 162 void __iomem *regs; 163 bool sink_is_hdmi; 164 bool sink_has_audio; 165 166 struct mutex mutex; /* for state below and previous_mode */ 167 enum drm_connector_force force; /* mutex-protected force state */ 168 bool disabled; /* DRM has disabled our bridge */ 169 bool bridge_is_on; /* indicates the bridge is on */ 170 bool rxsense; /* rxsense state */ 171 u8 phy_mask; /* desired phy int mask settings */ 172 u8 mc_clkdis; /* clock disable register */ 173 174 spinlock_t audio_lock; 175 struct mutex audio_mutex; 176 unsigned int sample_rate; 177 unsigned int audio_cts; 178 unsigned int audio_n; 179 bool audio_enable; 180 181 unsigned int reg_shift; 182 struct regmap *regm; 183 void (*enable_audio)(struct dw_hdmi *hdmi); 184 void (*disable_audio)(struct dw_hdmi *hdmi); 185 186 struct cec_notifier *cec_notifier; 187 }; 188 189 #define HDMI_IH_PHY_STAT0_RX_SENSE \ 190 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ 191 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) 192 193 #define HDMI_PHY_RX_SENSE \ 194 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ 195 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) 196 197 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 198 { 199 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); 200 } 201 202 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 203 { 204 unsigned int val = 0; 205 206 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); 207 208 return val; 209 } 210 211 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 212 { 213 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); 214 } 215 216 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 217 u8 shift, u8 mask) 218 { 219 hdmi_modb(hdmi, data << shift, mask, reg); 220 } 221 222 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 223 { 224 /* Software reset */ 225 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 226 227 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ 228 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); 229 230 /* Set done, not acknowledged and arbitration interrupt polarities */ 231 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 232 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 233 HDMI_I2CM_CTLINT); 234 235 /* Clear DONE and ERROR interrupts */ 236 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 237 HDMI_IH_I2CM_STAT0); 238 239 /* Mute DONE and ERROR interrupts */ 240 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 241 HDMI_IH_MUTE_I2CM_STAT0); 242 } 243 244 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 245 unsigned char *buf, unsigned int length) 246 { 247 struct dw_hdmi_i2c *i2c = hdmi->i2c; 248 int stat; 249 250 if (!i2c->is_regaddr) { 251 dev_dbg(hdmi->dev, "set read register address to 0\n"); 252 i2c->slave_reg = 0x00; 253 i2c->is_regaddr = true; 254 } 255 256 while (length--) { 257 reinit_completion(&i2c->cmp); 258 259 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 260 if (i2c->is_segment) 261 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 262 HDMI_I2CM_OPERATION); 263 else 264 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 265 HDMI_I2CM_OPERATION); 266 267 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 268 if (!stat) 269 return -EAGAIN; 270 271 /* Check for error condition on the bus */ 272 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 273 return -EIO; 274 275 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 276 } 277 i2c->is_segment = false; 278 279 return 0; 280 } 281 282 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 283 unsigned char *buf, unsigned int length) 284 { 285 struct dw_hdmi_i2c *i2c = hdmi->i2c; 286 int stat; 287 288 if (!i2c->is_regaddr) { 289 /* Use the first write byte as register address */ 290 i2c->slave_reg = buf[0]; 291 length--; 292 buf++; 293 i2c->is_regaddr = true; 294 } 295 296 while (length--) { 297 reinit_completion(&i2c->cmp); 298 299 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 300 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 301 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 302 HDMI_I2CM_OPERATION); 303 304 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 305 if (!stat) 306 return -EAGAIN; 307 308 /* Check for error condition on the bus */ 309 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 310 return -EIO; 311 } 312 313 return 0; 314 } 315 316 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, 317 struct i2c_msg *msgs, int num) 318 { 319 struct dw_hdmi *hdmi = i2c_get_adapdata(adap); 320 struct dw_hdmi_i2c *i2c = hdmi->i2c; 321 u8 addr = msgs[0].addr; 322 int i, ret = 0; 323 324 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); 325 326 for (i = 0; i < num; i++) { 327 if (msgs[i].len == 0) { 328 dev_dbg(hdmi->dev, 329 "unsupported transfer %d/%d, no data\n", 330 i + 1, num); 331 return -EOPNOTSUPP; 332 } 333 } 334 335 mutex_lock(&i2c->lock); 336 337 /* Unmute DONE and ERROR interrupts */ 338 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 339 340 /* Set slave device address taken from the first I2C message */ 341 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 342 343 /* Set slave device register address on transfer */ 344 i2c->is_regaddr = false; 345 346 /* Set segment pointer for I2C extended read mode operation */ 347 i2c->is_segment = false; 348 349 for (i = 0; i < num; i++) { 350 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", 351 i + 1, num, msgs[i].len, msgs[i].flags); 352 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 353 i2c->is_segment = true; 354 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 355 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 356 } else { 357 if (msgs[i].flags & I2C_M_RD) 358 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 359 msgs[i].len); 360 else 361 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 362 msgs[i].len); 363 } 364 if (ret < 0) 365 break; 366 } 367 368 if (!ret) 369 ret = num; 370 371 /* Mute DONE and ERROR interrupts */ 372 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 373 HDMI_IH_MUTE_I2CM_STAT0); 374 375 mutex_unlock(&i2c->lock); 376 377 return ret; 378 } 379 380 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) 381 { 382 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 383 } 384 385 static const struct i2c_algorithm dw_hdmi_algorithm = { 386 .master_xfer = dw_hdmi_i2c_xfer, 387 .functionality = dw_hdmi_i2c_func, 388 }; 389 390 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) 391 { 392 struct i2c_adapter *adap; 393 struct dw_hdmi_i2c *i2c; 394 int ret; 395 396 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 397 if (!i2c) 398 return ERR_PTR(-ENOMEM); 399 400 mutex_init(&i2c->lock); 401 init_completion(&i2c->cmp); 402 403 adap = &i2c->adap; 404 adap->class = I2C_CLASS_DDC; 405 adap->owner = THIS_MODULE; 406 adap->dev.parent = hdmi->dev; 407 adap->algo = &dw_hdmi_algorithm; 408 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name)); 409 i2c_set_adapdata(adap, hdmi); 410 411 ret = i2c_add_adapter(adap); 412 if (ret) { 413 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 414 devm_kfree(hdmi->dev, i2c); 415 return ERR_PTR(ret); 416 } 417 418 hdmi->i2c = i2c; 419 420 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 421 422 return adap; 423 } 424 425 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 426 unsigned int n) 427 { 428 /* Must be set/cleared first */ 429 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 430 431 /* nshift factor = 0 */ 432 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 433 434 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 435 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 436 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 437 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 438 439 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 440 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 441 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 442 } 443 444 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) 445 { 446 unsigned int n = (128 * freq) / 1000; 447 unsigned int mult = 1; 448 449 while (freq > 48000) { 450 mult *= 2; 451 freq /= 2; 452 } 453 454 switch (freq) { 455 case 32000: 456 if (pixel_clk == 25175000) 457 n = 4576; 458 else if (pixel_clk == 27027000) 459 n = 4096; 460 else if (pixel_clk == 74176000 || pixel_clk == 148352000) 461 n = 11648; 462 else 463 n = 4096; 464 n *= mult; 465 break; 466 467 case 44100: 468 if (pixel_clk == 25175000) 469 n = 7007; 470 else if (pixel_clk == 74176000) 471 n = 17836; 472 else if (pixel_clk == 148352000) 473 n = 8918; 474 else 475 n = 6272; 476 n *= mult; 477 break; 478 479 case 48000: 480 if (pixel_clk == 25175000) 481 n = 6864; 482 else if (pixel_clk == 27027000) 483 n = 6144; 484 else if (pixel_clk == 74176000) 485 n = 11648; 486 else if (pixel_clk == 148352000) 487 n = 5824; 488 else 489 n = 6144; 490 n *= mult; 491 break; 492 493 default: 494 break; 495 } 496 497 return n; 498 } 499 500 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, 501 unsigned long pixel_clk, unsigned int sample_rate) 502 { 503 unsigned long ftdms = pixel_clk; 504 unsigned int n, cts; 505 u64 tmp; 506 507 n = hdmi_compute_n(sample_rate, pixel_clk); 508 509 /* 510 * Compute the CTS value from the N value. Note that CTS and N 511 * can be up to 20 bits in total, so we need 64-bit math. Also 512 * note that our TDMS clock is not fully accurate; it is accurate 513 * to kHz. This can introduce an unnecessary remainder in the 514 * calculation below, so we don't try to warn about that. 515 */ 516 tmp = (u64)ftdms * n; 517 do_div(tmp, 128 * sample_rate); 518 cts = tmp; 519 520 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", 521 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, 522 n, cts); 523 524 spin_lock_irq(&hdmi->audio_lock); 525 hdmi->audio_n = n; 526 hdmi->audio_cts = cts; 527 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 528 spin_unlock_irq(&hdmi->audio_lock); 529 } 530 531 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) 532 { 533 mutex_lock(&hdmi->audio_mutex); 534 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); 535 mutex_unlock(&hdmi->audio_mutex); 536 } 537 538 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 539 { 540 mutex_lock(&hdmi->audio_mutex); 541 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock, 542 hdmi->sample_rate); 543 mutex_unlock(&hdmi->audio_mutex); 544 } 545 546 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 547 { 548 mutex_lock(&hdmi->audio_mutex); 549 hdmi->sample_rate = rate; 550 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock, 551 hdmi->sample_rate); 552 mutex_unlock(&hdmi->audio_mutex); 553 } 554 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); 555 556 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) 557 { 558 if (enable) 559 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; 560 else 561 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; 562 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 563 } 564 565 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi) 566 { 567 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 568 } 569 570 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi) 571 { 572 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 573 } 574 575 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi) 576 { 577 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 578 hdmi_enable_audio_clk(hdmi, true); 579 } 580 581 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi) 582 { 583 hdmi_enable_audio_clk(hdmi, false); 584 } 585 586 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 587 { 588 unsigned long flags; 589 590 spin_lock_irqsave(&hdmi->audio_lock, flags); 591 hdmi->audio_enable = true; 592 if (hdmi->enable_audio) 593 hdmi->enable_audio(hdmi); 594 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 595 } 596 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); 597 598 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 599 { 600 unsigned long flags; 601 602 spin_lock_irqsave(&hdmi->audio_lock, flags); 603 hdmi->audio_enable = false; 604 if (hdmi->disable_audio) 605 hdmi->disable_audio(hdmi); 606 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 607 } 608 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); 609 610 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 611 { 612 switch (bus_format) { 613 case MEDIA_BUS_FMT_RGB888_1X24: 614 case MEDIA_BUS_FMT_RGB101010_1X30: 615 case MEDIA_BUS_FMT_RGB121212_1X36: 616 case MEDIA_BUS_FMT_RGB161616_1X48: 617 return true; 618 619 default: 620 return false; 621 } 622 } 623 624 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 625 { 626 switch (bus_format) { 627 case MEDIA_BUS_FMT_YUV8_1X24: 628 case MEDIA_BUS_FMT_YUV10_1X30: 629 case MEDIA_BUS_FMT_YUV12_1X36: 630 case MEDIA_BUS_FMT_YUV16_1X48: 631 return true; 632 633 default: 634 return false; 635 } 636 } 637 638 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 639 { 640 switch (bus_format) { 641 case MEDIA_BUS_FMT_UYVY8_1X16: 642 case MEDIA_BUS_FMT_UYVY10_1X20: 643 case MEDIA_BUS_FMT_UYVY12_1X24: 644 return true; 645 646 default: 647 return false; 648 } 649 } 650 651 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 652 { 653 switch (bus_format) { 654 case MEDIA_BUS_FMT_RGB888_1X24: 655 case MEDIA_BUS_FMT_YUV8_1X24: 656 case MEDIA_BUS_FMT_UYVY8_1X16: 657 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 658 return 8; 659 660 case MEDIA_BUS_FMT_RGB101010_1X30: 661 case MEDIA_BUS_FMT_YUV10_1X30: 662 case MEDIA_BUS_FMT_UYVY10_1X20: 663 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 664 return 10; 665 666 case MEDIA_BUS_FMT_RGB121212_1X36: 667 case MEDIA_BUS_FMT_YUV12_1X36: 668 case MEDIA_BUS_FMT_UYVY12_1X24: 669 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 670 return 12; 671 672 case MEDIA_BUS_FMT_RGB161616_1X48: 673 case MEDIA_BUS_FMT_YUV16_1X48: 674 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 675 return 16; 676 677 default: 678 return 0; 679 } 680 } 681 682 /* 683 * this submodule is responsible for the video data synchronization. 684 * for example, for RGB 4:4:4 input, the data map is defined as 685 * pin{47~40} <==> R[7:0] 686 * pin{31~24} <==> G[7:0] 687 * pin{15~8} <==> B[7:0] 688 */ 689 static void hdmi_video_sample(struct dw_hdmi *hdmi) 690 { 691 int color_format = 0; 692 u8 val; 693 694 switch (hdmi->hdmi_data.enc_in_bus_format) { 695 case MEDIA_BUS_FMT_RGB888_1X24: 696 color_format = 0x01; 697 break; 698 case MEDIA_BUS_FMT_RGB101010_1X30: 699 color_format = 0x03; 700 break; 701 case MEDIA_BUS_FMT_RGB121212_1X36: 702 color_format = 0x05; 703 break; 704 case MEDIA_BUS_FMT_RGB161616_1X48: 705 color_format = 0x07; 706 break; 707 708 case MEDIA_BUS_FMT_YUV8_1X24: 709 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 710 color_format = 0x09; 711 break; 712 case MEDIA_BUS_FMT_YUV10_1X30: 713 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 714 color_format = 0x0B; 715 break; 716 case MEDIA_BUS_FMT_YUV12_1X36: 717 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 718 color_format = 0x0D; 719 break; 720 case MEDIA_BUS_FMT_YUV16_1X48: 721 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 722 color_format = 0x0F; 723 break; 724 725 case MEDIA_BUS_FMT_UYVY8_1X16: 726 color_format = 0x16; 727 break; 728 case MEDIA_BUS_FMT_UYVY10_1X20: 729 color_format = 0x14; 730 break; 731 case MEDIA_BUS_FMT_UYVY12_1X24: 732 color_format = 0x12; 733 break; 734 735 default: 736 return; 737 } 738 739 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 740 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 741 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 742 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 743 744 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 745 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 746 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 747 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 748 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 749 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 750 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 751 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 752 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 753 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 754 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 755 } 756 757 static int is_color_space_conversion(struct dw_hdmi *hdmi) 758 { 759 return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format; 760 } 761 762 static int is_color_space_decimation(struct dw_hdmi *hdmi) 763 { 764 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 765 return 0; 766 767 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 768 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 769 return 1; 770 771 return 0; 772 } 773 774 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 775 { 776 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 777 return 0; 778 779 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 780 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 781 return 1; 782 783 return 0; 784 } 785 786 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 787 { 788 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 789 unsigned i; 790 u32 csc_scale = 1; 791 792 if (is_color_space_conversion(hdmi)) { 793 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 794 if (hdmi->hdmi_data.enc_out_encoding == 795 V4L2_YCBCR_ENC_601) 796 csc_coeff = &csc_coeff_rgb_out_eitu601; 797 else 798 csc_coeff = &csc_coeff_rgb_out_eitu709; 799 } else if (hdmi_bus_fmt_is_rgb( 800 hdmi->hdmi_data.enc_in_bus_format)) { 801 if (hdmi->hdmi_data.enc_out_encoding == 802 V4L2_YCBCR_ENC_601) 803 csc_coeff = &csc_coeff_rgb_in_eitu601; 804 else 805 csc_coeff = &csc_coeff_rgb_in_eitu709; 806 csc_scale = 0; 807 } 808 } 809 810 /* The CSC registers are sequential, alternating MSB then LSB */ 811 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 812 u16 coeff_a = (*csc_coeff)[0][i]; 813 u16 coeff_b = (*csc_coeff)[1][i]; 814 u16 coeff_c = (*csc_coeff)[2][i]; 815 816 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 817 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 818 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 819 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 820 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 821 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 822 } 823 824 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 825 HDMI_CSC_SCALE); 826 } 827 828 static void hdmi_video_csc(struct dw_hdmi *hdmi) 829 { 830 int color_depth = 0; 831 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 832 int decimation = 0; 833 834 /* YCC422 interpolation to 444 mode */ 835 if (is_color_space_interpolation(hdmi)) 836 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 837 else if (is_color_space_decimation(hdmi)) 838 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 839 840 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 841 case 8: 842 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 843 break; 844 case 10: 845 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 846 break; 847 case 12: 848 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 849 break; 850 case 16: 851 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 852 break; 853 854 default: 855 return; 856 } 857 858 /* Configure the CSC registers */ 859 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 860 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 861 HDMI_CSC_SCALE); 862 863 dw_hdmi_update_csc_coeffs(hdmi); 864 } 865 866 /* 867 * HDMI video packetizer is used to packetize the data. 868 * for example, if input is YCC422 mode or repeater is used, 869 * data should be repacked this module can be bypassed. 870 */ 871 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 872 { 873 unsigned int color_depth = 0; 874 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 875 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 876 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 877 u8 val, vp_conf; 878 879 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 880 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) { 881 switch (hdmi_bus_fmt_color_depth( 882 hdmi->hdmi_data.enc_out_bus_format)) { 883 case 8: 884 color_depth = 4; 885 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 886 break; 887 case 10: 888 color_depth = 5; 889 break; 890 case 12: 891 color_depth = 6; 892 break; 893 case 16: 894 color_depth = 7; 895 break; 896 default: 897 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 898 } 899 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 900 switch (hdmi_bus_fmt_color_depth( 901 hdmi->hdmi_data.enc_out_bus_format)) { 902 case 0: 903 case 8: 904 remap_size = HDMI_VP_REMAP_YCC422_16bit; 905 break; 906 case 10: 907 remap_size = HDMI_VP_REMAP_YCC422_20bit; 908 break; 909 case 12: 910 remap_size = HDMI_VP_REMAP_YCC422_24bit; 911 break; 912 913 default: 914 return; 915 } 916 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 917 } else { 918 return; 919 } 920 921 /* set the packetizer registers */ 922 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 923 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | 924 ((hdmi_data->pix_repet_factor << 925 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & 926 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); 927 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 928 929 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 930 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 931 932 /* Data from pixel repeater block */ 933 if (hdmi_data->pix_repet_factor > 1) { 934 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 935 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 936 } else { /* data from packetizer block */ 937 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 938 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 939 } 940 941 hdmi_modb(hdmi, vp_conf, 942 HDMI_VP_CONF_PR_EN_MASK | 943 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 944 945 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 946 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 947 948 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 949 950 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 951 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 952 HDMI_VP_CONF_PP_EN_ENABLE | 953 HDMI_VP_CONF_YCC422_EN_DISABLE; 954 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 955 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 956 HDMI_VP_CONF_PP_EN_DISABLE | 957 HDMI_VP_CONF_YCC422_EN_ENABLE; 958 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 959 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 960 HDMI_VP_CONF_PP_EN_DISABLE | 961 HDMI_VP_CONF_YCC422_EN_DISABLE; 962 } else { 963 return; 964 } 965 966 hdmi_modb(hdmi, vp_conf, 967 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 968 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 969 970 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 971 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 972 HDMI_VP_STUFF_PP_STUFFING_MASK | 973 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 974 975 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 976 HDMI_VP_CONF); 977 } 978 979 /* ----------------------------------------------------------------------------- 980 * Synopsys PHY Handling 981 */ 982 983 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 984 unsigned char bit) 985 { 986 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 987 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 988 } 989 990 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 991 { 992 u32 val; 993 994 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 995 if (msec-- == 0) 996 return false; 997 udelay(1000); 998 } 999 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 1000 1001 return true; 1002 } 1003 1004 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 1005 unsigned char addr) 1006 { 1007 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 1008 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 1009 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 1010 HDMI_PHY_I2CM_DATAO_1_ADDR); 1011 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 1012 HDMI_PHY_I2CM_DATAO_0_ADDR); 1013 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 1014 HDMI_PHY_I2CM_OPERATION_ADDR); 1015 hdmi_phy_wait_i2c_done(hdmi, 1000); 1016 } 1017 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); 1018 1019 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 1020 { 1021 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 1022 HDMI_PHY_CONF0_PDZ_OFFSET, 1023 HDMI_PHY_CONF0_PDZ_MASK); 1024 } 1025 1026 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 1027 { 1028 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1029 HDMI_PHY_CONF0_ENTMDS_OFFSET, 1030 HDMI_PHY_CONF0_ENTMDS_MASK); 1031 } 1032 1033 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 1034 { 1035 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1036 HDMI_PHY_CONF0_SVSRET_OFFSET, 1037 HDMI_PHY_CONF0_SVSRET_MASK); 1038 } 1039 1040 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 1041 { 1042 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1043 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 1044 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 1045 } 1046 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq); 1047 1048 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 1049 { 1050 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1051 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 1052 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 1053 } 1054 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron); 1055 1056 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 1057 { 1058 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1059 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 1060 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 1061 } 1062 1063 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 1064 { 1065 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1066 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 1067 HDMI_PHY_CONF0_SELDIPIF_MASK); 1068 } 1069 1070 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi) 1071 { 1072 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 1073 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1074 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1075 } 1076 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset); 1077 1078 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) 1079 { 1080 hdmi_phy_test_clear(hdmi, 1); 1081 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR); 1082 hdmi_phy_test_clear(hdmi, 0); 1083 } 1084 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr); 1085 1086 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 1087 { 1088 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1089 unsigned int i; 1090 u16 val; 1091 1092 if (phy->gen == 1) { 1093 dw_hdmi_phy_enable_tmds(hdmi, 0); 1094 dw_hdmi_phy_enable_powerdown(hdmi, true); 1095 return; 1096 } 1097 1098 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 1099 1100 /* 1101 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 1102 * to low power mode. 1103 */ 1104 for (i = 0; i < 5; ++i) { 1105 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 1106 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 1107 break; 1108 1109 usleep_range(1000, 2000); 1110 } 1111 1112 if (val & HDMI_PHY_TX_PHY_LOCK) 1113 dev_warn(hdmi->dev, "PHY failed to power down\n"); 1114 else 1115 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); 1116 1117 dw_hdmi_phy_gen2_pddq(hdmi, 1); 1118 } 1119 1120 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 1121 { 1122 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1123 unsigned int i; 1124 u8 val; 1125 1126 if (phy->gen == 1) { 1127 dw_hdmi_phy_enable_powerdown(hdmi, false); 1128 1129 /* Toggle TMDS enable. */ 1130 dw_hdmi_phy_enable_tmds(hdmi, 0); 1131 dw_hdmi_phy_enable_tmds(hdmi, 1); 1132 return 0; 1133 } 1134 1135 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 1136 dw_hdmi_phy_gen2_pddq(hdmi, 0); 1137 1138 /* Wait for PHY PLL lock */ 1139 for (i = 0; i < 5; ++i) { 1140 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 1141 if (val) 1142 break; 1143 1144 usleep_range(1000, 2000); 1145 } 1146 1147 if (!val) { 1148 dev_err(hdmi->dev, "PHY PLL failed to lock\n"); 1149 return -ETIMEDOUT; 1150 } 1151 1152 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); 1153 return 0; 1154 } 1155 1156 /* 1157 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 1158 * information the DWC MHL PHY has the same register layout and is thus also 1159 * supported by this function. 1160 */ 1161 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 1162 const struct dw_hdmi_plat_data *pdata, 1163 unsigned long mpixelclock) 1164 { 1165 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 1166 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 1167 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 1168 1169 /* PLL/MPLL Cfg - always match on final entry */ 1170 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 1171 if (mpixelclock <= mpll_config->mpixelclock) 1172 break; 1173 1174 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 1175 if (mpixelclock <= curr_ctrl->mpixelclock) 1176 break; 1177 1178 for (; phy_config->mpixelclock != ~0UL; phy_config++) 1179 if (mpixelclock <= phy_config->mpixelclock) 1180 break; 1181 1182 if (mpll_config->mpixelclock == ~0UL || 1183 curr_ctrl->mpixelclock == ~0UL || 1184 phy_config->mpixelclock == ~0UL) 1185 return -EINVAL; 1186 1187 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 1188 HDMI_3D_TX_PHY_CPCE_CTRL); 1189 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 1190 HDMI_3D_TX_PHY_GMPCTRL); 1191 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 1192 HDMI_3D_TX_PHY_CURRCTRL); 1193 1194 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 1195 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 1196 HDMI_3D_TX_PHY_MSM_CTRL); 1197 1198 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 1199 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 1200 HDMI_3D_TX_PHY_CKSYMTXCTRL); 1201 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 1202 HDMI_3D_TX_PHY_VLEVCTRL); 1203 1204 /* Override and disable clock termination. */ 1205 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 1206 HDMI_3D_TX_PHY_CKCALCTRL); 1207 1208 return 0; 1209 } 1210 1211 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 1212 { 1213 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1214 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 1215 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 1216 int ret; 1217 1218 dw_hdmi_phy_power_off(hdmi); 1219 1220 /* Leave low power consumption mode by asserting SVSRET. */ 1221 if (phy->has_svsret) 1222 dw_hdmi_phy_enable_svsret(hdmi, 1); 1223 1224 dw_hdmi_phy_reset(hdmi); 1225 1226 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 1227 1228 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); 1229 1230 /* Write to the PHY as configured by the platform */ 1231 if (pdata->configure_phy) 1232 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 1233 else 1234 ret = phy->configure(hdmi, pdata, mpixelclock); 1235 if (ret) { 1236 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", 1237 mpixelclock); 1238 return ret; 1239 } 1240 1241 return dw_hdmi_phy_power_on(hdmi); 1242 } 1243 1244 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 1245 struct drm_display_mode *mode) 1246 { 1247 int i, ret; 1248 1249 /* HDMI Phy spec says to do the phy initialization sequence twice */ 1250 for (i = 0; i < 2; i++) { 1251 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 1252 dw_hdmi_phy_sel_interface_control(hdmi, 0); 1253 1254 ret = hdmi_phy_configure(hdmi); 1255 if (ret) 1256 return ret; 1257 } 1258 1259 return 0; 1260 } 1261 1262 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 1263 { 1264 dw_hdmi_phy_power_off(hdmi); 1265 } 1266 1267 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 1268 void *data) 1269 { 1270 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 1271 connector_status_connected : connector_status_disconnected; 1272 } 1273 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); 1274 1275 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 1276 bool force, bool disabled, bool rxsense) 1277 { 1278 u8 old_mask = hdmi->phy_mask; 1279 1280 if (force || disabled || !rxsense) 1281 hdmi->phy_mask |= HDMI_PHY_RX_SENSE; 1282 else 1283 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; 1284 1285 if (old_mask != hdmi->phy_mask) 1286 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1287 } 1288 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd); 1289 1290 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) 1291 { 1292 /* 1293 * Configure the PHY RX SENSE and HPD interrupts polarities and clear 1294 * any pending interrupt. 1295 */ 1296 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); 1297 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1298 HDMI_IH_PHY_STAT0); 1299 1300 /* Enable cable hot plug irq. */ 1301 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1302 1303 /* Clear and unmute interrupts. */ 1304 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1305 HDMI_IH_PHY_STAT0); 1306 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 1307 HDMI_IH_MUTE_PHY_STAT0); 1308 } 1309 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd); 1310 1311 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 1312 .init = dw_hdmi_phy_init, 1313 .disable = dw_hdmi_phy_disable, 1314 .read_hpd = dw_hdmi_phy_read_hpd, 1315 .update_hpd = dw_hdmi_phy_update_hpd, 1316 .setup_hpd = dw_hdmi_phy_setup_hpd, 1317 }; 1318 1319 /* ----------------------------------------------------------------------------- 1320 * HDMI TX Setup 1321 */ 1322 1323 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) 1324 { 1325 u8 de; 1326 1327 if (hdmi->hdmi_data.video_mode.mdataenablepolarity) 1328 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1329 else 1330 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; 1331 1332 /* disable rx detect */ 1333 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, 1334 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 1335 1336 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); 1337 1338 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, 1339 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); 1340 } 1341 1342 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1343 { 1344 struct hdmi_avi_infoframe frame; 1345 u8 val; 1346 1347 /* Initialise info frame from DRM mode */ 1348 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); 1349 1350 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1351 frame.colorspace = HDMI_COLORSPACE_YUV444; 1352 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1353 frame.colorspace = HDMI_COLORSPACE_YUV422; 1354 else 1355 frame.colorspace = HDMI_COLORSPACE_RGB; 1356 1357 /* Set up colorimetry */ 1358 switch (hdmi->hdmi_data.enc_out_encoding) { 1359 case V4L2_YCBCR_ENC_601: 1360 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1361 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1362 else 1363 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1364 frame.extended_colorimetry = 1365 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1366 break; 1367 case V4L2_YCBCR_ENC_709: 1368 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1369 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1370 else 1371 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1372 frame.extended_colorimetry = 1373 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1374 break; 1375 default: /* Carries no data */ 1376 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1377 frame.extended_colorimetry = 1378 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1379 break; 1380 } 1381 1382 frame.scan_mode = HDMI_SCAN_MODE_NONE; 1383 1384 /* 1385 * The Designware IP uses a different byte format from standard 1386 * AVI info frames, though generally the bits are in the correct 1387 * bytes. 1388 */ 1389 1390 /* 1391 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, 1392 * scan info in bits 4,5 rather than 0,1 and active aspect present in 1393 * bit 6 rather than 4. 1394 */ 1395 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); 1396 if (frame.active_aspect & 15) 1397 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1398 if (frame.top_bar || frame.bottom_bar) 1399 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1400 if (frame.left_bar || frame.right_bar) 1401 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1402 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1403 1404 /* AVI data byte 2 differences: none */ 1405 val = ((frame.colorimetry & 0x3) << 6) | 1406 ((frame.picture_aspect & 0x3) << 4) | 1407 (frame.active_aspect & 0xf); 1408 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1409 1410 /* AVI data byte 3 differences: none */ 1411 val = ((frame.extended_colorimetry & 0x7) << 4) | 1412 ((frame.quantization_range & 0x3) << 2) | 1413 (frame.nups & 0x3); 1414 if (frame.itc) 1415 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1416 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1417 1418 /* AVI data byte 4 differences: none */ 1419 val = frame.video_code & 0x7f; 1420 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1421 1422 /* AVI Data Byte 5- set up input and output pixel repetition */ 1423 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1424 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1425 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1426 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1427 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1428 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1429 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1430 1431 /* 1432 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1433 * ycc range in bits 2,3 rather than 6,7 1434 */ 1435 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1436 (frame.content_type & 0x3); 1437 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1438 1439 /* AVI Data Bytes 6-13 */ 1440 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1441 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1442 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1443 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1444 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1445 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1446 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1447 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1448 } 1449 1450 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1451 struct drm_display_mode *mode) 1452 { 1453 struct hdmi_vendor_infoframe frame; 1454 u8 buffer[10]; 1455 ssize_t err; 1456 1457 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, 1458 &hdmi->connector, 1459 mode); 1460 if (err < 0) 1461 /* 1462 * Going into that statement does not means vendor infoframe 1463 * fails. It just informed us that vendor infoframe is not 1464 * needed for the selected mode. Only 4k or stereoscopic 3D 1465 * mode requires vendor infoframe. So just simply return. 1466 */ 1467 return; 1468 1469 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1470 if (err < 0) { 1471 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1472 err); 1473 return; 1474 } 1475 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1476 HDMI_FC_DATAUTO0_VSD_MASK); 1477 1478 /* Set the length of HDMI vendor specific InfoFrame payload */ 1479 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1480 1481 /* Set 24bit IEEE Registration Identifier */ 1482 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1483 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1484 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1485 1486 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1487 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1488 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1489 1490 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1491 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1492 1493 /* Packet frame interpolation */ 1494 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1495 1496 /* Auto packets per frame and line spacing */ 1497 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1498 1499 /* Configures the Frame Composer On RDRB mode */ 1500 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1501 HDMI_FC_DATAUTO0_VSD_MASK); 1502 } 1503 1504 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1505 const struct drm_display_mode *mode) 1506 { 1507 u8 inv_val; 1508 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1509 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1510 unsigned int vdisplay; 1511 1512 vmode->mpixelclock = mode->clock * 1000; 1513 1514 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); 1515 1516 /* Set up HDMI_FC_INVIDCONF */ 1517 inv_val = (hdmi->hdmi_data.hdcp_enable ? 1518 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1519 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1520 1521 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1522 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1523 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1524 1525 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1526 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1527 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1528 1529 inv_val |= (vmode->mdataenablepolarity ? 1530 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1531 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1532 1533 if (hdmi->vic == 39) 1534 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1535 else 1536 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1537 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1538 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1539 1540 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1541 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1542 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1543 1544 inv_val |= hdmi->sink_is_hdmi ? 1545 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1546 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1547 1548 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1549 1550 vdisplay = mode->vdisplay; 1551 vblank = mode->vtotal - mode->vdisplay; 1552 v_de_vs = mode->vsync_start - mode->vdisplay; 1553 vsync_len = mode->vsync_end - mode->vsync_start; 1554 1555 /* 1556 * When we're setting an interlaced mode, we need 1557 * to adjust the vertical timing to suit. 1558 */ 1559 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1560 vdisplay /= 2; 1561 vblank /= 2; 1562 v_de_vs /= 2; 1563 vsync_len /= 2; 1564 } 1565 1566 /* Set up horizontal active pixel width */ 1567 hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1); 1568 hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0); 1569 1570 /* Set up vertical active lines */ 1571 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1572 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1573 1574 /* Set up horizontal blanking pixel region width */ 1575 hblank = mode->htotal - mode->hdisplay; 1576 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 1577 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 1578 1579 /* Set up vertical blanking pixel region width */ 1580 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 1581 1582 /* Set up HSYNC active edge delay width (in pixel clks) */ 1583 h_de_hs = mode->hsync_start - mode->hdisplay; 1584 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 1585 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 1586 1587 /* Set up VSYNC active edge delay (in lines) */ 1588 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 1589 1590 /* Set up HSYNC active pulse width (in pixel clks) */ 1591 hsync_len = mode->hsync_end - mode->hsync_start; 1592 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 1593 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 1594 1595 /* Set up VSYNC active edge delay (in lines) */ 1596 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 1597 } 1598 1599 /* HDMI Initialization Step B.4 */ 1600 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 1601 { 1602 /* control period minimum duration */ 1603 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 1604 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 1605 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 1606 1607 /* Set to fill TMDS data channels */ 1608 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 1609 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 1610 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 1611 1612 /* Enable pixel clock and tmds data path */ 1613 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE | 1614 HDMI_MC_CLKDIS_CSCCLK_DISABLE | 1615 HDMI_MC_CLKDIS_AUDCLK_DISABLE | 1616 HDMI_MC_CLKDIS_PREPCLK_DISABLE | 1617 HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1618 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 1619 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1620 1621 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1622 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1623 1624 /* Enable csc path */ 1625 if (is_color_space_conversion(hdmi)) { 1626 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 1627 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1628 } 1629 1630 /* Enable color space conversion if needed */ 1631 if (is_color_space_conversion(hdmi)) 1632 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 1633 HDMI_MC_FLOWCTRL); 1634 else 1635 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 1636 HDMI_MC_FLOWCTRL); 1637 } 1638 1639 /* Workaround to clear the overflow condition */ 1640 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 1641 { 1642 unsigned int count; 1643 unsigned int i; 1644 u8 val; 1645 1646 /* 1647 * Under some circumstances the Frame Composer arithmetic unit can miss 1648 * an FC register write due to being busy processing the previous one. 1649 * The issue can be worked around by issuing a TMDS software reset and 1650 * then write one of the FC registers several times. 1651 * 1652 * The number of iterations matters and depends on the HDMI TX revision 1653 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL 1654 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified 1655 * as needing the workaround, with 4 iterations for v1.30a and 1 1656 * iteration for others. 1657 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing 1658 * the workaround with a single iteration. 1659 */ 1660 1661 switch (hdmi->version) { 1662 case 0x130a: 1663 count = 4; 1664 break; 1665 case 0x131a: 1666 case 0x132a: 1667 case 0x201a: 1668 count = 1; 1669 break; 1670 default: 1671 return; 1672 } 1673 1674 /* TMDS software reset */ 1675 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 1676 1677 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 1678 for (i = 0; i < count; i++) 1679 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 1680 } 1681 1682 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi) 1683 { 1684 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2); 1685 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2); 1686 } 1687 1688 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 1689 { 1690 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 1691 HDMI_IH_MUTE_FC_STAT2); 1692 } 1693 1694 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1695 { 1696 int ret; 1697 1698 hdmi_disable_overflow_interrupts(hdmi); 1699 1700 hdmi->vic = drm_match_cea_mode(mode); 1701 1702 if (!hdmi->vic) { 1703 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); 1704 } else { 1705 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); 1706 } 1707 1708 if ((hdmi->vic == 6) || (hdmi->vic == 7) || 1709 (hdmi->vic == 21) || (hdmi->vic == 22) || 1710 (hdmi->vic == 2) || (hdmi->vic == 3) || 1711 (hdmi->vic == 17) || (hdmi->vic == 18)) 1712 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 1713 else 1714 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 1715 1716 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 1717 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 1718 1719 /* TOFIX: Get input format from plat data or fallback to RGB888 */ 1720 if (hdmi->plat_data->input_bus_format) 1721 hdmi->hdmi_data.enc_in_bus_format = 1722 hdmi->plat_data->input_bus_format; 1723 else 1724 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1725 1726 /* TOFIX: Get input encoding from plat data or fallback to none */ 1727 if (hdmi->plat_data->input_bus_encoding) 1728 hdmi->hdmi_data.enc_in_encoding = 1729 hdmi->plat_data->input_bus_encoding; 1730 else 1731 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 1732 1733 /* TOFIX: Default to RGB888 output format */ 1734 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1735 1736 hdmi->hdmi_data.pix_repet_factor = 0; 1737 hdmi->hdmi_data.hdcp_enable = 0; 1738 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 1739 1740 /* HDMI Initialization Step B.1 */ 1741 hdmi_av_composer(hdmi, mode); 1742 1743 /* HDMI Initializateion Step B.2 */ 1744 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode); 1745 if (ret) 1746 return ret; 1747 hdmi->phy.enabled = true; 1748 1749 /* HDMI Initialization Step B.3 */ 1750 dw_hdmi_enable_video_path(hdmi); 1751 1752 if (hdmi->sink_has_audio) { 1753 dev_dbg(hdmi->dev, "sink has audio support\n"); 1754 1755 /* HDMI Initialization Step E - Configure audio */ 1756 hdmi_clk_regenerator_update_pixel_clock(hdmi); 1757 hdmi_enable_audio_clk(hdmi, true); 1758 } 1759 1760 /* not for DVI mode */ 1761 if (hdmi->sink_is_hdmi) { 1762 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); 1763 1764 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 1765 hdmi_config_AVI(hdmi, mode); 1766 hdmi_config_vendor_specific_infoframe(hdmi, mode); 1767 } else { 1768 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); 1769 } 1770 1771 hdmi_video_packetize(hdmi); 1772 hdmi_video_csc(hdmi); 1773 hdmi_video_sample(hdmi); 1774 hdmi_tx_hdcp_config(hdmi); 1775 1776 dw_hdmi_clear_overflow(hdmi); 1777 if (hdmi->cable_plugin && hdmi->sink_is_hdmi) 1778 hdmi_enable_overflow_interrupts(hdmi); 1779 1780 return 0; 1781 } 1782 1783 static void dw_hdmi_setup_i2c(struct dw_hdmi *hdmi) 1784 { 1785 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, 1786 HDMI_PHY_I2CM_INT_ADDR); 1787 1788 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | 1789 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, 1790 HDMI_PHY_I2CM_CTLINT_ADDR); 1791 } 1792 1793 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) 1794 { 1795 u8 ih_mute; 1796 1797 /* 1798 * Boot up defaults are: 1799 * HDMI_IH_MUTE = 0x03 (disabled) 1800 * HDMI_IH_MUTE_* = 0x00 (enabled) 1801 * 1802 * Disable top level interrupt bits in HDMI block 1803 */ 1804 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | 1805 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 1806 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; 1807 1808 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 1809 1810 /* by default mask all interrupts */ 1811 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); 1812 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 1813 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 1814 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 1815 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); 1816 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); 1817 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); 1818 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); 1819 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); 1820 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); 1821 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); 1822 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); 1823 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); 1824 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); 1825 1826 /* Disable interrupts in the IH_MUTE_* registers */ 1827 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 1828 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 1829 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 1830 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 1831 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); 1832 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 1833 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 1834 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 1835 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 1836 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 1837 1838 /* Enable top level interrupt bits in HDMI block */ 1839 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 1840 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); 1841 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 1842 } 1843 1844 static void dw_hdmi_poweron(struct dw_hdmi *hdmi) 1845 { 1846 hdmi->bridge_is_on = true; 1847 dw_hdmi_setup(hdmi, &hdmi->previous_mode); 1848 } 1849 1850 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) 1851 { 1852 if (hdmi->phy.enabled) { 1853 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 1854 hdmi->phy.enabled = false; 1855 } 1856 1857 hdmi->bridge_is_on = false; 1858 } 1859 1860 static void dw_hdmi_update_power(struct dw_hdmi *hdmi) 1861 { 1862 int force = hdmi->force; 1863 1864 if (hdmi->disabled) { 1865 force = DRM_FORCE_OFF; 1866 } else if (force == DRM_FORCE_UNSPECIFIED) { 1867 if (hdmi->rxsense) 1868 force = DRM_FORCE_ON; 1869 else 1870 force = DRM_FORCE_OFF; 1871 } 1872 1873 if (force == DRM_FORCE_OFF) { 1874 if (hdmi->bridge_is_on) 1875 dw_hdmi_poweroff(hdmi); 1876 } else { 1877 if (!hdmi->bridge_is_on) 1878 dw_hdmi_poweron(hdmi); 1879 } 1880 } 1881 1882 /* 1883 * Adjust the detection of RXSENSE according to whether we have a forced 1884 * connection mode enabled, or whether we have been disabled. There is 1885 * no point processing RXSENSE interrupts if we have a forced connection 1886 * state, or DRM has us disabled. 1887 * 1888 * We also disable rxsense interrupts when we think we're disconnected 1889 * to avoid floating TDMS signals giving false rxsense interrupts. 1890 * 1891 * Note: we still need to listen for HPD interrupts even when DRM has us 1892 * disabled so that we can detect a connect event. 1893 */ 1894 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) 1895 { 1896 if (hdmi->phy.ops->update_hpd) 1897 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, 1898 hdmi->force, hdmi->disabled, 1899 hdmi->rxsense); 1900 } 1901 1902 static enum drm_connector_status 1903 dw_hdmi_connector_detect(struct drm_connector *connector, bool force) 1904 { 1905 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 1906 connector); 1907 1908 mutex_lock(&hdmi->mutex); 1909 hdmi->force = DRM_FORCE_UNSPECIFIED; 1910 dw_hdmi_update_power(hdmi); 1911 dw_hdmi_update_phy_mask(hdmi); 1912 mutex_unlock(&hdmi->mutex); 1913 1914 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 1915 } 1916 1917 static int dw_hdmi_connector_get_modes(struct drm_connector *connector) 1918 { 1919 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 1920 connector); 1921 struct edid *edid; 1922 int ret = 0; 1923 1924 if (!hdmi->ddc) 1925 return 0; 1926 1927 edid = drm_get_edid(connector, hdmi->ddc); 1928 if (edid) { 1929 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", 1930 edid->width_cm, edid->height_cm); 1931 1932 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); 1933 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 1934 drm_mode_connector_update_edid_property(connector, edid); 1935 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); 1936 ret = drm_add_edid_modes(connector, edid); 1937 kfree(edid); 1938 } else { 1939 dev_dbg(hdmi->dev, "failed to get edid\n"); 1940 } 1941 1942 return ret; 1943 } 1944 1945 static void dw_hdmi_connector_force(struct drm_connector *connector) 1946 { 1947 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 1948 connector); 1949 1950 mutex_lock(&hdmi->mutex); 1951 hdmi->force = connector->force; 1952 dw_hdmi_update_power(hdmi); 1953 dw_hdmi_update_phy_mask(hdmi); 1954 mutex_unlock(&hdmi->mutex); 1955 } 1956 1957 static const struct drm_connector_funcs dw_hdmi_connector_funcs = { 1958 .fill_modes = drm_helper_probe_single_connector_modes, 1959 .detect = dw_hdmi_connector_detect, 1960 .destroy = drm_connector_cleanup, 1961 .force = dw_hdmi_connector_force, 1962 .reset = drm_atomic_helper_connector_reset, 1963 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1964 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1965 }; 1966 1967 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { 1968 .get_modes = dw_hdmi_connector_get_modes, 1969 .best_encoder = drm_atomic_helper_best_encoder, 1970 }; 1971 1972 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge) 1973 { 1974 struct dw_hdmi *hdmi = bridge->driver_private; 1975 struct drm_encoder *encoder = bridge->encoder; 1976 struct drm_connector *connector = &hdmi->connector; 1977 1978 connector->interlace_allowed = 1; 1979 connector->polled = DRM_CONNECTOR_POLL_HPD; 1980 1981 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); 1982 1983 drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs, 1984 DRM_MODE_CONNECTOR_HDMIA); 1985 1986 drm_mode_connector_attach_encoder(connector, encoder); 1987 1988 return 0; 1989 } 1990 1991 static enum drm_mode_status 1992 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 1993 const struct drm_display_mode *mode) 1994 { 1995 struct dw_hdmi *hdmi = bridge->driver_private; 1996 struct drm_connector *connector = &hdmi->connector; 1997 enum drm_mode_status mode_status = MODE_OK; 1998 1999 /* We don't support double-clocked modes */ 2000 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2001 return MODE_BAD; 2002 2003 if (hdmi->plat_data->mode_valid) 2004 mode_status = hdmi->plat_data->mode_valid(connector, mode); 2005 2006 return mode_status; 2007 } 2008 2009 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, 2010 struct drm_display_mode *orig_mode, 2011 struct drm_display_mode *mode) 2012 { 2013 struct dw_hdmi *hdmi = bridge->driver_private; 2014 2015 mutex_lock(&hdmi->mutex); 2016 2017 /* Store the display mode for plugin/DKMS poweron events */ 2018 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 2019 2020 mutex_unlock(&hdmi->mutex); 2021 } 2022 2023 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge) 2024 { 2025 struct dw_hdmi *hdmi = bridge->driver_private; 2026 2027 mutex_lock(&hdmi->mutex); 2028 hdmi->disabled = true; 2029 dw_hdmi_update_power(hdmi); 2030 dw_hdmi_update_phy_mask(hdmi); 2031 mutex_unlock(&hdmi->mutex); 2032 } 2033 2034 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge) 2035 { 2036 struct dw_hdmi *hdmi = bridge->driver_private; 2037 2038 mutex_lock(&hdmi->mutex); 2039 hdmi->disabled = false; 2040 dw_hdmi_update_power(hdmi); 2041 dw_hdmi_update_phy_mask(hdmi); 2042 mutex_unlock(&hdmi->mutex); 2043 } 2044 2045 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { 2046 .attach = dw_hdmi_bridge_attach, 2047 .enable = dw_hdmi_bridge_enable, 2048 .disable = dw_hdmi_bridge_disable, 2049 .mode_set = dw_hdmi_bridge_mode_set, 2050 .mode_valid = dw_hdmi_bridge_mode_valid, 2051 }; 2052 2053 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) 2054 { 2055 struct dw_hdmi_i2c *i2c = hdmi->i2c; 2056 unsigned int stat; 2057 2058 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 2059 if (!stat) 2060 return IRQ_NONE; 2061 2062 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0); 2063 2064 i2c->stat = stat; 2065 2066 complete(&i2c->cmp); 2067 2068 return IRQ_HANDLED; 2069 } 2070 2071 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) 2072 { 2073 struct dw_hdmi *hdmi = dev_id; 2074 u8 intr_stat; 2075 irqreturn_t ret = IRQ_NONE; 2076 2077 if (hdmi->i2c) 2078 ret = dw_hdmi_i2c_irq(hdmi); 2079 2080 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2081 if (intr_stat) { 2082 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2083 return IRQ_WAKE_THREAD; 2084 } 2085 2086 return ret; 2087 } 2088 2089 void __dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) 2090 { 2091 mutex_lock(&hdmi->mutex); 2092 2093 if (!hdmi->force) { 2094 /* 2095 * If the RX sense status indicates we're disconnected, 2096 * clear the software rxsense status. 2097 */ 2098 if (!rx_sense) 2099 hdmi->rxsense = false; 2100 2101 /* 2102 * Only set the software rxsense status when both 2103 * rxsense and hpd indicates we're connected. 2104 * This avoids what seems to be bad behaviour in 2105 * at least iMX6S versions of the phy. 2106 */ 2107 if (hpd) 2108 hdmi->rxsense = true; 2109 2110 dw_hdmi_update_power(hdmi); 2111 dw_hdmi_update_phy_mask(hdmi); 2112 } 2113 mutex_unlock(&hdmi->mutex); 2114 } 2115 2116 void dw_hdmi_setup_rx_sense(struct device *dev, bool hpd, bool rx_sense) 2117 { 2118 struct dw_hdmi *hdmi = dev_get_drvdata(dev); 2119 2120 __dw_hdmi_setup_rx_sense(hdmi, hpd, rx_sense); 2121 } 2122 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); 2123 2124 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) 2125 { 2126 struct dw_hdmi *hdmi = dev_id; 2127 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; 2128 2129 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2130 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); 2131 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); 2132 2133 phy_pol_mask = 0; 2134 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) 2135 phy_pol_mask |= HDMI_PHY_HPD; 2136 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) 2137 phy_pol_mask |= HDMI_PHY_RX_SENSE0; 2138 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) 2139 phy_pol_mask |= HDMI_PHY_RX_SENSE1; 2140 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) 2141 phy_pol_mask |= HDMI_PHY_RX_SENSE2; 2142 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) 2143 phy_pol_mask |= HDMI_PHY_RX_SENSE3; 2144 2145 if (phy_pol_mask) 2146 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); 2147 2148 /* 2149 * RX sense tells us whether the TDMS transmitters are detecting 2150 * load - in other words, there's something listening on the 2151 * other end of the link. Use this to decide whether we should 2152 * power on the phy as HPD may be toggled by the sink to merely 2153 * ask the source to re-read the EDID. 2154 */ 2155 if (intr_stat & 2156 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { 2157 __dw_hdmi_setup_rx_sense(hdmi, 2158 phy_stat & HDMI_PHY_HPD, 2159 phy_stat & HDMI_PHY_RX_SENSE); 2160 2161 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) 2162 cec_notifier_set_phys_addr(hdmi->cec_notifier, 2163 CEC_PHYS_ADDR_INVALID); 2164 } 2165 2166 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { 2167 dev_dbg(hdmi->dev, "EVENT=%s\n", 2168 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout"); 2169 if (hdmi->bridge.dev) 2170 drm_helper_hpd_irq_event(hdmi->bridge.dev); 2171 } 2172 2173 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); 2174 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 2175 HDMI_IH_MUTE_PHY_STAT0); 2176 2177 return IRQ_HANDLED; 2178 } 2179 2180 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 2181 { 2182 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 2183 .name = "DWC HDMI TX PHY", 2184 .gen = 1, 2185 }, { 2186 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 2187 .name = "DWC MHL PHY + HEAC PHY", 2188 .gen = 2, 2189 .has_svsret = true, 2190 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2191 }, { 2192 .type = DW_HDMI_PHY_DWC_MHL_PHY, 2193 .name = "DWC MHL PHY", 2194 .gen = 2, 2195 .has_svsret = true, 2196 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2197 }, { 2198 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 2199 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 2200 .gen = 2, 2201 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2202 }, { 2203 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 2204 .name = "DWC HDMI 3D TX PHY", 2205 .gen = 2, 2206 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2207 }, { 2208 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 2209 .name = "DWC HDMI 2.0 TX PHY", 2210 .gen = 2, 2211 .has_svsret = true, 2212 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2213 }, { 2214 .type = DW_HDMI_PHY_VENDOR_PHY, 2215 .name = "Vendor PHY", 2216 } 2217 }; 2218 2219 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 2220 { 2221 unsigned int i; 2222 u8 phy_type; 2223 2224 phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID); 2225 2226 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { 2227 /* Vendor PHYs require support from the glue layer. */ 2228 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 2229 dev_err(hdmi->dev, 2230 "Vendor HDMI PHY not supported by glue layer\n"); 2231 return -ENODEV; 2232 } 2233 2234 hdmi->phy.ops = hdmi->plat_data->phy_ops; 2235 hdmi->phy.data = hdmi->plat_data->phy_data; 2236 hdmi->phy.name = hdmi->plat_data->phy_name; 2237 return 0; 2238 } 2239 2240 /* Synopsys PHYs are handled internally. */ 2241 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 2242 if (dw_hdmi_phys[i].type == phy_type) { 2243 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 2244 hdmi->phy.name = dw_hdmi_phys[i].name; 2245 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 2246 2247 if (!dw_hdmi_phys[i].configure && 2248 !hdmi->plat_data->configure_phy) { 2249 dev_err(hdmi->dev, "%s requires platform support\n", 2250 hdmi->phy.name); 2251 return -ENODEV; 2252 } 2253 2254 return 0; 2255 } 2256 } 2257 2258 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); 2259 return -ENODEV; 2260 } 2261 2262 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi) 2263 { 2264 mutex_lock(&hdmi->mutex); 2265 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE; 2266 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2267 mutex_unlock(&hdmi->mutex); 2268 } 2269 2270 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi) 2271 { 2272 mutex_lock(&hdmi->mutex); 2273 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE; 2274 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2275 mutex_unlock(&hdmi->mutex); 2276 } 2277 2278 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = { 2279 .write = hdmi_writeb, 2280 .read = hdmi_readb, 2281 .enable = dw_hdmi_cec_enable, 2282 .disable = dw_hdmi_cec_disable, 2283 }; 2284 2285 static const struct regmap_config hdmi_regmap_8bit_config = { 2286 .reg_bits = 32, 2287 .val_bits = 8, 2288 .reg_stride = 1, 2289 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, 2290 }; 2291 2292 static const struct regmap_config hdmi_regmap_32bit_config = { 2293 .reg_bits = 32, 2294 .val_bits = 32, 2295 .reg_stride = 4, 2296 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, 2297 }; 2298 2299 static struct dw_hdmi * 2300 __dw_hdmi_probe(struct platform_device *pdev, 2301 const struct dw_hdmi_plat_data *plat_data) 2302 { 2303 struct device *dev = &pdev->dev; 2304 struct device_node *np = dev->of_node; 2305 struct platform_device_info pdevinfo; 2306 struct device_node *ddc_node; 2307 struct dw_hdmi_cec_data cec; 2308 struct dw_hdmi *hdmi; 2309 struct resource *iores = NULL; 2310 int irq; 2311 int ret; 2312 u32 val = 1; 2313 u8 prod_id0; 2314 u8 prod_id1; 2315 u8 config0; 2316 u8 config3; 2317 2318 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 2319 if (!hdmi) 2320 return ERR_PTR(-ENOMEM); 2321 2322 hdmi->plat_data = plat_data; 2323 hdmi->dev = dev; 2324 hdmi->sample_rate = 48000; 2325 hdmi->disabled = true; 2326 hdmi->rxsense = true; 2327 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); 2328 hdmi->mc_clkdis = 0x7f; 2329 2330 mutex_init(&hdmi->mutex); 2331 mutex_init(&hdmi->audio_mutex); 2332 spin_lock_init(&hdmi->audio_lock); 2333 2334 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 2335 if (ddc_node) { 2336 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); 2337 of_node_put(ddc_node); 2338 if (!hdmi->ddc) { 2339 dev_dbg(hdmi->dev, "failed to read ddc node\n"); 2340 return ERR_PTR(-EPROBE_DEFER); 2341 } 2342 2343 } else { 2344 dev_dbg(hdmi->dev, "no ddc property found\n"); 2345 } 2346 2347 if (!plat_data->regm) { 2348 const struct regmap_config *reg_config; 2349 2350 of_property_read_u32(np, "reg-io-width", &val); 2351 switch (val) { 2352 case 4: 2353 reg_config = &hdmi_regmap_32bit_config; 2354 hdmi->reg_shift = 2; 2355 break; 2356 case 1: 2357 reg_config = &hdmi_regmap_8bit_config; 2358 break; 2359 default: 2360 dev_err(dev, "reg-io-width must be 1 or 4\n"); 2361 return ERR_PTR(-EINVAL); 2362 } 2363 2364 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2365 hdmi->regs = devm_ioremap_resource(dev, iores); 2366 if (IS_ERR(hdmi->regs)) { 2367 ret = PTR_ERR(hdmi->regs); 2368 goto err_res; 2369 } 2370 2371 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); 2372 if (IS_ERR(hdmi->regm)) { 2373 dev_err(dev, "Failed to configure regmap\n"); 2374 ret = PTR_ERR(hdmi->regm); 2375 goto err_res; 2376 } 2377 } else { 2378 hdmi->regm = plat_data->regm; 2379 } 2380 2381 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); 2382 if (IS_ERR(hdmi->isfr_clk)) { 2383 ret = PTR_ERR(hdmi->isfr_clk); 2384 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); 2385 goto err_res; 2386 } 2387 2388 ret = clk_prepare_enable(hdmi->isfr_clk); 2389 if (ret) { 2390 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret); 2391 goto err_res; 2392 } 2393 2394 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); 2395 if (IS_ERR(hdmi->iahb_clk)) { 2396 ret = PTR_ERR(hdmi->iahb_clk); 2397 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); 2398 goto err_isfr; 2399 } 2400 2401 ret = clk_prepare_enable(hdmi->iahb_clk); 2402 if (ret) { 2403 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret); 2404 goto err_isfr; 2405 } 2406 2407 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec"); 2408 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) { 2409 hdmi->cec_clk = NULL; 2410 } else if (IS_ERR(hdmi->cec_clk)) { 2411 ret = PTR_ERR(hdmi->cec_clk); 2412 if (ret != -EPROBE_DEFER) 2413 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n", 2414 ret); 2415 2416 hdmi->cec_clk = NULL; 2417 goto err_iahb; 2418 } else { 2419 ret = clk_prepare_enable(hdmi->cec_clk); 2420 if (ret) { 2421 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n", 2422 ret); 2423 goto err_iahb; 2424 } 2425 } 2426 2427 /* Product and revision IDs */ 2428 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 2429 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 2430 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); 2431 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); 2432 2433 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || 2434 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { 2435 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", 2436 hdmi->version, prod_id0, prod_id1); 2437 ret = -ENODEV; 2438 goto err_iahb; 2439 } 2440 2441 ret = dw_hdmi_detect_phy(hdmi); 2442 if (ret < 0) 2443 goto err_iahb; 2444 2445 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", 2446 hdmi->version >> 12, hdmi->version & 0xfff, 2447 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", 2448 hdmi->phy.name); 2449 2450 initialize_hdmi_ih_mutes(hdmi); 2451 2452 irq = platform_get_irq(pdev, 0); 2453 if (irq < 0) { 2454 ret = irq; 2455 goto err_iahb; 2456 } 2457 2458 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, 2459 dw_hdmi_irq, IRQF_SHARED, 2460 dev_name(dev), hdmi); 2461 if (ret) 2462 goto err_iahb; 2463 2464 hdmi->cec_notifier = cec_notifier_get(dev); 2465 if (!hdmi->cec_notifier) { 2466 ret = -ENOMEM; 2467 goto err_iahb; 2468 } 2469 2470 /* 2471 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator 2472 * N and cts values before enabling phy 2473 */ 2474 hdmi_init_clk_regenerator(hdmi); 2475 2476 /* If DDC bus is not specified, try to register HDMI I2C bus */ 2477 if (!hdmi->ddc) { 2478 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); 2479 if (IS_ERR(hdmi->ddc)) 2480 hdmi->ddc = NULL; 2481 } 2482 2483 hdmi->bridge.driver_private = hdmi; 2484 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; 2485 #ifdef CONFIG_OF 2486 hdmi->bridge.of_node = pdev->dev.of_node; 2487 #endif 2488 2489 dw_hdmi_setup_i2c(hdmi); 2490 if (hdmi->phy.ops->setup_hpd) 2491 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 2492 2493 memset(&pdevinfo, 0, sizeof(pdevinfo)); 2494 pdevinfo.parent = dev; 2495 pdevinfo.id = PLATFORM_DEVID_AUTO; 2496 2497 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); 2498 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 2499 2500 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { 2501 struct dw_hdmi_audio_data audio; 2502 2503 audio.phys = iores->start; 2504 audio.base = hdmi->regs; 2505 audio.irq = irq; 2506 audio.hdmi = hdmi; 2507 audio.eld = hdmi->connector.eld; 2508 hdmi->enable_audio = dw_hdmi_ahb_audio_enable; 2509 hdmi->disable_audio = dw_hdmi_ahb_audio_disable; 2510 2511 pdevinfo.name = "dw-hdmi-ahb-audio"; 2512 pdevinfo.data = &audio; 2513 pdevinfo.size_data = sizeof(audio); 2514 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2515 hdmi->audio = platform_device_register_full(&pdevinfo); 2516 } else if (config0 & HDMI_CONFIG0_I2S) { 2517 struct dw_hdmi_i2s_audio_data audio; 2518 2519 audio.hdmi = hdmi; 2520 audio.write = hdmi_writeb; 2521 audio.read = hdmi_readb; 2522 hdmi->enable_audio = dw_hdmi_i2s_audio_enable; 2523 hdmi->disable_audio = dw_hdmi_i2s_audio_disable; 2524 2525 pdevinfo.name = "dw-hdmi-i2s-audio"; 2526 pdevinfo.data = &audio; 2527 pdevinfo.size_data = sizeof(audio); 2528 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2529 hdmi->audio = platform_device_register_full(&pdevinfo); 2530 } 2531 2532 if (config0 & HDMI_CONFIG0_CEC) { 2533 cec.hdmi = hdmi; 2534 cec.ops = &dw_hdmi_cec_ops; 2535 cec.irq = irq; 2536 2537 pdevinfo.name = "dw-hdmi-cec"; 2538 pdevinfo.data = &cec; 2539 pdevinfo.size_data = sizeof(cec); 2540 pdevinfo.dma_mask = 0; 2541 2542 hdmi->cec = platform_device_register_full(&pdevinfo); 2543 } 2544 2545 /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */ 2546 if (hdmi->i2c) 2547 dw_hdmi_i2c_init(hdmi); 2548 2549 return hdmi; 2550 2551 err_iahb: 2552 if (hdmi->i2c) { 2553 i2c_del_adapter(&hdmi->i2c->adap); 2554 hdmi->ddc = NULL; 2555 } 2556 2557 if (hdmi->cec_notifier) 2558 cec_notifier_put(hdmi->cec_notifier); 2559 2560 clk_disable_unprepare(hdmi->iahb_clk); 2561 if (hdmi->cec_clk) 2562 clk_disable_unprepare(hdmi->cec_clk); 2563 err_isfr: 2564 clk_disable_unprepare(hdmi->isfr_clk); 2565 err_res: 2566 i2c_put_adapter(hdmi->ddc); 2567 2568 return ERR_PTR(ret); 2569 } 2570 2571 static void __dw_hdmi_remove(struct dw_hdmi *hdmi) 2572 { 2573 if (hdmi->audio && !IS_ERR(hdmi->audio)) 2574 platform_device_unregister(hdmi->audio); 2575 if (!IS_ERR(hdmi->cec)) 2576 platform_device_unregister(hdmi->cec); 2577 2578 /* Disable all interrupts */ 2579 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2580 2581 if (hdmi->cec_notifier) 2582 cec_notifier_put(hdmi->cec_notifier); 2583 2584 clk_disable_unprepare(hdmi->iahb_clk); 2585 clk_disable_unprepare(hdmi->isfr_clk); 2586 if (hdmi->cec_clk) 2587 clk_disable_unprepare(hdmi->cec_clk); 2588 2589 if (hdmi->i2c) 2590 i2c_del_adapter(&hdmi->i2c->adap); 2591 else 2592 i2c_put_adapter(hdmi->ddc); 2593 } 2594 2595 /* ----------------------------------------------------------------------------- 2596 * Probe/remove API, used from platforms based on the DRM bridge API. 2597 */ 2598 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, 2599 const struct dw_hdmi_plat_data *plat_data) 2600 { 2601 struct dw_hdmi *hdmi; 2602 2603 hdmi = __dw_hdmi_probe(pdev, plat_data); 2604 if (IS_ERR(hdmi)) 2605 return hdmi; 2606 2607 drm_bridge_add(&hdmi->bridge); 2608 2609 return hdmi; 2610 } 2611 EXPORT_SYMBOL_GPL(dw_hdmi_probe); 2612 2613 void dw_hdmi_remove(struct dw_hdmi *hdmi) 2614 { 2615 drm_bridge_remove(&hdmi->bridge); 2616 2617 __dw_hdmi_remove(hdmi); 2618 } 2619 EXPORT_SYMBOL_GPL(dw_hdmi_remove); 2620 2621 /* ----------------------------------------------------------------------------- 2622 * Bind/unbind API, used from platforms based on the component framework. 2623 */ 2624 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, 2625 struct drm_encoder *encoder, 2626 const struct dw_hdmi_plat_data *plat_data) 2627 { 2628 struct dw_hdmi *hdmi; 2629 int ret; 2630 2631 hdmi = __dw_hdmi_probe(pdev, plat_data); 2632 if (IS_ERR(hdmi)) 2633 return hdmi; 2634 2635 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL); 2636 if (ret) { 2637 dw_hdmi_remove(hdmi); 2638 DRM_ERROR("Failed to initialize bridge with drm\n"); 2639 return ERR_PTR(ret); 2640 } 2641 2642 return hdmi; 2643 } 2644 EXPORT_SYMBOL_GPL(dw_hdmi_bind); 2645 2646 void dw_hdmi_unbind(struct dw_hdmi *hdmi) 2647 { 2648 __dw_hdmi_remove(hdmi); 2649 } 2650 EXPORT_SYMBOL_GPL(dw_hdmi_unbind); 2651 2652 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 2653 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); 2654 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); 2655 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>"); 2656 MODULE_DESCRIPTION("DW HDMI transmitter driver"); 2657 MODULE_LICENSE("GPL"); 2658 MODULE_ALIAS("platform:dw-hdmi"); 2659