1 /* 2 * Silicon Image SiI8620 HDMI/MHL bridge driver 3 * 4 * Copyright (C) 2015, Samsung Electronics Co., Ltd. 5 * Andrzej Hajda <a.hajda@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <asm/unaligned.h> 13 14 #include <drm/bridge/mhl.h> 15 #include <drm/drm_crtc.h> 16 #include <drm/drm_edid.h> 17 #include <drm/drm_encoder.h> 18 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/extcon.h> 22 #include <linux/gpio/consumer.h> 23 #include <linux/i2c.h> 24 #include <linux/interrupt.h> 25 #include <linux/irq.h> 26 #include <linux/kernel.h> 27 #include <linux/list.h> 28 #include <linux/module.h> 29 #include <linux/mutex.h> 30 #include <linux/of_graph.h> 31 #include <linux/regulator/consumer.h> 32 #include <linux/slab.h> 33 34 #include <media/rc-core.h> 35 36 #include "sil-sii8620.h" 37 38 #define SII8620_BURST_BUF_LEN 288 39 #define VAL_RX_HDMI_CTRL2_DEFVAL VAL_RX_HDMI_CTRL2_IDLE_CNT(3) 40 41 #define MHL1_MAX_PCLK 75000 42 #define MHL1_MAX_PCLK_PP_MODE 150000 43 #define MHL3_MAX_PCLK 200000 44 #define MHL3_MAX_PCLK_PP_MODE 300000 45 46 enum sii8620_mode { 47 CM_DISCONNECTED, 48 CM_DISCOVERY, 49 CM_MHL1, 50 CM_MHL3, 51 CM_ECBUS_S 52 }; 53 54 enum sii8620_sink_type { 55 SINK_NONE, 56 SINK_HDMI, 57 SINK_DVI 58 }; 59 60 enum sii8620_mt_state { 61 MT_STATE_READY, 62 MT_STATE_BUSY, 63 MT_STATE_DONE 64 }; 65 66 struct sii8620 { 67 struct drm_bridge bridge; 68 struct device *dev; 69 struct rc_dev *rc_dev; 70 struct clk *clk_xtal; 71 struct gpio_desc *gpio_reset; 72 struct gpio_desc *gpio_int; 73 struct regulator_bulk_data supplies[2]; 74 struct mutex lock; /* context lock, protects fields below */ 75 int error; 76 unsigned int use_packed_pixel:1; 77 enum sii8620_mode mode; 78 enum sii8620_sink_type sink_type; 79 u8 cbus_status; 80 u8 stat[MHL_DST_SIZE]; 81 u8 xstat[MHL_XDS_SIZE]; 82 u8 devcap[MHL_DCAP_SIZE]; 83 u8 xdevcap[MHL_XDC_SIZE]; 84 bool feature_complete; 85 bool devcap_read; 86 bool sink_detected; 87 struct edid *edid; 88 unsigned int gen2_write_burst:1; 89 enum sii8620_mt_state mt_state; 90 struct extcon_dev *extcon; 91 struct notifier_block extcon_nb; 92 struct work_struct extcon_wq; 93 int cable_state; 94 struct list_head mt_queue; 95 struct { 96 int r_size; 97 int r_count; 98 int rx_ack; 99 int rx_count; 100 u8 rx_buf[32]; 101 int tx_count; 102 u8 tx_buf[32]; 103 } burst; 104 }; 105 106 struct sii8620_mt_msg; 107 108 typedef void (*sii8620_mt_msg_cb)(struct sii8620 *ctx, 109 struct sii8620_mt_msg *msg); 110 111 typedef void (*sii8620_cb)(struct sii8620 *ctx, int ret); 112 113 struct sii8620_mt_msg { 114 struct list_head node; 115 u8 reg[4]; 116 u8 ret; 117 sii8620_mt_msg_cb send; 118 sii8620_mt_msg_cb recv; 119 sii8620_cb continuation; 120 }; 121 122 static const u8 sii8620_i2c_page[] = { 123 0x39, /* Main System */ 124 0x3d, /* TDM and HSIC */ 125 0x49, /* TMDS Receiver, MHL EDID */ 126 0x4d, /* eMSC, HDCP, HSIC */ 127 0x5d, /* MHL Spec */ 128 0x64, /* MHL CBUS */ 129 0x59, /* Hardware TPI (Transmitter Programming Interface) */ 130 0x61, /* eCBUS-S, eCBUS-D */ 131 }; 132 133 static void sii8620_fetch_edid(struct sii8620 *ctx); 134 static void sii8620_set_upstream_edid(struct sii8620 *ctx); 135 static void sii8620_enable_hpd(struct sii8620 *ctx); 136 static void sii8620_mhl_disconnected(struct sii8620 *ctx); 137 static void sii8620_disconnect(struct sii8620 *ctx); 138 139 static int sii8620_clear_error(struct sii8620 *ctx) 140 { 141 int ret = ctx->error; 142 143 ctx->error = 0; 144 return ret; 145 } 146 147 static void sii8620_read_buf(struct sii8620 *ctx, u16 addr, u8 *buf, int len) 148 { 149 struct device *dev = ctx->dev; 150 struct i2c_client *client = to_i2c_client(dev); 151 u8 data = addr; 152 struct i2c_msg msg[] = { 153 { 154 .addr = sii8620_i2c_page[addr >> 8], 155 .flags = client->flags, 156 .len = 1, 157 .buf = &data 158 }, 159 { 160 .addr = sii8620_i2c_page[addr >> 8], 161 .flags = client->flags | I2C_M_RD, 162 .len = len, 163 .buf = buf 164 }, 165 }; 166 int ret; 167 168 if (ctx->error) 169 return; 170 171 ret = i2c_transfer(client->adapter, msg, 2); 172 dev_dbg(dev, "read at %04x: %*ph, %d\n", addr, len, buf, ret); 173 174 if (ret != 2) { 175 dev_err(dev, "Read at %#06x of %d bytes failed with code %d.\n", 176 addr, len, ret); 177 ctx->error = ret < 0 ? ret : -EIO; 178 } 179 } 180 181 static u8 sii8620_readb(struct sii8620 *ctx, u16 addr) 182 { 183 u8 ret; 184 185 sii8620_read_buf(ctx, addr, &ret, 1); 186 return ret; 187 } 188 189 static void sii8620_write_buf(struct sii8620 *ctx, u16 addr, const u8 *buf, 190 int len) 191 { 192 struct device *dev = ctx->dev; 193 struct i2c_client *client = to_i2c_client(dev); 194 u8 data[2]; 195 struct i2c_msg msg = { 196 .addr = sii8620_i2c_page[addr >> 8], 197 .flags = client->flags, 198 .len = len + 1, 199 }; 200 int ret; 201 202 if (ctx->error) 203 return; 204 205 if (len > 1) { 206 msg.buf = kmalloc(len + 1, GFP_KERNEL); 207 if (!msg.buf) { 208 ctx->error = -ENOMEM; 209 return; 210 } 211 memcpy(msg.buf + 1, buf, len); 212 } else { 213 msg.buf = data; 214 msg.buf[1] = *buf; 215 } 216 217 msg.buf[0] = addr; 218 219 ret = i2c_transfer(client->adapter, &msg, 1); 220 dev_dbg(dev, "write at %04x: %*ph, %d\n", addr, len, buf, ret); 221 222 if (ret != 1) { 223 dev_err(dev, "Write at %#06x of %*ph failed with code %d.\n", 224 addr, len, buf, ret); 225 ctx->error = ret ?: -EIO; 226 } 227 228 if (len > 1) 229 kfree(msg.buf); 230 } 231 232 #define sii8620_write(ctx, addr, arr...) \ 233 ({\ 234 u8 d[] = { arr }; \ 235 sii8620_write_buf(ctx, addr, d, ARRAY_SIZE(d)); \ 236 }) 237 238 static void __sii8620_write_seq(struct sii8620 *ctx, const u16 *seq, int len) 239 { 240 int i; 241 242 for (i = 0; i < len; i += 2) 243 sii8620_write(ctx, seq[i], seq[i + 1]); 244 } 245 246 #define sii8620_write_seq(ctx, seq...) \ 247 ({\ 248 const u16 d[] = { seq }; \ 249 __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \ 250 }) 251 252 #define sii8620_write_seq_static(ctx, seq...) \ 253 ({\ 254 static const u16 d[] = { seq }; \ 255 __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \ 256 }) 257 258 static void sii8620_setbits(struct sii8620 *ctx, u16 addr, u8 mask, u8 val) 259 { 260 val = (val & mask) | (sii8620_readb(ctx, addr) & ~mask); 261 sii8620_write(ctx, addr, val); 262 } 263 264 static inline bool sii8620_is_mhl3(struct sii8620 *ctx) 265 { 266 return ctx->mode >= CM_MHL3; 267 } 268 269 static void sii8620_mt_cleanup(struct sii8620 *ctx) 270 { 271 struct sii8620_mt_msg *msg, *n; 272 273 list_for_each_entry_safe(msg, n, &ctx->mt_queue, node) { 274 list_del(&msg->node); 275 kfree(msg); 276 } 277 ctx->mt_state = MT_STATE_READY; 278 } 279 280 static void sii8620_mt_work(struct sii8620 *ctx) 281 { 282 struct sii8620_mt_msg *msg; 283 284 if (ctx->error) 285 return; 286 if (ctx->mt_state == MT_STATE_BUSY || list_empty(&ctx->mt_queue)) 287 return; 288 289 if (ctx->mt_state == MT_STATE_DONE) { 290 ctx->mt_state = MT_STATE_READY; 291 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, 292 node); 293 list_del(&msg->node); 294 if (msg->recv) 295 msg->recv(ctx, msg); 296 if (msg->continuation) 297 msg->continuation(ctx, msg->ret); 298 kfree(msg); 299 } 300 301 if (ctx->mt_state != MT_STATE_READY || list_empty(&ctx->mt_queue)) 302 return; 303 304 ctx->mt_state = MT_STATE_BUSY; 305 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 306 if (msg->send) 307 msg->send(ctx, msg); 308 } 309 310 static void sii8620_enable_gen2_write_burst(struct sii8620 *ctx) 311 { 312 u8 ctrl = BIT_MDT_RCV_CTRL_MDT_RCV_EN; 313 314 if (ctx->gen2_write_burst) 315 return; 316 317 if (ctx->mode >= CM_MHL1) 318 ctrl |= BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN; 319 320 sii8620_write_seq(ctx, 321 REG_MDT_RCV_TIMEOUT, 100, 322 REG_MDT_RCV_CTRL, ctrl 323 ); 324 ctx->gen2_write_burst = 1; 325 } 326 327 static void sii8620_disable_gen2_write_burst(struct sii8620 *ctx) 328 { 329 if (!ctx->gen2_write_burst) 330 return; 331 332 sii8620_write_seq_static(ctx, 333 REG_MDT_XMIT_CTRL, 0, 334 REG_MDT_RCV_CTRL, 0 335 ); 336 ctx->gen2_write_burst = 0; 337 } 338 339 static void sii8620_start_gen2_write_burst(struct sii8620 *ctx) 340 { 341 sii8620_write_seq_static(ctx, 342 REG_MDT_INT_1_MASK, BIT_MDT_RCV_TIMEOUT 343 | BIT_MDT_RCV_SM_ABORT_PKT_RCVD | BIT_MDT_RCV_SM_ERROR 344 | BIT_MDT_XMIT_TIMEOUT | BIT_MDT_XMIT_SM_ABORT_PKT_RCVD 345 | BIT_MDT_XMIT_SM_ERROR, 346 REG_MDT_INT_0_MASK, BIT_MDT_XFIFO_EMPTY 347 | BIT_MDT_IDLE_AFTER_HAWB_DISABLE 348 | BIT_MDT_RFIFO_DATA_RDY 349 ); 350 sii8620_enable_gen2_write_burst(ctx); 351 } 352 353 static void sii8620_mt_msc_cmd_send(struct sii8620 *ctx, 354 struct sii8620_mt_msg *msg) 355 { 356 if (msg->reg[0] == MHL_SET_INT && 357 msg->reg[1] == MHL_INT_REG(RCHANGE) && 358 msg->reg[2] == MHL_INT_RC_FEAT_REQ) 359 sii8620_enable_gen2_write_burst(ctx); 360 else 361 sii8620_disable_gen2_write_burst(ctx); 362 363 switch (msg->reg[0]) { 364 case MHL_WRITE_STAT: 365 case MHL_SET_INT: 366 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg + 1, 2); 367 sii8620_write(ctx, REG_MSC_COMMAND_START, 368 BIT_MSC_COMMAND_START_WRITE_STAT); 369 break; 370 case MHL_MSC_MSG: 371 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg, 3); 372 sii8620_write(ctx, REG_MSC_COMMAND_START, 373 BIT_MSC_COMMAND_START_MSC_MSG); 374 break; 375 case MHL_READ_DEVCAP_REG: 376 case MHL_READ_XDEVCAP_REG: 377 sii8620_write(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg[1]); 378 sii8620_write(ctx, REG_MSC_COMMAND_START, 379 BIT_MSC_COMMAND_START_READ_DEVCAP); 380 break; 381 default: 382 dev_err(ctx->dev, "%s: command %#x not supported\n", __func__, 383 msg->reg[0]); 384 } 385 } 386 387 static struct sii8620_mt_msg *sii8620_mt_msg_new(struct sii8620 *ctx) 388 { 389 struct sii8620_mt_msg *msg = kzalloc(sizeof(*msg), GFP_KERNEL); 390 391 if (!msg) 392 ctx->error = -ENOMEM; 393 else 394 list_add_tail(&msg->node, &ctx->mt_queue); 395 396 return msg; 397 } 398 399 static void sii8620_mt_set_cont(struct sii8620 *ctx, sii8620_cb cont) 400 { 401 struct sii8620_mt_msg *msg; 402 403 if (ctx->error) 404 return; 405 406 if (list_empty(&ctx->mt_queue)) { 407 ctx->error = -EINVAL; 408 return; 409 } 410 msg = list_last_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 411 msg->continuation = cont; 412 } 413 414 static void sii8620_mt_msc_cmd(struct sii8620 *ctx, u8 cmd, u8 arg1, u8 arg2) 415 { 416 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 417 418 if (!msg) 419 return; 420 421 msg->reg[0] = cmd; 422 msg->reg[1] = arg1; 423 msg->reg[2] = arg2; 424 msg->send = sii8620_mt_msc_cmd_send; 425 } 426 427 static void sii8620_mt_write_stat(struct sii8620 *ctx, u8 reg, u8 val) 428 { 429 sii8620_mt_msc_cmd(ctx, MHL_WRITE_STAT, reg, val); 430 } 431 432 static inline void sii8620_mt_set_int(struct sii8620 *ctx, u8 irq, u8 mask) 433 { 434 sii8620_mt_msc_cmd(ctx, MHL_SET_INT, irq, mask); 435 } 436 437 static void sii8620_mt_msc_msg(struct sii8620 *ctx, u8 cmd, u8 data) 438 { 439 sii8620_mt_msc_cmd(ctx, MHL_MSC_MSG, cmd, data); 440 } 441 442 static void sii8620_mt_rap(struct sii8620 *ctx, u8 code) 443 { 444 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RAP, code); 445 } 446 447 static void sii8620_mt_rcpk(struct sii8620 *ctx, u8 code) 448 { 449 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPK, code); 450 } 451 452 static void sii8620_mt_rcpe(struct sii8620 *ctx, u8 code) 453 { 454 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPE, code); 455 } 456 457 static void sii8620_mt_read_devcap_send(struct sii8620 *ctx, 458 struct sii8620_mt_msg *msg) 459 { 460 u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP 461 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 462 | BIT_EDID_CTRL_EDID_MODE_EN; 463 464 if (msg->reg[0] == MHL_READ_XDEVCAP) 465 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN; 466 467 sii8620_write_seq(ctx, 468 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE, 469 REG_EDID_CTRL, ctrl, 470 REG_TPI_CBUS_START, BIT_TPI_CBUS_START_GET_DEVCAP_START 471 ); 472 } 473 474 /* copy src to dst and set changed bits in src */ 475 static void sii8620_update_array(u8 *dst, u8 *src, int count) 476 { 477 while (--count >= 0) { 478 *src ^= *dst; 479 *dst++ ^= *src++; 480 } 481 } 482 483 static void sii8620_identify_sink(struct sii8620 *ctx) 484 { 485 static const char * const sink_str[] = { 486 [SINK_NONE] = "NONE", 487 [SINK_HDMI] = "HDMI", 488 [SINK_DVI] = "DVI" 489 }; 490 491 char sink_name[20]; 492 struct device *dev = ctx->dev; 493 494 if (!ctx->sink_detected || !ctx->devcap_read) 495 return; 496 497 sii8620_fetch_edid(ctx); 498 if (!ctx->edid) { 499 dev_err(ctx->dev, "Cannot fetch EDID\n"); 500 sii8620_mhl_disconnected(ctx); 501 return; 502 } 503 sii8620_set_upstream_edid(ctx); 504 505 if (drm_detect_hdmi_monitor(ctx->edid)) 506 ctx->sink_type = SINK_HDMI; 507 else 508 ctx->sink_type = SINK_DVI; 509 510 drm_edid_get_monitor_name(ctx->edid, sink_name, ARRAY_SIZE(sink_name)); 511 512 dev_info(dev, "detected sink(type: %s): %s\n", 513 sink_str[ctx->sink_type], sink_name); 514 } 515 516 static void sii8620_mr_devcap(struct sii8620 *ctx) 517 { 518 u8 dcap[MHL_DCAP_SIZE]; 519 struct device *dev = ctx->dev; 520 521 sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, dcap, MHL_DCAP_SIZE); 522 if (ctx->error < 0) 523 return; 524 525 dev_info(dev, "detected dongle MHL %d.%d, ChipID %02x%02x:%02x%02x\n", 526 dcap[MHL_DCAP_MHL_VERSION] / 16, 527 dcap[MHL_DCAP_MHL_VERSION] % 16, 528 dcap[MHL_DCAP_ADOPTER_ID_H], dcap[MHL_DCAP_ADOPTER_ID_L], 529 dcap[MHL_DCAP_DEVICE_ID_H], dcap[MHL_DCAP_DEVICE_ID_L]); 530 sii8620_update_array(ctx->devcap, dcap, MHL_DCAP_SIZE); 531 ctx->devcap_read = true; 532 sii8620_identify_sink(ctx); 533 } 534 535 static void sii8620_mr_xdevcap(struct sii8620 *ctx) 536 { 537 sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, ctx->xdevcap, 538 MHL_XDC_SIZE); 539 } 540 541 static void sii8620_mt_read_devcap_recv(struct sii8620 *ctx, 542 struct sii8620_mt_msg *msg) 543 { 544 u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP 545 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 546 | BIT_EDID_CTRL_EDID_MODE_EN; 547 548 if (msg->reg[0] == MHL_READ_XDEVCAP) 549 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN; 550 551 sii8620_write_seq(ctx, 552 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE | BIT_INTR9_EDID_DONE 553 | BIT_INTR9_EDID_ERROR, 554 REG_EDID_CTRL, ctrl, 555 REG_EDID_FIFO_ADDR, 0 556 ); 557 558 if (msg->reg[0] == MHL_READ_XDEVCAP) 559 sii8620_mr_xdevcap(ctx); 560 else 561 sii8620_mr_devcap(ctx); 562 } 563 564 static void sii8620_mt_read_devcap(struct sii8620 *ctx, bool xdevcap) 565 { 566 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 567 568 if (!msg) 569 return; 570 571 msg->reg[0] = xdevcap ? MHL_READ_XDEVCAP : MHL_READ_DEVCAP; 572 msg->send = sii8620_mt_read_devcap_send; 573 msg->recv = sii8620_mt_read_devcap_recv; 574 } 575 576 static void sii8620_mt_read_devcap_reg_recv(struct sii8620 *ctx, 577 struct sii8620_mt_msg *msg) 578 { 579 u8 reg = msg->reg[1] & 0x7f; 580 581 if (msg->reg[1] & 0x80) 582 ctx->xdevcap[reg] = msg->ret; 583 else 584 ctx->devcap[reg] = msg->ret; 585 } 586 587 static void sii8620_mt_read_devcap_reg(struct sii8620 *ctx, u8 reg) 588 { 589 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 590 591 if (!msg) 592 return; 593 594 msg->reg[0] = (reg & 0x80) ? MHL_READ_XDEVCAP_REG : MHL_READ_DEVCAP_REG; 595 msg->reg[1] = reg; 596 msg->send = sii8620_mt_msc_cmd_send; 597 msg->recv = sii8620_mt_read_devcap_reg_recv; 598 } 599 600 static inline void sii8620_mt_read_xdevcap_reg(struct sii8620 *ctx, u8 reg) 601 { 602 sii8620_mt_read_devcap_reg(ctx, reg | 0x80); 603 } 604 605 static void *sii8620_burst_get_tx_buf(struct sii8620 *ctx, int len) 606 { 607 u8 *buf = &ctx->burst.tx_buf[ctx->burst.tx_count]; 608 int size = len + 2; 609 610 if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) { 611 dev_err(ctx->dev, "TX-BLK buffer exhausted\n"); 612 ctx->error = -EINVAL; 613 return NULL; 614 } 615 616 ctx->burst.tx_count += size; 617 buf[1] = len; 618 619 return buf + 2; 620 } 621 622 static u8 *sii8620_burst_get_rx_buf(struct sii8620 *ctx, int len) 623 { 624 u8 *buf = &ctx->burst.rx_buf[ctx->burst.rx_count]; 625 int size = len + 1; 626 627 if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) { 628 dev_err(ctx->dev, "RX-BLK buffer exhausted\n"); 629 ctx->error = -EINVAL; 630 return NULL; 631 } 632 633 ctx->burst.rx_count += size; 634 buf[0] = len; 635 636 return buf + 1; 637 } 638 639 static void sii8620_burst_send(struct sii8620 *ctx) 640 { 641 int tx_left = ctx->burst.tx_count; 642 u8 *d = ctx->burst.tx_buf; 643 644 while (tx_left > 0) { 645 int len = d[1] + 2; 646 647 if (ctx->burst.r_count + len > ctx->burst.r_size) 648 break; 649 d[0] = min(ctx->burst.rx_ack, 255); 650 ctx->burst.rx_ack -= d[0]; 651 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, d, len); 652 ctx->burst.r_count += len; 653 tx_left -= len; 654 d += len; 655 } 656 657 ctx->burst.tx_count = tx_left; 658 659 while (ctx->burst.rx_ack > 0) { 660 u8 b[2] = { min(ctx->burst.rx_ack, 255), 0 }; 661 662 if (ctx->burst.r_count + 2 > ctx->burst.r_size) 663 break; 664 ctx->burst.rx_ack -= b[0]; 665 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, b, 2); 666 ctx->burst.r_count += 2; 667 } 668 } 669 670 static void sii8620_burst_receive(struct sii8620 *ctx) 671 { 672 u8 buf[3], *d; 673 int count; 674 675 sii8620_read_buf(ctx, REG_EMSCRFIFOBCNTL, buf, 2); 676 count = get_unaligned_le16(buf); 677 while (count > 0) { 678 int len = min(count, 3); 679 680 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, buf, len); 681 count -= len; 682 ctx->burst.rx_ack += len - 1; 683 ctx->burst.r_count -= buf[1]; 684 if (ctx->burst.r_count < 0) 685 ctx->burst.r_count = 0; 686 687 if (len < 3 || !buf[2]) 688 continue; 689 690 len = buf[2]; 691 d = sii8620_burst_get_rx_buf(ctx, len); 692 if (!d) 693 continue; 694 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, d, len); 695 count -= len; 696 ctx->burst.rx_ack += len; 697 } 698 } 699 700 static void sii8620_burst_tx_rbuf_info(struct sii8620 *ctx, int size) 701 { 702 struct mhl_burst_blk_rcv_buffer_info *d = 703 sii8620_burst_get_tx_buf(ctx, sizeof(*d)); 704 if (!d) 705 return; 706 707 d->id = cpu_to_be16(MHL_BURST_ID_BLK_RCV_BUFFER_INFO); 708 d->size = cpu_to_le16(size); 709 } 710 711 static u8 sii8620_checksum(void *ptr, int size) 712 { 713 u8 *d = ptr, sum = 0; 714 715 while (size--) 716 sum += *d++; 717 718 return sum; 719 } 720 721 static void sii8620_mhl_burst_hdr_set(struct mhl3_burst_header *h, 722 enum mhl_burst_id id) 723 { 724 h->id = cpu_to_be16(id); 725 h->total_entries = 1; 726 h->sequence_index = 1; 727 } 728 729 static void sii8620_burst_tx_bits_per_pixel_fmt(struct sii8620 *ctx, u8 fmt) 730 { 731 struct mhl_burst_bits_per_pixel_fmt *d; 732 const int size = sizeof(*d) + sizeof(d->desc[0]); 733 734 d = sii8620_burst_get_tx_buf(ctx, size); 735 if (!d) 736 return; 737 738 sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_BITS_PER_PIXEL_FMT); 739 d->num_entries = 1; 740 d->desc[0].stream_id = 0; 741 d->desc[0].pixel_format = fmt; 742 d->hdr.checksum -= sii8620_checksum(d, size); 743 } 744 745 static void sii8620_burst_rx_all(struct sii8620 *ctx) 746 { 747 u8 *d = ctx->burst.rx_buf; 748 int count = ctx->burst.rx_count; 749 750 while (count-- > 0) { 751 int len = *d++; 752 int id = get_unaligned_be16(&d[0]); 753 754 switch (id) { 755 case MHL_BURST_ID_BLK_RCV_BUFFER_INFO: 756 ctx->burst.r_size = get_unaligned_le16(&d[2]); 757 break; 758 default: 759 break; 760 } 761 count -= len; 762 d += len; 763 } 764 ctx->burst.rx_count = 0; 765 } 766 767 static void sii8620_fetch_edid(struct sii8620 *ctx) 768 { 769 u8 lm_ddc, ddc_cmd, int3, cbus; 770 unsigned long timeout; 771 int fetched, i; 772 int edid_len = EDID_LENGTH; 773 u8 *edid; 774 775 sii8620_readb(ctx, REG_CBUS_STATUS); 776 lm_ddc = sii8620_readb(ctx, REG_LM_DDC); 777 ddc_cmd = sii8620_readb(ctx, REG_DDC_CMD); 778 779 sii8620_write_seq(ctx, 780 REG_INTR9_MASK, 0, 781 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO, 782 REG_HDCP2X_POLL_CS, 0x71, 783 REG_HDCP2X_CTRL_0, BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX, 784 REG_LM_DDC, lm_ddc | BIT_LM_DDC_SW_TPI_EN_DISABLED, 785 ); 786 787 for (i = 0; i < 256; ++i) { 788 u8 ddc_stat = sii8620_readb(ctx, REG_DDC_STATUS); 789 790 if (!(ddc_stat & BIT_DDC_STATUS_DDC_I2C_IN_PROG)) 791 break; 792 sii8620_write(ctx, REG_DDC_STATUS, 793 BIT_DDC_STATUS_DDC_FIFO_EMPTY); 794 } 795 796 sii8620_write(ctx, REG_DDC_ADDR, 0x50 << 1); 797 798 edid = kmalloc(EDID_LENGTH, GFP_KERNEL); 799 if (!edid) { 800 ctx->error = -ENOMEM; 801 return; 802 } 803 804 #define FETCH_SIZE 16 805 for (fetched = 0; fetched < edid_len; fetched += FETCH_SIZE) { 806 sii8620_readb(ctx, REG_DDC_STATUS); 807 sii8620_write_seq(ctx, 808 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_ABORT, 809 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_CLEAR_FIFO, 810 REG_DDC_STATUS, BIT_DDC_STATUS_DDC_FIFO_EMPTY 811 ); 812 sii8620_write_seq(ctx, 813 REG_DDC_SEGM, fetched >> 8, 814 REG_DDC_OFFSET, fetched & 0xff, 815 REG_DDC_DIN_CNT1, FETCH_SIZE, 816 REG_DDC_DIN_CNT2, 0, 817 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_ENH_DDC_READ_NO_ACK 818 ); 819 820 int3 = 0; 821 timeout = jiffies + msecs_to_jiffies(200); 822 for (;;) { 823 cbus = sii8620_readb(ctx, REG_CBUS_STATUS); 824 if (~cbus & BIT_CBUS_STATUS_CBUS_CONNECTED) { 825 kfree(edid); 826 edid = NULL; 827 goto end; 828 } 829 if (int3 & BIT_DDC_CMD_DONE) { 830 if (sii8620_readb(ctx, REG_DDC_DOUT_CNT) 831 >= FETCH_SIZE) 832 break; 833 } else { 834 int3 = sii8620_readb(ctx, REG_INTR3); 835 } 836 if (time_is_before_jiffies(timeout)) { 837 ctx->error = -ETIMEDOUT; 838 dev_err(ctx->dev, "timeout during EDID read\n"); 839 kfree(edid); 840 edid = NULL; 841 goto end; 842 } 843 usleep_range(10, 20); 844 } 845 846 sii8620_read_buf(ctx, REG_DDC_DATA, edid + fetched, FETCH_SIZE); 847 if (fetched + FETCH_SIZE == EDID_LENGTH) { 848 u8 ext = ((struct edid *)edid)->extensions; 849 850 if (ext) { 851 u8 *new_edid; 852 853 edid_len += ext * EDID_LENGTH; 854 new_edid = krealloc(edid, edid_len, GFP_KERNEL); 855 if (!new_edid) { 856 kfree(edid); 857 ctx->error = -ENOMEM; 858 return; 859 } 860 edid = new_edid; 861 } 862 } 863 } 864 865 sii8620_write_seq(ctx, 866 REG_INTR3_MASK, BIT_DDC_CMD_DONE, 867 REG_LM_DDC, lm_ddc 868 ); 869 870 end: 871 kfree(ctx->edid); 872 ctx->edid = (struct edid *)edid; 873 } 874 875 static void sii8620_set_upstream_edid(struct sii8620 *ctx) 876 { 877 sii8620_setbits(ctx, REG_DPD, BIT_DPD_PDNRX12 | BIT_DPD_PDIDCK_N 878 | BIT_DPD_PD_MHL_CLK_N, 0xff); 879 880 sii8620_write_seq_static(ctx, 881 REG_RX_HDMI_CTRL3, 0x00, 882 REG_PKT_FILTER_0, 0xFF, 883 REG_PKT_FILTER_1, 0xFF, 884 REG_ALICE0_BW_I2C, 0x06 885 ); 886 887 sii8620_setbits(ctx, REG_RX_HDMI_CLR_BUFFER, 888 BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN, 0xff); 889 890 sii8620_write_seq_static(ctx, 891 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 892 | BIT_EDID_CTRL_EDID_MODE_EN, 893 REG_EDID_FIFO_ADDR, 0, 894 ); 895 896 sii8620_write_buf(ctx, REG_EDID_FIFO_WR_DATA, (u8 *)ctx->edid, 897 (ctx->edid->extensions + 1) * EDID_LENGTH); 898 899 sii8620_write_seq_static(ctx, 900 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID 901 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 902 | BIT_EDID_CTRL_EDID_MODE_EN, 903 REG_INTR5_MASK, BIT_INTR_SCDT_CHANGE, 904 REG_INTR9_MASK, 0 905 ); 906 } 907 908 static void sii8620_xtal_set_rate(struct sii8620 *ctx) 909 { 910 static const struct { 911 unsigned int rate; 912 u8 div; 913 u8 tp1; 914 } rates[] = { 915 { 19200, 0x04, 0x53 }, 916 { 20000, 0x04, 0x62 }, 917 { 24000, 0x05, 0x75 }, 918 { 30000, 0x06, 0x92 }, 919 { 38400, 0x0c, 0xbc }, 920 }; 921 unsigned long rate = clk_get_rate(ctx->clk_xtal) / 1000; 922 int i; 923 924 for (i = 0; i < ARRAY_SIZE(rates) - 1; ++i) 925 if (rate <= rates[i].rate) 926 break; 927 928 if (rate != rates[i].rate) 929 dev_err(ctx->dev, "xtal clock rate(%lukHz) not supported, setting MHL for %ukHz.\n", 930 rate, rates[i].rate); 931 932 sii8620_write(ctx, REG_DIV_CTL_MAIN, rates[i].div); 933 sii8620_write(ctx, REG_HDCP2X_TP1, rates[i].tp1); 934 } 935 936 static int sii8620_hw_on(struct sii8620 *ctx) 937 { 938 int ret; 939 940 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 941 if (ret) 942 return ret; 943 944 usleep_range(10000, 20000); 945 ret = clk_prepare_enable(ctx->clk_xtal); 946 if (ret) 947 return ret; 948 949 msleep(100); 950 gpiod_set_value(ctx->gpio_reset, 0); 951 msleep(100); 952 953 return 0; 954 } 955 956 static int sii8620_hw_off(struct sii8620 *ctx) 957 { 958 clk_disable_unprepare(ctx->clk_xtal); 959 gpiod_set_value(ctx->gpio_reset, 1); 960 return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 961 } 962 963 static void sii8620_cbus_reset(struct sii8620 *ctx) 964 { 965 sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST 966 | BIT_PWD_SRST_CBUS_RST_SW_EN); 967 usleep_range(10000, 20000); 968 sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN); 969 } 970 971 static void sii8620_set_auto_zone(struct sii8620 *ctx) 972 { 973 if (ctx->mode != CM_MHL1) { 974 sii8620_write_seq_static(ctx, 975 REG_TX_ZONE_CTL1, 0x0, 976 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 977 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 978 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE 979 ); 980 } else { 981 sii8620_write_seq_static(ctx, 982 REG_TX_ZONE_CTL1, VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE, 983 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 984 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE 985 ); 986 } 987 } 988 989 static void sii8620_stop_video(struct sii8620 *ctx) 990 { 991 u8 uninitialized_var(val); 992 993 sii8620_write_seq_static(ctx, 994 REG_TPI_INTR_EN, 0, 995 REG_HDCP2X_INTR0_MASK, 0, 996 REG_TPI_COPP_DATA2, 0, 997 REG_TPI_INTR_ST0, ~0, 998 ); 999 1000 switch (ctx->sink_type) { 1001 case SINK_DVI: 1002 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN 1003 | BIT_TPI_SC_TPI_AV_MUTE; 1004 break; 1005 case SINK_HDMI: 1006 default: 1007 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN 1008 | BIT_TPI_SC_TPI_AV_MUTE 1009 | BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI; 1010 break; 1011 } 1012 1013 sii8620_write(ctx, REG_TPI_SC, val); 1014 } 1015 1016 static void sii8620_set_format(struct sii8620 *ctx) 1017 { 1018 if (sii8620_is_mhl3(ctx)) { 1019 sii8620_setbits(ctx, REG_M3_P0CTRL, 1020 BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED, 1021 ctx->use_packed_pixel ? ~0 : 0); 1022 } else { 1023 sii8620_write_seq_static(ctx, 1024 REG_VID_MODE, 0, 1025 REG_MHL_TOP_CTL, 1, 1026 REG_MHLTX_CTL6, 0xa0 1027 ); 1028 } 1029 1030 sii8620_write_seq(ctx, 1031 REG_TPI_INPUT, VAL_TPI_FORMAT(RGB, FULL), 1032 REG_TPI_OUTPUT, VAL_TPI_FORMAT(RGB, FULL), 1033 ); 1034 } 1035 1036 static int mhl3_infoframe_init(struct mhl3_infoframe *frame) 1037 { 1038 memset(frame, 0, sizeof(*frame)); 1039 1040 frame->version = 3; 1041 frame->hev_format = -1; 1042 return 0; 1043 } 1044 1045 static ssize_t mhl3_infoframe_pack(struct mhl3_infoframe *frame, 1046 void *buffer, size_t size) 1047 { 1048 const int frm_len = HDMI_INFOFRAME_HEADER_SIZE + MHL3_INFOFRAME_SIZE; 1049 u8 *ptr = buffer; 1050 1051 if (size < frm_len) 1052 return -ENOSPC; 1053 1054 memset(buffer, 0, size); 1055 ptr[0] = HDMI_INFOFRAME_TYPE_VENDOR; 1056 ptr[1] = frame->version; 1057 ptr[2] = MHL3_INFOFRAME_SIZE; 1058 ptr[4] = MHL3_IEEE_OUI & 0xff; 1059 ptr[5] = (MHL3_IEEE_OUI >> 8) & 0xff; 1060 ptr[6] = (MHL3_IEEE_OUI >> 16) & 0xff; 1061 ptr[7] = frame->video_format & 0x3; 1062 ptr[7] |= (frame->format_type & 0x7) << 2; 1063 ptr[7] |= frame->sep_audio ? BIT(5) : 0; 1064 if (frame->hev_format >= 0) { 1065 ptr[9] = 1; 1066 ptr[10] = (frame->hev_format >> 8) & 0xff; 1067 ptr[11] = frame->hev_format & 0xff; 1068 } 1069 if (frame->av_delay) { 1070 bool sign = frame->av_delay < 0; 1071 int delay = sign ? -frame->av_delay : frame->av_delay; 1072 1073 ptr[12] = (delay >> 16) & 0xf; 1074 if (sign) 1075 ptr[12] |= BIT(4); 1076 ptr[13] = (delay >> 8) & 0xff; 1077 ptr[14] = delay & 0xff; 1078 } 1079 ptr[3] -= sii8620_checksum(buffer, frm_len); 1080 return frm_len; 1081 } 1082 1083 static void sii8620_set_infoframes(struct sii8620 *ctx, 1084 struct drm_display_mode *mode) 1085 { 1086 struct mhl3_infoframe mhl_frm; 1087 union hdmi_infoframe frm; 1088 u8 buf[31]; 1089 int ret; 1090 1091 ret = drm_hdmi_avi_infoframe_from_display_mode(&frm.avi, 1092 mode, 1093 true); 1094 if (ctx->use_packed_pixel) 1095 frm.avi.colorspace = HDMI_COLORSPACE_YUV422; 1096 1097 if (!ret) 1098 ret = hdmi_avi_infoframe_pack(&frm.avi, buf, ARRAY_SIZE(buf)); 1099 if (ret > 0) 1100 sii8620_write_buf(ctx, REG_TPI_AVI_CHSUM, buf + 3, ret - 3); 1101 1102 if (!sii8620_is_mhl3(ctx) || !ctx->use_packed_pixel) { 1103 sii8620_write(ctx, REG_TPI_SC, 1104 BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI); 1105 sii8620_write(ctx, REG_PKT_FILTER_0, 1106 BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT | 1107 BIT_PKT_FILTER_0_DROP_MPEG_PKT | 1108 BIT_PKT_FILTER_0_DROP_GCP_PKT, 1109 BIT_PKT_FILTER_1_DROP_GEN_PKT); 1110 return; 1111 } 1112 1113 sii8620_write(ctx, REG_PKT_FILTER_0, 1114 BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT | 1115 BIT_PKT_FILTER_0_DROP_MPEG_PKT | 1116 BIT_PKT_FILTER_0_DROP_AVI_PKT | 1117 BIT_PKT_FILTER_0_DROP_GCP_PKT, 1118 BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS | 1119 BIT_PKT_FILTER_1_DROP_GEN_PKT | 1120 BIT_PKT_FILTER_1_DROP_VSIF_PKT); 1121 1122 sii8620_write(ctx, REG_TPI_INFO_FSEL, BIT_TPI_INFO_FSEL_EN 1123 | BIT_TPI_INFO_FSEL_RPT | VAL_TPI_INFO_FSEL_VSI); 1124 ret = mhl3_infoframe_init(&mhl_frm); 1125 if (!ret) 1126 ret = mhl3_infoframe_pack(&mhl_frm, buf, ARRAY_SIZE(buf)); 1127 sii8620_write_buf(ctx, REG_TPI_INFO_B0, buf, ret); 1128 } 1129 1130 static void sii8620_start_video(struct sii8620 *ctx) 1131 { 1132 struct drm_display_mode *mode = 1133 &ctx->bridge.encoder->crtc->state->adjusted_mode; 1134 1135 if (!sii8620_is_mhl3(ctx)) 1136 sii8620_stop_video(ctx); 1137 1138 if (ctx->sink_type == SINK_DVI && !sii8620_is_mhl3(ctx)) { 1139 sii8620_write(ctx, REG_RX_HDMI_CTRL2, 1140 VAL_RX_HDMI_CTRL2_DEFVAL); 1141 sii8620_write(ctx, REG_TPI_SC, 0); 1142 return; 1143 } 1144 1145 sii8620_write_seq_static(ctx, 1146 REG_RX_HDMI_CTRL2, VAL_RX_HDMI_CTRL2_DEFVAL 1147 | BIT_RX_HDMI_CTRL2_USE_AV_MUTE, 1148 REG_VID_OVRRD, BIT_VID_OVRRD_PP_AUTO_DISABLE 1149 | BIT_VID_OVRRD_M1080P_OVRRD); 1150 sii8620_set_format(ctx); 1151 1152 if (!sii8620_is_mhl3(ctx)) { 1153 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE), 1154 MHL_DST_LM_CLK_MODE_NORMAL | MHL_DST_LM_PATH_ENABLED); 1155 sii8620_set_auto_zone(ctx); 1156 } else { 1157 static const struct { 1158 int max_clk; 1159 u8 zone; 1160 u8 link_rate; 1161 u8 rrp_decode; 1162 } clk_spec[] = { 1163 { 150000, VAL_TX_ZONE_CTL3_TX_ZONE_1_5GBPS, 1164 MHL_XDS_LINK_RATE_1_5_GBPS, 0x38 }, 1165 { 300000, VAL_TX_ZONE_CTL3_TX_ZONE_3GBPS, 1166 MHL_XDS_LINK_RATE_3_0_GBPS, 0x40 }, 1167 { 600000, VAL_TX_ZONE_CTL3_TX_ZONE_6GBPS, 1168 MHL_XDS_LINK_RATE_6_0_GBPS, 0x40 }, 1169 }; 1170 u8 p0_ctrl = BIT_M3_P0CTRL_MHL3_P0_PORT_EN; 1171 int clk = mode->clock * (ctx->use_packed_pixel ? 2 : 3); 1172 int i; 1173 1174 for (i = 0; i < ARRAY_SIZE(clk_spec) - 1; ++i) 1175 if (clk < clk_spec[i].max_clk) 1176 break; 1177 1178 if (100 * clk >= 98 * clk_spec[i].max_clk) 1179 p0_ctrl |= BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN; 1180 1181 sii8620_burst_tx_bits_per_pixel_fmt(ctx, ctx->use_packed_pixel); 1182 sii8620_burst_send(ctx); 1183 sii8620_write_seq(ctx, 1184 REG_MHL_DP_CTL0, 0xf0, 1185 REG_MHL3_TX_ZONE_CTL, clk_spec[i].zone); 1186 sii8620_setbits(ctx, REG_M3_P0CTRL, 1187 BIT_M3_P0CTRL_MHL3_P0_PORT_EN 1188 | BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN, p0_ctrl); 1189 sii8620_setbits(ctx, REG_M3_POSTM, MSK_M3_POSTM_RRP_DECODE, 1190 clk_spec[i].rrp_decode); 1191 sii8620_write_seq_static(ctx, 1192 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE 1193 | BIT_M3_CTRL_H2M_SWRST, 1194 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE 1195 ); 1196 sii8620_mt_write_stat(ctx, MHL_XDS_REG(AVLINK_MODE_CONTROL), 1197 clk_spec[i].link_rate); 1198 } 1199 1200 sii8620_set_infoframes(ctx, mode); 1201 } 1202 1203 static void sii8620_disable_hpd(struct sii8620 *ctx) 1204 { 1205 sii8620_setbits(ctx, REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID, 0); 1206 sii8620_write_seq_static(ctx, 1207 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN, 1208 REG_INTR8_MASK, 0 1209 ); 1210 } 1211 1212 static void sii8620_enable_hpd(struct sii8620 *ctx) 1213 { 1214 sii8620_setbits(ctx, REG_TMDS_CSTAT_P3, 1215 BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS 1216 | BIT_TMDS_CSTAT_P3_CLR_AVI, ~0); 1217 sii8620_write_seq_static(ctx, 1218 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN 1219 | BIT_HPD_CTRL_HPD_HIGH, 1220 ); 1221 } 1222 1223 static void sii8620_mhl_discover(struct sii8620 *ctx) 1224 { 1225 sii8620_write_seq_static(ctx, 1226 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1227 | BIT_DISC_CTRL9_DISC_PULSE_PROCEED, 1228 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_5K, VAL_PUP_20K), 1229 REG_CBUS_DISC_INTR0_MASK, BIT_MHL3_EST_INT 1230 | BIT_MHL_EST_INT 1231 | BIT_NOT_MHL_EST_INT 1232 | BIT_CBUS_MHL3_DISCON_INT 1233 | BIT_CBUS_MHL12_DISCON_INT 1234 | BIT_RGND_READY_INT, 1235 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 1236 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 1237 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE, 1238 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE 1239 | BIT_MHL_DP_CTL0_TX_OE_OVR, 1240 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE, 1241 REG_MHL_DP_CTL1, 0xA2, 1242 REG_MHL_DP_CTL2, 0x03, 1243 REG_MHL_DP_CTL3, 0x35, 1244 REG_MHL_DP_CTL5, 0x02, 1245 REG_MHL_DP_CTL6, 0x02, 1246 REG_MHL_DP_CTL7, 0x03, 1247 REG_COC_CTLC, 0xFF, 1248 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 1249 | BIT_DPD_OSC_EN | BIT_DPD_PWRON_HSIC, 1250 REG_COC_INTR_MASK, BIT_COC_PLL_LOCK_STATUS_CHANGE 1251 | BIT_COC_CALIBRATION_DONE, 1252 REG_CBUS_INT_1_MASK, BIT_CBUS_MSC_ABORT_RCVD 1253 | BIT_CBUS_CMD_ABORT, 1254 REG_CBUS_INT_0_MASK, BIT_CBUS_MSC_MT_DONE 1255 | BIT_CBUS_HPD_CHG 1256 | BIT_CBUS_MSC_MR_WRITE_STAT 1257 | BIT_CBUS_MSC_MR_MSC_MSG 1258 | BIT_CBUS_MSC_MR_WRITE_BURST 1259 | BIT_CBUS_MSC_MR_SET_INT 1260 | BIT_CBUS_MSC_MT_DONE_NACK 1261 ); 1262 } 1263 1264 static void sii8620_peer_specific_init(struct sii8620 *ctx) 1265 { 1266 if (sii8620_is_mhl3(ctx)) 1267 sii8620_write_seq_static(ctx, 1268 REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD, 1269 REG_EMSCINTRMASK1, 1270 BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR 1271 ); 1272 else 1273 sii8620_write_seq_static(ctx, 1274 REG_HDCP2X_INTR0_MASK, 0x00, 1275 REG_EMSCINTRMASK1, 0x00, 1276 REG_HDCP2X_INTR0, 0xFF, 1277 REG_INTR1, 0xFF, 1278 REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD 1279 | BIT_SYS_CTRL1_TX_CTRL_HDMI 1280 ); 1281 } 1282 1283 #define SII8620_MHL_VERSION 0x32 1284 #define SII8620_SCRATCHPAD_SIZE 16 1285 #define SII8620_INT_STAT_SIZE 0x33 1286 1287 static void sii8620_set_dev_cap(struct sii8620 *ctx) 1288 { 1289 static const u8 devcap[MHL_DCAP_SIZE] = { 1290 [MHL_DCAP_MHL_VERSION] = SII8620_MHL_VERSION, 1291 [MHL_DCAP_CAT] = MHL_DCAP_CAT_SOURCE | MHL_DCAP_CAT_POWER, 1292 [MHL_DCAP_ADOPTER_ID_H] = 0x01, 1293 [MHL_DCAP_ADOPTER_ID_L] = 0x41, 1294 [MHL_DCAP_VID_LINK_MODE] = MHL_DCAP_VID_LINK_RGB444 1295 | MHL_DCAP_VID_LINK_PPIXEL 1296 | MHL_DCAP_VID_LINK_16BPP, 1297 [MHL_DCAP_AUD_LINK_MODE] = MHL_DCAP_AUD_LINK_2CH, 1298 [MHL_DCAP_VIDEO_TYPE] = MHL_DCAP_VT_GRAPHICS, 1299 [MHL_DCAP_LOG_DEV_MAP] = MHL_DCAP_LD_GUI, 1300 [MHL_DCAP_BANDWIDTH] = 0x0f, 1301 [MHL_DCAP_FEATURE_FLAG] = MHL_DCAP_FEATURE_RCP_SUPPORT 1302 | MHL_DCAP_FEATURE_RAP_SUPPORT 1303 | MHL_DCAP_FEATURE_SP_SUPPORT, 1304 [MHL_DCAP_SCRATCHPAD_SIZE] = SII8620_SCRATCHPAD_SIZE, 1305 [MHL_DCAP_INT_STAT_SIZE] = SII8620_INT_STAT_SIZE, 1306 }; 1307 static const u8 xdcap[MHL_XDC_SIZE] = { 1308 [MHL_XDC_ECBUS_SPEEDS] = MHL_XDC_ECBUS_S_075 1309 | MHL_XDC_ECBUS_S_8BIT, 1310 [MHL_XDC_TMDS_SPEEDS] = MHL_XDC_TMDS_150 1311 | MHL_XDC_TMDS_300 | MHL_XDC_TMDS_600, 1312 [MHL_XDC_ECBUS_ROLES] = MHL_XDC_DEV_HOST, 1313 [MHL_XDC_LOG_DEV_MAPX] = MHL_XDC_LD_PHONE, 1314 }; 1315 1316 sii8620_write_buf(ctx, REG_MHL_DEVCAP_0, devcap, ARRAY_SIZE(devcap)); 1317 sii8620_write_buf(ctx, REG_MHL_EXTDEVCAP_0, xdcap, ARRAY_SIZE(xdcap)); 1318 } 1319 1320 static void sii8620_mhl_init(struct sii8620 *ctx) 1321 { 1322 sii8620_write_seq_static(ctx, 1323 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1324 REG_CBUS_MSC_COMPAT_CTRL, 1325 BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN, 1326 ); 1327 1328 sii8620_peer_specific_init(ctx); 1329 1330 sii8620_disable_hpd(ctx); 1331 1332 sii8620_write_seq_static(ctx, 1333 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO, 1334 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1335 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1336 REG_TMDS0_CCTRL1, 0x90, 1337 REG_TMDS_CLK_EN, 0x01, 1338 REG_TMDS_CH_EN, 0x11, 1339 REG_BGR_BIAS, 0x87, 1340 REG_ALICE0_ZONE_CTRL, 0xE8, 1341 REG_ALICE0_MODE_CTRL, 0x04, 1342 ); 1343 sii8620_setbits(ctx, REG_LM_DDC, BIT_LM_DDC_SW_TPI_EN_DISABLED, 0); 1344 sii8620_write_seq_static(ctx, 1345 REG_TPI_HW_OPT3, 0x76, 1346 REG_TMDS_CCTRL, BIT_TMDS_CCTRL_TMDS_OE, 1347 REG_TPI_DTD_B2, 79, 1348 ); 1349 sii8620_set_dev_cap(ctx); 1350 sii8620_write_seq_static(ctx, 1351 REG_MDT_XMIT_TIMEOUT, 100, 1352 REG_MDT_XMIT_CTRL, 0x03, 1353 REG_MDT_XFIFO_STAT, 0x00, 1354 REG_MDT_RCV_TIMEOUT, 100, 1355 REG_CBUS_LINK_CTRL_8, 0x1D, 1356 ); 1357 1358 sii8620_start_gen2_write_burst(ctx); 1359 sii8620_write_seq_static(ctx, 1360 REG_BIST_CTRL, 0x00, 1361 REG_COC_CTL1, 0x10, 1362 REG_COC_CTL2, 0x18, 1363 REG_COC_CTLF, 0x07, 1364 REG_COC_CTL11, 0xF8, 1365 REG_COC_CTL17, 0x61, 1366 REG_COC_CTL18, 0x46, 1367 REG_COC_CTL19, 0x15, 1368 REG_COC_CTL1A, 0x01, 1369 REG_MHL_COC_CTL3, BIT_MHL_COC_CTL3_COC_AECHO_EN, 1370 REG_MHL_COC_CTL4, 0x2D, 1371 REG_MHL_COC_CTL5, 0xF9, 1372 REG_MSC_HEARTBEAT_CTRL, 0x27, 1373 ); 1374 sii8620_disable_gen2_write_burst(ctx); 1375 1376 sii8620_mt_write_stat(ctx, MHL_DST_REG(VERSION), SII8620_MHL_VERSION); 1377 sii8620_mt_write_stat(ctx, MHL_DST_REG(CONNECTED_RDY), 1378 MHL_DST_CONN_DCAP_RDY | MHL_DST_CONN_XDEVCAPP_SUPP 1379 | MHL_DST_CONN_POW_STAT); 1380 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), MHL_INT_RC_DCAP_CHG); 1381 } 1382 1383 static void sii8620_emsc_enable(struct sii8620 *ctx) 1384 { 1385 u8 reg; 1386 1387 sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_EMSC_EN 1388 | BIT_GENCTL_CLR_EMSC_RFIFO 1389 | BIT_GENCTL_CLR_EMSC_XFIFO, ~0); 1390 sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_CLR_EMSC_RFIFO 1391 | BIT_GENCTL_CLR_EMSC_XFIFO, 0); 1392 sii8620_setbits(ctx, REG_COMMECNT, BIT_COMMECNT_I2C_TO_EMSC_EN, ~0); 1393 reg = sii8620_readb(ctx, REG_EMSCINTR); 1394 sii8620_write(ctx, REG_EMSCINTR, reg); 1395 sii8620_write(ctx, REG_EMSCINTRMASK, BIT_EMSCINTR_SPI_DVLD); 1396 } 1397 1398 static int sii8620_wait_for_fsm_state(struct sii8620 *ctx, u8 state) 1399 { 1400 int i; 1401 1402 for (i = 0; i < 10; ++i) { 1403 u8 s = sii8620_readb(ctx, REG_COC_STAT_0); 1404 1405 if ((s & MSK_COC_STAT_0_FSM_STATE) == state) 1406 return 0; 1407 if (!(s & BIT_COC_STAT_0_PLL_LOCKED)) 1408 return -EBUSY; 1409 usleep_range(4000, 6000); 1410 } 1411 return -ETIMEDOUT; 1412 } 1413 1414 static void sii8620_set_mode(struct sii8620 *ctx, enum sii8620_mode mode) 1415 { 1416 int ret; 1417 1418 if (ctx->mode == mode) 1419 return; 1420 1421 switch (mode) { 1422 case CM_MHL1: 1423 sii8620_write_seq_static(ctx, 1424 REG_CBUS_MSC_COMPAT_CTRL, 0x02, 1425 REG_M3_CTRL, VAL_M3_CTRL_MHL1_2_VALUE, 1426 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 1427 | BIT_DPD_OSC_EN, 1428 REG_COC_INTR_MASK, 0 1429 ); 1430 ctx->mode = mode; 1431 break; 1432 case CM_MHL3: 1433 sii8620_write(ctx, REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE); 1434 ctx->mode = mode; 1435 return; 1436 case CM_ECBUS_S: 1437 sii8620_emsc_enable(ctx); 1438 sii8620_write_seq_static(ctx, 1439 REG_TTXSPINUMS, 4, 1440 REG_TRXSPINUMS, 4, 1441 REG_TTXHSICNUMS, 0x14, 1442 REG_TRXHSICNUMS, 0x14, 1443 REG_TTXTOTNUMS, 0x18, 1444 REG_TRXTOTNUMS, 0x18, 1445 REG_PWD_SRST, BIT_PWD_SRST_COC_DOC_RST 1446 | BIT_PWD_SRST_CBUS_RST_SW_EN, 1447 REG_MHL_COC_CTL1, 0xbd, 1448 REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN, 1449 REG_COC_CTLB, 0x01, 1450 REG_COC_CTL0, 0x5c, 1451 REG_COC_CTL14, 0x03, 1452 REG_COC_CTL15, 0x80, 1453 REG_MHL_DP_CTL6, BIT_MHL_DP_CTL6_DP_TAP1_SGN 1454 | BIT_MHL_DP_CTL6_DP_TAP1_EN 1455 | BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN, 1456 REG_MHL_DP_CTL8, 0x03 1457 ); 1458 ret = sii8620_wait_for_fsm_state(ctx, 0x03); 1459 sii8620_write_seq_static(ctx, 1460 REG_COC_CTL14, 0x00, 1461 REG_COC_CTL15, 0x80 1462 ); 1463 if (!ret) 1464 sii8620_write(ctx, REG_CBUS3_CNVT, 0x85); 1465 else 1466 sii8620_disconnect(ctx); 1467 return; 1468 case CM_DISCONNECTED: 1469 ctx->mode = mode; 1470 break; 1471 default: 1472 dev_err(ctx->dev, "%s mode %d not supported\n", __func__, mode); 1473 break; 1474 } 1475 1476 sii8620_set_auto_zone(ctx); 1477 1478 if (mode != CM_MHL1) 1479 return; 1480 1481 sii8620_write_seq_static(ctx, 1482 REG_MHL_DP_CTL0, 0xBC, 1483 REG_MHL_DP_CTL1, 0xBB, 1484 REG_MHL_DP_CTL3, 0x48, 1485 REG_MHL_DP_CTL5, 0x39, 1486 REG_MHL_DP_CTL2, 0x2A, 1487 REG_MHL_DP_CTL6, 0x2A, 1488 REG_MHL_DP_CTL7, 0x08 1489 ); 1490 } 1491 1492 static void sii8620_hpd_unplugged(struct sii8620 *ctx) 1493 { 1494 sii8620_disable_hpd(ctx); 1495 ctx->sink_type = SINK_NONE; 1496 ctx->sink_detected = false; 1497 ctx->feature_complete = false; 1498 kfree(ctx->edid); 1499 ctx->edid = NULL; 1500 } 1501 1502 static void sii8620_disconnect(struct sii8620 *ctx) 1503 { 1504 sii8620_disable_gen2_write_burst(ctx); 1505 sii8620_stop_video(ctx); 1506 msleep(100); 1507 sii8620_cbus_reset(ctx); 1508 sii8620_set_mode(ctx, CM_DISCONNECTED); 1509 sii8620_write_seq_static(ctx, 1510 REG_TX_ZONE_CTL1, 0, 1511 REG_MHL_PLL_CTL0, 0x07, 1512 REG_COC_CTL0, 0x40, 1513 REG_CBUS3_CNVT, 0x84, 1514 REG_COC_CTL14, 0x00, 1515 REG_COC_CTL0, 0x40, 1516 REG_HRXCTRL3, 0x07, 1517 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 1518 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 1519 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE, 1520 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE 1521 | BIT_MHL_DP_CTL0_TX_OE_OVR, 1522 REG_MHL_DP_CTL1, 0xBB, 1523 REG_MHL_DP_CTL3, 0x48, 1524 REG_MHL_DP_CTL5, 0x3F, 1525 REG_MHL_DP_CTL2, 0x2F, 1526 REG_MHL_DP_CTL6, 0x2A, 1527 REG_MHL_DP_CTL7, 0x03 1528 ); 1529 sii8620_hpd_unplugged(ctx); 1530 sii8620_write_seq_static(ctx, 1531 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE, 1532 REG_MHL_COC_CTL1, 0x07, 1533 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1534 REG_DISC_CTRL8, 0x00, 1535 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1536 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1537 REG_INT_CTRL, 0x00, 1538 REG_MSC_HEARTBEAT_CTRL, 0x27, 1539 REG_DISC_CTRL1, 0x25, 1540 REG_CBUS_DISC_INTR0, (u8)~BIT_RGND_READY_INT, 1541 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT, 1542 REG_MDT_INT_1, 0xff, 1543 REG_MDT_INT_1_MASK, 0x00, 1544 REG_MDT_INT_0, 0xff, 1545 REG_MDT_INT_0_MASK, 0x00, 1546 REG_COC_INTR, 0xff, 1547 REG_COC_INTR_MASK, 0x00, 1548 REG_TRXINTH, 0xff, 1549 REG_TRXINTMH, 0x00, 1550 REG_CBUS_INT_0, 0xff, 1551 REG_CBUS_INT_0_MASK, 0x00, 1552 REG_CBUS_INT_1, 0xff, 1553 REG_CBUS_INT_1_MASK, 0x00, 1554 REG_EMSCINTR, 0xff, 1555 REG_EMSCINTRMASK, 0x00, 1556 REG_EMSCINTR1, 0xff, 1557 REG_EMSCINTRMASK1, 0x00, 1558 REG_INTR8, 0xff, 1559 REG_INTR8_MASK, 0x00, 1560 REG_TPI_INTR_ST0, 0xff, 1561 REG_TPI_INTR_EN, 0x00, 1562 REG_HDCP2X_INTR0, 0xff, 1563 REG_HDCP2X_INTR0_MASK, 0x00, 1564 REG_INTR9, 0xff, 1565 REG_INTR9_MASK, 0x00, 1566 REG_INTR3, 0xff, 1567 REG_INTR3_MASK, 0x00, 1568 REG_INTR5, 0xff, 1569 REG_INTR5_MASK, 0x00, 1570 REG_INTR2, 0xff, 1571 REG_INTR2_MASK, 0x00, 1572 ); 1573 memset(ctx->stat, 0, sizeof(ctx->stat)); 1574 memset(ctx->xstat, 0, sizeof(ctx->xstat)); 1575 memset(ctx->devcap, 0, sizeof(ctx->devcap)); 1576 memset(ctx->xdevcap, 0, sizeof(ctx->xdevcap)); 1577 ctx->devcap_read = false; 1578 ctx->cbus_status = 0; 1579 sii8620_mt_cleanup(ctx); 1580 } 1581 1582 static void sii8620_mhl_disconnected(struct sii8620 *ctx) 1583 { 1584 sii8620_write_seq_static(ctx, 1585 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1586 REG_CBUS_MSC_COMPAT_CTRL, 1587 BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN 1588 ); 1589 sii8620_disconnect(ctx); 1590 } 1591 1592 static void sii8620_irq_disc(struct sii8620 *ctx) 1593 { 1594 u8 stat = sii8620_readb(ctx, REG_CBUS_DISC_INTR0); 1595 1596 if (stat & VAL_CBUS_MHL_DISCON) 1597 sii8620_mhl_disconnected(ctx); 1598 1599 if (stat & BIT_RGND_READY_INT) { 1600 u8 stat2 = sii8620_readb(ctx, REG_DISC_STAT2); 1601 1602 if ((stat2 & MSK_DISC_STAT2_RGND) == VAL_RGND_1K) { 1603 sii8620_mhl_discover(ctx); 1604 } else { 1605 sii8620_write_seq_static(ctx, 1606 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1607 | BIT_DISC_CTRL9_NOMHL_EST 1608 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1609 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT 1610 | BIT_CBUS_MHL3_DISCON_INT 1611 | BIT_CBUS_MHL12_DISCON_INT 1612 | BIT_NOT_MHL_EST_INT 1613 ); 1614 } 1615 } 1616 if (stat & BIT_MHL_EST_INT) 1617 sii8620_mhl_init(ctx); 1618 1619 sii8620_write(ctx, REG_CBUS_DISC_INTR0, stat); 1620 } 1621 1622 static void sii8620_read_burst(struct sii8620 *ctx) 1623 { 1624 u8 buf[17]; 1625 1626 sii8620_read_buf(ctx, REG_MDT_RCV_READ_PORT, buf, ARRAY_SIZE(buf)); 1627 sii8620_write(ctx, REG_MDT_RCV_CTRL, BIT_MDT_RCV_CTRL_MDT_RCV_EN | 1628 BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN | 1629 BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR); 1630 sii8620_readb(ctx, REG_MDT_RFIFO_STAT); 1631 } 1632 1633 static void sii8620_irq_g2wb(struct sii8620 *ctx) 1634 { 1635 u8 stat = sii8620_readb(ctx, REG_MDT_INT_0); 1636 1637 if (stat & BIT_MDT_IDLE_AFTER_HAWB_DISABLE) 1638 if (sii8620_is_mhl3(ctx)) 1639 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), 1640 MHL_INT_RC_FEAT_COMPLETE); 1641 1642 if (stat & BIT_MDT_RFIFO_DATA_RDY) 1643 sii8620_read_burst(ctx); 1644 1645 if (stat & BIT_MDT_XFIFO_EMPTY) 1646 sii8620_write(ctx, REG_MDT_XMIT_CTRL, 0); 1647 1648 sii8620_write(ctx, REG_MDT_INT_0, stat); 1649 } 1650 1651 static void sii8620_status_dcap_ready(struct sii8620 *ctx) 1652 { 1653 enum sii8620_mode mode; 1654 1655 mode = ctx->stat[MHL_DST_VERSION] >= 0x30 ? CM_MHL3 : CM_MHL1; 1656 if (mode > ctx->mode) 1657 sii8620_set_mode(ctx, mode); 1658 sii8620_peer_specific_init(ctx); 1659 sii8620_write(ctx, REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE 1660 | BIT_INTR9_EDID_DONE | BIT_INTR9_EDID_ERROR); 1661 } 1662 1663 static void sii8620_status_changed_path(struct sii8620 *ctx) 1664 { 1665 if (ctx->stat[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED) { 1666 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE), 1667 MHL_DST_LM_CLK_MODE_NORMAL 1668 | MHL_DST_LM_PATH_ENABLED); 1669 } else { 1670 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE), 1671 MHL_DST_LM_CLK_MODE_NORMAL); 1672 } 1673 } 1674 1675 static void sii8620_msc_mr_write_stat(struct sii8620 *ctx) 1676 { 1677 u8 st[MHL_DST_SIZE], xst[MHL_XDS_SIZE]; 1678 1679 sii8620_read_buf(ctx, REG_MHL_STAT_0, st, MHL_DST_SIZE); 1680 sii8620_read_buf(ctx, REG_MHL_EXTSTAT_0, xst, MHL_XDS_SIZE); 1681 1682 sii8620_update_array(ctx->stat, st, MHL_DST_SIZE); 1683 sii8620_update_array(ctx->xstat, xst, MHL_XDS_SIZE); 1684 1685 if (ctx->stat[MHL_DST_CONNECTED_RDY] & st[MHL_DST_CONNECTED_RDY] & 1686 MHL_DST_CONN_DCAP_RDY) { 1687 sii8620_status_dcap_ready(ctx); 1688 1689 if (!sii8620_is_mhl3(ctx)) 1690 sii8620_mt_read_devcap(ctx, false); 1691 } 1692 1693 if (st[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED) 1694 sii8620_status_changed_path(ctx); 1695 } 1696 1697 static void sii8620_ecbus_up(struct sii8620 *ctx, int ret) 1698 { 1699 if (ret < 0) 1700 return; 1701 1702 sii8620_set_mode(ctx, CM_ECBUS_S); 1703 } 1704 1705 static void sii8620_got_ecbus_speed(struct sii8620 *ctx, int ret) 1706 { 1707 if (ret < 0) 1708 return; 1709 1710 sii8620_mt_write_stat(ctx, MHL_XDS_REG(CURR_ECBUS_MODE), 1711 MHL_XDS_ECBUS_S | MHL_XDS_SLOT_MODE_8BIT); 1712 sii8620_mt_rap(ctx, MHL_RAP_CBUS_MODE_UP); 1713 sii8620_mt_set_cont(ctx, sii8620_ecbus_up); 1714 } 1715 1716 static void sii8620_mhl_burst_emsc_support_set(struct mhl_burst_emsc_support *d, 1717 enum mhl_burst_id id) 1718 { 1719 sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_EMSC_SUPPORT); 1720 d->num_entries = 1; 1721 d->burst_id[0] = cpu_to_be16(id); 1722 } 1723 1724 static void sii8620_send_features(struct sii8620 *ctx) 1725 { 1726 u8 buf[16]; 1727 1728 sii8620_write(ctx, REG_MDT_XMIT_CTRL, BIT_MDT_XMIT_CTRL_EN 1729 | BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN); 1730 sii8620_mhl_burst_emsc_support_set((void *)buf, 1731 MHL_BURST_ID_HID_PAYLOAD); 1732 sii8620_write_buf(ctx, REG_MDT_XMIT_WRITE_PORT, buf, ARRAY_SIZE(buf)); 1733 } 1734 1735 static bool sii8620_rcp_consume(struct sii8620 *ctx, u8 scancode) 1736 { 1737 bool pressed = !(scancode & MHL_RCP_KEY_RELEASED_MASK); 1738 1739 scancode &= MHL_RCP_KEY_ID_MASK; 1740 1741 if (!ctx->rc_dev) { 1742 dev_dbg(ctx->dev, "RCP input device not initialized\n"); 1743 return false; 1744 } 1745 1746 if (pressed) 1747 rc_keydown(ctx->rc_dev, RC_PROTO_CEC, scancode, 0); 1748 else 1749 rc_keyup(ctx->rc_dev); 1750 1751 return true; 1752 } 1753 1754 static void sii8620_msc_mr_set_int(struct sii8620 *ctx) 1755 { 1756 u8 ints[MHL_INT_SIZE]; 1757 1758 sii8620_read_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE); 1759 sii8620_write_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE); 1760 1761 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_DCAP_CHG) { 1762 switch (ctx->mode) { 1763 case CM_MHL3: 1764 sii8620_mt_read_xdevcap_reg(ctx, MHL_XDC_ECBUS_SPEEDS); 1765 sii8620_mt_set_cont(ctx, sii8620_got_ecbus_speed); 1766 break; 1767 case CM_ECBUS_S: 1768 sii8620_mt_read_devcap(ctx, true); 1769 break; 1770 default: 1771 break; 1772 } 1773 } 1774 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_REQ) 1775 sii8620_send_features(ctx); 1776 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_COMPLETE) { 1777 ctx->feature_complete = true; 1778 if (ctx->edid) 1779 sii8620_enable_hpd(ctx); 1780 } 1781 } 1782 1783 static struct sii8620_mt_msg *sii8620_msc_msg_first(struct sii8620 *ctx) 1784 { 1785 struct device *dev = ctx->dev; 1786 1787 if (list_empty(&ctx->mt_queue)) { 1788 dev_err(dev, "unexpected MSC MT response\n"); 1789 return NULL; 1790 } 1791 1792 return list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 1793 } 1794 1795 static void sii8620_msc_mt_done(struct sii8620 *ctx) 1796 { 1797 struct sii8620_mt_msg *msg = sii8620_msc_msg_first(ctx); 1798 1799 if (!msg) 1800 return; 1801 1802 msg->ret = sii8620_readb(ctx, REG_MSC_MT_RCVD_DATA0); 1803 ctx->mt_state = MT_STATE_DONE; 1804 } 1805 1806 static void sii8620_msc_mr_msc_msg(struct sii8620 *ctx) 1807 { 1808 struct sii8620_mt_msg *msg; 1809 u8 buf[2]; 1810 1811 sii8620_read_buf(ctx, REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA, buf, 2); 1812 1813 switch (buf[0]) { 1814 case MHL_MSC_MSG_RAPK: 1815 msg = sii8620_msc_msg_first(ctx); 1816 if (!msg) 1817 return; 1818 msg->ret = buf[1]; 1819 ctx->mt_state = MT_STATE_DONE; 1820 break; 1821 case MHL_MSC_MSG_RCP: 1822 if (!sii8620_rcp_consume(ctx, buf[1])) 1823 sii8620_mt_rcpe(ctx, 1824 MHL_RCPE_STATUS_INEFFECTIVE_KEY_CODE); 1825 sii8620_mt_rcpk(ctx, buf[1]); 1826 break; 1827 default: 1828 dev_err(ctx->dev, "%s message type %d,%d not supported", 1829 __func__, buf[0], buf[1]); 1830 } 1831 } 1832 1833 static void sii8620_irq_msc(struct sii8620 *ctx) 1834 { 1835 u8 stat = sii8620_readb(ctx, REG_CBUS_INT_0); 1836 1837 if (stat & ~BIT_CBUS_HPD_CHG) 1838 sii8620_write(ctx, REG_CBUS_INT_0, stat & ~BIT_CBUS_HPD_CHG); 1839 1840 if (stat & BIT_CBUS_HPD_CHG) { 1841 u8 cbus_stat = sii8620_readb(ctx, REG_CBUS_STATUS); 1842 1843 if ((cbus_stat ^ ctx->cbus_status) & BIT_CBUS_STATUS_CBUS_HPD) { 1844 sii8620_write(ctx, REG_CBUS_INT_0, BIT_CBUS_HPD_CHG); 1845 } else { 1846 stat ^= BIT_CBUS_STATUS_CBUS_HPD; 1847 cbus_stat ^= BIT_CBUS_STATUS_CBUS_HPD; 1848 } 1849 ctx->cbus_status = cbus_stat; 1850 } 1851 1852 if (stat & BIT_CBUS_MSC_MR_WRITE_STAT) 1853 sii8620_msc_mr_write_stat(ctx); 1854 1855 if (stat & BIT_CBUS_HPD_CHG) { 1856 if (ctx->cbus_status & BIT_CBUS_STATUS_CBUS_HPD) { 1857 ctx->sink_detected = true; 1858 sii8620_identify_sink(ctx); 1859 } else { 1860 sii8620_hpd_unplugged(ctx); 1861 } 1862 } 1863 1864 if (stat & BIT_CBUS_MSC_MR_SET_INT) 1865 sii8620_msc_mr_set_int(ctx); 1866 1867 if (stat & BIT_CBUS_MSC_MT_DONE) 1868 sii8620_msc_mt_done(ctx); 1869 1870 if (stat & BIT_CBUS_MSC_MR_MSC_MSG) 1871 sii8620_msc_mr_msc_msg(ctx); 1872 } 1873 1874 static void sii8620_irq_coc(struct sii8620 *ctx) 1875 { 1876 u8 stat = sii8620_readb(ctx, REG_COC_INTR); 1877 1878 if (stat & BIT_COC_CALIBRATION_DONE) { 1879 u8 cstat = sii8620_readb(ctx, REG_COC_STAT_0); 1880 1881 cstat &= BIT_COC_STAT_0_PLL_LOCKED | MSK_COC_STAT_0_FSM_STATE; 1882 if (cstat == (BIT_COC_STAT_0_PLL_LOCKED | 0x02)) { 1883 sii8620_write_seq_static(ctx, 1884 REG_COC_CTLB, 0, 1885 REG_TRXINTMH, BIT_TDM_INTR_SYNC_DATA 1886 | BIT_TDM_INTR_SYNC_WAIT 1887 ); 1888 } 1889 } 1890 1891 sii8620_write(ctx, REG_COC_INTR, stat); 1892 } 1893 1894 static void sii8620_irq_merr(struct sii8620 *ctx) 1895 { 1896 u8 stat = sii8620_readb(ctx, REG_CBUS_INT_1); 1897 1898 sii8620_write(ctx, REG_CBUS_INT_1, stat); 1899 } 1900 1901 static void sii8620_irq_edid(struct sii8620 *ctx) 1902 { 1903 u8 stat = sii8620_readb(ctx, REG_INTR9); 1904 1905 sii8620_write(ctx, REG_INTR9, stat); 1906 1907 if (stat & BIT_INTR9_DEVCAP_DONE) 1908 ctx->mt_state = MT_STATE_DONE; 1909 } 1910 1911 static void sii8620_irq_scdt(struct sii8620 *ctx) 1912 { 1913 u8 stat = sii8620_readb(ctx, REG_INTR5); 1914 1915 if (stat & BIT_INTR_SCDT_CHANGE) { 1916 u8 cstat = sii8620_readb(ctx, REG_TMDS_CSTAT_P3); 1917 1918 if (cstat & BIT_TMDS_CSTAT_P3_SCDT) 1919 sii8620_start_video(ctx); 1920 } 1921 1922 sii8620_write(ctx, REG_INTR5, stat); 1923 } 1924 1925 static void sii8620_got_xdevcap(struct sii8620 *ctx, int ret) 1926 { 1927 if (ret < 0) 1928 return; 1929 1930 sii8620_mt_read_devcap(ctx, false); 1931 } 1932 1933 static void sii8620_irq_tdm(struct sii8620 *ctx) 1934 { 1935 u8 stat = sii8620_readb(ctx, REG_TRXINTH); 1936 u8 tdm = sii8620_readb(ctx, REG_TRXSTA2); 1937 1938 if ((tdm & MSK_TDM_SYNCHRONIZED) == VAL_TDM_SYNCHRONIZED) { 1939 ctx->mode = CM_ECBUS_S; 1940 ctx->burst.rx_ack = 0; 1941 ctx->burst.r_size = SII8620_BURST_BUF_LEN; 1942 sii8620_burst_tx_rbuf_info(ctx, SII8620_BURST_BUF_LEN); 1943 sii8620_mt_read_devcap(ctx, true); 1944 sii8620_mt_set_cont(ctx, sii8620_got_xdevcap); 1945 } else { 1946 sii8620_write_seq_static(ctx, 1947 REG_MHL_PLL_CTL2, 0, 1948 REG_MHL_PLL_CTL2, BIT_MHL_PLL_CTL2_CLKDETECT_EN 1949 ); 1950 } 1951 1952 sii8620_write(ctx, REG_TRXINTH, stat); 1953 } 1954 1955 static void sii8620_irq_block(struct sii8620 *ctx) 1956 { 1957 u8 stat = sii8620_readb(ctx, REG_EMSCINTR); 1958 1959 if (stat & BIT_EMSCINTR_SPI_DVLD) { 1960 u8 bstat = sii8620_readb(ctx, REG_SPIBURSTSTAT); 1961 1962 if (bstat & BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE) 1963 sii8620_burst_receive(ctx); 1964 } 1965 1966 sii8620_write(ctx, REG_EMSCINTR, stat); 1967 } 1968 1969 static void sii8620_irq_ddc(struct sii8620 *ctx) 1970 { 1971 u8 stat = sii8620_readb(ctx, REG_INTR3); 1972 1973 if (stat & BIT_DDC_CMD_DONE) { 1974 sii8620_write(ctx, REG_INTR3_MASK, 0); 1975 if (sii8620_is_mhl3(ctx) && !ctx->feature_complete) 1976 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), 1977 MHL_INT_RC_FEAT_REQ); 1978 else 1979 sii8620_enable_hpd(ctx); 1980 } 1981 sii8620_write(ctx, REG_INTR3, stat); 1982 } 1983 1984 /* endian agnostic, non-volatile version of test_bit */ 1985 static bool sii8620_test_bit(unsigned int nr, const u8 *addr) 1986 { 1987 return 1 & (addr[nr / BITS_PER_BYTE] >> (nr % BITS_PER_BYTE)); 1988 } 1989 1990 static irqreturn_t sii8620_irq_thread(int irq, void *data) 1991 { 1992 static const struct { 1993 int bit; 1994 void (*handler)(struct sii8620 *ctx); 1995 } irq_vec[] = { 1996 { BIT_FAST_INTR_STAT_DISC, sii8620_irq_disc }, 1997 { BIT_FAST_INTR_STAT_G2WB, sii8620_irq_g2wb }, 1998 { BIT_FAST_INTR_STAT_COC, sii8620_irq_coc }, 1999 { BIT_FAST_INTR_STAT_TDM, sii8620_irq_tdm }, 2000 { BIT_FAST_INTR_STAT_MSC, sii8620_irq_msc }, 2001 { BIT_FAST_INTR_STAT_MERR, sii8620_irq_merr }, 2002 { BIT_FAST_INTR_STAT_BLOCK, sii8620_irq_block }, 2003 { BIT_FAST_INTR_STAT_EDID, sii8620_irq_edid }, 2004 { BIT_FAST_INTR_STAT_DDC, sii8620_irq_ddc }, 2005 { BIT_FAST_INTR_STAT_SCDT, sii8620_irq_scdt }, 2006 }; 2007 struct sii8620 *ctx = data; 2008 u8 stats[LEN_FAST_INTR_STAT]; 2009 int i, ret; 2010 2011 mutex_lock(&ctx->lock); 2012 2013 sii8620_read_buf(ctx, REG_FAST_INTR_STAT, stats, ARRAY_SIZE(stats)); 2014 for (i = 0; i < ARRAY_SIZE(irq_vec); ++i) 2015 if (sii8620_test_bit(irq_vec[i].bit, stats)) 2016 irq_vec[i].handler(ctx); 2017 2018 sii8620_burst_rx_all(ctx); 2019 sii8620_mt_work(ctx); 2020 sii8620_burst_send(ctx); 2021 2022 ret = sii8620_clear_error(ctx); 2023 if (ret) { 2024 dev_err(ctx->dev, "Error during IRQ handling, %d.\n", ret); 2025 sii8620_mhl_disconnected(ctx); 2026 } 2027 mutex_unlock(&ctx->lock); 2028 2029 return IRQ_HANDLED; 2030 } 2031 2032 static void sii8620_cable_in(struct sii8620 *ctx) 2033 { 2034 struct device *dev = ctx->dev; 2035 u8 ver[5]; 2036 int ret; 2037 2038 ret = sii8620_hw_on(ctx); 2039 if (ret) { 2040 dev_err(dev, "Error powering on, %d.\n", ret); 2041 return; 2042 } 2043 2044 sii8620_read_buf(ctx, REG_VND_IDL, ver, ARRAY_SIZE(ver)); 2045 ret = sii8620_clear_error(ctx); 2046 if (ret) { 2047 dev_err(dev, "Error accessing I2C bus, %d.\n", ret); 2048 return; 2049 } 2050 2051 dev_info(dev, "ChipID %02x%02x:%02x%02x rev %02x.\n", ver[1], ver[0], 2052 ver[3], ver[2], ver[4]); 2053 2054 sii8620_write(ctx, REG_DPD, 2055 BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN); 2056 2057 sii8620_xtal_set_rate(ctx); 2058 sii8620_disconnect(ctx); 2059 2060 sii8620_write_seq_static(ctx, 2061 REG_MHL_CBUS_CTL0, VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONG 2062 | VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_734, 2063 REG_MHL_CBUS_CTL1, VAL_MHL_CBUS_CTL1_1115_OHM, 2064 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN, 2065 ); 2066 2067 ret = sii8620_clear_error(ctx); 2068 if (ret) { 2069 dev_err(dev, "Error accessing I2C bus, %d.\n", ret); 2070 return; 2071 } 2072 2073 enable_irq(to_i2c_client(ctx->dev)->irq); 2074 } 2075 2076 static void sii8620_init_rcp_input_dev(struct sii8620 *ctx) 2077 { 2078 struct rc_dev *rc_dev; 2079 int ret; 2080 2081 rc_dev = rc_allocate_device(RC_DRIVER_SCANCODE); 2082 if (!rc_dev) { 2083 dev_err(ctx->dev, "Failed to allocate RC device\n"); 2084 ctx->error = -ENOMEM; 2085 return; 2086 } 2087 2088 rc_dev->input_phys = "sii8620/input0"; 2089 rc_dev->input_id.bustype = BUS_VIRTUAL; 2090 rc_dev->map_name = RC_MAP_CEC; 2091 rc_dev->allowed_protocols = RC_PROTO_BIT_CEC; 2092 rc_dev->driver_name = "sii8620"; 2093 rc_dev->device_name = "sii8620"; 2094 2095 ret = rc_register_device(rc_dev); 2096 2097 if (ret) { 2098 dev_err(ctx->dev, "Failed to register RC device\n"); 2099 ctx->error = ret; 2100 rc_free_device(ctx->rc_dev); 2101 return; 2102 } 2103 ctx->rc_dev = rc_dev; 2104 } 2105 2106 static void sii8620_cable_out(struct sii8620 *ctx) 2107 { 2108 disable_irq(to_i2c_client(ctx->dev)->irq); 2109 sii8620_hw_off(ctx); 2110 } 2111 2112 static void sii8620_extcon_work(struct work_struct *work) 2113 { 2114 struct sii8620 *ctx = 2115 container_of(work, struct sii8620, extcon_wq); 2116 int state = extcon_get_state(ctx->extcon, EXTCON_DISP_MHL); 2117 2118 if (state == ctx->cable_state) 2119 return; 2120 2121 ctx->cable_state = state; 2122 2123 if (state > 0) 2124 sii8620_cable_in(ctx); 2125 else 2126 sii8620_cable_out(ctx); 2127 } 2128 2129 static int sii8620_extcon_notifier(struct notifier_block *self, 2130 unsigned long event, void *ptr) 2131 { 2132 struct sii8620 *ctx = 2133 container_of(self, struct sii8620, extcon_nb); 2134 2135 schedule_work(&ctx->extcon_wq); 2136 2137 return NOTIFY_DONE; 2138 } 2139 2140 static int sii8620_extcon_init(struct sii8620 *ctx) 2141 { 2142 struct extcon_dev *edev; 2143 struct device_node *musb, *muic; 2144 int ret; 2145 2146 /* get micro-USB connector node */ 2147 musb = of_graph_get_remote_node(ctx->dev->of_node, 1, -1); 2148 /* next get micro-USB Interface Controller node */ 2149 muic = of_get_next_parent(musb); 2150 2151 if (!muic) { 2152 dev_info(ctx->dev, "no extcon found, switching to 'always on' mode\n"); 2153 return 0; 2154 } 2155 2156 edev = extcon_find_edev_by_node(muic); 2157 of_node_put(muic); 2158 if (IS_ERR(edev)) { 2159 if (PTR_ERR(edev) == -EPROBE_DEFER) 2160 return -EPROBE_DEFER; 2161 dev_err(ctx->dev, "Invalid or missing extcon\n"); 2162 return PTR_ERR(edev); 2163 } 2164 2165 ctx->extcon = edev; 2166 ctx->extcon_nb.notifier_call = sii8620_extcon_notifier; 2167 INIT_WORK(&ctx->extcon_wq, sii8620_extcon_work); 2168 ret = extcon_register_notifier(edev, EXTCON_DISP_MHL, &ctx->extcon_nb); 2169 if (ret) { 2170 dev_err(ctx->dev, "failed to register notifier for MHL\n"); 2171 return ret; 2172 } 2173 2174 return 0; 2175 } 2176 2177 static inline struct sii8620 *bridge_to_sii8620(struct drm_bridge *bridge) 2178 { 2179 return container_of(bridge, struct sii8620, bridge); 2180 } 2181 2182 static int sii8620_attach(struct drm_bridge *bridge) 2183 { 2184 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2185 2186 sii8620_init_rcp_input_dev(ctx); 2187 2188 return sii8620_clear_error(ctx); 2189 } 2190 2191 static void sii8620_detach(struct drm_bridge *bridge) 2192 { 2193 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2194 2195 rc_unregister_device(ctx->rc_dev); 2196 } 2197 2198 static int sii8620_is_packing_required(struct sii8620 *ctx, 2199 const struct drm_display_mode *mode) 2200 { 2201 int max_pclk, max_pclk_pp_mode; 2202 2203 if (sii8620_is_mhl3(ctx)) { 2204 max_pclk = MHL3_MAX_PCLK; 2205 max_pclk_pp_mode = MHL3_MAX_PCLK_PP_MODE; 2206 } else { 2207 max_pclk = MHL1_MAX_PCLK; 2208 max_pclk_pp_mode = MHL1_MAX_PCLK_PP_MODE; 2209 } 2210 2211 if (mode->clock < max_pclk) 2212 return 0; 2213 else if (mode->clock < max_pclk_pp_mode) 2214 return 1; 2215 else 2216 return -1; 2217 } 2218 2219 static enum drm_mode_status sii8620_mode_valid(struct drm_bridge *bridge, 2220 const struct drm_display_mode *mode) 2221 { 2222 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2223 int pack_required = sii8620_is_packing_required(ctx, mode); 2224 bool can_pack = ctx->devcap[MHL_DCAP_VID_LINK_MODE] & 2225 MHL_DCAP_VID_LINK_PPIXEL; 2226 2227 switch (pack_required) { 2228 case 0: 2229 return MODE_OK; 2230 case 1: 2231 return (can_pack) ? MODE_OK : MODE_CLOCK_HIGH; 2232 default: 2233 return MODE_CLOCK_HIGH; 2234 } 2235 } 2236 2237 static bool sii8620_mode_fixup(struct drm_bridge *bridge, 2238 const struct drm_display_mode *mode, 2239 struct drm_display_mode *adjusted_mode) 2240 { 2241 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2242 2243 mutex_lock(&ctx->lock); 2244 2245 ctx->use_packed_pixel = sii8620_is_packing_required(ctx, adjusted_mode); 2246 2247 mutex_unlock(&ctx->lock); 2248 2249 return true; 2250 } 2251 2252 static const struct drm_bridge_funcs sii8620_bridge_funcs = { 2253 .attach = sii8620_attach, 2254 .detach = sii8620_detach, 2255 .mode_fixup = sii8620_mode_fixup, 2256 .mode_valid = sii8620_mode_valid, 2257 }; 2258 2259 static int sii8620_probe(struct i2c_client *client, 2260 const struct i2c_device_id *id) 2261 { 2262 struct device *dev = &client->dev; 2263 struct sii8620 *ctx; 2264 int ret; 2265 2266 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 2267 if (!ctx) 2268 return -ENOMEM; 2269 2270 ctx->dev = dev; 2271 mutex_init(&ctx->lock); 2272 INIT_LIST_HEAD(&ctx->mt_queue); 2273 2274 ctx->clk_xtal = devm_clk_get(dev, "xtal"); 2275 if (IS_ERR(ctx->clk_xtal)) { 2276 dev_err(dev, "failed to get xtal clock from DT\n"); 2277 return PTR_ERR(ctx->clk_xtal); 2278 } 2279 2280 if (!client->irq) { 2281 dev_err(dev, "no irq provided\n"); 2282 return -EINVAL; 2283 } 2284 irq_set_status_flags(client->irq, IRQ_NOAUTOEN); 2285 ret = devm_request_threaded_irq(dev, client->irq, NULL, 2286 sii8620_irq_thread, 2287 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 2288 "sii8620", ctx); 2289 if (ret < 0) { 2290 dev_err(dev, "failed to install IRQ handler\n"); 2291 return ret; 2292 } 2293 2294 ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); 2295 if (IS_ERR(ctx->gpio_reset)) { 2296 dev_err(dev, "failed to get reset gpio from DT\n"); 2297 return PTR_ERR(ctx->gpio_reset); 2298 } 2299 2300 ctx->supplies[0].supply = "cvcc10"; 2301 ctx->supplies[1].supply = "iovcc18"; 2302 ret = devm_regulator_bulk_get(dev, 2, ctx->supplies); 2303 if (ret) 2304 return ret; 2305 2306 ret = sii8620_extcon_init(ctx); 2307 if (ret < 0) { 2308 dev_err(ctx->dev, "failed to initialize EXTCON\n"); 2309 return ret; 2310 } 2311 2312 i2c_set_clientdata(client, ctx); 2313 2314 ctx->bridge.funcs = &sii8620_bridge_funcs; 2315 ctx->bridge.of_node = dev->of_node; 2316 drm_bridge_add(&ctx->bridge); 2317 2318 if (!ctx->extcon) 2319 sii8620_cable_in(ctx); 2320 2321 return 0; 2322 } 2323 2324 static int sii8620_remove(struct i2c_client *client) 2325 { 2326 struct sii8620 *ctx = i2c_get_clientdata(client); 2327 2328 if (ctx->extcon) { 2329 extcon_unregister_notifier(ctx->extcon, EXTCON_DISP_MHL, 2330 &ctx->extcon_nb); 2331 flush_work(&ctx->extcon_wq); 2332 if (ctx->cable_state > 0) 2333 sii8620_cable_out(ctx); 2334 } else { 2335 sii8620_cable_out(ctx); 2336 } 2337 drm_bridge_remove(&ctx->bridge); 2338 2339 return 0; 2340 } 2341 2342 static const struct of_device_id sii8620_dt_match[] = { 2343 { .compatible = "sil,sii8620" }, 2344 { }, 2345 }; 2346 MODULE_DEVICE_TABLE(of, sii8620_dt_match); 2347 2348 static const struct i2c_device_id sii8620_id[] = { 2349 { "sii8620", 0 }, 2350 { }, 2351 }; 2352 2353 MODULE_DEVICE_TABLE(i2c, sii8620_id); 2354 static struct i2c_driver sii8620_driver = { 2355 .driver = { 2356 .name = "sii8620", 2357 .of_match_table = of_match_ptr(sii8620_dt_match), 2358 }, 2359 .probe = sii8620_probe, 2360 .remove = sii8620_remove, 2361 .id_table = sii8620_id, 2362 }; 2363 2364 module_i2c_driver(sii8620_driver); 2365 MODULE_LICENSE("GPL v2"); 2366