1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Silicon Image SiI8620 HDMI/MHL bridge driver 4 * 5 * Copyright (C) 2015, Samsung Electronics Co., Ltd. 6 * Andrzej Hajda <a.hajda@samsung.com> 7 */ 8 9 #include <asm/unaligned.h> 10 11 #include <drm/bridge/mhl.h> 12 #include <drm/drm_crtc.h> 13 #include <drm/drm_edid.h> 14 #include <drm/drm_encoder.h> 15 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/extcon.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/i2c.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/kernel.h> 24 #include <linux/list.h> 25 #include <linux/module.h> 26 #include <linux/mutex.h> 27 #include <linux/of_graph.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/slab.h> 30 31 #include <media/rc-core.h> 32 33 #include "sil-sii8620.h" 34 35 #define SII8620_BURST_BUF_LEN 288 36 #define VAL_RX_HDMI_CTRL2_DEFVAL VAL_RX_HDMI_CTRL2_IDLE_CNT(3) 37 38 #define MHL1_MAX_PCLK 75000 39 #define MHL1_MAX_PCLK_PP_MODE 150000 40 #define MHL3_MAX_PCLK 200000 41 #define MHL3_MAX_PCLK_PP_MODE 300000 42 43 enum sii8620_mode { 44 CM_DISCONNECTED, 45 CM_DISCOVERY, 46 CM_MHL1, 47 CM_MHL3, 48 CM_ECBUS_S 49 }; 50 51 enum sii8620_sink_type { 52 SINK_NONE, 53 SINK_HDMI, 54 SINK_DVI 55 }; 56 57 enum sii8620_mt_state { 58 MT_STATE_READY, 59 MT_STATE_BUSY, 60 MT_STATE_DONE 61 }; 62 63 struct sii8620 { 64 struct drm_bridge bridge; 65 struct device *dev; 66 struct rc_dev *rc_dev; 67 struct clk *clk_xtal; 68 struct gpio_desc *gpio_reset; 69 struct gpio_desc *gpio_int; 70 struct regulator_bulk_data supplies[2]; 71 struct mutex lock; /* context lock, protects fields below */ 72 int error; 73 unsigned int use_packed_pixel:1; 74 enum sii8620_mode mode; 75 enum sii8620_sink_type sink_type; 76 u8 cbus_status; 77 u8 stat[MHL_DST_SIZE]; 78 u8 xstat[MHL_XDS_SIZE]; 79 u8 devcap[MHL_DCAP_SIZE]; 80 u8 xdevcap[MHL_XDC_SIZE]; 81 bool feature_complete; 82 bool devcap_read; 83 bool sink_detected; 84 struct edid *edid; 85 unsigned int gen2_write_burst:1; 86 enum sii8620_mt_state mt_state; 87 struct extcon_dev *extcon; 88 struct notifier_block extcon_nb; 89 struct work_struct extcon_wq; 90 int cable_state; 91 struct list_head mt_queue; 92 struct { 93 int r_size; 94 int r_count; 95 int rx_ack; 96 int rx_count; 97 u8 rx_buf[32]; 98 int tx_count; 99 u8 tx_buf[32]; 100 } burst; 101 }; 102 103 struct sii8620_mt_msg; 104 105 typedef void (*sii8620_mt_msg_cb)(struct sii8620 *ctx, 106 struct sii8620_mt_msg *msg); 107 108 typedef void (*sii8620_cb)(struct sii8620 *ctx, int ret); 109 110 struct sii8620_mt_msg { 111 struct list_head node; 112 u8 reg[4]; 113 u8 ret; 114 sii8620_mt_msg_cb send; 115 sii8620_mt_msg_cb recv; 116 sii8620_cb continuation; 117 }; 118 119 static const u8 sii8620_i2c_page[] = { 120 0x39, /* Main System */ 121 0x3d, /* TDM and HSIC */ 122 0x49, /* TMDS Receiver, MHL EDID */ 123 0x4d, /* eMSC, HDCP, HSIC */ 124 0x5d, /* MHL Spec */ 125 0x64, /* MHL CBUS */ 126 0x59, /* Hardware TPI (Transmitter Programming Interface) */ 127 0x61, /* eCBUS-S, eCBUS-D */ 128 }; 129 130 static void sii8620_fetch_edid(struct sii8620 *ctx); 131 static void sii8620_set_upstream_edid(struct sii8620 *ctx); 132 static void sii8620_enable_hpd(struct sii8620 *ctx); 133 static void sii8620_mhl_disconnected(struct sii8620 *ctx); 134 static void sii8620_disconnect(struct sii8620 *ctx); 135 136 static int sii8620_clear_error(struct sii8620 *ctx) 137 { 138 int ret = ctx->error; 139 140 ctx->error = 0; 141 return ret; 142 } 143 144 static void sii8620_read_buf(struct sii8620 *ctx, u16 addr, u8 *buf, int len) 145 { 146 struct device *dev = ctx->dev; 147 struct i2c_client *client = to_i2c_client(dev); 148 u8 data = addr; 149 struct i2c_msg msg[] = { 150 { 151 .addr = sii8620_i2c_page[addr >> 8], 152 .flags = client->flags, 153 .len = 1, 154 .buf = &data 155 }, 156 { 157 .addr = sii8620_i2c_page[addr >> 8], 158 .flags = client->flags | I2C_M_RD, 159 .len = len, 160 .buf = buf 161 }, 162 }; 163 int ret; 164 165 if (ctx->error) 166 return; 167 168 ret = i2c_transfer(client->adapter, msg, 2); 169 dev_dbg(dev, "read at %04x: %*ph, %d\n", addr, len, buf, ret); 170 171 if (ret != 2) { 172 dev_err(dev, "Read at %#06x of %d bytes failed with code %d.\n", 173 addr, len, ret); 174 ctx->error = ret < 0 ? ret : -EIO; 175 } 176 } 177 178 static u8 sii8620_readb(struct sii8620 *ctx, u16 addr) 179 { 180 u8 ret; 181 182 sii8620_read_buf(ctx, addr, &ret, 1); 183 return ret; 184 } 185 186 static void sii8620_write_buf(struct sii8620 *ctx, u16 addr, const u8 *buf, 187 int len) 188 { 189 struct device *dev = ctx->dev; 190 struct i2c_client *client = to_i2c_client(dev); 191 u8 data[2]; 192 struct i2c_msg msg = { 193 .addr = sii8620_i2c_page[addr >> 8], 194 .flags = client->flags, 195 .len = len + 1, 196 }; 197 int ret; 198 199 if (ctx->error) 200 return; 201 202 if (len > 1) { 203 msg.buf = kmalloc(len + 1, GFP_KERNEL); 204 if (!msg.buf) { 205 ctx->error = -ENOMEM; 206 return; 207 } 208 memcpy(msg.buf + 1, buf, len); 209 } else { 210 msg.buf = data; 211 msg.buf[1] = *buf; 212 } 213 214 msg.buf[0] = addr; 215 216 ret = i2c_transfer(client->adapter, &msg, 1); 217 dev_dbg(dev, "write at %04x: %*ph, %d\n", addr, len, buf, ret); 218 219 if (ret != 1) { 220 dev_err(dev, "Write at %#06x of %*ph failed with code %d.\n", 221 addr, len, buf, ret); 222 ctx->error = ret ?: -EIO; 223 } 224 225 if (len > 1) 226 kfree(msg.buf); 227 } 228 229 #define sii8620_write(ctx, addr, arr...) \ 230 ({\ 231 u8 d[] = { arr }; \ 232 sii8620_write_buf(ctx, addr, d, ARRAY_SIZE(d)); \ 233 }) 234 235 static void __sii8620_write_seq(struct sii8620 *ctx, const u16 *seq, int len) 236 { 237 int i; 238 239 for (i = 0; i < len; i += 2) 240 sii8620_write(ctx, seq[i], seq[i + 1]); 241 } 242 243 #define sii8620_write_seq(ctx, seq...) \ 244 ({\ 245 const u16 d[] = { seq }; \ 246 __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \ 247 }) 248 249 #define sii8620_write_seq_static(ctx, seq...) \ 250 ({\ 251 static const u16 d[] = { seq }; \ 252 __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \ 253 }) 254 255 static void sii8620_setbits(struct sii8620 *ctx, u16 addr, u8 mask, u8 val) 256 { 257 val = (val & mask) | (sii8620_readb(ctx, addr) & ~mask); 258 sii8620_write(ctx, addr, val); 259 } 260 261 static inline bool sii8620_is_mhl3(struct sii8620 *ctx) 262 { 263 return ctx->mode >= CM_MHL3; 264 } 265 266 static void sii8620_mt_cleanup(struct sii8620 *ctx) 267 { 268 struct sii8620_mt_msg *msg, *n; 269 270 list_for_each_entry_safe(msg, n, &ctx->mt_queue, node) { 271 list_del(&msg->node); 272 kfree(msg); 273 } 274 ctx->mt_state = MT_STATE_READY; 275 } 276 277 static void sii8620_mt_work(struct sii8620 *ctx) 278 { 279 struct sii8620_mt_msg *msg; 280 281 if (ctx->error) 282 return; 283 if (ctx->mt_state == MT_STATE_BUSY || list_empty(&ctx->mt_queue)) 284 return; 285 286 if (ctx->mt_state == MT_STATE_DONE) { 287 ctx->mt_state = MT_STATE_READY; 288 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, 289 node); 290 list_del(&msg->node); 291 if (msg->recv) 292 msg->recv(ctx, msg); 293 if (msg->continuation) 294 msg->continuation(ctx, msg->ret); 295 kfree(msg); 296 } 297 298 if (ctx->mt_state != MT_STATE_READY || list_empty(&ctx->mt_queue)) 299 return; 300 301 ctx->mt_state = MT_STATE_BUSY; 302 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 303 if (msg->send) 304 msg->send(ctx, msg); 305 } 306 307 static void sii8620_enable_gen2_write_burst(struct sii8620 *ctx) 308 { 309 u8 ctrl = BIT_MDT_RCV_CTRL_MDT_RCV_EN; 310 311 if (ctx->gen2_write_burst) 312 return; 313 314 if (ctx->mode >= CM_MHL1) 315 ctrl |= BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN; 316 317 sii8620_write_seq(ctx, 318 REG_MDT_RCV_TIMEOUT, 100, 319 REG_MDT_RCV_CTRL, ctrl 320 ); 321 ctx->gen2_write_burst = 1; 322 } 323 324 static void sii8620_disable_gen2_write_burst(struct sii8620 *ctx) 325 { 326 if (!ctx->gen2_write_burst) 327 return; 328 329 sii8620_write_seq_static(ctx, 330 REG_MDT_XMIT_CTRL, 0, 331 REG_MDT_RCV_CTRL, 0 332 ); 333 ctx->gen2_write_burst = 0; 334 } 335 336 static void sii8620_start_gen2_write_burst(struct sii8620 *ctx) 337 { 338 sii8620_write_seq_static(ctx, 339 REG_MDT_INT_1_MASK, BIT_MDT_RCV_TIMEOUT 340 | BIT_MDT_RCV_SM_ABORT_PKT_RCVD | BIT_MDT_RCV_SM_ERROR 341 | BIT_MDT_XMIT_TIMEOUT | BIT_MDT_XMIT_SM_ABORT_PKT_RCVD 342 | BIT_MDT_XMIT_SM_ERROR, 343 REG_MDT_INT_0_MASK, BIT_MDT_XFIFO_EMPTY 344 | BIT_MDT_IDLE_AFTER_HAWB_DISABLE 345 | BIT_MDT_RFIFO_DATA_RDY 346 ); 347 sii8620_enable_gen2_write_burst(ctx); 348 } 349 350 static void sii8620_mt_msc_cmd_send(struct sii8620 *ctx, 351 struct sii8620_mt_msg *msg) 352 { 353 if (msg->reg[0] == MHL_SET_INT && 354 msg->reg[1] == MHL_INT_REG(RCHANGE) && 355 msg->reg[2] == MHL_INT_RC_FEAT_REQ) 356 sii8620_enable_gen2_write_burst(ctx); 357 else 358 sii8620_disable_gen2_write_burst(ctx); 359 360 switch (msg->reg[0]) { 361 case MHL_WRITE_STAT: 362 case MHL_SET_INT: 363 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg + 1, 2); 364 sii8620_write(ctx, REG_MSC_COMMAND_START, 365 BIT_MSC_COMMAND_START_WRITE_STAT); 366 break; 367 case MHL_MSC_MSG: 368 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg, 3); 369 sii8620_write(ctx, REG_MSC_COMMAND_START, 370 BIT_MSC_COMMAND_START_MSC_MSG); 371 break; 372 case MHL_READ_DEVCAP_REG: 373 case MHL_READ_XDEVCAP_REG: 374 sii8620_write(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg[1]); 375 sii8620_write(ctx, REG_MSC_COMMAND_START, 376 BIT_MSC_COMMAND_START_READ_DEVCAP); 377 break; 378 default: 379 dev_err(ctx->dev, "%s: command %#x not supported\n", __func__, 380 msg->reg[0]); 381 } 382 } 383 384 static struct sii8620_mt_msg *sii8620_mt_msg_new(struct sii8620 *ctx) 385 { 386 struct sii8620_mt_msg *msg = kzalloc(sizeof(*msg), GFP_KERNEL); 387 388 if (!msg) 389 ctx->error = -ENOMEM; 390 else 391 list_add_tail(&msg->node, &ctx->mt_queue); 392 393 return msg; 394 } 395 396 static void sii8620_mt_set_cont(struct sii8620 *ctx, sii8620_cb cont) 397 { 398 struct sii8620_mt_msg *msg; 399 400 if (ctx->error) 401 return; 402 403 if (list_empty(&ctx->mt_queue)) { 404 ctx->error = -EINVAL; 405 return; 406 } 407 msg = list_last_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 408 msg->continuation = cont; 409 } 410 411 static void sii8620_mt_msc_cmd(struct sii8620 *ctx, u8 cmd, u8 arg1, u8 arg2) 412 { 413 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 414 415 if (!msg) 416 return; 417 418 msg->reg[0] = cmd; 419 msg->reg[1] = arg1; 420 msg->reg[2] = arg2; 421 msg->send = sii8620_mt_msc_cmd_send; 422 } 423 424 static void sii8620_mt_write_stat(struct sii8620 *ctx, u8 reg, u8 val) 425 { 426 sii8620_mt_msc_cmd(ctx, MHL_WRITE_STAT, reg, val); 427 } 428 429 static inline void sii8620_mt_set_int(struct sii8620 *ctx, u8 irq, u8 mask) 430 { 431 sii8620_mt_msc_cmd(ctx, MHL_SET_INT, irq, mask); 432 } 433 434 static void sii8620_mt_msc_msg(struct sii8620 *ctx, u8 cmd, u8 data) 435 { 436 sii8620_mt_msc_cmd(ctx, MHL_MSC_MSG, cmd, data); 437 } 438 439 static void sii8620_mt_rap(struct sii8620 *ctx, u8 code) 440 { 441 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RAP, code); 442 } 443 444 static void sii8620_mt_rcpk(struct sii8620 *ctx, u8 code) 445 { 446 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPK, code); 447 } 448 449 static void sii8620_mt_rcpe(struct sii8620 *ctx, u8 code) 450 { 451 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPE, code); 452 } 453 454 static void sii8620_mt_read_devcap_send(struct sii8620 *ctx, 455 struct sii8620_mt_msg *msg) 456 { 457 u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP 458 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 459 | BIT_EDID_CTRL_EDID_MODE_EN; 460 461 if (msg->reg[0] == MHL_READ_XDEVCAP) 462 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN; 463 464 sii8620_write_seq(ctx, 465 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE, 466 REG_EDID_CTRL, ctrl, 467 REG_TPI_CBUS_START, BIT_TPI_CBUS_START_GET_DEVCAP_START 468 ); 469 } 470 471 /* copy src to dst and set changed bits in src */ 472 static void sii8620_update_array(u8 *dst, u8 *src, int count) 473 { 474 while (--count >= 0) { 475 *src ^= *dst; 476 *dst++ ^= *src++; 477 } 478 } 479 480 static void sii8620_identify_sink(struct sii8620 *ctx) 481 { 482 static const char * const sink_str[] = { 483 [SINK_NONE] = "NONE", 484 [SINK_HDMI] = "HDMI", 485 [SINK_DVI] = "DVI" 486 }; 487 488 char sink_name[20]; 489 struct device *dev = ctx->dev; 490 491 if (!ctx->sink_detected || !ctx->devcap_read) 492 return; 493 494 sii8620_fetch_edid(ctx); 495 if (!ctx->edid) { 496 dev_err(ctx->dev, "Cannot fetch EDID\n"); 497 sii8620_mhl_disconnected(ctx); 498 return; 499 } 500 sii8620_set_upstream_edid(ctx); 501 502 if (drm_detect_hdmi_monitor(ctx->edid)) 503 ctx->sink_type = SINK_HDMI; 504 else 505 ctx->sink_type = SINK_DVI; 506 507 drm_edid_get_monitor_name(ctx->edid, sink_name, ARRAY_SIZE(sink_name)); 508 509 dev_info(dev, "detected sink(type: %s): %s\n", 510 sink_str[ctx->sink_type], sink_name); 511 } 512 513 static void sii8620_mr_devcap(struct sii8620 *ctx) 514 { 515 u8 dcap[MHL_DCAP_SIZE]; 516 struct device *dev = ctx->dev; 517 518 sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, dcap, MHL_DCAP_SIZE); 519 if (ctx->error < 0) 520 return; 521 522 dev_info(dev, "detected dongle MHL %d.%d, ChipID %02x%02x:%02x%02x\n", 523 dcap[MHL_DCAP_MHL_VERSION] / 16, 524 dcap[MHL_DCAP_MHL_VERSION] % 16, 525 dcap[MHL_DCAP_ADOPTER_ID_H], dcap[MHL_DCAP_ADOPTER_ID_L], 526 dcap[MHL_DCAP_DEVICE_ID_H], dcap[MHL_DCAP_DEVICE_ID_L]); 527 sii8620_update_array(ctx->devcap, dcap, MHL_DCAP_SIZE); 528 ctx->devcap_read = true; 529 sii8620_identify_sink(ctx); 530 } 531 532 static void sii8620_mr_xdevcap(struct sii8620 *ctx) 533 { 534 sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, ctx->xdevcap, 535 MHL_XDC_SIZE); 536 } 537 538 static void sii8620_mt_read_devcap_recv(struct sii8620 *ctx, 539 struct sii8620_mt_msg *msg) 540 { 541 u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP 542 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 543 | BIT_EDID_CTRL_EDID_MODE_EN; 544 545 if (msg->reg[0] == MHL_READ_XDEVCAP) 546 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN; 547 548 sii8620_write_seq(ctx, 549 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE | BIT_INTR9_EDID_DONE 550 | BIT_INTR9_EDID_ERROR, 551 REG_EDID_CTRL, ctrl, 552 REG_EDID_FIFO_ADDR, 0 553 ); 554 555 if (msg->reg[0] == MHL_READ_XDEVCAP) 556 sii8620_mr_xdevcap(ctx); 557 else 558 sii8620_mr_devcap(ctx); 559 } 560 561 static void sii8620_mt_read_devcap(struct sii8620 *ctx, bool xdevcap) 562 { 563 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 564 565 if (!msg) 566 return; 567 568 msg->reg[0] = xdevcap ? MHL_READ_XDEVCAP : MHL_READ_DEVCAP; 569 msg->send = sii8620_mt_read_devcap_send; 570 msg->recv = sii8620_mt_read_devcap_recv; 571 } 572 573 static void sii8620_mt_read_devcap_reg_recv(struct sii8620 *ctx, 574 struct sii8620_mt_msg *msg) 575 { 576 u8 reg = msg->reg[1] & 0x7f; 577 578 if (msg->reg[1] & 0x80) 579 ctx->xdevcap[reg] = msg->ret; 580 else 581 ctx->devcap[reg] = msg->ret; 582 } 583 584 static void sii8620_mt_read_devcap_reg(struct sii8620 *ctx, u8 reg) 585 { 586 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 587 588 if (!msg) 589 return; 590 591 msg->reg[0] = (reg & 0x80) ? MHL_READ_XDEVCAP_REG : MHL_READ_DEVCAP_REG; 592 msg->reg[1] = reg; 593 msg->send = sii8620_mt_msc_cmd_send; 594 msg->recv = sii8620_mt_read_devcap_reg_recv; 595 } 596 597 static inline void sii8620_mt_read_xdevcap_reg(struct sii8620 *ctx, u8 reg) 598 { 599 sii8620_mt_read_devcap_reg(ctx, reg | 0x80); 600 } 601 602 static void *sii8620_burst_get_tx_buf(struct sii8620 *ctx, int len) 603 { 604 u8 *buf = &ctx->burst.tx_buf[ctx->burst.tx_count]; 605 int size = len + 2; 606 607 if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) { 608 dev_err(ctx->dev, "TX-BLK buffer exhausted\n"); 609 ctx->error = -EINVAL; 610 return NULL; 611 } 612 613 ctx->burst.tx_count += size; 614 buf[1] = len; 615 616 return buf + 2; 617 } 618 619 static u8 *sii8620_burst_get_rx_buf(struct sii8620 *ctx, int len) 620 { 621 u8 *buf = &ctx->burst.rx_buf[ctx->burst.rx_count]; 622 int size = len + 1; 623 624 if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) { 625 dev_err(ctx->dev, "RX-BLK buffer exhausted\n"); 626 ctx->error = -EINVAL; 627 return NULL; 628 } 629 630 ctx->burst.rx_count += size; 631 buf[0] = len; 632 633 return buf + 1; 634 } 635 636 static void sii8620_burst_send(struct sii8620 *ctx) 637 { 638 int tx_left = ctx->burst.tx_count; 639 u8 *d = ctx->burst.tx_buf; 640 641 while (tx_left > 0) { 642 int len = d[1] + 2; 643 644 if (ctx->burst.r_count + len > ctx->burst.r_size) 645 break; 646 d[0] = min(ctx->burst.rx_ack, 255); 647 ctx->burst.rx_ack -= d[0]; 648 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, d, len); 649 ctx->burst.r_count += len; 650 tx_left -= len; 651 d += len; 652 } 653 654 ctx->burst.tx_count = tx_left; 655 656 while (ctx->burst.rx_ack > 0) { 657 u8 b[2] = { min(ctx->burst.rx_ack, 255), 0 }; 658 659 if (ctx->burst.r_count + 2 > ctx->burst.r_size) 660 break; 661 ctx->burst.rx_ack -= b[0]; 662 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, b, 2); 663 ctx->burst.r_count += 2; 664 } 665 } 666 667 static void sii8620_burst_receive(struct sii8620 *ctx) 668 { 669 u8 buf[3], *d; 670 int count; 671 672 sii8620_read_buf(ctx, REG_EMSCRFIFOBCNTL, buf, 2); 673 count = get_unaligned_le16(buf); 674 while (count > 0) { 675 int len = min(count, 3); 676 677 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, buf, len); 678 count -= len; 679 ctx->burst.rx_ack += len - 1; 680 ctx->burst.r_count -= buf[1]; 681 if (ctx->burst.r_count < 0) 682 ctx->burst.r_count = 0; 683 684 if (len < 3 || !buf[2]) 685 continue; 686 687 len = buf[2]; 688 d = sii8620_burst_get_rx_buf(ctx, len); 689 if (!d) 690 continue; 691 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, d, len); 692 count -= len; 693 ctx->burst.rx_ack += len; 694 } 695 } 696 697 static void sii8620_burst_tx_rbuf_info(struct sii8620 *ctx, int size) 698 { 699 struct mhl_burst_blk_rcv_buffer_info *d = 700 sii8620_burst_get_tx_buf(ctx, sizeof(*d)); 701 if (!d) 702 return; 703 704 d->id = cpu_to_be16(MHL_BURST_ID_BLK_RCV_BUFFER_INFO); 705 d->size = cpu_to_le16(size); 706 } 707 708 static u8 sii8620_checksum(void *ptr, int size) 709 { 710 u8 *d = ptr, sum = 0; 711 712 while (size--) 713 sum += *d++; 714 715 return sum; 716 } 717 718 static void sii8620_mhl_burst_hdr_set(struct mhl3_burst_header *h, 719 enum mhl_burst_id id) 720 { 721 h->id = cpu_to_be16(id); 722 h->total_entries = 1; 723 h->sequence_index = 1; 724 } 725 726 static void sii8620_burst_tx_bits_per_pixel_fmt(struct sii8620 *ctx, u8 fmt) 727 { 728 struct mhl_burst_bits_per_pixel_fmt *d; 729 const int size = sizeof(*d) + sizeof(d->desc[0]); 730 731 d = sii8620_burst_get_tx_buf(ctx, size); 732 if (!d) 733 return; 734 735 sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_BITS_PER_PIXEL_FMT); 736 d->num_entries = 1; 737 d->desc[0].stream_id = 0; 738 d->desc[0].pixel_format = fmt; 739 d->hdr.checksum -= sii8620_checksum(d, size); 740 } 741 742 static void sii8620_burst_rx_all(struct sii8620 *ctx) 743 { 744 u8 *d = ctx->burst.rx_buf; 745 int count = ctx->burst.rx_count; 746 747 while (count-- > 0) { 748 int len = *d++; 749 int id = get_unaligned_be16(&d[0]); 750 751 switch (id) { 752 case MHL_BURST_ID_BLK_RCV_BUFFER_INFO: 753 ctx->burst.r_size = get_unaligned_le16(&d[2]); 754 break; 755 default: 756 break; 757 } 758 count -= len; 759 d += len; 760 } 761 ctx->burst.rx_count = 0; 762 } 763 764 static void sii8620_fetch_edid(struct sii8620 *ctx) 765 { 766 u8 lm_ddc, ddc_cmd, int3, cbus; 767 unsigned long timeout; 768 int fetched, i; 769 int edid_len = EDID_LENGTH; 770 u8 *edid; 771 772 sii8620_readb(ctx, REG_CBUS_STATUS); 773 lm_ddc = sii8620_readb(ctx, REG_LM_DDC); 774 ddc_cmd = sii8620_readb(ctx, REG_DDC_CMD); 775 776 sii8620_write_seq(ctx, 777 REG_INTR9_MASK, 0, 778 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO, 779 REG_HDCP2X_POLL_CS, 0x71, 780 REG_HDCP2X_CTRL_0, BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX, 781 REG_LM_DDC, lm_ddc | BIT_LM_DDC_SW_TPI_EN_DISABLED, 782 ); 783 784 for (i = 0; i < 256; ++i) { 785 u8 ddc_stat = sii8620_readb(ctx, REG_DDC_STATUS); 786 787 if (!(ddc_stat & BIT_DDC_STATUS_DDC_I2C_IN_PROG)) 788 break; 789 sii8620_write(ctx, REG_DDC_STATUS, 790 BIT_DDC_STATUS_DDC_FIFO_EMPTY); 791 } 792 793 sii8620_write(ctx, REG_DDC_ADDR, 0x50 << 1); 794 795 edid = kmalloc(EDID_LENGTH, GFP_KERNEL); 796 if (!edid) { 797 ctx->error = -ENOMEM; 798 return; 799 } 800 801 #define FETCH_SIZE 16 802 for (fetched = 0; fetched < edid_len; fetched += FETCH_SIZE) { 803 sii8620_readb(ctx, REG_DDC_STATUS); 804 sii8620_write_seq(ctx, 805 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_ABORT, 806 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_CLEAR_FIFO, 807 REG_DDC_STATUS, BIT_DDC_STATUS_DDC_FIFO_EMPTY 808 ); 809 sii8620_write_seq(ctx, 810 REG_DDC_SEGM, fetched >> 8, 811 REG_DDC_OFFSET, fetched & 0xff, 812 REG_DDC_DIN_CNT1, FETCH_SIZE, 813 REG_DDC_DIN_CNT2, 0, 814 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_ENH_DDC_READ_NO_ACK 815 ); 816 817 int3 = 0; 818 timeout = jiffies + msecs_to_jiffies(200); 819 for (;;) { 820 cbus = sii8620_readb(ctx, REG_CBUS_STATUS); 821 if (~cbus & BIT_CBUS_STATUS_CBUS_CONNECTED) { 822 kfree(edid); 823 edid = NULL; 824 goto end; 825 } 826 if (int3 & BIT_DDC_CMD_DONE) { 827 if (sii8620_readb(ctx, REG_DDC_DOUT_CNT) 828 >= FETCH_SIZE) 829 break; 830 } else { 831 int3 = sii8620_readb(ctx, REG_INTR3); 832 } 833 if (time_is_before_jiffies(timeout)) { 834 ctx->error = -ETIMEDOUT; 835 dev_err(ctx->dev, "timeout during EDID read\n"); 836 kfree(edid); 837 edid = NULL; 838 goto end; 839 } 840 usleep_range(10, 20); 841 } 842 843 sii8620_read_buf(ctx, REG_DDC_DATA, edid + fetched, FETCH_SIZE); 844 if (fetched + FETCH_SIZE == EDID_LENGTH) { 845 u8 ext = ((struct edid *)edid)->extensions; 846 847 if (ext) { 848 u8 *new_edid; 849 850 edid_len += ext * EDID_LENGTH; 851 new_edid = krealloc(edid, edid_len, GFP_KERNEL); 852 if (!new_edid) { 853 kfree(edid); 854 ctx->error = -ENOMEM; 855 return; 856 } 857 edid = new_edid; 858 } 859 } 860 } 861 862 sii8620_write_seq(ctx, 863 REG_INTR3_MASK, BIT_DDC_CMD_DONE, 864 REG_LM_DDC, lm_ddc 865 ); 866 867 end: 868 kfree(ctx->edid); 869 ctx->edid = (struct edid *)edid; 870 } 871 872 static void sii8620_set_upstream_edid(struct sii8620 *ctx) 873 { 874 sii8620_setbits(ctx, REG_DPD, BIT_DPD_PDNRX12 | BIT_DPD_PDIDCK_N 875 | BIT_DPD_PD_MHL_CLK_N, 0xff); 876 877 sii8620_write_seq_static(ctx, 878 REG_RX_HDMI_CTRL3, 0x00, 879 REG_PKT_FILTER_0, 0xFF, 880 REG_PKT_FILTER_1, 0xFF, 881 REG_ALICE0_BW_I2C, 0x06 882 ); 883 884 sii8620_setbits(ctx, REG_RX_HDMI_CLR_BUFFER, 885 BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN, 0xff); 886 887 sii8620_write_seq_static(ctx, 888 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 889 | BIT_EDID_CTRL_EDID_MODE_EN, 890 REG_EDID_FIFO_ADDR, 0, 891 ); 892 893 sii8620_write_buf(ctx, REG_EDID_FIFO_WR_DATA, (u8 *)ctx->edid, 894 (ctx->edid->extensions + 1) * EDID_LENGTH); 895 896 sii8620_write_seq_static(ctx, 897 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID 898 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 899 | BIT_EDID_CTRL_EDID_MODE_EN, 900 REG_INTR5_MASK, BIT_INTR_SCDT_CHANGE, 901 REG_INTR9_MASK, 0 902 ); 903 } 904 905 static void sii8620_xtal_set_rate(struct sii8620 *ctx) 906 { 907 static const struct { 908 unsigned int rate; 909 u8 div; 910 u8 tp1; 911 } rates[] = { 912 { 19200, 0x04, 0x53 }, 913 { 20000, 0x04, 0x62 }, 914 { 24000, 0x05, 0x75 }, 915 { 30000, 0x06, 0x92 }, 916 { 38400, 0x0c, 0xbc }, 917 }; 918 unsigned long rate = clk_get_rate(ctx->clk_xtal) / 1000; 919 int i; 920 921 for (i = 0; i < ARRAY_SIZE(rates) - 1; ++i) 922 if (rate <= rates[i].rate) 923 break; 924 925 if (rate != rates[i].rate) 926 dev_err(ctx->dev, "xtal clock rate(%lukHz) not supported, setting MHL for %ukHz.\n", 927 rate, rates[i].rate); 928 929 sii8620_write(ctx, REG_DIV_CTL_MAIN, rates[i].div); 930 sii8620_write(ctx, REG_HDCP2X_TP1, rates[i].tp1); 931 } 932 933 static int sii8620_hw_on(struct sii8620 *ctx) 934 { 935 int ret; 936 937 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 938 if (ret) 939 return ret; 940 941 usleep_range(10000, 20000); 942 ret = clk_prepare_enable(ctx->clk_xtal); 943 if (ret) 944 return ret; 945 946 msleep(100); 947 gpiod_set_value(ctx->gpio_reset, 0); 948 msleep(100); 949 950 return 0; 951 } 952 953 static int sii8620_hw_off(struct sii8620 *ctx) 954 { 955 clk_disable_unprepare(ctx->clk_xtal); 956 gpiod_set_value(ctx->gpio_reset, 1); 957 return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 958 } 959 960 static void sii8620_cbus_reset(struct sii8620 *ctx) 961 { 962 sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST 963 | BIT_PWD_SRST_CBUS_RST_SW_EN); 964 usleep_range(10000, 20000); 965 sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN); 966 } 967 968 static void sii8620_set_auto_zone(struct sii8620 *ctx) 969 { 970 if (ctx->mode != CM_MHL1) { 971 sii8620_write_seq_static(ctx, 972 REG_TX_ZONE_CTL1, 0x0, 973 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 974 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 975 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE 976 ); 977 } else { 978 sii8620_write_seq_static(ctx, 979 REG_TX_ZONE_CTL1, VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE, 980 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 981 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE 982 ); 983 } 984 } 985 986 static void sii8620_stop_video(struct sii8620 *ctx) 987 { 988 u8 uninitialized_var(val); 989 990 sii8620_write_seq_static(ctx, 991 REG_TPI_INTR_EN, 0, 992 REG_HDCP2X_INTR0_MASK, 0, 993 REG_TPI_COPP_DATA2, 0, 994 REG_TPI_INTR_ST0, ~0, 995 ); 996 997 switch (ctx->sink_type) { 998 case SINK_DVI: 999 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN 1000 | BIT_TPI_SC_TPI_AV_MUTE; 1001 break; 1002 case SINK_HDMI: 1003 default: 1004 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN 1005 | BIT_TPI_SC_TPI_AV_MUTE 1006 | BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI; 1007 break; 1008 } 1009 1010 sii8620_write(ctx, REG_TPI_SC, val); 1011 } 1012 1013 static void sii8620_set_format(struct sii8620 *ctx) 1014 { 1015 u8 out_fmt; 1016 1017 if (sii8620_is_mhl3(ctx)) { 1018 sii8620_setbits(ctx, REG_M3_P0CTRL, 1019 BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED, 1020 ctx->use_packed_pixel ? ~0 : 0); 1021 } else { 1022 if (ctx->use_packed_pixel) { 1023 sii8620_write_seq_static(ctx, 1024 REG_VID_MODE, BIT_VID_MODE_M1080P, 1025 REG_MHL_TOP_CTL, BIT_MHL_TOP_CTL_MHL_PP_SEL | 1, 1026 REG_MHLTX_CTL6, 0x60 1027 ); 1028 } else { 1029 sii8620_write_seq_static(ctx, 1030 REG_VID_MODE, 0, 1031 REG_MHL_TOP_CTL, 1, 1032 REG_MHLTX_CTL6, 0xa0 1033 ); 1034 } 1035 } 1036 1037 if (ctx->use_packed_pixel) 1038 out_fmt = VAL_TPI_FORMAT(YCBCR422, FULL); 1039 else 1040 out_fmt = VAL_TPI_FORMAT(RGB, FULL); 1041 1042 sii8620_write_seq(ctx, 1043 REG_TPI_INPUT, VAL_TPI_FORMAT(RGB, FULL), 1044 REG_TPI_OUTPUT, out_fmt, 1045 ); 1046 } 1047 1048 static int mhl3_infoframe_init(struct mhl3_infoframe *frame) 1049 { 1050 memset(frame, 0, sizeof(*frame)); 1051 1052 frame->version = 3; 1053 frame->hev_format = -1; 1054 return 0; 1055 } 1056 1057 static ssize_t mhl3_infoframe_pack(struct mhl3_infoframe *frame, 1058 void *buffer, size_t size) 1059 { 1060 const int frm_len = HDMI_INFOFRAME_HEADER_SIZE + MHL3_INFOFRAME_SIZE; 1061 u8 *ptr = buffer; 1062 1063 if (size < frm_len) 1064 return -ENOSPC; 1065 1066 memset(buffer, 0, size); 1067 ptr[0] = HDMI_INFOFRAME_TYPE_VENDOR; 1068 ptr[1] = frame->version; 1069 ptr[2] = MHL3_INFOFRAME_SIZE; 1070 ptr[4] = MHL3_IEEE_OUI & 0xff; 1071 ptr[5] = (MHL3_IEEE_OUI >> 8) & 0xff; 1072 ptr[6] = (MHL3_IEEE_OUI >> 16) & 0xff; 1073 ptr[7] = frame->video_format & 0x3; 1074 ptr[7] |= (frame->format_type & 0x7) << 2; 1075 ptr[7] |= frame->sep_audio ? BIT(5) : 0; 1076 if (frame->hev_format >= 0) { 1077 ptr[9] = 1; 1078 ptr[10] = (frame->hev_format >> 8) & 0xff; 1079 ptr[11] = frame->hev_format & 0xff; 1080 } 1081 if (frame->av_delay) { 1082 bool sign = frame->av_delay < 0; 1083 int delay = sign ? -frame->av_delay : frame->av_delay; 1084 1085 ptr[12] = (delay >> 16) & 0xf; 1086 if (sign) 1087 ptr[12] |= BIT(4); 1088 ptr[13] = (delay >> 8) & 0xff; 1089 ptr[14] = delay & 0xff; 1090 } 1091 ptr[3] -= sii8620_checksum(buffer, frm_len); 1092 return frm_len; 1093 } 1094 1095 static void sii8620_set_infoframes(struct sii8620 *ctx, 1096 struct drm_display_mode *mode) 1097 { 1098 struct mhl3_infoframe mhl_frm; 1099 union hdmi_infoframe frm; 1100 u8 buf[31]; 1101 int ret; 1102 1103 ret = drm_hdmi_avi_infoframe_from_display_mode(&frm.avi, 1104 NULL, mode); 1105 if (ctx->use_packed_pixel) 1106 frm.avi.colorspace = HDMI_COLORSPACE_YUV422; 1107 1108 if (!ret) 1109 ret = hdmi_avi_infoframe_pack(&frm.avi, buf, ARRAY_SIZE(buf)); 1110 if (ret > 0) 1111 sii8620_write_buf(ctx, REG_TPI_AVI_CHSUM, buf + 3, ret - 3); 1112 1113 if (!sii8620_is_mhl3(ctx) || !ctx->use_packed_pixel) { 1114 sii8620_write(ctx, REG_TPI_SC, 1115 BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI); 1116 sii8620_write(ctx, REG_PKT_FILTER_0, 1117 BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT | 1118 BIT_PKT_FILTER_0_DROP_MPEG_PKT | 1119 BIT_PKT_FILTER_0_DROP_GCP_PKT, 1120 BIT_PKT_FILTER_1_DROP_GEN_PKT); 1121 return; 1122 } 1123 1124 sii8620_write(ctx, REG_PKT_FILTER_0, 1125 BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT | 1126 BIT_PKT_FILTER_0_DROP_MPEG_PKT | 1127 BIT_PKT_FILTER_0_DROP_AVI_PKT | 1128 BIT_PKT_FILTER_0_DROP_GCP_PKT, 1129 BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS | 1130 BIT_PKT_FILTER_1_DROP_GEN_PKT | 1131 BIT_PKT_FILTER_1_DROP_VSIF_PKT); 1132 1133 sii8620_write(ctx, REG_TPI_INFO_FSEL, BIT_TPI_INFO_FSEL_EN 1134 | BIT_TPI_INFO_FSEL_RPT | VAL_TPI_INFO_FSEL_VSI); 1135 ret = mhl3_infoframe_init(&mhl_frm); 1136 if (!ret) 1137 ret = mhl3_infoframe_pack(&mhl_frm, buf, ARRAY_SIZE(buf)); 1138 sii8620_write_buf(ctx, REG_TPI_INFO_B0, buf, ret); 1139 } 1140 1141 static void sii8620_start_video(struct sii8620 *ctx) 1142 { 1143 struct drm_display_mode *mode = 1144 &ctx->bridge.encoder->crtc->state->adjusted_mode; 1145 1146 if (!sii8620_is_mhl3(ctx)) 1147 sii8620_stop_video(ctx); 1148 1149 if (ctx->sink_type == SINK_DVI && !sii8620_is_mhl3(ctx)) { 1150 sii8620_write(ctx, REG_RX_HDMI_CTRL2, 1151 VAL_RX_HDMI_CTRL2_DEFVAL); 1152 sii8620_write(ctx, REG_TPI_SC, 0); 1153 return; 1154 } 1155 1156 sii8620_write_seq_static(ctx, 1157 REG_RX_HDMI_CTRL2, VAL_RX_HDMI_CTRL2_DEFVAL 1158 | BIT_RX_HDMI_CTRL2_USE_AV_MUTE, 1159 REG_VID_OVRRD, BIT_VID_OVRRD_PP_AUTO_DISABLE 1160 | BIT_VID_OVRRD_M1080P_OVRRD); 1161 sii8620_set_format(ctx); 1162 1163 if (!sii8620_is_mhl3(ctx)) { 1164 u8 link_mode = MHL_DST_LM_PATH_ENABLED; 1165 1166 if (ctx->use_packed_pixel) 1167 link_mode |= MHL_DST_LM_CLK_MODE_PACKED_PIXEL; 1168 else 1169 link_mode |= MHL_DST_LM_CLK_MODE_NORMAL; 1170 1171 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE), link_mode); 1172 sii8620_set_auto_zone(ctx); 1173 } else { 1174 static const struct { 1175 int max_clk; 1176 u8 zone; 1177 u8 link_rate; 1178 u8 rrp_decode; 1179 } clk_spec[] = { 1180 { 150000, VAL_TX_ZONE_CTL3_TX_ZONE_1_5GBPS, 1181 MHL_XDS_LINK_RATE_1_5_GBPS, 0x38 }, 1182 { 300000, VAL_TX_ZONE_CTL3_TX_ZONE_3GBPS, 1183 MHL_XDS_LINK_RATE_3_0_GBPS, 0x40 }, 1184 { 600000, VAL_TX_ZONE_CTL3_TX_ZONE_6GBPS, 1185 MHL_XDS_LINK_RATE_6_0_GBPS, 0x40 }, 1186 }; 1187 u8 p0_ctrl = BIT_M3_P0CTRL_MHL3_P0_PORT_EN; 1188 int clk = mode->clock * (ctx->use_packed_pixel ? 2 : 3); 1189 int i; 1190 1191 for (i = 0; i < ARRAY_SIZE(clk_spec) - 1; ++i) 1192 if (clk < clk_spec[i].max_clk) 1193 break; 1194 1195 if (100 * clk >= 98 * clk_spec[i].max_clk) 1196 p0_ctrl |= BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN; 1197 1198 sii8620_burst_tx_bits_per_pixel_fmt(ctx, ctx->use_packed_pixel); 1199 sii8620_burst_send(ctx); 1200 sii8620_write_seq(ctx, 1201 REG_MHL_DP_CTL0, 0xf0, 1202 REG_MHL3_TX_ZONE_CTL, clk_spec[i].zone); 1203 sii8620_setbits(ctx, REG_M3_P0CTRL, 1204 BIT_M3_P0CTRL_MHL3_P0_PORT_EN 1205 | BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN, p0_ctrl); 1206 sii8620_setbits(ctx, REG_M3_POSTM, MSK_M3_POSTM_RRP_DECODE, 1207 clk_spec[i].rrp_decode); 1208 sii8620_write_seq_static(ctx, 1209 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE 1210 | BIT_M3_CTRL_H2M_SWRST, 1211 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE 1212 ); 1213 sii8620_mt_write_stat(ctx, MHL_XDS_REG(AVLINK_MODE_CONTROL), 1214 clk_spec[i].link_rate); 1215 } 1216 1217 sii8620_set_infoframes(ctx, mode); 1218 } 1219 1220 static void sii8620_disable_hpd(struct sii8620 *ctx) 1221 { 1222 sii8620_setbits(ctx, REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID, 0); 1223 sii8620_write_seq_static(ctx, 1224 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN, 1225 REG_INTR8_MASK, 0 1226 ); 1227 } 1228 1229 static void sii8620_enable_hpd(struct sii8620 *ctx) 1230 { 1231 sii8620_setbits(ctx, REG_TMDS_CSTAT_P3, 1232 BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS 1233 | BIT_TMDS_CSTAT_P3_CLR_AVI, ~0); 1234 sii8620_write_seq_static(ctx, 1235 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN 1236 | BIT_HPD_CTRL_HPD_HIGH, 1237 ); 1238 } 1239 1240 static void sii8620_mhl_discover(struct sii8620 *ctx) 1241 { 1242 sii8620_write_seq_static(ctx, 1243 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1244 | BIT_DISC_CTRL9_DISC_PULSE_PROCEED, 1245 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_5K, VAL_PUP_20K), 1246 REG_CBUS_DISC_INTR0_MASK, BIT_MHL3_EST_INT 1247 | BIT_MHL_EST_INT 1248 | BIT_NOT_MHL_EST_INT 1249 | BIT_CBUS_MHL3_DISCON_INT 1250 | BIT_CBUS_MHL12_DISCON_INT 1251 | BIT_RGND_READY_INT, 1252 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 1253 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 1254 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE, 1255 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE 1256 | BIT_MHL_DP_CTL0_TX_OE_OVR, 1257 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE, 1258 REG_MHL_DP_CTL1, 0xA2, 1259 REG_MHL_DP_CTL2, 0x03, 1260 REG_MHL_DP_CTL3, 0x35, 1261 REG_MHL_DP_CTL5, 0x02, 1262 REG_MHL_DP_CTL6, 0x02, 1263 REG_MHL_DP_CTL7, 0x03, 1264 REG_COC_CTLC, 0xFF, 1265 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 1266 | BIT_DPD_OSC_EN | BIT_DPD_PWRON_HSIC, 1267 REG_COC_INTR_MASK, BIT_COC_PLL_LOCK_STATUS_CHANGE 1268 | BIT_COC_CALIBRATION_DONE, 1269 REG_CBUS_INT_1_MASK, BIT_CBUS_MSC_ABORT_RCVD 1270 | BIT_CBUS_CMD_ABORT, 1271 REG_CBUS_INT_0_MASK, BIT_CBUS_MSC_MT_DONE 1272 | BIT_CBUS_HPD_CHG 1273 | BIT_CBUS_MSC_MR_WRITE_STAT 1274 | BIT_CBUS_MSC_MR_MSC_MSG 1275 | BIT_CBUS_MSC_MR_WRITE_BURST 1276 | BIT_CBUS_MSC_MR_SET_INT 1277 | BIT_CBUS_MSC_MT_DONE_NACK 1278 ); 1279 } 1280 1281 static void sii8620_peer_specific_init(struct sii8620 *ctx) 1282 { 1283 if (sii8620_is_mhl3(ctx)) 1284 sii8620_write_seq_static(ctx, 1285 REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD, 1286 REG_EMSCINTRMASK1, 1287 BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR 1288 ); 1289 else 1290 sii8620_write_seq_static(ctx, 1291 REG_HDCP2X_INTR0_MASK, 0x00, 1292 REG_EMSCINTRMASK1, 0x00, 1293 REG_HDCP2X_INTR0, 0xFF, 1294 REG_INTR1, 0xFF, 1295 REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD 1296 | BIT_SYS_CTRL1_TX_CTRL_HDMI 1297 ); 1298 } 1299 1300 #define SII8620_MHL_VERSION 0x32 1301 #define SII8620_SCRATCHPAD_SIZE 16 1302 #define SII8620_INT_STAT_SIZE 0x33 1303 1304 static void sii8620_set_dev_cap(struct sii8620 *ctx) 1305 { 1306 static const u8 devcap[MHL_DCAP_SIZE] = { 1307 [MHL_DCAP_MHL_VERSION] = SII8620_MHL_VERSION, 1308 [MHL_DCAP_CAT] = MHL_DCAP_CAT_SOURCE | MHL_DCAP_CAT_POWER, 1309 [MHL_DCAP_ADOPTER_ID_H] = 0x01, 1310 [MHL_DCAP_ADOPTER_ID_L] = 0x41, 1311 [MHL_DCAP_VID_LINK_MODE] = MHL_DCAP_VID_LINK_RGB444 1312 | MHL_DCAP_VID_LINK_PPIXEL 1313 | MHL_DCAP_VID_LINK_16BPP, 1314 [MHL_DCAP_AUD_LINK_MODE] = MHL_DCAP_AUD_LINK_2CH, 1315 [MHL_DCAP_VIDEO_TYPE] = MHL_DCAP_VT_GRAPHICS, 1316 [MHL_DCAP_LOG_DEV_MAP] = MHL_DCAP_LD_GUI, 1317 [MHL_DCAP_BANDWIDTH] = 0x0f, 1318 [MHL_DCAP_FEATURE_FLAG] = MHL_DCAP_FEATURE_RCP_SUPPORT 1319 | MHL_DCAP_FEATURE_RAP_SUPPORT 1320 | MHL_DCAP_FEATURE_SP_SUPPORT, 1321 [MHL_DCAP_SCRATCHPAD_SIZE] = SII8620_SCRATCHPAD_SIZE, 1322 [MHL_DCAP_INT_STAT_SIZE] = SII8620_INT_STAT_SIZE, 1323 }; 1324 static const u8 xdcap[MHL_XDC_SIZE] = { 1325 [MHL_XDC_ECBUS_SPEEDS] = MHL_XDC_ECBUS_S_075 1326 | MHL_XDC_ECBUS_S_8BIT, 1327 [MHL_XDC_TMDS_SPEEDS] = MHL_XDC_TMDS_150 1328 | MHL_XDC_TMDS_300 | MHL_XDC_TMDS_600, 1329 [MHL_XDC_ECBUS_ROLES] = MHL_XDC_DEV_HOST, 1330 [MHL_XDC_LOG_DEV_MAPX] = MHL_XDC_LD_PHONE, 1331 }; 1332 1333 sii8620_write_buf(ctx, REG_MHL_DEVCAP_0, devcap, ARRAY_SIZE(devcap)); 1334 sii8620_write_buf(ctx, REG_MHL_EXTDEVCAP_0, xdcap, ARRAY_SIZE(xdcap)); 1335 } 1336 1337 static void sii8620_mhl_init(struct sii8620 *ctx) 1338 { 1339 sii8620_write_seq_static(ctx, 1340 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1341 REG_CBUS_MSC_COMPAT_CTRL, 1342 BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN, 1343 ); 1344 1345 sii8620_peer_specific_init(ctx); 1346 1347 sii8620_disable_hpd(ctx); 1348 1349 sii8620_write_seq_static(ctx, 1350 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO, 1351 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1352 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1353 REG_TMDS0_CCTRL1, 0x90, 1354 REG_TMDS_CLK_EN, 0x01, 1355 REG_TMDS_CH_EN, 0x11, 1356 REG_BGR_BIAS, 0x87, 1357 REG_ALICE0_ZONE_CTRL, 0xE8, 1358 REG_ALICE0_MODE_CTRL, 0x04, 1359 ); 1360 sii8620_setbits(ctx, REG_LM_DDC, BIT_LM_DDC_SW_TPI_EN_DISABLED, 0); 1361 sii8620_write_seq_static(ctx, 1362 REG_TPI_HW_OPT3, 0x76, 1363 REG_TMDS_CCTRL, BIT_TMDS_CCTRL_TMDS_OE, 1364 REG_TPI_DTD_B2, 79, 1365 ); 1366 sii8620_set_dev_cap(ctx); 1367 sii8620_write_seq_static(ctx, 1368 REG_MDT_XMIT_TIMEOUT, 100, 1369 REG_MDT_XMIT_CTRL, 0x03, 1370 REG_MDT_XFIFO_STAT, 0x00, 1371 REG_MDT_RCV_TIMEOUT, 100, 1372 REG_CBUS_LINK_CTRL_8, 0x1D, 1373 ); 1374 1375 sii8620_start_gen2_write_burst(ctx); 1376 sii8620_write_seq_static(ctx, 1377 REG_BIST_CTRL, 0x00, 1378 REG_COC_CTL1, 0x10, 1379 REG_COC_CTL2, 0x18, 1380 REG_COC_CTLF, 0x07, 1381 REG_COC_CTL11, 0xF8, 1382 REG_COC_CTL17, 0x61, 1383 REG_COC_CTL18, 0x46, 1384 REG_COC_CTL19, 0x15, 1385 REG_COC_CTL1A, 0x01, 1386 REG_MHL_COC_CTL3, BIT_MHL_COC_CTL3_COC_AECHO_EN, 1387 REG_MHL_COC_CTL4, 0x2D, 1388 REG_MHL_COC_CTL5, 0xF9, 1389 REG_MSC_HEARTBEAT_CTRL, 0x27, 1390 ); 1391 sii8620_disable_gen2_write_burst(ctx); 1392 1393 sii8620_mt_write_stat(ctx, MHL_DST_REG(VERSION), SII8620_MHL_VERSION); 1394 sii8620_mt_write_stat(ctx, MHL_DST_REG(CONNECTED_RDY), 1395 MHL_DST_CONN_DCAP_RDY | MHL_DST_CONN_XDEVCAPP_SUPP 1396 | MHL_DST_CONN_POW_STAT); 1397 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), MHL_INT_RC_DCAP_CHG); 1398 } 1399 1400 static void sii8620_emsc_enable(struct sii8620 *ctx) 1401 { 1402 u8 reg; 1403 1404 sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_EMSC_EN 1405 | BIT_GENCTL_CLR_EMSC_RFIFO 1406 | BIT_GENCTL_CLR_EMSC_XFIFO, ~0); 1407 sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_CLR_EMSC_RFIFO 1408 | BIT_GENCTL_CLR_EMSC_XFIFO, 0); 1409 sii8620_setbits(ctx, REG_COMMECNT, BIT_COMMECNT_I2C_TO_EMSC_EN, ~0); 1410 reg = sii8620_readb(ctx, REG_EMSCINTR); 1411 sii8620_write(ctx, REG_EMSCINTR, reg); 1412 sii8620_write(ctx, REG_EMSCINTRMASK, BIT_EMSCINTR_SPI_DVLD); 1413 } 1414 1415 static int sii8620_wait_for_fsm_state(struct sii8620 *ctx, u8 state) 1416 { 1417 int i; 1418 1419 for (i = 0; i < 10; ++i) { 1420 u8 s = sii8620_readb(ctx, REG_COC_STAT_0); 1421 1422 if ((s & MSK_COC_STAT_0_FSM_STATE) == state) 1423 return 0; 1424 if (!(s & BIT_COC_STAT_0_PLL_LOCKED)) 1425 return -EBUSY; 1426 usleep_range(4000, 6000); 1427 } 1428 return -ETIMEDOUT; 1429 } 1430 1431 static void sii8620_set_mode(struct sii8620 *ctx, enum sii8620_mode mode) 1432 { 1433 int ret; 1434 1435 if (ctx->mode == mode) 1436 return; 1437 1438 switch (mode) { 1439 case CM_MHL1: 1440 sii8620_write_seq_static(ctx, 1441 REG_CBUS_MSC_COMPAT_CTRL, 0x02, 1442 REG_M3_CTRL, VAL_M3_CTRL_MHL1_2_VALUE, 1443 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 1444 | BIT_DPD_OSC_EN, 1445 REG_COC_INTR_MASK, 0 1446 ); 1447 ctx->mode = mode; 1448 break; 1449 case CM_MHL3: 1450 sii8620_write(ctx, REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE); 1451 ctx->mode = mode; 1452 return; 1453 case CM_ECBUS_S: 1454 sii8620_emsc_enable(ctx); 1455 sii8620_write_seq_static(ctx, 1456 REG_TTXSPINUMS, 4, 1457 REG_TRXSPINUMS, 4, 1458 REG_TTXHSICNUMS, 0x14, 1459 REG_TRXHSICNUMS, 0x14, 1460 REG_TTXTOTNUMS, 0x18, 1461 REG_TRXTOTNUMS, 0x18, 1462 REG_PWD_SRST, BIT_PWD_SRST_COC_DOC_RST 1463 | BIT_PWD_SRST_CBUS_RST_SW_EN, 1464 REG_MHL_COC_CTL1, 0xbd, 1465 REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN, 1466 REG_COC_CTLB, 0x01, 1467 REG_COC_CTL0, 0x5c, 1468 REG_COC_CTL14, 0x03, 1469 REG_COC_CTL15, 0x80, 1470 REG_MHL_DP_CTL6, BIT_MHL_DP_CTL6_DP_TAP1_SGN 1471 | BIT_MHL_DP_CTL6_DP_TAP1_EN 1472 | BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN, 1473 REG_MHL_DP_CTL8, 0x03 1474 ); 1475 ret = sii8620_wait_for_fsm_state(ctx, 0x03); 1476 sii8620_write_seq_static(ctx, 1477 REG_COC_CTL14, 0x00, 1478 REG_COC_CTL15, 0x80 1479 ); 1480 if (!ret) 1481 sii8620_write(ctx, REG_CBUS3_CNVT, 0x85); 1482 else 1483 sii8620_disconnect(ctx); 1484 return; 1485 case CM_DISCONNECTED: 1486 ctx->mode = mode; 1487 break; 1488 default: 1489 dev_err(ctx->dev, "%s mode %d not supported\n", __func__, mode); 1490 break; 1491 } 1492 1493 sii8620_set_auto_zone(ctx); 1494 1495 if (mode != CM_MHL1) 1496 return; 1497 1498 sii8620_write_seq_static(ctx, 1499 REG_MHL_DP_CTL0, 0xBC, 1500 REG_MHL_DP_CTL1, 0xBB, 1501 REG_MHL_DP_CTL3, 0x48, 1502 REG_MHL_DP_CTL5, 0x39, 1503 REG_MHL_DP_CTL2, 0x2A, 1504 REG_MHL_DP_CTL6, 0x2A, 1505 REG_MHL_DP_CTL7, 0x08 1506 ); 1507 } 1508 1509 static void sii8620_hpd_unplugged(struct sii8620 *ctx) 1510 { 1511 sii8620_disable_hpd(ctx); 1512 ctx->sink_type = SINK_NONE; 1513 ctx->sink_detected = false; 1514 ctx->feature_complete = false; 1515 kfree(ctx->edid); 1516 ctx->edid = NULL; 1517 } 1518 1519 static void sii8620_disconnect(struct sii8620 *ctx) 1520 { 1521 sii8620_disable_gen2_write_burst(ctx); 1522 sii8620_stop_video(ctx); 1523 msleep(100); 1524 sii8620_cbus_reset(ctx); 1525 sii8620_set_mode(ctx, CM_DISCONNECTED); 1526 sii8620_write_seq_static(ctx, 1527 REG_TX_ZONE_CTL1, 0, 1528 REG_MHL_PLL_CTL0, 0x07, 1529 REG_COC_CTL0, 0x40, 1530 REG_CBUS3_CNVT, 0x84, 1531 REG_COC_CTL14, 0x00, 1532 REG_COC_CTL0, 0x40, 1533 REG_HRXCTRL3, 0x07, 1534 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 1535 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 1536 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE, 1537 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE 1538 | BIT_MHL_DP_CTL0_TX_OE_OVR, 1539 REG_MHL_DP_CTL1, 0xBB, 1540 REG_MHL_DP_CTL3, 0x48, 1541 REG_MHL_DP_CTL5, 0x3F, 1542 REG_MHL_DP_CTL2, 0x2F, 1543 REG_MHL_DP_CTL6, 0x2A, 1544 REG_MHL_DP_CTL7, 0x03 1545 ); 1546 sii8620_hpd_unplugged(ctx); 1547 sii8620_write_seq_static(ctx, 1548 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE, 1549 REG_MHL_COC_CTL1, 0x07, 1550 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1551 REG_DISC_CTRL8, 0x00, 1552 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1553 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1554 REG_INT_CTRL, 0x00, 1555 REG_MSC_HEARTBEAT_CTRL, 0x27, 1556 REG_DISC_CTRL1, 0x25, 1557 REG_CBUS_DISC_INTR0, (u8)~BIT_RGND_READY_INT, 1558 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT, 1559 REG_MDT_INT_1, 0xff, 1560 REG_MDT_INT_1_MASK, 0x00, 1561 REG_MDT_INT_0, 0xff, 1562 REG_MDT_INT_0_MASK, 0x00, 1563 REG_COC_INTR, 0xff, 1564 REG_COC_INTR_MASK, 0x00, 1565 REG_TRXINTH, 0xff, 1566 REG_TRXINTMH, 0x00, 1567 REG_CBUS_INT_0, 0xff, 1568 REG_CBUS_INT_0_MASK, 0x00, 1569 REG_CBUS_INT_1, 0xff, 1570 REG_CBUS_INT_1_MASK, 0x00, 1571 REG_EMSCINTR, 0xff, 1572 REG_EMSCINTRMASK, 0x00, 1573 REG_EMSCINTR1, 0xff, 1574 REG_EMSCINTRMASK1, 0x00, 1575 REG_INTR8, 0xff, 1576 REG_INTR8_MASK, 0x00, 1577 REG_TPI_INTR_ST0, 0xff, 1578 REG_TPI_INTR_EN, 0x00, 1579 REG_HDCP2X_INTR0, 0xff, 1580 REG_HDCP2X_INTR0_MASK, 0x00, 1581 REG_INTR9, 0xff, 1582 REG_INTR9_MASK, 0x00, 1583 REG_INTR3, 0xff, 1584 REG_INTR3_MASK, 0x00, 1585 REG_INTR5, 0xff, 1586 REG_INTR5_MASK, 0x00, 1587 REG_INTR2, 0xff, 1588 REG_INTR2_MASK, 0x00, 1589 ); 1590 memset(ctx->stat, 0, sizeof(ctx->stat)); 1591 memset(ctx->xstat, 0, sizeof(ctx->xstat)); 1592 memset(ctx->devcap, 0, sizeof(ctx->devcap)); 1593 memset(ctx->xdevcap, 0, sizeof(ctx->xdevcap)); 1594 ctx->devcap_read = false; 1595 ctx->cbus_status = 0; 1596 sii8620_mt_cleanup(ctx); 1597 } 1598 1599 static void sii8620_mhl_disconnected(struct sii8620 *ctx) 1600 { 1601 sii8620_write_seq_static(ctx, 1602 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1603 REG_CBUS_MSC_COMPAT_CTRL, 1604 BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN 1605 ); 1606 sii8620_disconnect(ctx); 1607 } 1608 1609 static void sii8620_irq_disc(struct sii8620 *ctx) 1610 { 1611 u8 stat = sii8620_readb(ctx, REG_CBUS_DISC_INTR0); 1612 1613 if (stat & VAL_CBUS_MHL_DISCON) 1614 sii8620_mhl_disconnected(ctx); 1615 1616 if (stat & BIT_RGND_READY_INT) { 1617 u8 stat2 = sii8620_readb(ctx, REG_DISC_STAT2); 1618 1619 if ((stat2 & MSK_DISC_STAT2_RGND) == VAL_RGND_1K) { 1620 sii8620_mhl_discover(ctx); 1621 } else { 1622 sii8620_write_seq_static(ctx, 1623 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1624 | BIT_DISC_CTRL9_NOMHL_EST 1625 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1626 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT 1627 | BIT_CBUS_MHL3_DISCON_INT 1628 | BIT_CBUS_MHL12_DISCON_INT 1629 | BIT_NOT_MHL_EST_INT 1630 ); 1631 } 1632 } 1633 if (stat & BIT_MHL_EST_INT) 1634 sii8620_mhl_init(ctx); 1635 1636 sii8620_write(ctx, REG_CBUS_DISC_INTR0, stat); 1637 } 1638 1639 static void sii8620_read_burst(struct sii8620 *ctx) 1640 { 1641 u8 buf[17]; 1642 1643 sii8620_read_buf(ctx, REG_MDT_RCV_READ_PORT, buf, ARRAY_SIZE(buf)); 1644 sii8620_write(ctx, REG_MDT_RCV_CTRL, BIT_MDT_RCV_CTRL_MDT_RCV_EN | 1645 BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN | 1646 BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR); 1647 sii8620_readb(ctx, REG_MDT_RFIFO_STAT); 1648 } 1649 1650 static void sii8620_irq_g2wb(struct sii8620 *ctx) 1651 { 1652 u8 stat = sii8620_readb(ctx, REG_MDT_INT_0); 1653 1654 if (stat & BIT_MDT_IDLE_AFTER_HAWB_DISABLE) 1655 if (sii8620_is_mhl3(ctx)) 1656 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), 1657 MHL_INT_RC_FEAT_COMPLETE); 1658 1659 if (stat & BIT_MDT_RFIFO_DATA_RDY) 1660 sii8620_read_burst(ctx); 1661 1662 if (stat & BIT_MDT_XFIFO_EMPTY) 1663 sii8620_write(ctx, REG_MDT_XMIT_CTRL, 0); 1664 1665 sii8620_write(ctx, REG_MDT_INT_0, stat); 1666 } 1667 1668 static void sii8620_status_dcap_ready(struct sii8620 *ctx) 1669 { 1670 enum sii8620_mode mode; 1671 1672 mode = ctx->stat[MHL_DST_VERSION] >= 0x30 ? CM_MHL3 : CM_MHL1; 1673 if (mode > ctx->mode) 1674 sii8620_set_mode(ctx, mode); 1675 sii8620_peer_specific_init(ctx); 1676 sii8620_write(ctx, REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE 1677 | BIT_INTR9_EDID_DONE | BIT_INTR9_EDID_ERROR); 1678 } 1679 1680 static void sii8620_status_changed_path(struct sii8620 *ctx) 1681 { 1682 u8 link_mode; 1683 1684 if (ctx->use_packed_pixel) 1685 link_mode = MHL_DST_LM_CLK_MODE_PACKED_PIXEL; 1686 else 1687 link_mode = MHL_DST_LM_CLK_MODE_NORMAL; 1688 1689 if (ctx->stat[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED) 1690 link_mode |= MHL_DST_LM_PATH_ENABLED; 1691 1692 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE), 1693 link_mode); 1694 } 1695 1696 static void sii8620_msc_mr_write_stat(struct sii8620 *ctx) 1697 { 1698 u8 st[MHL_DST_SIZE], xst[MHL_XDS_SIZE]; 1699 1700 sii8620_read_buf(ctx, REG_MHL_STAT_0, st, MHL_DST_SIZE); 1701 sii8620_read_buf(ctx, REG_MHL_EXTSTAT_0, xst, MHL_XDS_SIZE); 1702 1703 sii8620_update_array(ctx->stat, st, MHL_DST_SIZE); 1704 sii8620_update_array(ctx->xstat, xst, MHL_XDS_SIZE); 1705 1706 if (ctx->stat[MHL_DST_CONNECTED_RDY] & st[MHL_DST_CONNECTED_RDY] & 1707 MHL_DST_CONN_DCAP_RDY) { 1708 sii8620_status_dcap_ready(ctx); 1709 1710 if (!sii8620_is_mhl3(ctx)) 1711 sii8620_mt_read_devcap(ctx, false); 1712 } 1713 1714 if (st[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED) 1715 sii8620_status_changed_path(ctx); 1716 } 1717 1718 static void sii8620_ecbus_up(struct sii8620 *ctx, int ret) 1719 { 1720 if (ret < 0) 1721 return; 1722 1723 sii8620_set_mode(ctx, CM_ECBUS_S); 1724 } 1725 1726 static void sii8620_got_ecbus_speed(struct sii8620 *ctx, int ret) 1727 { 1728 if (ret < 0) 1729 return; 1730 1731 sii8620_mt_write_stat(ctx, MHL_XDS_REG(CURR_ECBUS_MODE), 1732 MHL_XDS_ECBUS_S | MHL_XDS_SLOT_MODE_8BIT); 1733 sii8620_mt_rap(ctx, MHL_RAP_CBUS_MODE_UP); 1734 sii8620_mt_set_cont(ctx, sii8620_ecbus_up); 1735 } 1736 1737 static void sii8620_mhl_burst_emsc_support_set(struct mhl_burst_emsc_support *d, 1738 enum mhl_burst_id id) 1739 { 1740 sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_EMSC_SUPPORT); 1741 d->num_entries = 1; 1742 d->burst_id[0] = cpu_to_be16(id); 1743 } 1744 1745 static void sii8620_send_features(struct sii8620 *ctx) 1746 { 1747 u8 buf[16]; 1748 1749 sii8620_write(ctx, REG_MDT_XMIT_CTRL, BIT_MDT_XMIT_CTRL_EN 1750 | BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN); 1751 sii8620_mhl_burst_emsc_support_set((void *)buf, 1752 MHL_BURST_ID_HID_PAYLOAD); 1753 sii8620_write_buf(ctx, REG_MDT_XMIT_WRITE_PORT, buf, ARRAY_SIZE(buf)); 1754 } 1755 1756 static bool sii8620_rcp_consume(struct sii8620 *ctx, u8 scancode) 1757 { 1758 bool pressed = !(scancode & MHL_RCP_KEY_RELEASED_MASK); 1759 1760 scancode &= MHL_RCP_KEY_ID_MASK; 1761 1762 if (!ctx->rc_dev) { 1763 dev_dbg(ctx->dev, "RCP input device not initialized\n"); 1764 return false; 1765 } 1766 1767 if (pressed) 1768 rc_keydown(ctx->rc_dev, RC_PROTO_CEC, scancode, 0); 1769 else 1770 rc_keyup(ctx->rc_dev); 1771 1772 return true; 1773 } 1774 1775 static void sii8620_msc_mr_set_int(struct sii8620 *ctx) 1776 { 1777 u8 ints[MHL_INT_SIZE]; 1778 1779 sii8620_read_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE); 1780 sii8620_write_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE); 1781 1782 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_DCAP_CHG) { 1783 switch (ctx->mode) { 1784 case CM_MHL3: 1785 sii8620_mt_read_xdevcap_reg(ctx, MHL_XDC_ECBUS_SPEEDS); 1786 sii8620_mt_set_cont(ctx, sii8620_got_ecbus_speed); 1787 break; 1788 case CM_ECBUS_S: 1789 sii8620_mt_read_devcap(ctx, true); 1790 break; 1791 default: 1792 break; 1793 } 1794 } 1795 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_REQ) 1796 sii8620_send_features(ctx); 1797 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_COMPLETE) { 1798 ctx->feature_complete = true; 1799 if (ctx->edid) 1800 sii8620_enable_hpd(ctx); 1801 } 1802 } 1803 1804 static struct sii8620_mt_msg *sii8620_msc_msg_first(struct sii8620 *ctx) 1805 { 1806 struct device *dev = ctx->dev; 1807 1808 if (list_empty(&ctx->mt_queue)) { 1809 dev_err(dev, "unexpected MSC MT response\n"); 1810 return NULL; 1811 } 1812 1813 return list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 1814 } 1815 1816 static void sii8620_msc_mt_done(struct sii8620 *ctx) 1817 { 1818 struct sii8620_mt_msg *msg = sii8620_msc_msg_first(ctx); 1819 1820 if (!msg) 1821 return; 1822 1823 msg->ret = sii8620_readb(ctx, REG_MSC_MT_RCVD_DATA0); 1824 ctx->mt_state = MT_STATE_DONE; 1825 } 1826 1827 static void sii8620_msc_mr_msc_msg(struct sii8620 *ctx) 1828 { 1829 struct sii8620_mt_msg *msg; 1830 u8 buf[2]; 1831 1832 sii8620_read_buf(ctx, REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA, buf, 2); 1833 1834 switch (buf[0]) { 1835 case MHL_MSC_MSG_RAPK: 1836 msg = sii8620_msc_msg_first(ctx); 1837 if (!msg) 1838 return; 1839 msg->ret = buf[1]; 1840 ctx->mt_state = MT_STATE_DONE; 1841 break; 1842 case MHL_MSC_MSG_RCP: 1843 if (!sii8620_rcp_consume(ctx, buf[1])) 1844 sii8620_mt_rcpe(ctx, 1845 MHL_RCPE_STATUS_INEFFECTIVE_KEY_CODE); 1846 sii8620_mt_rcpk(ctx, buf[1]); 1847 break; 1848 default: 1849 dev_err(ctx->dev, "%s message type %d,%d not supported", 1850 __func__, buf[0], buf[1]); 1851 } 1852 } 1853 1854 static void sii8620_irq_msc(struct sii8620 *ctx) 1855 { 1856 u8 stat = sii8620_readb(ctx, REG_CBUS_INT_0); 1857 1858 if (stat & ~BIT_CBUS_HPD_CHG) 1859 sii8620_write(ctx, REG_CBUS_INT_0, stat & ~BIT_CBUS_HPD_CHG); 1860 1861 if (stat & BIT_CBUS_HPD_CHG) { 1862 u8 cbus_stat = sii8620_readb(ctx, REG_CBUS_STATUS); 1863 1864 if ((cbus_stat ^ ctx->cbus_status) & BIT_CBUS_STATUS_CBUS_HPD) { 1865 sii8620_write(ctx, REG_CBUS_INT_0, BIT_CBUS_HPD_CHG); 1866 } else { 1867 stat ^= BIT_CBUS_STATUS_CBUS_HPD; 1868 cbus_stat ^= BIT_CBUS_STATUS_CBUS_HPD; 1869 } 1870 ctx->cbus_status = cbus_stat; 1871 } 1872 1873 if (stat & BIT_CBUS_MSC_MR_WRITE_STAT) 1874 sii8620_msc_mr_write_stat(ctx); 1875 1876 if (stat & BIT_CBUS_HPD_CHG) { 1877 if (ctx->cbus_status & BIT_CBUS_STATUS_CBUS_HPD) { 1878 ctx->sink_detected = true; 1879 sii8620_identify_sink(ctx); 1880 } else { 1881 sii8620_hpd_unplugged(ctx); 1882 } 1883 } 1884 1885 if (stat & BIT_CBUS_MSC_MR_SET_INT) 1886 sii8620_msc_mr_set_int(ctx); 1887 1888 if (stat & BIT_CBUS_MSC_MT_DONE) 1889 sii8620_msc_mt_done(ctx); 1890 1891 if (stat & BIT_CBUS_MSC_MR_MSC_MSG) 1892 sii8620_msc_mr_msc_msg(ctx); 1893 } 1894 1895 static void sii8620_irq_coc(struct sii8620 *ctx) 1896 { 1897 u8 stat = sii8620_readb(ctx, REG_COC_INTR); 1898 1899 if (stat & BIT_COC_CALIBRATION_DONE) { 1900 u8 cstat = sii8620_readb(ctx, REG_COC_STAT_0); 1901 1902 cstat &= BIT_COC_STAT_0_PLL_LOCKED | MSK_COC_STAT_0_FSM_STATE; 1903 if (cstat == (BIT_COC_STAT_0_PLL_LOCKED | 0x02)) { 1904 sii8620_write_seq_static(ctx, 1905 REG_COC_CTLB, 0, 1906 REG_TRXINTMH, BIT_TDM_INTR_SYNC_DATA 1907 | BIT_TDM_INTR_SYNC_WAIT 1908 ); 1909 } 1910 } 1911 1912 sii8620_write(ctx, REG_COC_INTR, stat); 1913 } 1914 1915 static void sii8620_irq_merr(struct sii8620 *ctx) 1916 { 1917 u8 stat = sii8620_readb(ctx, REG_CBUS_INT_1); 1918 1919 sii8620_write(ctx, REG_CBUS_INT_1, stat); 1920 } 1921 1922 static void sii8620_irq_edid(struct sii8620 *ctx) 1923 { 1924 u8 stat = sii8620_readb(ctx, REG_INTR9); 1925 1926 sii8620_write(ctx, REG_INTR9, stat); 1927 1928 if (stat & BIT_INTR9_DEVCAP_DONE) 1929 ctx->mt_state = MT_STATE_DONE; 1930 } 1931 1932 static void sii8620_irq_scdt(struct sii8620 *ctx) 1933 { 1934 u8 stat = sii8620_readb(ctx, REG_INTR5); 1935 1936 if (stat & BIT_INTR_SCDT_CHANGE) { 1937 u8 cstat = sii8620_readb(ctx, REG_TMDS_CSTAT_P3); 1938 1939 if (cstat & BIT_TMDS_CSTAT_P3_SCDT) 1940 sii8620_start_video(ctx); 1941 } 1942 1943 sii8620_write(ctx, REG_INTR5, stat); 1944 } 1945 1946 static void sii8620_got_xdevcap(struct sii8620 *ctx, int ret) 1947 { 1948 if (ret < 0) 1949 return; 1950 1951 sii8620_mt_read_devcap(ctx, false); 1952 } 1953 1954 static void sii8620_irq_tdm(struct sii8620 *ctx) 1955 { 1956 u8 stat = sii8620_readb(ctx, REG_TRXINTH); 1957 u8 tdm = sii8620_readb(ctx, REG_TRXSTA2); 1958 1959 if ((tdm & MSK_TDM_SYNCHRONIZED) == VAL_TDM_SYNCHRONIZED) { 1960 ctx->mode = CM_ECBUS_S; 1961 ctx->burst.rx_ack = 0; 1962 ctx->burst.r_size = SII8620_BURST_BUF_LEN; 1963 sii8620_burst_tx_rbuf_info(ctx, SII8620_BURST_BUF_LEN); 1964 sii8620_mt_read_devcap(ctx, true); 1965 sii8620_mt_set_cont(ctx, sii8620_got_xdevcap); 1966 } else { 1967 sii8620_write_seq_static(ctx, 1968 REG_MHL_PLL_CTL2, 0, 1969 REG_MHL_PLL_CTL2, BIT_MHL_PLL_CTL2_CLKDETECT_EN 1970 ); 1971 } 1972 1973 sii8620_write(ctx, REG_TRXINTH, stat); 1974 } 1975 1976 static void sii8620_irq_block(struct sii8620 *ctx) 1977 { 1978 u8 stat = sii8620_readb(ctx, REG_EMSCINTR); 1979 1980 if (stat & BIT_EMSCINTR_SPI_DVLD) { 1981 u8 bstat = sii8620_readb(ctx, REG_SPIBURSTSTAT); 1982 1983 if (bstat & BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE) 1984 sii8620_burst_receive(ctx); 1985 } 1986 1987 sii8620_write(ctx, REG_EMSCINTR, stat); 1988 } 1989 1990 static void sii8620_irq_ddc(struct sii8620 *ctx) 1991 { 1992 u8 stat = sii8620_readb(ctx, REG_INTR3); 1993 1994 if (stat & BIT_DDC_CMD_DONE) { 1995 sii8620_write(ctx, REG_INTR3_MASK, 0); 1996 if (sii8620_is_mhl3(ctx) && !ctx->feature_complete) 1997 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), 1998 MHL_INT_RC_FEAT_REQ); 1999 else 2000 sii8620_enable_hpd(ctx); 2001 } 2002 sii8620_write(ctx, REG_INTR3, stat); 2003 } 2004 2005 /* endian agnostic, non-volatile version of test_bit */ 2006 static bool sii8620_test_bit(unsigned int nr, const u8 *addr) 2007 { 2008 return 1 & (addr[nr / BITS_PER_BYTE] >> (nr % BITS_PER_BYTE)); 2009 } 2010 2011 static irqreturn_t sii8620_irq_thread(int irq, void *data) 2012 { 2013 static const struct { 2014 int bit; 2015 void (*handler)(struct sii8620 *ctx); 2016 } irq_vec[] = { 2017 { BIT_FAST_INTR_STAT_DISC, sii8620_irq_disc }, 2018 { BIT_FAST_INTR_STAT_G2WB, sii8620_irq_g2wb }, 2019 { BIT_FAST_INTR_STAT_COC, sii8620_irq_coc }, 2020 { BIT_FAST_INTR_STAT_TDM, sii8620_irq_tdm }, 2021 { BIT_FAST_INTR_STAT_MSC, sii8620_irq_msc }, 2022 { BIT_FAST_INTR_STAT_MERR, sii8620_irq_merr }, 2023 { BIT_FAST_INTR_STAT_BLOCK, sii8620_irq_block }, 2024 { BIT_FAST_INTR_STAT_EDID, sii8620_irq_edid }, 2025 { BIT_FAST_INTR_STAT_DDC, sii8620_irq_ddc }, 2026 { BIT_FAST_INTR_STAT_SCDT, sii8620_irq_scdt }, 2027 }; 2028 struct sii8620 *ctx = data; 2029 u8 stats[LEN_FAST_INTR_STAT]; 2030 int i, ret; 2031 2032 mutex_lock(&ctx->lock); 2033 2034 sii8620_read_buf(ctx, REG_FAST_INTR_STAT, stats, ARRAY_SIZE(stats)); 2035 for (i = 0; i < ARRAY_SIZE(irq_vec); ++i) 2036 if (sii8620_test_bit(irq_vec[i].bit, stats)) 2037 irq_vec[i].handler(ctx); 2038 2039 sii8620_burst_rx_all(ctx); 2040 sii8620_mt_work(ctx); 2041 sii8620_burst_send(ctx); 2042 2043 ret = sii8620_clear_error(ctx); 2044 if (ret) { 2045 dev_err(ctx->dev, "Error during IRQ handling, %d.\n", ret); 2046 sii8620_mhl_disconnected(ctx); 2047 } 2048 mutex_unlock(&ctx->lock); 2049 2050 return IRQ_HANDLED; 2051 } 2052 2053 static void sii8620_cable_in(struct sii8620 *ctx) 2054 { 2055 struct device *dev = ctx->dev; 2056 u8 ver[5]; 2057 int ret; 2058 2059 ret = sii8620_hw_on(ctx); 2060 if (ret) { 2061 dev_err(dev, "Error powering on, %d.\n", ret); 2062 return; 2063 } 2064 2065 sii8620_read_buf(ctx, REG_VND_IDL, ver, ARRAY_SIZE(ver)); 2066 ret = sii8620_clear_error(ctx); 2067 if (ret) { 2068 dev_err(dev, "Error accessing I2C bus, %d.\n", ret); 2069 return; 2070 } 2071 2072 dev_info(dev, "ChipID %02x%02x:%02x%02x rev %02x.\n", ver[1], ver[0], 2073 ver[3], ver[2], ver[4]); 2074 2075 sii8620_write(ctx, REG_DPD, 2076 BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN); 2077 2078 sii8620_xtal_set_rate(ctx); 2079 sii8620_disconnect(ctx); 2080 2081 sii8620_write_seq_static(ctx, 2082 REG_MHL_CBUS_CTL0, VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONG 2083 | VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_734, 2084 REG_MHL_CBUS_CTL1, VAL_MHL_CBUS_CTL1_1115_OHM, 2085 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN, 2086 ); 2087 2088 ret = sii8620_clear_error(ctx); 2089 if (ret) { 2090 dev_err(dev, "Error accessing I2C bus, %d.\n", ret); 2091 return; 2092 } 2093 2094 enable_irq(to_i2c_client(ctx->dev)->irq); 2095 } 2096 2097 static void sii8620_init_rcp_input_dev(struct sii8620 *ctx) 2098 { 2099 struct rc_dev *rc_dev; 2100 int ret; 2101 2102 rc_dev = rc_allocate_device(RC_DRIVER_SCANCODE); 2103 if (!rc_dev) { 2104 dev_err(ctx->dev, "Failed to allocate RC device\n"); 2105 ctx->error = -ENOMEM; 2106 return; 2107 } 2108 2109 rc_dev->input_phys = "sii8620/input0"; 2110 rc_dev->input_id.bustype = BUS_VIRTUAL; 2111 rc_dev->map_name = RC_MAP_CEC; 2112 rc_dev->allowed_protocols = RC_PROTO_BIT_CEC; 2113 rc_dev->driver_name = "sii8620"; 2114 rc_dev->device_name = "sii8620"; 2115 2116 ret = rc_register_device(rc_dev); 2117 2118 if (ret) { 2119 dev_err(ctx->dev, "Failed to register RC device\n"); 2120 ctx->error = ret; 2121 rc_free_device(ctx->rc_dev); 2122 return; 2123 } 2124 ctx->rc_dev = rc_dev; 2125 } 2126 2127 static void sii8620_cable_out(struct sii8620 *ctx) 2128 { 2129 disable_irq(to_i2c_client(ctx->dev)->irq); 2130 sii8620_hw_off(ctx); 2131 } 2132 2133 static void sii8620_extcon_work(struct work_struct *work) 2134 { 2135 struct sii8620 *ctx = 2136 container_of(work, struct sii8620, extcon_wq); 2137 int state = extcon_get_state(ctx->extcon, EXTCON_DISP_MHL); 2138 2139 if (state == ctx->cable_state) 2140 return; 2141 2142 ctx->cable_state = state; 2143 2144 if (state > 0) 2145 sii8620_cable_in(ctx); 2146 else 2147 sii8620_cable_out(ctx); 2148 } 2149 2150 static int sii8620_extcon_notifier(struct notifier_block *self, 2151 unsigned long event, void *ptr) 2152 { 2153 struct sii8620 *ctx = 2154 container_of(self, struct sii8620, extcon_nb); 2155 2156 schedule_work(&ctx->extcon_wq); 2157 2158 return NOTIFY_DONE; 2159 } 2160 2161 static int sii8620_extcon_init(struct sii8620 *ctx) 2162 { 2163 struct extcon_dev *edev; 2164 struct device_node *musb, *muic; 2165 int ret; 2166 2167 /* get micro-USB connector node */ 2168 musb = of_graph_get_remote_node(ctx->dev->of_node, 1, -1); 2169 /* next get micro-USB Interface Controller node */ 2170 muic = of_get_next_parent(musb); 2171 2172 if (!muic) { 2173 dev_info(ctx->dev, "no extcon found, switching to 'always on' mode\n"); 2174 return 0; 2175 } 2176 2177 edev = extcon_find_edev_by_node(muic); 2178 of_node_put(muic); 2179 if (IS_ERR(edev)) { 2180 if (PTR_ERR(edev) == -EPROBE_DEFER) 2181 return -EPROBE_DEFER; 2182 dev_err(ctx->dev, "Invalid or missing extcon\n"); 2183 return PTR_ERR(edev); 2184 } 2185 2186 ctx->extcon = edev; 2187 ctx->extcon_nb.notifier_call = sii8620_extcon_notifier; 2188 INIT_WORK(&ctx->extcon_wq, sii8620_extcon_work); 2189 ret = extcon_register_notifier(edev, EXTCON_DISP_MHL, &ctx->extcon_nb); 2190 if (ret) { 2191 dev_err(ctx->dev, "failed to register notifier for MHL\n"); 2192 return ret; 2193 } 2194 2195 return 0; 2196 } 2197 2198 static inline struct sii8620 *bridge_to_sii8620(struct drm_bridge *bridge) 2199 { 2200 return container_of(bridge, struct sii8620, bridge); 2201 } 2202 2203 static int sii8620_attach(struct drm_bridge *bridge) 2204 { 2205 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2206 2207 sii8620_init_rcp_input_dev(ctx); 2208 2209 return sii8620_clear_error(ctx); 2210 } 2211 2212 static void sii8620_detach(struct drm_bridge *bridge) 2213 { 2214 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2215 2216 rc_unregister_device(ctx->rc_dev); 2217 } 2218 2219 static int sii8620_is_packing_required(struct sii8620 *ctx, 2220 const struct drm_display_mode *mode) 2221 { 2222 int max_pclk, max_pclk_pp_mode; 2223 2224 if (sii8620_is_mhl3(ctx)) { 2225 max_pclk = MHL3_MAX_PCLK; 2226 max_pclk_pp_mode = MHL3_MAX_PCLK_PP_MODE; 2227 } else { 2228 max_pclk = MHL1_MAX_PCLK; 2229 max_pclk_pp_mode = MHL1_MAX_PCLK_PP_MODE; 2230 } 2231 2232 if (mode->clock < max_pclk) 2233 return 0; 2234 else if (mode->clock < max_pclk_pp_mode) 2235 return 1; 2236 else 2237 return -1; 2238 } 2239 2240 static enum drm_mode_status sii8620_mode_valid(struct drm_bridge *bridge, 2241 const struct drm_display_mode *mode) 2242 { 2243 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2244 int pack_required = sii8620_is_packing_required(ctx, mode); 2245 bool can_pack = ctx->devcap[MHL_DCAP_VID_LINK_MODE] & 2246 MHL_DCAP_VID_LINK_PPIXEL; 2247 2248 switch (pack_required) { 2249 case 0: 2250 return MODE_OK; 2251 case 1: 2252 return (can_pack) ? MODE_OK : MODE_CLOCK_HIGH; 2253 default: 2254 return MODE_CLOCK_HIGH; 2255 } 2256 } 2257 2258 static bool sii8620_mode_fixup(struct drm_bridge *bridge, 2259 const struct drm_display_mode *mode, 2260 struct drm_display_mode *adjusted_mode) 2261 { 2262 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2263 2264 mutex_lock(&ctx->lock); 2265 2266 ctx->use_packed_pixel = sii8620_is_packing_required(ctx, adjusted_mode); 2267 2268 mutex_unlock(&ctx->lock); 2269 2270 return true; 2271 } 2272 2273 static const struct drm_bridge_funcs sii8620_bridge_funcs = { 2274 .attach = sii8620_attach, 2275 .detach = sii8620_detach, 2276 .mode_fixup = sii8620_mode_fixup, 2277 .mode_valid = sii8620_mode_valid, 2278 }; 2279 2280 static int sii8620_probe(struct i2c_client *client, 2281 const struct i2c_device_id *id) 2282 { 2283 struct device *dev = &client->dev; 2284 struct sii8620 *ctx; 2285 int ret; 2286 2287 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 2288 if (!ctx) 2289 return -ENOMEM; 2290 2291 ctx->dev = dev; 2292 mutex_init(&ctx->lock); 2293 INIT_LIST_HEAD(&ctx->mt_queue); 2294 2295 ctx->clk_xtal = devm_clk_get(dev, "xtal"); 2296 if (IS_ERR(ctx->clk_xtal)) { 2297 dev_err(dev, "failed to get xtal clock from DT\n"); 2298 return PTR_ERR(ctx->clk_xtal); 2299 } 2300 2301 if (!client->irq) { 2302 dev_err(dev, "no irq provided\n"); 2303 return -EINVAL; 2304 } 2305 irq_set_status_flags(client->irq, IRQ_NOAUTOEN); 2306 ret = devm_request_threaded_irq(dev, client->irq, NULL, 2307 sii8620_irq_thread, 2308 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 2309 "sii8620", ctx); 2310 if (ret < 0) { 2311 dev_err(dev, "failed to install IRQ handler\n"); 2312 return ret; 2313 } 2314 2315 ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); 2316 if (IS_ERR(ctx->gpio_reset)) { 2317 dev_err(dev, "failed to get reset gpio from DT\n"); 2318 return PTR_ERR(ctx->gpio_reset); 2319 } 2320 2321 ctx->supplies[0].supply = "cvcc10"; 2322 ctx->supplies[1].supply = "iovcc18"; 2323 ret = devm_regulator_bulk_get(dev, 2, ctx->supplies); 2324 if (ret) 2325 return ret; 2326 2327 ret = sii8620_extcon_init(ctx); 2328 if (ret < 0) { 2329 dev_err(ctx->dev, "failed to initialize EXTCON\n"); 2330 return ret; 2331 } 2332 2333 i2c_set_clientdata(client, ctx); 2334 2335 ctx->bridge.funcs = &sii8620_bridge_funcs; 2336 ctx->bridge.of_node = dev->of_node; 2337 drm_bridge_add(&ctx->bridge); 2338 2339 if (!ctx->extcon) 2340 sii8620_cable_in(ctx); 2341 2342 return 0; 2343 } 2344 2345 static int sii8620_remove(struct i2c_client *client) 2346 { 2347 struct sii8620 *ctx = i2c_get_clientdata(client); 2348 2349 if (ctx->extcon) { 2350 extcon_unregister_notifier(ctx->extcon, EXTCON_DISP_MHL, 2351 &ctx->extcon_nb); 2352 flush_work(&ctx->extcon_wq); 2353 if (ctx->cable_state > 0) 2354 sii8620_cable_out(ctx); 2355 } else { 2356 sii8620_cable_out(ctx); 2357 } 2358 drm_bridge_remove(&ctx->bridge); 2359 2360 return 0; 2361 } 2362 2363 static const struct of_device_id sii8620_dt_match[] = { 2364 { .compatible = "sil,sii8620" }, 2365 { }, 2366 }; 2367 MODULE_DEVICE_TABLE(of, sii8620_dt_match); 2368 2369 static const struct i2c_device_id sii8620_id[] = { 2370 { "sii8620", 0 }, 2371 { }, 2372 }; 2373 2374 MODULE_DEVICE_TABLE(i2c, sii8620_id); 2375 static struct i2c_driver sii8620_driver = { 2376 .driver = { 2377 .name = "sii8620", 2378 .of_match_table = of_match_ptr(sii8620_dt_match), 2379 }, 2380 .probe = sii8620_probe, 2381 .remove = sii8620_remove, 2382 .id_table = sii8620_id, 2383 }; 2384 2385 module_i2c_driver(sii8620_driver); 2386 MODULE_LICENSE("GPL v2"); 2387