1 /* 2 * Silicon Image SiI8620 HDMI/MHL bridge driver 3 * 4 * Copyright (C) 2015, Samsung Electronics Co., Ltd. 5 * Andrzej Hajda <a.hajda@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <asm/unaligned.h> 13 14 #include <drm/bridge/mhl.h> 15 #include <drm/drm_crtc.h> 16 #include <drm/drm_edid.h> 17 18 #include <linux/clk.h> 19 #include <linux/delay.h> 20 #include <linux/gpio/consumer.h> 21 #include <linux/i2c.h> 22 #include <linux/interrupt.h> 23 #include <linux/irq.h> 24 #include <linux/kernel.h> 25 #include <linux/list.h> 26 #include <linux/module.h> 27 #include <linux/mutex.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/slab.h> 30 31 #include <media/rc-core.h> 32 33 #include "sil-sii8620.h" 34 35 #define SII8620_BURST_BUF_LEN 288 36 #define VAL_RX_HDMI_CTRL2_DEFVAL VAL_RX_HDMI_CTRL2_IDLE_CNT(3) 37 #define MHL1_MAX_LCLK 225000 38 #define MHL3_MAX_LCLK 600000 39 40 enum sii8620_mode { 41 CM_DISCONNECTED, 42 CM_DISCOVERY, 43 CM_MHL1, 44 CM_MHL3, 45 CM_ECBUS_S 46 }; 47 48 enum sii8620_sink_type { 49 SINK_NONE, 50 SINK_HDMI, 51 SINK_DVI 52 }; 53 54 enum sii8620_mt_state { 55 MT_STATE_READY, 56 MT_STATE_BUSY, 57 MT_STATE_DONE 58 }; 59 60 struct sii8620 { 61 struct drm_bridge bridge; 62 struct device *dev; 63 struct rc_dev *rc_dev; 64 struct clk *clk_xtal; 65 struct gpio_desc *gpio_reset; 66 struct gpio_desc *gpio_int; 67 struct regulator_bulk_data supplies[2]; 68 struct mutex lock; /* context lock, protects fields below */ 69 int error; 70 int pixel_clock; 71 unsigned int use_packed_pixel:1; 72 int video_code; 73 enum sii8620_mode mode; 74 enum sii8620_sink_type sink_type; 75 u8 cbus_status; 76 u8 stat[MHL_DST_SIZE]; 77 u8 xstat[MHL_XDS_SIZE]; 78 u8 devcap[MHL_DCAP_SIZE]; 79 u8 xdevcap[MHL_XDC_SIZE]; 80 u8 avif[HDMI_INFOFRAME_SIZE(AVI)]; 81 struct edid *edid; 82 unsigned int gen2_write_burst:1; 83 enum sii8620_mt_state mt_state; 84 struct list_head mt_queue; 85 struct { 86 int r_size; 87 int r_count; 88 int rx_ack; 89 int rx_count; 90 u8 rx_buf[32]; 91 int tx_count; 92 u8 tx_buf[32]; 93 } burst; 94 }; 95 96 struct sii8620_mt_msg; 97 98 typedef void (*sii8620_mt_msg_cb)(struct sii8620 *ctx, 99 struct sii8620_mt_msg *msg); 100 101 typedef void (*sii8620_cb)(struct sii8620 *ctx, int ret); 102 103 struct sii8620_mt_msg { 104 struct list_head node; 105 u8 reg[4]; 106 u8 ret; 107 sii8620_mt_msg_cb send; 108 sii8620_mt_msg_cb recv; 109 sii8620_cb continuation; 110 }; 111 112 static const u8 sii8620_i2c_page[] = { 113 0x39, /* Main System */ 114 0x3d, /* TDM and HSIC */ 115 0x49, /* TMDS Receiver, MHL EDID */ 116 0x4d, /* eMSC, HDCP, HSIC */ 117 0x5d, /* MHL Spec */ 118 0x64, /* MHL CBUS */ 119 0x59, /* Hardware TPI (Transmitter Programming Interface) */ 120 0x61, /* eCBUS-S, eCBUS-D */ 121 }; 122 123 static void sii8620_fetch_edid(struct sii8620 *ctx); 124 static void sii8620_set_upstream_edid(struct sii8620 *ctx); 125 static void sii8620_enable_hpd(struct sii8620 *ctx); 126 static void sii8620_mhl_disconnected(struct sii8620 *ctx); 127 static void sii8620_disconnect(struct sii8620 *ctx); 128 129 static int sii8620_clear_error(struct sii8620 *ctx) 130 { 131 int ret = ctx->error; 132 133 ctx->error = 0; 134 return ret; 135 } 136 137 static void sii8620_read_buf(struct sii8620 *ctx, u16 addr, u8 *buf, int len) 138 { 139 struct device *dev = ctx->dev; 140 struct i2c_client *client = to_i2c_client(dev); 141 u8 data = addr; 142 struct i2c_msg msg[] = { 143 { 144 .addr = sii8620_i2c_page[addr >> 8], 145 .flags = client->flags, 146 .len = 1, 147 .buf = &data 148 }, 149 { 150 .addr = sii8620_i2c_page[addr >> 8], 151 .flags = client->flags | I2C_M_RD, 152 .len = len, 153 .buf = buf 154 }, 155 }; 156 int ret; 157 158 if (ctx->error) 159 return; 160 161 ret = i2c_transfer(client->adapter, msg, 2); 162 dev_dbg(dev, "read at %04x: %*ph, %d\n", addr, len, buf, ret); 163 164 if (ret != 2) { 165 dev_err(dev, "Read at %#06x of %d bytes failed with code %d.\n", 166 addr, len, ret); 167 ctx->error = ret < 0 ? ret : -EIO; 168 } 169 } 170 171 static u8 sii8620_readb(struct sii8620 *ctx, u16 addr) 172 { 173 u8 ret; 174 175 sii8620_read_buf(ctx, addr, &ret, 1); 176 return ret; 177 } 178 179 static void sii8620_write_buf(struct sii8620 *ctx, u16 addr, const u8 *buf, 180 int len) 181 { 182 struct device *dev = ctx->dev; 183 struct i2c_client *client = to_i2c_client(dev); 184 u8 data[2]; 185 struct i2c_msg msg = { 186 .addr = sii8620_i2c_page[addr >> 8], 187 .flags = client->flags, 188 .len = len + 1, 189 }; 190 int ret; 191 192 if (ctx->error) 193 return; 194 195 if (len > 1) { 196 msg.buf = kmalloc(len + 1, GFP_KERNEL); 197 if (!msg.buf) { 198 ctx->error = -ENOMEM; 199 return; 200 } 201 memcpy(msg.buf + 1, buf, len); 202 } else { 203 msg.buf = data; 204 msg.buf[1] = *buf; 205 } 206 207 msg.buf[0] = addr; 208 209 ret = i2c_transfer(client->adapter, &msg, 1); 210 dev_dbg(dev, "write at %04x: %*ph, %d\n", addr, len, buf, ret); 211 212 if (ret != 1) { 213 dev_err(dev, "Write at %#06x of %*ph failed with code %d.\n", 214 addr, len, buf, ret); 215 ctx->error = ret ?: -EIO; 216 } 217 218 if (len > 1) 219 kfree(msg.buf); 220 } 221 222 #define sii8620_write(ctx, addr, arr...) \ 223 ({\ 224 u8 d[] = { arr }; \ 225 sii8620_write_buf(ctx, addr, d, ARRAY_SIZE(d)); \ 226 }) 227 228 static void __sii8620_write_seq(struct sii8620 *ctx, const u16 *seq, int len) 229 { 230 int i; 231 232 for (i = 0; i < len; i += 2) 233 sii8620_write(ctx, seq[i], seq[i + 1]); 234 } 235 236 #define sii8620_write_seq(ctx, seq...) \ 237 ({\ 238 const u16 d[] = { seq }; \ 239 __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \ 240 }) 241 242 #define sii8620_write_seq_static(ctx, seq...) \ 243 ({\ 244 static const u16 d[] = { seq }; \ 245 __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \ 246 }) 247 248 static void sii8620_setbits(struct sii8620 *ctx, u16 addr, u8 mask, u8 val) 249 { 250 val = (val & mask) | (sii8620_readb(ctx, addr) & ~mask); 251 sii8620_write(ctx, addr, val); 252 } 253 254 static inline bool sii8620_is_mhl3(struct sii8620 *ctx) 255 { 256 return ctx->mode >= CM_MHL3; 257 } 258 259 static void sii8620_mt_cleanup(struct sii8620 *ctx) 260 { 261 struct sii8620_mt_msg *msg, *n; 262 263 list_for_each_entry_safe(msg, n, &ctx->mt_queue, node) { 264 list_del(&msg->node); 265 kfree(msg); 266 } 267 ctx->mt_state = MT_STATE_READY; 268 } 269 270 static void sii8620_mt_work(struct sii8620 *ctx) 271 { 272 struct sii8620_mt_msg *msg; 273 274 if (ctx->error) 275 return; 276 if (ctx->mt_state == MT_STATE_BUSY || list_empty(&ctx->mt_queue)) 277 return; 278 279 if (ctx->mt_state == MT_STATE_DONE) { 280 ctx->mt_state = MT_STATE_READY; 281 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, 282 node); 283 list_del(&msg->node); 284 if (msg->recv) 285 msg->recv(ctx, msg); 286 if (msg->continuation) 287 msg->continuation(ctx, msg->ret); 288 kfree(msg); 289 } 290 291 if (ctx->mt_state != MT_STATE_READY || list_empty(&ctx->mt_queue)) 292 return; 293 294 ctx->mt_state = MT_STATE_BUSY; 295 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 296 if (msg->send) 297 msg->send(ctx, msg); 298 } 299 300 static void sii8620_enable_gen2_write_burst(struct sii8620 *ctx) 301 { 302 u8 ctrl = BIT_MDT_RCV_CTRL_MDT_RCV_EN; 303 304 if (ctx->gen2_write_burst) 305 return; 306 307 if (ctx->mode >= CM_MHL1) 308 ctrl |= BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN; 309 310 sii8620_write_seq(ctx, 311 REG_MDT_RCV_TIMEOUT, 100, 312 REG_MDT_RCV_CTRL, ctrl 313 ); 314 ctx->gen2_write_burst = 1; 315 } 316 317 static void sii8620_disable_gen2_write_burst(struct sii8620 *ctx) 318 { 319 if (!ctx->gen2_write_burst) 320 return; 321 322 sii8620_write_seq_static(ctx, 323 REG_MDT_XMIT_CTRL, 0, 324 REG_MDT_RCV_CTRL, 0 325 ); 326 ctx->gen2_write_burst = 0; 327 } 328 329 static void sii8620_start_gen2_write_burst(struct sii8620 *ctx) 330 { 331 sii8620_write_seq_static(ctx, 332 REG_MDT_INT_1_MASK, BIT_MDT_RCV_TIMEOUT 333 | BIT_MDT_RCV_SM_ABORT_PKT_RCVD | BIT_MDT_RCV_SM_ERROR 334 | BIT_MDT_XMIT_TIMEOUT | BIT_MDT_XMIT_SM_ABORT_PKT_RCVD 335 | BIT_MDT_XMIT_SM_ERROR, 336 REG_MDT_INT_0_MASK, BIT_MDT_XFIFO_EMPTY 337 | BIT_MDT_IDLE_AFTER_HAWB_DISABLE 338 | BIT_MDT_RFIFO_DATA_RDY 339 ); 340 sii8620_enable_gen2_write_burst(ctx); 341 } 342 343 static void sii8620_mt_msc_cmd_send(struct sii8620 *ctx, 344 struct sii8620_mt_msg *msg) 345 { 346 if (msg->reg[0] == MHL_SET_INT && 347 msg->reg[1] == MHL_INT_REG(RCHANGE) && 348 msg->reg[2] == MHL_INT_RC_FEAT_REQ) 349 sii8620_enable_gen2_write_burst(ctx); 350 else 351 sii8620_disable_gen2_write_burst(ctx); 352 353 switch (msg->reg[0]) { 354 case MHL_WRITE_STAT: 355 case MHL_SET_INT: 356 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg + 1, 2); 357 sii8620_write(ctx, REG_MSC_COMMAND_START, 358 BIT_MSC_COMMAND_START_WRITE_STAT); 359 break; 360 case MHL_MSC_MSG: 361 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg, 3); 362 sii8620_write(ctx, REG_MSC_COMMAND_START, 363 BIT_MSC_COMMAND_START_MSC_MSG); 364 break; 365 case MHL_READ_DEVCAP_REG: 366 case MHL_READ_XDEVCAP_REG: 367 sii8620_write(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg[1]); 368 sii8620_write(ctx, REG_MSC_COMMAND_START, 369 BIT_MSC_COMMAND_START_READ_DEVCAP); 370 break; 371 default: 372 dev_err(ctx->dev, "%s: command %#x not supported\n", __func__, 373 msg->reg[0]); 374 } 375 } 376 377 static struct sii8620_mt_msg *sii8620_mt_msg_new(struct sii8620 *ctx) 378 { 379 struct sii8620_mt_msg *msg = kzalloc(sizeof(*msg), GFP_KERNEL); 380 381 if (!msg) 382 ctx->error = -ENOMEM; 383 else 384 list_add_tail(&msg->node, &ctx->mt_queue); 385 386 return msg; 387 } 388 389 static void sii8620_mt_set_cont(struct sii8620 *ctx, sii8620_cb cont) 390 { 391 struct sii8620_mt_msg *msg; 392 393 if (ctx->error) 394 return; 395 396 if (list_empty(&ctx->mt_queue)) { 397 ctx->error = -EINVAL; 398 return; 399 } 400 msg = list_last_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 401 msg->continuation = cont; 402 } 403 404 static void sii8620_mt_msc_cmd(struct sii8620 *ctx, u8 cmd, u8 arg1, u8 arg2) 405 { 406 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 407 408 if (!msg) 409 return; 410 411 msg->reg[0] = cmd; 412 msg->reg[1] = arg1; 413 msg->reg[2] = arg2; 414 msg->send = sii8620_mt_msc_cmd_send; 415 } 416 417 static void sii8620_mt_write_stat(struct sii8620 *ctx, u8 reg, u8 val) 418 { 419 sii8620_mt_msc_cmd(ctx, MHL_WRITE_STAT, reg, val); 420 } 421 422 static inline void sii8620_mt_set_int(struct sii8620 *ctx, u8 irq, u8 mask) 423 { 424 sii8620_mt_msc_cmd(ctx, MHL_SET_INT, irq, mask); 425 } 426 427 static void sii8620_mt_msc_msg(struct sii8620 *ctx, u8 cmd, u8 data) 428 { 429 sii8620_mt_msc_cmd(ctx, MHL_MSC_MSG, cmd, data); 430 } 431 432 static void sii8620_mt_rap(struct sii8620 *ctx, u8 code) 433 { 434 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RAP, code); 435 } 436 437 static void sii8620_mt_rcpk(struct sii8620 *ctx, u8 code) 438 { 439 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPK, code); 440 } 441 442 static void sii8620_mt_rcpe(struct sii8620 *ctx, u8 code) 443 { 444 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPE, code); 445 } 446 447 static void sii8620_mt_read_devcap_send(struct sii8620 *ctx, 448 struct sii8620_mt_msg *msg) 449 { 450 u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP 451 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 452 | BIT_EDID_CTRL_EDID_MODE_EN; 453 454 if (msg->reg[0] == MHL_READ_XDEVCAP) 455 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN; 456 457 sii8620_write_seq(ctx, 458 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE, 459 REG_EDID_CTRL, ctrl, 460 REG_TPI_CBUS_START, BIT_TPI_CBUS_START_GET_DEVCAP_START 461 ); 462 } 463 464 /* copy src to dst and set changed bits in src */ 465 static void sii8620_update_array(u8 *dst, u8 *src, int count) 466 { 467 while (--count >= 0) { 468 *src ^= *dst; 469 *dst++ ^= *src++; 470 } 471 } 472 473 static void sii8620_sink_detected(struct sii8620 *ctx, int ret) 474 { 475 static const char * const sink_str[] = { 476 [SINK_NONE] = "NONE", 477 [SINK_HDMI] = "HDMI", 478 [SINK_DVI] = "DVI" 479 }; 480 481 char sink_name[20]; 482 struct device *dev = ctx->dev; 483 484 if (ret < 0) 485 return; 486 487 sii8620_fetch_edid(ctx); 488 if (!ctx->edid) { 489 dev_err(ctx->dev, "Cannot fetch EDID\n"); 490 sii8620_mhl_disconnected(ctx); 491 return; 492 } 493 494 if (drm_detect_hdmi_monitor(ctx->edid)) 495 ctx->sink_type = SINK_HDMI; 496 else 497 ctx->sink_type = SINK_DVI; 498 499 drm_edid_get_monitor_name(ctx->edid, sink_name, ARRAY_SIZE(sink_name)); 500 501 dev_info(dev, "detected sink(type: %s): %s\n", 502 sink_str[ctx->sink_type], sink_name); 503 } 504 505 static void sii8620_hsic_init(struct sii8620 *ctx) 506 { 507 if (!sii8620_is_mhl3(ctx)) 508 return; 509 510 sii8620_write(ctx, REG_FCGC, 511 BIT_FCGC_HSIC_HOSTMODE | BIT_FCGC_HSIC_ENABLE); 512 sii8620_setbits(ctx, REG_HRXCTRL3, 513 BIT_HRXCTRL3_HRX_STAY_RESET | BIT_HRXCTRL3_STATUS_EN, ~0); 514 sii8620_setbits(ctx, REG_TTXNUMB, MSK_TTXNUMB_TTX_NUMBPS, 4); 515 sii8620_setbits(ctx, REG_TRXCTRL, BIT_TRXCTRL_TRX_FROM_SE_COC, ~0); 516 sii8620_setbits(ctx, REG_HTXCTRL, BIT_HTXCTRL_HTX_DRVCONN1, 0); 517 sii8620_setbits(ctx, REG_KEEPER, MSK_KEEPER_MODE, VAL_KEEPER_MODE_HOST); 518 sii8620_write_seq_static(ctx, 519 REG_TDMLLCTL, 0, 520 REG_UTSRST, BIT_UTSRST_HRX_SRST | BIT_UTSRST_HTX_SRST | 521 BIT_UTSRST_KEEPER_SRST | BIT_UTSRST_FC_SRST, 522 REG_UTSRST, BIT_UTSRST_HRX_SRST | BIT_UTSRST_HTX_SRST, 523 REG_HRXINTL, 0xff, 524 REG_HRXINTH, 0xff, 525 REG_TTXINTL, 0xff, 526 REG_TTXINTH, 0xff, 527 REG_TRXINTL, 0xff, 528 REG_TRXINTH, 0xff, 529 REG_HTXINTL, 0xff, 530 REG_HTXINTH, 0xff, 531 REG_FCINTR0, 0xff, 532 REG_FCINTR1, 0xff, 533 REG_FCINTR2, 0xff, 534 REG_FCINTR3, 0xff, 535 REG_FCINTR4, 0xff, 536 REG_FCINTR5, 0xff, 537 REG_FCINTR6, 0xff, 538 REG_FCINTR7, 0xff 539 ); 540 } 541 542 static void sii8620_edid_read(struct sii8620 *ctx, int ret) 543 { 544 if (ret < 0) 545 return; 546 547 sii8620_set_upstream_edid(ctx); 548 sii8620_hsic_init(ctx); 549 sii8620_enable_hpd(ctx); 550 } 551 552 static void sii8620_mr_devcap(struct sii8620 *ctx) 553 { 554 u8 dcap[MHL_DCAP_SIZE]; 555 struct device *dev = ctx->dev; 556 557 sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, dcap, MHL_DCAP_SIZE); 558 if (ctx->error < 0) 559 return; 560 561 dev_info(dev, "detected dongle MHL %d.%d, ChipID %02x%02x:%02x%02x\n", 562 dcap[MHL_DCAP_MHL_VERSION] / 16, 563 dcap[MHL_DCAP_MHL_VERSION] % 16, 564 dcap[MHL_DCAP_ADOPTER_ID_H], dcap[MHL_DCAP_ADOPTER_ID_L], 565 dcap[MHL_DCAP_DEVICE_ID_H], dcap[MHL_DCAP_DEVICE_ID_L]); 566 sii8620_update_array(ctx->devcap, dcap, MHL_DCAP_SIZE); 567 } 568 569 static void sii8620_mr_xdevcap(struct sii8620 *ctx) 570 { 571 sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, ctx->xdevcap, 572 MHL_XDC_SIZE); 573 } 574 575 static void sii8620_mt_read_devcap_recv(struct sii8620 *ctx, 576 struct sii8620_mt_msg *msg) 577 { 578 u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP 579 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 580 | BIT_EDID_CTRL_EDID_MODE_EN; 581 582 if (msg->reg[0] == MHL_READ_XDEVCAP) 583 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN; 584 585 sii8620_write_seq(ctx, 586 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE | BIT_INTR9_EDID_DONE 587 | BIT_INTR9_EDID_ERROR, 588 REG_EDID_CTRL, ctrl, 589 REG_EDID_FIFO_ADDR, 0 590 ); 591 592 if (msg->reg[0] == MHL_READ_XDEVCAP) 593 sii8620_mr_xdevcap(ctx); 594 else 595 sii8620_mr_devcap(ctx); 596 } 597 598 static void sii8620_mt_read_devcap(struct sii8620 *ctx, bool xdevcap) 599 { 600 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 601 602 if (!msg) 603 return; 604 605 msg->reg[0] = xdevcap ? MHL_READ_XDEVCAP : MHL_READ_DEVCAP; 606 msg->send = sii8620_mt_read_devcap_send; 607 msg->recv = sii8620_mt_read_devcap_recv; 608 } 609 610 static void sii8620_mt_read_devcap_reg_recv(struct sii8620 *ctx, 611 struct sii8620_mt_msg *msg) 612 { 613 u8 reg = msg->reg[1] & 0x7f; 614 615 if (msg->reg[1] & 0x80) 616 ctx->xdevcap[reg] = msg->ret; 617 else 618 ctx->devcap[reg] = msg->ret; 619 } 620 621 static void sii8620_mt_read_devcap_reg(struct sii8620 *ctx, u8 reg) 622 { 623 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 624 625 if (!msg) 626 return; 627 628 msg->reg[0] = (reg & 0x80) ? MHL_READ_XDEVCAP_REG : MHL_READ_DEVCAP_REG; 629 msg->reg[1] = reg; 630 msg->send = sii8620_mt_msc_cmd_send; 631 msg->recv = sii8620_mt_read_devcap_reg_recv; 632 } 633 634 static inline void sii8620_mt_read_xdevcap_reg(struct sii8620 *ctx, u8 reg) 635 { 636 sii8620_mt_read_devcap_reg(ctx, reg | 0x80); 637 } 638 639 static void *sii8620_burst_get_tx_buf(struct sii8620 *ctx, int len) 640 { 641 u8 *buf = &ctx->burst.tx_buf[ctx->burst.tx_count]; 642 int size = len + 2; 643 644 if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) { 645 dev_err(ctx->dev, "TX-BLK buffer exhausted\n"); 646 ctx->error = -EINVAL; 647 return NULL; 648 } 649 650 ctx->burst.tx_count += size; 651 buf[1] = len; 652 653 return buf + 2; 654 } 655 656 static u8 *sii8620_burst_get_rx_buf(struct sii8620 *ctx, int len) 657 { 658 u8 *buf = &ctx->burst.rx_buf[ctx->burst.rx_count]; 659 int size = len + 1; 660 661 if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) { 662 dev_err(ctx->dev, "RX-BLK buffer exhausted\n"); 663 ctx->error = -EINVAL; 664 return NULL; 665 } 666 667 ctx->burst.rx_count += size; 668 buf[0] = len; 669 670 return buf + 1; 671 } 672 673 static void sii8620_burst_send(struct sii8620 *ctx) 674 { 675 int tx_left = ctx->burst.tx_count; 676 u8 *d = ctx->burst.tx_buf; 677 678 while (tx_left > 0) { 679 int len = d[1] + 2; 680 681 if (ctx->burst.r_count + len > ctx->burst.r_size) 682 break; 683 d[0] = min(ctx->burst.rx_ack, 255); 684 ctx->burst.rx_ack -= d[0]; 685 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, d, len); 686 ctx->burst.r_count += len; 687 tx_left -= len; 688 d += len; 689 } 690 691 ctx->burst.tx_count = tx_left; 692 693 while (ctx->burst.rx_ack > 0) { 694 u8 b[2] = { min(ctx->burst.rx_ack, 255), 0 }; 695 696 if (ctx->burst.r_count + 2 > ctx->burst.r_size) 697 break; 698 ctx->burst.rx_ack -= b[0]; 699 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, b, 2); 700 ctx->burst.r_count += 2; 701 } 702 } 703 704 static void sii8620_burst_receive(struct sii8620 *ctx) 705 { 706 u8 buf[3], *d; 707 int count; 708 709 sii8620_read_buf(ctx, REG_EMSCRFIFOBCNTL, buf, 2); 710 count = get_unaligned_le16(buf); 711 while (count > 0) { 712 int len = min(count, 3); 713 714 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, buf, len); 715 count -= len; 716 ctx->burst.rx_ack += len - 1; 717 ctx->burst.r_count -= buf[1]; 718 if (ctx->burst.r_count < 0) 719 ctx->burst.r_count = 0; 720 721 if (len < 3 || !buf[2]) 722 continue; 723 724 len = buf[2]; 725 d = sii8620_burst_get_rx_buf(ctx, len); 726 if (!d) 727 continue; 728 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, d, len); 729 count -= len; 730 ctx->burst.rx_ack += len; 731 } 732 } 733 734 static void sii8620_burst_tx_rbuf_info(struct sii8620 *ctx, int size) 735 { 736 struct mhl_burst_blk_rcv_buffer_info *d = 737 sii8620_burst_get_tx_buf(ctx, sizeof(*d)); 738 if (!d) 739 return; 740 741 d->id = cpu_to_be16(MHL_BURST_ID_BLK_RCV_BUFFER_INFO); 742 d->size = cpu_to_le16(size); 743 } 744 745 static u8 sii8620_checksum(void *ptr, int size) 746 { 747 u8 *d = ptr, sum = 0; 748 749 while (size--) 750 sum += *d++; 751 752 return sum; 753 } 754 755 static void sii8620_mhl_burst_hdr_set(struct mhl3_burst_header *h, 756 enum mhl_burst_id id) 757 { 758 h->id = cpu_to_be16(id); 759 h->total_entries = 1; 760 h->sequence_index = 1; 761 } 762 763 static void sii8620_burst_tx_bits_per_pixel_fmt(struct sii8620 *ctx, u8 fmt) 764 { 765 struct mhl_burst_bits_per_pixel_fmt *d; 766 const int size = sizeof(*d) + sizeof(d->desc[0]); 767 768 d = sii8620_burst_get_tx_buf(ctx, size); 769 if (!d) 770 return; 771 772 sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_BITS_PER_PIXEL_FMT); 773 d->num_entries = 1; 774 d->desc[0].stream_id = 0; 775 d->desc[0].pixel_format = fmt; 776 d->hdr.checksum -= sii8620_checksum(d, size); 777 } 778 779 static void sii8620_burst_rx_all(struct sii8620 *ctx) 780 { 781 u8 *d = ctx->burst.rx_buf; 782 int count = ctx->burst.rx_count; 783 784 while (count-- > 0) { 785 int len = *d++; 786 int id = get_unaligned_be16(&d[0]); 787 788 switch (id) { 789 case MHL_BURST_ID_BLK_RCV_BUFFER_INFO: 790 ctx->burst.r_size = get_unaligned_le16(&d[2]); 791 break; 792 default: 793 break; 794 } 795 count -= len; 796 d += len; 797 } 798 ctx->burst.rx_count = 0; 799 } 800 801 static void sii8620_fetch_edid(struct sii8620 *ctx) 802 { 803 u8 lm_ddc, ddc_cmd, int3, cbus; 804 int fetched, i; 805 int edid_len = EDID_LENGTH; 806 u8 *edid; 807 808 sii8620_readb(ctx, REG_CBUS_STATUS); 809 lm_ddc = sii8620_readb(ctx, REG_LM_DDC); 810 ddc_cmd = sii8620_readb(ctx, REG_DDC_CMD); 811 812 sii8620_write_seq(ctx, 813 REG_INTR9_MASK, 0, 814 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO, 815 REG_HDCP2X_POLL_CS, 0x71, 816 REG_HDCP2X_CTRL_0, BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX, 817 REG_LM_DDC, lm_ddc | BIT_LM_DDC_SW_TPI_EN_DISABLED, 818 ); 819 820 for (i = 0; i < 256; ++i) { 821 u8 ddc_stat = sii8620_readb(ctx, REG_DDC_STATUS); 822 823 if (!(ddc_stat & BIT_DDC_STATUS_DDC_I2C_IN_PROG)) 824 break; 825 sii8620_write(ctx, REG_DDC_STATUS, 826 BIT_DDC_STATUS_DDC_FIFO_EMPTY); 827 } 828 829 sii8620_write(ctx, REG_DDC_ADDR, 0x50 << 1); 830 831 edid = kmalloc(EDID_LENGTH, GFP_KERNEL); 832 if (!edid) { 833 ctx->error = -ENOMEM; 834 return; 835 } 836 837 #define FETCH_SIZE 16 838 for (fetched = 0; fetched < edid_len; fetched += FETCH_SIZE) { 839 sii8620_readb(ctx, REG_DDC_STATUS); 840 sii8620_write_seq(ctx, 841 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_ABORT, 842 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_CLEAR_FIFO, 843 REG_DDC_STATUS, BIT_DDC_STATUS_DDC_FIFO_EMPTY 844 ); 845 sii8620_write_seq(ctx, 846 REG_DDC_SEGM, fetched >> 8, 847 REG_DDC_OFFSET, fetched & 0xff, 848 REG_DDC_DIN_CNT1, FETCH_SIZE, 849 REG_DDC_DIN_CNT2, 0, 850 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_ENH_DDC_READ_NO_ACK 851 ); 852 853 do { 854 int3 = sii8620_readb(ctx, REG_INTR3); 855 cbus = sii8620_readb(ctx, REG_CBUS_STATUS); 856 857 if (int3 & BIT_DDC_CMD_DONE) 858 break; 859 860 if (!(cbus & BIT_CBUS_STATUS_CBUS_CONNECTED)) { 861 kfree(edid); 862 edid = NULL; 863 goto end; 864 } 865 } while (1); 866 867 sii8620_readb(ctx, REG_DDC_STATUS); 868 while (sii8620_readb(ctx, REG_DDC_DOUT_CNT) < FETCH_SIZE) 869 usleep_range(10, 20); 870 871 sii8620_read_buf(ctx, REG_DDC_DATA, edid + fetched, FETCH_SIZE); 872 if (fetched + FETCH_SIZE == EDID_LENGTH) { 873 u8 ext = ((struct edid *)edid)->extensions; 874 875 if (ext) { 876 u8 *new_edid; 877 878 edid_len += ext * EDID_LENGTH; 879 new_edid = krealloc(edid, edid_len, GFP_KERNEL); 880 if (!new_edid) { 881 kfree(edid); 882 ctx->error = -ENOMEM; 883 return; 884 } 885 edid = new_edid; 886 } 887 } 888 } 889 890 sii8620_write_seq(ctx, 891 REG_INTR3_MASK, BIT_DDC_CMD_DONE, 892 REG_LM_DDC, lm_ddc 893 ); 894 895 end: 896 kfree(ctx->edid); 897 ctx->edid = (struct edid *)edid; 898 } 899 900 static void sii8620_set_upstream_edid(struct sii8620 *ctx) 901 { 902 sii8620_setbits(ctx, REG_DPD, BIT_DPD_PDNRX12 | BIT_DPD_PDIDCK_N 903 | BIT_DPD_PD_MHL_CLK_N, 0xff); 904 905 sii8620_write_seq_static(ctx, 906 REG_RX_HDMI_CTRL3, 0x00, 907 REG_PKT_FILTER_0, 0xFF, 908 REG_PKT_FILTER_1, 0xFF, 909 REG_ALICE0_BW_I2C, 0x06 910 ); 911 912 sii8620_setbits(ctx, REG_RX_HDMI_CLR_BUFFER, 913 BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN, 0xff); 914 915 sii8620_write_seq_static(ctx, 916 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 917 | BIT_EDID_CTRL_EDID_MODE_EN, 918 REG_EDID_FIFO_ADDR, 0, 919 ); 920 921 sii8620_write_buf(ctx, REG_EDID_FIFO_WR_DATA, (u8 *)ctx->edid, 922 (ctx->edid->extensions + 1) * EDID_LENGTH); 923 924 sii8620_write_seq_static(ctx, 925 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID 926 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 927 | BIT_EDID_CTRL_EDID_MODE_EN, 928 REG_INTR5_MASK, BIT_INTR_SCDT_CHANGE, 929 REG_INTR9_MASK, 0 930 ); 931 } 932 933 static void sii8620_xtal_set_rate(struct sii8620 *ctx) 934 { 935 static const struct { 936 unsigned int rate; 937 u8 div; 938 u8 tp1; 939 } rates[] = { 940 { 19200, 0x04, 0x53 }, 941 { 20000, 0x04, 0x62 }, 942 { 24000, 0x05, 0x75 }, 943 { 30000, 0x06, 0x92 }, 944 { 38400, 0x0c, 0xbc }, 945 }; 946 unsigned long rate = clk_get_rate(ctx->clk_xtal) / 1000; 947 int i; 948 949 for (i = 0; i < ARRAY_SIZE(rates) - 1; ++i) 950 if (rate <= rates[i].rate) 951 break; 952 953 if (rate != rates[i].rate) 954 dev_err(ctx->dev, "xtal clock rate(%lukHz) not supported, setting MHL for %ukHz.\n", 955 rate, rates[i].rate); 956 957 sii8620_write(ctx, REG_DIV_CTL_MAIN, rates[i].div); 958 sii8620_write(ctx, REG_HDCP2X_TP1, rates[i].tp1); 959 } 960 961 static int sii8620_hw_on(struct sii8620 *ctx) 962 { 963 int ret; 964 965 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 966 if (ret) 967 return ret; 968 usleep_range(10000, 20000); 969 return clk_prepare_enable(ctx->clk_xtal); 970 } 971 972 static int sii8620_hw_off(struct sii8620 *ctx) 973 { 974 clk_disable_unprepare(ctx->clk_xtal); 975 gpiod_set_value(ctx->gpio_reset, 1); 976 return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 977 } 978 979 static void sii8620_hw_reset(struct sii8620 *ctx) 980 { 981 usleep_range(10000, 20000); 982 gpiod_set_value(ctx->gpio_reset, 0); 983 usleep_range(5000, 20000); 984 gpiod_set_value(ctx->gpio_reset, 1); 985 usleep_range(10000, 20000); 986 gpiod_set_value(ctx->gpio_reset, 0); 987 msleep(300); 988 } 989 990 static void sii8620_cbus_reset(struct sii8620 *ctx) 991 { 992 sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST 993 | BIT_PWD_SRST_CBUS_RST_SW_EN); 994 usleep_range(10000, 20000); 995 sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN); 996 } 997 998 static void sii8620_set_auto_zone(struct sii8620 *ctx) 999 { 1000 if (ctx->mode != CM_MHL1) { 1001 sii8620_write_seq_static(ctx, 1002 REG_TX_ZONE_CTL1, 0x0, 1003 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 1004 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 1005 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE 1006 ); 1007 } else { 1008 sii8620_write_seq_static(ctx, 1009 REG_TX_ZONE_CTL1, VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE, 1010 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 1011 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE 1012 ); 1013 } 1014 } 1015 1016 static void sii8620_stop_video(struct sii8620 *ctx) 1017 { 1018 u8 uninitialized_var(val); 1019 1020 sii8620_write_seq_static(ctx, 1021 REG_TPI_INTR_EN, 0, 1022 REG_HDCP2X_INTR0_MASK, 0, 1023 REG_TPI_COPP_DATA2, 0, 1024 REG_TPI_INTR_ST0, ~0, 1025 ); 1026 1027 switch (ctx->sink_type) { 1028 case SINK_DVI: 1029 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN 1030 | BIT_TPI_SC_TPI_AV_MUTE; 1031 break; 1032 case SINK_HDMI: 1033 default: 1034 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN 1035 | BIT_TPI_SC_TPI_AV_MUTE 1036 | BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI; 1037 break; 1038 } 1039 1040 sii8620_write(ctx, REG_TPI_SC, val); 1041 } 1042 1043 static void sii8620_set_format(struct sii8620 *ctx) 1044 { 1045 u8 out_fmt; 1046 1047 if (sii8620_is_mhl3(ctx)) { 1048 sii8620_setbits(ctx, REG_M3_P0CTRL, 1049 BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED, 1050 ctx->use_packed_pixel ? ~0 : 0); 1051 } else { 1052 if (ctx->use_packed_pixel) 1053 sii8620_write_seq_static(ctx, 1054 REG_VID_MODE, BIT_VID_MODE_M1080P, 1055 REG_MHL_TOP_CTL, BIT_MHL_TOP_CTL_MHL_PP_SEL | 1, 1056 REG_MHLTX_CTL6, 0x60 1057 ); 1058 else 1059 sii8620_write_seq_static(ctx, 1060 REG_VID_MODE, 0, 1061 REG_MHL_TOP_CTL, 1, 1062 REG_MHLTX_CTL6, 0xa0 1063 ); 1064 } 1065 1066 if (ctx->use_packed_pixel) 1067 out_fmt = VAL_TPI_FORMAT(YCBCR422, FULL) | 1068 BIT_TPI_OUTPUT_CSCMODE709; 1069 else 1070 out_fmt = VAL_TPI_FORMAT(RGB, FULL); 1071 1072 sii8620_write_seq(ctx, 1073 REG_TPI_INPUT, VAL_TPI_FORMAT(RGB, FULL), 1074 REG_TPI_OUTPUT, out_fmt, 1075 ); 1076 } 1077 1078 static int mhl3_infoframe_init(struct mhl3_infoframe *frame) 1079 { 1080 memset(frame, 0, sizeof(*frame)); 1081 1082 frame->version = 3; 1083 frame->hev_format = -1; 1084 return 0; 1085 } 1086 1087 static ssize_t mhl3_infoframe_pack(struct mhl3_infoframe *frame, 1088 void *buffer, size_t size) 1089 { 1090 const int frm_len = HDMI_INFOFRAME_HEADER_SIZE + MHL3_INFOFRAME_SIZE; 1091 u8 *ptr = buffer; 1092 1093 if (size < frm_len) 1094 return -ENOSPC; 1095 1096 memset(buffer, 0, size); 1097 ptr[0] = HDMI_INFOFRAME_TYPE_VENDOR; 1098 ptr[1] = frame->version; 1099 ptr[2] = MHL3_INFOFRAME_SIZE; 1100 ptr[4] = MHL3_IEEE_OUI & 0xff; 1101 ptr[5] = (MHL3_IEEE_OUI >> 8) & 0xff; 1102 ptr[6] = (MHL3_IEEE_OUI >> 16) & 0xff; 1103 ptr[7] = frame->video_format & 0x3; 1104 ptr[7] |= (frame->format_type & 0x7) << 2; 1105 ptr[7] |= frame->sep_audio ? BIT(5) : 0; 1106 if (frame->hev_format >= 0) { 1107 ptr[9] = 1; 1108 ptr[10] = (frame->hev_format >> 8) & 0xff; 1109 ptr[11] = frame->hev_format & 0xff; 1110 } 1111 if (frame->av_delay) { 1112 bool sign = frame->av_delay < 0; 1113 int delay = sign ? -frame->av_delay : frame->av_delay; 1114 1115 ptr[12] = (delay >> 16) & 0xf; 1116 if (sign) 1117 ptr[12] |= BIT(4); 1118 ptr[13] = (delay >> 8) & 0xff; 1119 ptr[14] = delay & 0xff; 1120 } 1121 ptr[3] -= sii8620_checksum(buffer, frm_len); 1122 return frm_len; 1123 } 1124 1125 static void sii8620_set_infoframes(struct sii8620 *ctx) 1126 { 1127 struct mhl3_infoframe mhl_frm; 1128 union hdmi_infoframe frm; 1129 u8 buf[31]; 1130 int ret; 1131 1132 if (!sii8620_is_mhl3(ctx) || !ctx->use_packed_pixel) { 1133 sii8620_write(ctx, REG_TPI_SC, 1134 BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI); 1135 sii8620_write_buf(ctx, REG_TPI_AVI_CHSUM, ctx->avif + 3, 1136 ARRAY_SIZE(ctx->avif) - 3); 1137 sii8620_write(ctx, REG_PKT_FILTER_0, 1138 BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT | 1139 BIT_PKT_FILTER_0_DROP_MPEG_PKT | 1140 BIT_PKT_FILTER_0_DROP_GCP_PKT, 1141 BIT_PKT_FILTER_1_DROP_GEN_PKT); 1142 return; 1143 } 1144 1145 ret = hdmi_avi_infoframe_init(&frm.avi); 1146 frm.avi.colorspace = HDMI_COLORSPACE_YUV422; 1147 frm.avi.active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 1148 frm.avi.picture_aspect = HDMI_PICTURE_ASPECT_16_9; 1149 frm.avi.colorimetry = HDMI_COLORIMETRY_ITU_709; 1150 frm.avi.video_code = ctx->video_code; 1151 if (!ret) 1152 ret = hdmi_avi_infoframe_pack(&frm.avi, buf, ARRAY_SIZE(buf)); 1153 if (ret > 0) 1154 sii8620_write_buf(ctx, REG_TPI_AVI_CHSUM, buf + 3, ret - 3); 1155 sii8620_write(ctx, REG_PKT_FILTER_0, 1156 BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT | 1157 BIT_PKT_FILTER_0_DROP_MPEG_PKT | 1158 BIT_PKT_FILTER_0_DROP_AVI_PKT | 1159 BIT_PKT_FILTER_0_DROP_GCP_PKT, 1160 BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS | 1161 BIT_PKT_FILTER_1_DROP_GEN_PKT | 1162 BIT_PKT_FILTER_1_DROP_VSIF_PKT); 1163 1164 sii8620_write(ctx, REG_TPI_INFO_FSEL, BIT_TPI_INFO_FSEL_EN 1165 | BIT_TPI_INFO_FSEL_RPT | VAL_TPI_INFO_FSEL_VSI); 1166 ret = mhl3_infoframe_init(&mhl_frm); 1167 if (!ret) 1168 ret = mhl3_infoframe_pack(&mhl_frm, buf, ARRAY_SIZE(buf)); 1169 sii8620_write_buf(ctx, REG_TPI_INFO_B0, buf, ret); 1170 } 1171 1172 static void sii8620_start_hdmi(struct sii8620 *ctx) 1173 { 1174 sii8620_write_seq_static(ctx, 1175 REG_RX_HDMI_CTRL2, VAL_RX_HDMI_CTRL2_DEFVAL 1176 | BIT_RX_HDMI_CTRL2_USE_AV_MUTE, 1177 REG_VID_OVRRD, BIT_VID_OVRRD_PP_AUTO_DISABLE 1178 | BIT_VID_OVRRD_M1080P_OVRRD); 1179 sii8620_set_format(ctx); 1180 1181 if (!sii8620_is_mhl3(ctx)) { 1182 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE), 1183 MHL_DST_LM_CLK_MODE_NORMAL | MHL_DST_LM_PATH_ENABLED); 1184 sii8620_set_auto_zone(ctx); 1185 } else { 1186 static const struct { 1187 int max_clk; 1188 u8 zone; 1189 u8 link_rate; 1190 u8 rrp_decode; 1191 } clk_spec[] = { 1192 { 150000, VAL_TX_ZONE_CTL3_TX_ZONE_1_5GBPS, 1193 MHL_XDS_LINK_RATE_1_5_GBPS, 0x38 }, 1194 { 300000, VAL_TX_ZONE_CTL3_TX_ZONE_3GBPS, 1195 MHL_XDS_LINK_RATE_3_0_GBPS, 0x40 }, 1196 { 600000, VAL_TX_ZONE_CTL3_TX_ZONE_6GBPS, 1197 MHL_XDS_LINK_RATE_6_0_GBPS, 0x40 }, 1198 }; 1199 u8 p0_ctrl = BIT_M3_P0CTRL_MHL3_P0_PORT_EN; 1200 int clk = ctx->pixel_clock * (ctx->use_packed_pixel ? 2 : 3); 1201 int i; 1202 1203 for (i = 0; i < ARRAY_SIZE(clk_spec); ++i) 1204 if (clk < clk_spec[i].max_clk) 1205 break; 1206 1207 if (100 * clk >= 98 * clk_spec[i].max_clk) 1208 p0_ctrl |= BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN; 1209 1210 sii8620_burst_tx_bits_per_pixel_fmt(ctx, ctx->use_packed_pixel); 1211 sii8620_burst_send(ctx); 1212 sii8620_write_seq(ctx, 1213 REG_MHL_DP_CTL0, 0xf0, 1214 REG_MHL3_TX_ZONE_CTL, clk_spec[i].zone); 1215 sii8620_setbits(ctx, REG_M3_P0CTRL, 1216 BIT_M3_P0CTRL_MHL3_P0_PORT_EN 1217 | BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN, p0_ctrl); 1218 sii8620_setbits(ctx, REG_M3_POSTM, MSK_M3_POSTM_RRP_DECODE, 1219 clk_spec[i].rrp_decode); 1220 sii8620_write_seq_static(ctx, 1221 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE 1222 | BIT_M3_CTRL_H2M_SWRST, 1223 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE 1224 ); 1225 sii8620_mt_write_stat(ctx, MHL_XDS_REG(AVLINK_MODE_CONTROL), 1226 clk_spec[i].link_rate); 1227 } 1228 1229 sii8620_set_infoframes(ctx); 1230 } 1231 1232 static void sii8620_start_video(struct sii8620 *ctx) 1233 { 1234 if (!sii8620_is_mhl3(ctx)) 1235 sii8620_stop_video(ctx); 1236 1237 switch (ctx->sink_type) { 1238 case SINK_HDMI: 1239 sii8620_start_hdmi(ctx); 1240 break; 1241 case SINK_DVI: 1242 default: 1243 break; 1244 } 1245 } 1246 1247 static void sii8620_disable_hpd(struct sii8620 *ctx) 1248 { 1249 sii8620_setbits(ctx, REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID, 0); 1250 sii8620_write_seq_static(ctx, 1251 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN, 1252 REG_INTR8_MASK, 0 1253 ); 1254 } 1255 1256 static void sii8620_enable_hpd(struct sii8620 *ctx) 1257 { 1258 sii8620_setbits(ctx, REG_TMDS_CSTAT_P3, 1259 BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS 1260 | BIT_TMDS_CSTAT_P3_CLR_AVI, ~0); 1261 sii8620_write_seq_static(ctx, 1262 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN 1263 | BIT_HPD_CTRL_HPD_HIGH, 1264 ); 1265 } 1266 1267 static void sii8620_mhl_discover(struct sii8620 *ctx) 1268 { 1269 sii8620_write_seq_static(ctx, 1270 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1271 | BIT_DISC_CTRL9_DISC_PULSE_PROCEED, 1272 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_5K, VAL_PUP_20K), 1273 REG_CBUS_DISC_INTR0_MASK, BIT_MHL3_EST_INT 1274 | BIT_MHL_EST_INT 1275 | BIT_NOT_MHL_EST_INT 1276 | BIT_CBUS_MHL3_DISCON_INT 1277 | BIT_CBUS_MHL12_DISCON_INT 1278 | BIT_RGND_READY_INT, 1279 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 1280 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 1281 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE, 1282 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE 1283 | BIT_MHL_DP_CTL0_TX_OE_OVR, 1284 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE, 1285 REG_MHL_DP_CTL1, 0xA2, 1286 REG_MHL_DP_CTL2, 0x03, 1287 REG_MHL_DP_CTL3, 0x35, 1288 REG_MHL_DP_CTL5, 0x02, 1289 REG_MHL_DP_CTL6, 0x02, 1290 REG_MHL_DP_CTL7, 0x03, 1291 REG_COC_CTLC, 0xFF, 1292 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 1293 | BIT_DPD_OSC_EN | BIT_DPD_PWRON_HSIC, 1294 REG_COC_INTR_MASK, BIT_COC_PLL_LOCK_STATUS_CHANGE 1295 | BIT_COC_CALIBRATION_DONE, 1296 REG_CBUS_INT_1_MASK, BIT_CBUS_MSC_ABORT_RCVD 1297 | BIT_CBUS_CMD_ABORT, 1298 REG_CBUS_INT_0_MASK, BIT_CBUS_MSC_MT_DONE 1299 | BIT_CBUS_HPD_CHG 1300 | BIT_CBUS_MSC_MR_WRITE_STAT 1301 | BIT_CBUS_MSC_MR_MSC_MSG 1302 | BIT_CBUS_MSC_MR_WRITE_BURST 1303 | BIT_CBUS_MSC_MR_SET_INT 1304 | BIT_CBUS_MSC_MT_DONE_NACK 1305 ); 1306 } 1307 1308 static void sii8620_peer_specific_init(struct sii8620 *ctx) 1309 { 1310 if (sii8620_is_mhl3(ctx)) 1311 sii8620_write_seq_static(ctx, 1312 REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD, 1313 REG_EMSCINTRMASK1, 1314 BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR 1315 ); 1316 else 1317 sii8620_write_seq_static(ctx, 1318 REG_HDCP2X_INTR0_MASK, 0x00, 1319 REG_EMSCINTRMASK1, 0x00, 1320 REG_HDCP2X_INTR0, 0xFF, 1321 REG_INTR1, 0xFF, 1322 REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD 1323 | BIT_SYS_CTRL1_TX_CTRL_HDMI 1324 ); 1325 } 1326 1327 #define SII8620_MHL_VERSION 0x32 1328 #define SII8620_SCRATCHPAD_SIZE 16 1329 #define SII8620_INT_STAT_SIZE 0x33 1330 1331 static void sii8620_set_dev_cap(struct sii8620 *ctx) 1332 { 1333 static const u8 devcap[MHL_DCAP_SIZE] = { 1334 [MHL_DCAP_MHL_VERSION] = SII8620_MHL_VERSION, 1335 [MHL_DCAP_CAT] = MHL_DCAP_CAT_SOURCE | MHL_DCAP_CAT_POWER, 1336 [MHL_DCAP_ADOPTER_ID_H] = 0x01, 1337 [MHL_DCAP_ADOPTER_ID_L] = 0x41, 1338 [MHL_DCAP_VID_LINK_MODE] = MHL_DCAP_VID_LINK_RGB444 1339 | MHL_DCAP_VID_LINK_PPIXEL 1340 | MHL_DCAP_VID_LINK_16BPP, 1341 [MHL_DCAP_AUD_LINK_MODE] = MHL_DCAP_AUD_LINK_2CH, 1342 [MHL_DCAP_VIDEO_TYPE] = MHL_DCAP_VT_GRAPHICS, 1343 [MHL_DCAP_LOG_DEV_MAP] = MHL_DCAP_LD_GUI, 1344 [MHL_DCAP_BANDWIDTH] = 0x0f, 1345 [MHL_DCAP_FEATURE_FLAG] = MHL_DCAP_FEATURE_RCP_SUPPORT 1346 | MHL_DCAP_FEATURE_RAP_SUPPORT 1347 | MHL_DCAP_FEATURE_SP_SUPPORT, 1348 [MHL_DCAP_SCRATCHPAD_SIZE] = SII8620_SCRATCHPAD_SIZE, 1349 [MHL_DCAP_INT_STAT_SIZE] = SII8620_INT_STAT_SIZE, 1350 }; 1351 static const u8 xdcap[MHL_XDC_SIZE] = { 1352 [MHL_XDC_ECBUS_SPEEDS] = MHL_XDC_ECBUS_S_075 1353 | MHL_XDC_ECBUS_S_8BIT, 1354 [MHL_XDC_TMDS_SPEEDS] = MHL_XDC_TMDS_150 1355 | MHL_XDC_TMDS_300 | MHL_XDC_TMDS_600, 1356 [MHL_XDC_ECBUS_ROLES] = MHL_XDC_DEV_HOST, 1357 [MHL_XDC_LOG_DEV_MAPX] = MHL_XDC_LD_PHONE, 1358 }; 1359 1360 sii8620_write_buf(ctx, REG_MHL_DEVCAP_0, devcap, ARRAY_SIZE(devcap)); 1361 sii8620_write_buf(ctx, REG_MHL_EXTDEVCAP_0, xdcap, ARRAY_SIZE(xdcap)); 1362 } 1363 1364 static void sii8620_mhl_init(struct sii8620 *ctx) 1365 { 1366 sii8620_write_seq_static(ctx, 1367 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1368 REG_CBUS_MSC_COMPAT_CTRL, 1369 BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN, 1370 ); 1371 1372 sii8620_peer_specific_init(ctx); 1373 1374 sii8620_disable_hpd(ctx); 1375 1376 sii8620_write_seq_static(ctx, 1377 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO, 1378 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1379 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1380 REG_TMDS0_CCTRL1, 0x90, 1381 REG_TMDS_CLK_EN, 0x01, 1382 REG_TMDS_CH_EN, 0x11, 1383 REG_BGR_BIAS, 0x87, 1384 REG_ALICE0_ZONE_CTRL, 0xE8, 1385 REG_ALICE0_MODE_CTRL, 0x04, 1386 ); 1387 sii8620_setbits(ctx, REG_LM_DDC, BIT_LM_DDC_SW_TPI_EN_DISABLED, 0); 1388 sii8620_write_seq_static(ctx, 1389 REG_TPI_HW_OPT3, 0x76, 1390 REG_TMDS_CCTRL, BIT_TMDS_CCTRL_TMDS_OE, 1391 REG_TPI_DTD_B2, 79, 1392 ); 1393 sii8620_set_dev_cap(ctx); 1394 sii8620_write_seq_static(ctx, 1395 REG_MDT_XMIT_TIMEOUT, 100, 1396 REG_MDT_XMIT_CTRL, 0x03, 1397 REG_MDT_XFIFO_STAT, 0x00, 1398 REG_MDT_RCV_TIMEOUT, 100, 1399 REG_CBUS_LINK_CTRL_8, 0x1D, 1400 ); 1401 1402 sii8620_start_gen2_write_burst(ctx); 1403 sii8620_write_seq_static(ctx, 1404 REG_BIST_CTRL, 0x00, 1405 REG_COC_CTL1, 0x10, 1406 REG_COC_CTL2, 0x18, 1407 REG_COC_CTLF, 0x07, 1408 REG_COC_CTL11, 0xF8, 1409 REG_COC_CTL17, 0x61, 1410 REG_COC_CTL18, 0x46, 1411 REG_COC_CTL19, 0x15, 1412 REG_COC_CTL1A, 0x01, 1413 REG_MHL_COC_CTL3, BIT_MHL_COC_CTL3_COC_AECHO_EN, 1414 REG_MHL_COC_CTL4, 0x2D, 1415 REG_MHL_COC_CTL5, 0xF9, 1416 REG_MSC_HEARTBEAT_CTRL, 0x27, 1417 ); 1418 sii8620_disable_gen2_write_burst(ctx); 1419 1420 sii8620_mt_write_stat(ctx, MHL_DST_REG(VERSION), SII8620_MHL_VERSION); 1421 sii8620_mt_write_stat(ctx, MHL_DST_REG(CONNECTED_RDY), 1422 MHL_DST_CONN_DCAP_RDY | MHL_DST_CONN_XDEVCAPP_SUPP 1423 | MHL_DST_CONN_POW_STAT); 1424 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), MHL_INT_RC_DCAP_CHG); 1425 } 1426 1427 static void sii8620_emsc_enable(struct sii8620 *ctx) 1428 { 1429 u8 reg; 1430 1431 sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_EMSC_EN 1432 | BIT_GENCTL_CLR_EMSC_RFIFO 1433 | BIT_GENCTL_CLR_EMSC_XFIFO, ~0); 1434 sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_CLR_EMSC_RFIFO 1435 | BIT_GENCTL_CLR_EMSC_XFIFO, 0); 1436 sii8620_setbits(ctx, REG_COMMECNT, BIT_COMMECNT_I2C_TO_EMSC_EN, ~0); 1437 reg = sii8620_readb(ctx, REG_EMSCINTR); 1438 sii8620_write(ctx, REG_EMSCINTR, reg); 1439 sii8620_write(ctx, REG_EMSCINTRMASK, BIT_EMSCINTR_SPI_DVLD); 1440 } 1441 1442 static int sii8620_wait_for_fsm_state(struct sii8620 *ctx, u8 state) 1443 { 1444 int i; 1445 1446 for (i = 0; i < 10; ++i) { 1447 u8 s = sii8620_readb(ctx, REG_COC_STAT_0); 1448 1449 if ((s & MSK_COC_STAT_0_FSM_STATE) == state) 1450 return 0; 1451 if (!(s & BIT_COC_STAT_0_PLL_LOCKED)) 1452 return -EBUSY; 1453 usleep_range(4000, 6000); 1454 } 1455 return -ETIMEDOUT; 1456 } 1457 1458 static void sii8620_set_mode(struct sii8620 *ctx, enum sii8620_mode mode) 1459 { 1460 int ret; 1461 1462 if (ctx->mode == mode) 1463 return; 1464 1465 switch (mode) { 1466 case CM_MHL1: 1467 sii8620_write_seq_static(ctx, 1468 REG_CBUS_MSC_COMPAT_CTRL, 0x02, 1469 REG_M3_CTRL, VAL_M3_CTRL_MHL1_2_VALUE, 1470 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 1471 | BIT_DPD_OSC_EN, 1472 REG_COC_INTR_MASK, 0 1473 ); 1474 ctx->mode = mode; 1475 break; 1476 case CM_MHL3: 1477 sii8620_write(ctx, REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE); 1478 ctx->mode = mode; 1479 return; 1480 case CM_ECBUS_S: 1481 sii8620_emsc_enable(ctx); 1482 sii8620_write_seq_static(ctx, 1483 REG_TTXSPINUMS, 4, 1484 REG_TRXSPINUMS, 4, 1485 REG_TTXHSICNUMS, 0x14, 1486 REG_TRXHSICNUMS, 0x14, 1487 REG_TTXTOTNUMS, 0x18, 1488 REG_TRXTOTNUMS, 0x18, 1489 REG_PWD_SRST, BIT_PWD_SRST_COC_DOC_RST 1490 | BIT_PWD_SRST_CBUS_RST_SW_EN, 1491 REG_MHL_COC_CTL1, 0xbd, 1492 REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN, 1493 REG_COC_CTLB, 0x01, 1494 REG_COC_CTL0, 0x5c, 1495 REG_COC_CTL14, 0x03, 1496 REG_COC_CTL15, 0x80, 1497 REG_MHL_DP_CTL6, BIT_MHL_DP_CTL6_DP_TAP1_SGN 1498 | BIT_MHL_DP_CTL6_DP_TAP1_EN 1499 | BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN, 1500 REG_MHL_DP_CTL8, 0x03 1501 ); 1502 ret = sii8620_wait_for_fsm_state(ctx, 0x03); 1503 sii8620_write_seq_static(ctx, 1504 REG_COC_CTL14, 0x00, 1505 REG_COC_CTL15, 0x80 1506 ); 1507 if (!ret) 1508 sii8620_write(ctx, REG_CBUS3_CNVT, 0x85); 1509 else 1510 sii8620_disconnect(ctx); 1511 return; 1512 case CM_DISCONNECTED: 1513 ctx->mode = mode; 1514 break; 1515 default: 1516 dev_err(ctx->dev, "%s mode %d not supported\n", __func__, mode); 1517 break; 1518 } 1519 1520 sii8620_set_auto_zone(ctx); 1521 1522 if (mode != CM_MHL1) 1523 return; 1524 1525 sii8620_write_seq_static(ctx, 1526 REG_MHL_DP_CTL0, 0xBC, 1527 REG_MHL_DP_CTL1, 0xBB, 1528 REG_MHL_DP_CTL3, 0x48, 1529 REG_MHL_DP_CTL5, 0x39, 1530 REG_MHL_DP_CTL2, 0x2A, 1531 REG_MHL_DP_CTL6, 0x2A, 1532 REG_MHL_DP_CTL7, 0x08 1533 ); 1534 } 1535 1536 static void sii8620_disconnect(struct sii8620 *ctx) 1537 { 1538 sii8620_disable_gen2_write_burst(ctx); 1539 sii8620_stop_video(ctx); 1540 msleep(100); 1541 sii8620_cbus_reset(ctx); 1542 sii8620_set_mode(ctx, CM_DISCONNECTED); 1543 sii8620_write_seq_static(ctx, 1544 REG_TX_ZONE_CTL1, 0, 1545 REG_MHL_PLL_CTL0, 0x07, 1546 REG_COC_CTL0, 0x40, 1547 REG_CBUS3_CNVT, 0x84, 1548 REG_COC_CTL14, 0x00, 1549 REG_COC_CTL0, 0x40, 1550 REG_HRXCTRL3, 0x07, 1551 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 1552 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 1553 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE, 1554 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE 1555 | BIT_MHL_DP_CTL0_TX_OE_OVR, 1556 REG_MHL_DP_CTL1, 0xBB, 1557 REG_MHL_DP_CTL3, 0x48, 1558 REG_MHL_DP_CTL5, 0x3F, 1559 REG_MHL_DP_CTL2, 0x2F, 1560 REG_MHL_DP_CTL6, 0x2A, 1561 REG_MHL_DP_CTL7, 0x03 1562 ); 1563 sii8620_disable_hpd(ctx); 1564 sii8620_write_seq_static(ctx, 1565 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE, 1566 REG_MHL_COC_CTL1, 0x07, 1567 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1568 REG_DISC_CTRL8, 0x00, 1569 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1570 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1571 REG_INT_CTRL, 0x00, 1572 REG_MSC_HEARTBEAT_CTRL, 0x27, 1573 REG_DISC_CTRL1, 0x25, 1574 REG_CBUS_DISC_INTR0, (u8)~BIT_RGND_READY_INT, 1575 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT, 1576 REG_MDT_INT_1, 0xff, 1577 REG_MDT_INT_1_MASK, 0x00, 1578 REG_MDT_INT_0, 0xff, 1579 REG_MDT_INT_0_MASK, 0x00, 1580 REG_COC_INTR, 0xff, 1581 REG_COC_INTR_MASK, 0x00, 1582 REG_TRXINTH, 0xff, 1583 REG_TRXINTMH, 0x00, 1584 REG_CBUS_INT_0, 0xff, 1585 REG_CBUS_INT_0_MASK, 0x00, 1586 REG_CBUS_INT_1, 0xff, 1587 REG_CBUS_INT_1_MASK, 0x00, 1588 REG_EMSCINTR, 0xff, 1589 REG_EMSCINTRMASK, 0x00, 1590 REG_EMSCINTR1, 0xff, 1591 REG_EMSCINTRMASK1, 0x00, 1592 REG_INTR8, 0xff, 1593 REG_INTR8_MASK, 0x00, 1594 REG_TPI_INTR_ST0, 0xff, 1595 REG_TPI_INTR_EN, 0x00, 1596 REG_HDCP2X_INTR0, 0xff, 1597 REG_HDCP2X_INTR0_MASK, 0x00, 1598 REG_INTR9, 0xff, 1599 REG_INTR9_MASK, 0x00, 1600 REG_INTR3, 0xff, 1601 REG_INTR3_MASK, 0x00, 1602 REG_INTR5, 0xff, 1603 REG_INTR5_MASK, 0x00, 1604 REG_INTR2, 0xff, 1605 REG_INTR2_MASK, 0x00, 1606 ); 1607 memset(ctx->stat, 0, sizeof(ctx->stat)); 1608 memset(ctx->xstat, 0, sizeof(ctx->xstat)); 1609 memset(ctx->devcap, 0, sizeof(ctx->devcap)); 1610 memset(ctx->xdevcap, 0, sizeof(ctx->xdevcap)); 1611 ctx->cbus_status = 0; 1612 ctx->sink_type = SINK_NONE; 1613 kfree(ctx->edid); 1614 ctx->edid = NULL; 1615 sii8620_mt_cleanup(ctx); 1616 } 1617 1618 static void sii8620_mhl_disconnected(struct sii8620 *ctx) 1619 { 1620 sii8620_write_seq_static(ctx, 1621 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1622 REG_CBUS_MSC_COMPAT_CTRL, 1623 BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN 1624 ); 1625 sii8620_disconnect(ctx); 1626 } 1627 1628 static void sii8620_irq_disc(struct sii8620 *ctx) 1629 { 1630 u8 stat = sii8620_readb(ctx, REG_CBUS_DISC_INTR0); 1631 1632 if (stat & VAL_CBUS_MHL_DISCON) 1633 sii8620_mhl_disconnected(ctx); 1634 1635 if (stat & BIT_RGND_READY_INT) { 1636 u8 stat2 = sii8620_readb(ctx, REG_DISC_STAT2); 1637 1638 if ((stat2 & MSK_DISC_STAT2_RGND) == VAL_RGND_1K) { 1639 sii8620_mhl_discover(ctx); 1640 } else { 1641 sii8620_write_seq_static(ctx, 1642 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1643 | BIT_DISC_CTRL9_NOMHL_EST 1644 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1645 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT 1646 | BIT_CBUS_MHL3_DISCON_INT 1647 | BIT_CBUS_MHL12_DISCON_INT 1648 | BIT_NOT_MHL_EST_INT 1649 ); 1650 } 1651 } 1652 if (stat & BIT_MHL_EST_INT) 1653 sii8620_mhl_init(ctx); 1654 1655 sii8620_write(ctx, REG_CBUS_DISC_INTR0, stat); 1656 } 1657 1658 static void sii8620_read_burst(struct sii8620 *ctx) 1659 { 1660 u8 buf[17]; 1661 1662 sii8620_read_buf(ctx, REG_MDT_RCV_READ_PORT, buf, ARRAY_SIZE(buf)); 1663 sii8620_write(ctx, REG_MDT_RCV_CTRL, BIT_MDT_RCV_CTRL_MDT_RCV_EN | 1664 BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN | 1665 BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR); 1666 sii8620_readb(ctx, REG_MDT_RFIFO_STAT); 1667 } 1668 1669 static void sii8620_irq_g2wb(struct sii8620 *ctx) 1670 { 1671 u8 stat = sii8620_readb(ctx, REG_MDT_INT_0); 1672 1673 if (stat & BIT_MDT_IDLE_AFTER_HAWB_DISABLE) 1674 if (sii8620_is_mhl3(ctx)) 1675 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), 1676 MHL_INT_RC_FEAT_COMPLETE); 1677 1678 if (stat & BIT_MDT_RFIFO_DATA_RDY) 1679 sii8620_read_burst(ctx); 1680 1681 if (stat & BIT_MDT_XFIFO_EMPTY) 1682 sii8620_write(ctx, REG_MDT_XMIT_CTRL, 0); 1683 1684 sii8620_write(ctx, REG_MDT_INT_0, stat); 1685 } 1686 1687 static void sii8620_status_dcap_ready(struct sii8620 *ctx) 1688 { 1689 enum sii8620_mode mode; 1690 1691 mode = ctx->stat[MHL_DST_VERSION] >= 0x30 ? CM_MHL3 : CM_MHL1; 1692 if (mode > ctx->mode) 1693 sii8620_set_mode(ctx, mode); 1694 sii8620_peer_specific_init(ctx); 1695 sii8620_write(ctx, REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE 1696 | BIT_INTR9_EDID_DONE | BIT_INTR9_EDID_ERROR); 1697 } 1698 1699 static void sii8620_status_changed_path(struct sii8620 *ctx) 1700 { 1701 if (ctx->stat[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED) { 1702 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE), 1703 MHL_DST_LM_CLK_MODE_NORMAL 1704 | MHL_DST_LM_PATH_ENABLED); 1705 if (!sii8620_is_mhl3(ctx)) 1706 sii8620_mt_read_devcap(ctx, false); 1707 sii8620_mt_set_cont(ctx, sii8620_sink_detected); 1708 } else { 1709 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE), 1710 MHL_DST_LM_CLK_MODE_NORMAL); 1711 } 1712 } 1713 1714 static void sii8620_msc_mr_write_stat(struct sii8620 *ctx) 1715 { 1716 u8 st[MHL_DST_SIZE], xst[MHL_XDS_SIZE]; 1717 1718 sii8620_read_buf(ctx, REG_MHL_STAT_0, st, MHL_DST_SIZE); 1719 sii8620_read_buf(ctx, REG_MHL_EXTSTAT_0, xst, MHL_XDS_SIZE); 1720 1721 sii8620_update_array(ctx->stat, st, MHL_DST_SIZE); 1722 sii8620_update_array(ctx->xstat, xst, MHL_XDS_SIZE); 1723 1724 if (ctx->stat[MHL_DST_CONNECTED_RDY] & MHL_DST_CONN_DCAP_RDY) 1725 sii8620_status_dcap_ready(ctx); 1726 1727 if (st[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED) 1728 sii8620_status_changed_path(ctx); 1729 } 1730 1731 static void sii8620_ecbus_up(struct sii8620 *ctx, int ret) 1732 { 1733 if (ret < 0) 1734 return; 1735 1736 sii8620_set_mode(ctx, CM_ECBUS_S); 1737 } 1738 1739 static void sii8620_got_ecbus_speed(struct sii8620 *ctx, int ret) 1740 { 1741 if (ret < 0) 1742 return; 1743 1744 sii8620_mt_write_stat(ctx, MHL_XDS_REG(CURR_ECBUS_MODE), 1745 MHL_XDS_ECBUS_S | MHL_XDS_SLOT_MODE_8BIT); 1746 sii8620_mt_rap(ctx, MHL_RAP_CBUS_MODE_UP); 1747 sii8620_mt_set_cont(ctx, sii8620_ecbus_up); 1748 } 1749 1750 static void sii8620_mhl_burst_emsc_support_set(struct mhl_burst_emsc_support *d, 1751 enum mhl_burst_id id) 1752 { 1753 sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_EMSC_SUPPORT); 1754 d->num_entries = 1; 1755 d->burst_id[0] = cpu_to_be16(id); 1756 } 1757 1758 static void sii8620_send_features(struct sii8620 *ctx) 1759 { 1760 u8 buf[16]; 1761 1762 sii8620_write(ctx, REG_MDT_XMIT_CTRL, BIT_MDT_XMIT_CTRL_EN 1763 | BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN); 1764 sii8620_mhl_burst_emsc_support_set((void *)buf, 1765 MHL_BURST_ID_HID_PAYLOAD); 1766 sii8620_write_buf(ctx, REG_MDT_XMIT_WRITE_PORT, buf, ARRAY_SIZE(buf)); 1767 } 1768 1769 static bool sii8620_rcp_consume(struct sii8620 *ctx, u8 scancode) 1770 { 1771 bool pressed = !(scancode & MHL_RCP_KEY_RELEASED_MASK); 1772 1773 scancode &= MHL_RCP_KEY_ID_MASK; 1774 1775 if (!ctx->rc_dev) { 1776 dev_dbg(ctx->dev, "RCP input device not initialized\n"); 1777 return false; 1778 } 1779 1780 if (pressed) 1781 rc_keydown(ctx->rc_dev, RC_PROTO_CEC, scancode, 0); 1782 else 1783 rc_keyup(ctx->rc_dev); 1784 1785 return true; 1786 } 1787 1788 static void sii8620_msc_mr_set_int(struct sii8620 *ctx) 1789 { 1790 u8 ints[MHL_INT_SIZE]; 1791 1792 sii8620_read_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE); 1793 sii8620_write_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE); 1794 1795 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_DCAP_CHG) { 1796 switch (ctx->mode) { 1797 case CM_MHL3: 1798 sii8620_mt_read_xdevcap_reg(ctx, MHL_XDC_ECBUS_SPEEDS); 1799 sii8620_mt_set_cont(ctx, sii8620_got_ecbus_speed); 1800 break; 1801 case CM_ECBUS_S: 1802 sii8620_mt_read_devcap(ctx, true); 1803 break; 1804 default: 1805 break; 1806 } 1807 } 1808 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_REQ) 1809 sii8620_send_features(ctx); 1810 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_COMPLETE) 1811 sii8620_edid_read(ctx, 0); 1812 } 1813 1814 static struct sii8620_mt_msg *sii8620_msc_msg_first(struct sii8620 *ctx) 1815 { 1816 struct device *dev = ctx->dev; 1817 1818 if (list_empty(&ctx->mt_queue)) { 1819 dev_err(dev, "unexpected MSC MT response\n"); 1820 return NULL; 1821 } 1822 1823 return list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 1824 } 1825 1826 static void sii8620_msc_mt_done(struct sii8620 *ctx) 1827 { 1828 struct sii8620_mt_msg *msg = sii8620_msc_msg_first(ctx); 1829 1830 if (!msg) 1831 return; 1832 1833 msg->ret = sii8620_readb(ctx, REG_MSC_MT_RCVD_DATA0); 1834 ctx->mt_state = MT_STATE_DONE; 1835 } 1836 1837 static void sii8620_msc_mr_msc_msg(struct sii8620 *ctx) 1838 { 1839 struct sii8620_mt_msg *msg; 1840 u8 buf[2]; 1841 1842 sii8620_read_buf(ctx, REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA, buf, 2); 1843 1844 switch (buf[0]) { 1845 case MHL_MSC_MSG_RAPK: 1846 msg = sii8620_msc_msg_first(ctx); 1847 if (!msg) 1848 return; 1849 msg->ret = buf[1]; 1850 ctx->mt_state = MT_STATE_DONE; 1851 break; 1852 case MHL_MSC_MSG_RCP: 1853 if (!sii8620_rcp_consume(ctx, buf[1])) 1854 sii8620_mt_rcpe(ctx, 1855 MHL_RCPE_STATUS_INEFFECTIVE_KEY_CODE); 1856 sii8620_mt_rcpk(ctx, buf[1]); 1857 break; 1858 default: 1859 dev_err(ctx->dev, "%s message type %d,%d not supported", 1860 __func__, buf[0], buf[1]); 1861 } 1862 } 1863 1864 static void sii8620_irq_msc(struct sii8620 *ctx) 1865 { 1866 u8 stat = sii8620_readb(ctx, REG_CBUS_INT_0); 1867 1868 if (stat & ~BIT_CBUS_HPD_CHG) 1869 sii8620_write(ctx, REG_CBUS_INT_0, stat & ~BIT_CBUS_HPD_CHG); 1870 1871 if (stat & BIT_CBUS_HPD_CHG) { 1872 u8 cbus_stat = sii8620_readb(ctx, REG_CBUS_STATUS); 1873 1874 if ((cbus_stat ^ ctx->cbus_status) & BIT_CBUS_STATUS_CBUS_HPD) { 1875 sii8620_write(ctx, REG_CBUS_INT_0, BIT_CBUS_HPD_CHG); 1876 } else { 1877 stat ^= BIT_CBUS_STATUS_CBUS_HPD; 1878 cbus_stat ^= BIT_CBUS_STATUS_CBUS_HPD; 1879 } 1880 ctx->cbus_status = cbus_stat; 1881 } 1882 1883 if (stat & BIT_CBUS_MSC_MR_WRITE_STAT) 1884 sii8620_msc_mr_write_stat(ctx); 1885 1886 if (stat & BIT_CBUS_MSC_MR_SET_INT) 1887 sii8620_msc_mr_set_int(ctx); 1888 1889 if (stat & BIT_CBUS_MSC_MT_DONE) 1890 sii8620_msc_mt_done(ctx); 1891 1892 if (stat & BIT_CBUS_MSC_MR_MSC_MSG) 1893 sii8620_msc_mr_msc_msg(ctx); 1894 } 1895 1896 static void sii8620_irq_coc(struct sii8620 *ctx) 1897 { 1898 u8 stat = sii8620_readb(ctx, REG_COC_INTR); 1899 1900 if (stat & BIT_COC_CALIBRATION_DONE) { 1901 u8 cstat = sii8620_readb(ctx, REG_COC_STAT_0); 1902 1903 cstat &= BIT_COC_STAT_0_PLL_LOCKED | MSK_COC_STAT_0_FSM_STATE; 1904 if (cstat == (BIT_COC_STAT_0_PLL_LOCKED | 0x02)) { 1905 sii8620_write_seq_static(ctx, 1906 REG_COC_CTLB, 0, 1907 REG_TRXINTMH, BIT_TDM_INTR_SYNC_DATA 1908 | BIT_TDM_INTR_SYNC_WAIT 1909 ); 1910 } 1911 } 1912 1913 sii8620_write(ctx, REG_COC_INTR, stat); 1914 } 1915 1916 static void sii8620_irq_merr(struct sii8620 *ctx) 1917 { 1918 u8 stat = sii8620_readb(ctx, REG_CBUS_INT_1); 1919 1920 sii8620_write(ctx, REG_CBUS_INT_1, stat); 1921 } 1922 1923 static void sii8620_irq_edid(struct sii8620 *ctx) 1924 { 1925 u8 stat = sii8620_readb(ctx, REG_INTR9); 1926 1927 sii8620_write(ctx, REG_INTR9, stat); 1928 1929 if (stat & BIT_INTR9_DEVCAP_DONE) 1930 ctx->mt_state = MT_STATE_DONE; 1931 } 1932 1933 static void sii8620_scdt_high(struct sii8620 *ctx) 1934 { 1935 sii8620_write_seq_static(ctx, 1936 REG_INTR8_MASK, BIT_CEA_NEW_AVI | BIT_CEA_NEW_VSI, 1937 REG_TPI_SC, BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI, 1938 ); 1939 } 1940 1941 static void sii8620_irq_scdt(struct sii8620 *ctx) 1942 { 1943 u8 stat = sii8620_readb(ctx, REG_INTR5); 1944 1945 if (stat & BIT_INTR_SCDT_CHANGE) { 1946 u8 cstat = sii8620_readb(ctx, REG_TMDS_CSTAT_P3); 1947 1948 if (cstat & BIT_TMDS_CSTAT_P3_SCDT) 1949 sii8620_scdt_high(ctx); 1950 } 1951 1952 sii8620_write(ctx, REG_INTR5, stat); 1953 } 1954 1955 static void sii8620_new_vsi(struct sii8620 *ctx) 1956 { 1957 u8 vsif[11]; 1958 1959 sii8620_write(ctx, REG_RX_HDMI_CTRL2, 1960 VAL_RX_HDMI_CTRL2_DEFVAL | 1961 BIT_RX_HDMI_CTRL2_VSI_MON_SEL_VSI); 1962 sii8620_read_buf(ctx, REG_RX_HDMI_MON_PKT_HEADER1, vsif, 1963 ARRAY_SIZE(vsif)); 1964 } 1965 1966 static void sii8620_new_avi(struct sii8620 *ctx) 1967 { 1968 sii8620_write(ctx, REG_RX_HDMI_CTRL2, VAL_RX_HDMI_CTRL2_DEFVAL); 1969 sii8620_read_buf(ctx, REG_RX_HDMI_MON_PKT_HEADER1, ctx->avif, 1970 ARRAY_SIZE(ctx->avif)); 1971 } 1972 1973 static void sii8620_irq_infr(struct sii8620 *ctx) 1974 { 1975 u8 stat = sii8620_readb(ctx, REG_INTR8) 1976 & (BIT_CEA_NEW_VSI | BIT_CEA_NEW_AVI); 1977 1978 sii8620_write(ctx, REG_INTR8, stat); 1979 1980 if (stat & BIT_CEA_NEW_VSI) 1981 sii8620_new_vsi(ctx); 1982 1983 if (stat & BIT_CEA_NEW_AVI) 1984 sii8620_new_avi(ctx); 1985 1986 if (stat & (BIT_CEA_NEW_VSI | BIT_CEA_NEW_AVI)) 1987 sii8620_start_video(ctx); 1988 } 1989 1990 static void sii8620_got_xdevcap(struct sii8620 *ctx, int ret) 1991 { 1992 if (ret < 0) 1993 return; 1994 1995 sii8620_mt_read_devcap(ctx, false); 1996 } 1997 1998 static void sii8620_irq_tdm(struct sii8620 *ctx) 1999 { 2000 u8 stat = sii8620_readb(ctx, REG_TRXINTH); 2001 u8 tdm = sii8620_readb(ctx, REG_TRXSTA2); 2002 2003 if ((tdm & MSK_TDM_SYNCHRONIZED) == VAL_TDM_SYNCHRONIZED) { 2004 ctx->mode = CM_ECBUS_S; 2005 ctx->burst.rx_ack = 0; 2006 ctx->burst.r_size = SII8620_BURST_BUF_LEN; 2007 sii8620_burst_tx_rbuf_info(ctx, SII8620_BURST_BUF_LEN); 2008 sii8620_mt_read_devcap(ctx, true); 2009 sii8620_mt_set_cont(ctx, sii8620_got_xdevcap); 2010 } else { 2011 sii8620_write_seq_static(ctx, 2012 REG_MHL_PLL_CTL2, 0, 2013 REG_MHL_PLL_CTL2, BIT_MHL_PLL_CTL2_CLKDETECT_EN 2014 ); 2015 } 2016 2017 sii8620_write(ctx, REG_TRXINTH, stat); 2018 } 2019 2020 static void sii8620_irq_block(struct sii8620 *ctx) 2021 { 2022 u8 stat = sii8620_readb(ctx, REG_EMSCINTR); 2023 2024 if (stat & BIT_EMSCINTR_SPI_DVLD) { 2025 u8 bstat = sii8620_readb(ctx, REG_SPIBURSTSTAT); 2026 2027 if (bstat & BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE) 2028 sii8620_burst_receive(ctx); 2029 } 2030 2031 sii8620_write(ctx, REG_EMSCINTR, stat); 2032 } 2033 2034 static void sii8620_irq_ddc(struct sii8620 *ctx) 2035 { 2036 u8 stat = sii8620_readb(ctx, REG_INTR3); 2037 2038 if (stat & BIT_DDC_CMD_DONE) { 2039 sii8620_write(ctx, REG_INTR3_MASK, 0); 2040 if (sii8620_is_mhl3(ctx)) 2041 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), 2042 MHL_INT_RC_FEAT_REQ); 2043 else 2044 sii8620_edid_read(ctx, 0); 2045 } 2046 sii8620_write(ctx, REG_INTR3, stat); 2047 } 2048 2049 /* endian agnostic, non-volatile version of test_bit */ 2050 static bool sii8620_test_bit(unsigned int nr, const u8 *addr) 2051 { 2052 return 1 & (addr[nr / BITS_PER_BYTE] >> (nr % BITS_PER_BYTE)); 2053 } 2054 2055 static irqreturn_t sii8620_irq_thread(int irq, void *data) 2056 { 2057 static const struct { 2058 int bit; 2059 void (*handler)(struct sii8620 *ctx); 2060 } irq_vec[] = { 2061 { BIT_FAST_INTR_STAT_DISC, sii8620_irq_disc }, 2062 { BIT_FAST_INTR_STAT_G2WB, sii8620_irq_g2wb }, 2063 { BIT_FAST_INTR_STAT_COC, sii8620_irq_coc }, 2064 { BIT_FAST_INTR_STAT_TDM, sii8620_irq_tdm }, 2065 { BIT_FAST_INTR_STAT_MSC, sii8620_irq_msc }, 2066 { BIT_FAST_INTR_STAT_MERR, sii8620_irq_merr }, 2067 { BIT_FAST_INTR_STAT_BLOCK, sii8620_irq_block }, 2068 { BIT_FAST_INTR_STAT_EDID, sii8620_irq_edid }, 2069 { BIT_FAST_INTR_STAT_DDC, sii8620_irq_ddc }, 2070 { BIT_FAST_INTR_STAT_SCDT, sii8620_irq_scdt }, 2071 { BIT_FAST_INTR_STAT_INFR, sii8620_irq_infr }, 2072 }; 2073 struct sii8620 *ctx = data; 2074 u8 stats[LEN_FAST_INTR_STAT]; 2075 int i, ret; 2076 2077 mutex_lock(&ctx->lock); 2078 2079 sii8620_read_buf(ctx, REG_FAST_INTR_STAT, stats, ARRAY_SIZE(stats)); 2080 for (i = 0; i < ARRAY_SIZE(irq_vec); ++i) 2081 if (sii8620_test_bit(irq_vec[i].bit, stats)) 2082 irq_vec[i].handler(ctx); 2083 2084 sii8620_burst_rx_all(ctx); 2085 sii8620_mt_work(ctx); 2086 sii8620_burst_send(ctx); 2087 2088 ret = sii8620_clear_error(ctx); 2089 if (ret) { 2090 dev_err(ctx->dev, "Error during IRQ handling, %d.\n", ret); 2091 sii8620_mhl_disconnected(ctx); 2092 } 2093 mutex_unlock(&ctx->lock); 2094 2095 return IRQ_HANDLED; 2096 } 2097 2098 static void sii8620_cable_in(struct sii8620 *ctx) 2099 { 2100 struct device *dev = ctx->dev; 2101 u8 ver[5]; 2102 int ret; 2103 2104 ret = sii8620_hw_on(ctx); 2105 if (ret) { 2106 dev_err(dev, "Error powering on, %d.\n", ret); 2107 return; 2108 } 2109 sii8620_hw_reset(ctx); 2110 2111 sii8620_read_buf(ctx, REG_VND_IDL, ver, ARRAY_SIZE(ver)); 2112 ret = sii8620_clear_error(ctx); 2113 if (ret) { 2114 dev_err(dev, "Error accessing I2C bus, %d.\n", ret); 2115 return; 2116 } 2117 2118 dev_info(dev, "ChipID %02x%02x:%02x%02x rev %02x.\n", ver[1], ver[0], 2119 ver[3], ver[2], ver[4]); 2120 2121 sii8620_write(ctx, REG_DPD, 2122 BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN); 2123 2124 sii8620_xtal_set_rate(ctx); 2125 sii8620_disconnect(ctx); 2126 2127 sii8620_write_seq_static(ctx, 2128 REG_MHL_CBUS_CTL0, VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONG 2129 | VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_734, 2130 REG_MHL_CBUS_CTL1, VAL_MHL_CBUS_CTL1_1115_OHM, 2131 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN, 2132 ); 2133 2134 ret = sii8620_clear_error(ctx); 2135 if (ret) { 2136 dev_err(dev, "Error accessing I2C bus, %d.\n", ret); 2137 return; 2138 } 2139 2140 enable_irq(to_i2c_client(ctx->dev)->irq); 2141 } 2142 2143 static void sii8620_init_rcp_input_dev(struct sii8620 *ctx) 2144 { 2145 struct rc_dev *rc_dev; 2146 int ret; 2147 2148 rc_dev = rc_allocate_device(RC_DRIVER_SCANCODE); 2149 if (!rc_dev) { 2150 dev_err(ctx->dev, "Failed to allocate RC device\n"); 2151 ctx->error = -ENOMEM; 2152 return; 2153 } 2154 2155 rc_dev->input_phys = "sii8620/input0"; 2156 rc_dev->input_id.bustype = BUS_VIRTUAL; 2157 rc_dev->map_name = RC_MAP_CEC; 2158 rc_dev->allowed_protocols = RC_PROTO_BIT_CEC; 2159 rc_dev->driver_name = "sii8620"; 2160 rc_dev->device_name = "sii8620"; 2161 2162 ret = rc_register_device(rc_dev); 2163 2164 if (ret) { 2165 dev_err(ctx->dev, "Failed to register RC device\n"); 2166 ctx->error = ret; 2167 rc_free_device(ctx->rc_dev); 2168 return; 2169 } 2170 ctx->rc_dev = rc_dev; 2171 } 2172 2173 static inline struct sii8620 *bridge_to_sii8620(struct drm_bridge *bridge) 2174 { 2175 return container_of(bridge, struct sii8620, bridge); 2176 } 2177 2178 static int sii8620_attach(struct drm_bridge *bridge) 2179 { 2180 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2181 2182 sii8620_init_rcp_input_dev(ctx); 2183 2184 return sii8620_clear_error(ctx); 2185 } 2186 2187 static void sii8620_detach(struct drm_bridge *bridge) 2188 { 2189 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2190 2191 rc_unregister_device(ctx->rc_dev); 2192 } 2193 2194 static enum drm_mode_status sii8620_mode_valid(struct drm_bridge *bridge, 2195 const struct drm_display_mode *mode) 2196 { 2197 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2198 bool can_pack = ctx->devcap[MHL_DCAP_VID_LINK_MODE] & 2199 MHL_DCAP_VID_LINK_PPIXEL; 2200 unsigned int max_pclk = sii8620_is_mhl3(ctx) ? MHL3_MAX_LCLK : 2201 MHL1_MAX_LCLK; 2202 max_pclk /= can_pack ? 2 : 3; 2203 2204 return (mode->clock > max_pclk) ? MODE_CLOCK_HIGH : MODE_OK; 2205 } 2206 2207 static bool sii8620_mode_fixup(struct drm_bridge *bridge, 2208 const struct drm_display_mode *mode, 2209 struct drm_display_mode *adjusted_mode) 2210 { 2211 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2212 int max_lclk; 2213 bool ret = true; 2214 2215 mutex_lock(&ctx->lock); 2216 2217 max_lclk = sii8620_is_mhl3(ctx) ? MHL3_MAX_LCLK : MHL1_MAX_LCLK; 2218 if (max_lclk > 3 * adjusted_mode->clock) { 2219 ctx->use_packed_pixel = 0; 2220 goto end; 2221 } 2222 if ((ctx->devcap[MHL_DCAP_VID_LINK_MODE] & MHL_DCAP_VID_LINK_PPIXEL) && 2223 max_lclk > 2 * adjusted_mode->clock) { 2224 ctx->use_packed_pixel = 1; 2225 goto end; 2226 } 2227 ret = false; 2228 end: 2229 if (ret) { 2230 u8 vic = drm_match_cea_mode(adjusted_mode); 2231 2232 if (!vic) { 2233 union hdmi_infoframe frm; 2234 u8 mhl_vic[] = { 0, 95, 94, 93, 98 }; 2235 2236 drm_hdmi_vendor_infoframe_from_display_mode( 2237 &frm.vendor.hdmi, adjusted_mode); 2238 vic = frm.vendor.hdmi.vic; 2239 if (vic >= ARRAY_SIZE(mhl_vic)) 2240 vic = 0; 2241 vic = mhl_vic[vic]; 2242 } 2243 ctx->video_code = vic; 2244 ctx->pixel_clock = adjusted_mode->clock; 2245 } 2246 mutex_unlock(&ctx->lock); 2247 return ret; 2248 } 2249 2250 static const struct drm_bridge_funcs sii8620_bridge_funcs = { 2251 .attach = sii8620_attach, 2252 .detach = sii8620_detach, 2253 .mode_fixup = sii8620_mode_fixup, 2254 .mode_valid = sii8620_mode_valid, 2255 }; 2256 2257 static int sii8620_probe(struct i2c_client *client, 2258 const struct i2c_device_id *id) 2259 { 2260 struct device *dev = &client->dev; 2261 struct sii8620 *ctx; 2262 int ret; 2263 2264 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 2265 if (!ctx) 2266 return -ENOMEM; 2267 2268 ctx->dev = dev; 2269 mutex_init(&ctx->lock); 2270 INIT_LIST_HEAD(&ctx->mt_queue); 2271 2272 ctx->clk_xtal = devm_clk_get(dev, "xtal"); 2273 if (IS_ERR(ctx->clk_xtal)) { 2274 dev_err(dev, "failed to get xtal clock from DT\n"); 2275 return PTR_ERR(ctx->clk_xtal); 2276 } 2277 2278 if (!client->irq) { 2279 dev_err(dev, "no irq provided\n"); 2280 return -EINVAL; 2281 } 2282 irq_set_status_flags(client->irq, IRQ_NOAUTOEN); 2283 ret = devm_request_threaded_irq(dev, client->irq, NULL, 2284 sii8620_irq_thread, 2285 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 2286 "sii8620", ctx); 2287 if (ret < 0) { 2288 dev_err(dev, "failed to install IRQ handler\n"); 2289 return ret; 2290 } 2291 2292 ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); 2293 if (IS_ERR(ctx->gpio_reset)) { 2294 dev_err(dev, "failed to get reset gpio from DT\n"); 2295 return PTR_ERR(ctx->gpio_reset); 2296 } 2297 2298 ctx->supplies[0].supply = "cvcc10"; 2299 ctx->supplies[1].supply = "iovcc18"; 2300 ret = devm_regulator_bulk_get(dev, 2, ctx->supplies); 2301 if (ret) 2302 return ret; 2303 2304 i2c_set_clientdata(client, ctx); 2305 2306 ctx->bridge.funcs = &sii8620_bridge_funcs; 2307 ctx->bridge.of_node = dev->of_node; 2308 drm_bridge_add(&ctx->bridge); 2309 2310 sii8620_cable_in(ctx); 2311 2312 return 0; 2313 } 2314 2315 static int sii8620_remove(struct i2c_client *client) 2316 { 2317 struct sii8620 *ctx = i2c_get_clientdata(client); 2318 2319 disable_irq(to_i2c_client(ctx->dev)->irq); 2320 sii8620_hw_off(ctx); 2321 drm_bridge_remove(&ctx->bridge); 2322 2323 return 0; 2324 } 2325 2326 static const struct of_device_id sii8620_dt_match[] = { 2327 { .compatible = "sil,sii8620" }, 2328 { }, 2329 }; 2330 MODULE_DEVICE_TABLE(of, sii8620_dt_match); 2331 2332 static const struct i2c_device_id sii8620_id[] = { 2333 { "sii8620", 0 }, 2334 { }, 2335 }; 2336 2337 MODULE_DEVICE_TABLE(i2c, sii8620_id); 2338 static struct i2c_driver sii8620_driver = { 2339 .driver = { 2340 .name = "sii8620", 2341 .of_match_table = of_match_ptr(sii8620_dt_match), 2342 }, 2343 .probe = sii8620_probe, 2344 .remove = sii8620_remove, 2345 .id_table = sii8620_id, 2346 }; 2347 2348 module_i2c_driver(sii8620_driver); 2349 MODULE_LICENSE("GPL v2"); 2350