1 /* 2 * Silicon Image SiI8620 HDMI/MHL bridge driver 3 * 4 * Copyright (C) 2015, Samsung Electronics Co., Ltd. 5 * Andrzej Hajda <a.hajda@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <asm/unaligned.h> 13 14 #include <drm/bridge/mhl.h> 15 #include <drm/drm_crtc.h> 16 #include <drm/drm_edid.h> 17 18 #include <linux/clk.h> 19 #include <linux/delay.h> 20 #include <linux/extcon.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/i2c.h> 23 #include <linux/interrupt.h> 24 #include <linux/irq.h> 25 #include <linux/kernel.h> 26 #include <linux/list.h> 27 #include <linux/module.h> 28 #include <linux/mutex.h> 29 #include <linux/of_graph.h> 30 #include <linux/regulator/consumer.h> 31 #include <linux/slab.h> 32 33 #include <media/rc-core.h> 34 35 #include "sil-sii8620.h" 36 37 #define SII8620_BURST_BUF_LEN 288 38 #define VAL_RX_HDMI_CTRL2_DEFVAL VAL_RX_HDMI_CTRL2_IDLE_CNT(3) 39 40 #define MHL1_MAX_PCLK 75000 41 #define MHL1_MAX_PCLK_PP_MODE 150000 42 #define MHL3_MAX_PCLK 200000 43 #define MHL3_MAX_PCLK_PP_MODE 300000 44 45 enum sii8620_mode { 46 CM_DISCONNECTED, 47 CM_DISCOVERY, 48 CM_MHL1, 49 CM_MHL3, 50 CM_ECBUS_S 51 }; 52 53 enum sii8620_sink_type { 54 SINK_NONE, 55 SINK_HDMI, 56 SINK_DVI 57 }; 58 59 enum sii8620_mt_state { 60 MT_STATE_READY, 61 MT_STATE_BUSY, 62 MT_STATE_DONE 63 }; 64 65 struct sii8620 { 66 struct drm_bridge bridge; 67 struct device *dev; 68 struct rc_dev *rc_dev; 69 struct clk *clk_xtal; 70 struct gpio_desc *gpio_reset; 71 struct gpio_desc *gpio_int; 72 struct regulator_bulk_data supplies[2]; 73 struct mutex lock; /* context lock, protects fields below */ 74 int error; 75 int pixel_clock; 76 unsigned int use_packed_pixel:1; 77 int video_code; 78 enum sii8620_mode mode; 79 enum sii8620_sink_type sink_type; 80 u8 cbus_status; 81 u8 stat[MHL_DST_SIZE]; 82 u8 xstat[MHL_XDS_SIZE]; 83 u8 devcap[MHL_DCAP_SIZE]; 84 u8 xdevcap[MHL_XDC_SIZE]; 85 u8 avif[HDMI_INFOFRAME_SIZE(AVI)]; 86 struct edid *edid; 87 unsigned int gen2_write_burst:1; 88 enum sii8620_mt_state mt_state; 89 struct extcon_dev *extcon; 90 struct notifier_block extcon_nb; 91 struct work_struct extcon_wq; 92 int cable_state; 93 struct list_head mt_queue; 94 struct { 95 int r_size; 96 int r_count; 97 int rx_ack; 98 int rx_count; 99 u8 rx_buf[32]; 100 int tx_count; 101 u8 tx_buf[32]; 102 } burst; 103 }; 104 105 struct sii8620_mt_msg; 106 107 typedef void (*sii8620_mt_msg_cb)(struct sii8620 *ctx, 108 struct sii8620_mt_msg *msg); 109 110 typedef void (*sii8620_cb)(struct sii8620 *ctx, int ret); 111 112 struct sii8620_mt_msg { 113 struct list_head node; 114 u8 reg[4]; 115 u8 ret; 116 sii8620_mt_msg_cb send; 117 sii8620_mt_msg_cb recv; 118 sii8620_cb continuation; 119 }; 120 121 static const u8 sii8620_i2c_page[] = { 122 0x39, /* Main System */ 123 0x3d, /* TDM and HSIC */ 124 0x49, /* TMDS Receiver, MHL EDID */ 125 0x4d, /* eMSC, HDCP, HSIC */ 126 0x5d, /* MHL Spec */ 127 0x64, /* MHL CBUS */ 128 0x59, /* Hardware TPI (Transmitter Programming Interface) */ 129 0x61, /* eCBUS-S, eCBUS-D */ 130 }; 131 132 static void sii8620_fetch_edid(struct sii8620 *ctx); 133 static void sii8620_set_upstream_edid(struct sii8620 *ctx); 134 static void sii8620_enable_hpd(struct sii8620 *ctx); 135 static void sii8620_mhl_disconnected(struct sii8620 *ctx); 136 static void sii8620_disconnect(struct sii8620 *ctx); 137 138 static int sii8620_clear_error(struct sii8620 *ctx) 139 { 140 int ret = ctx->error; 141 142 ctx->error = 0; 143 return ret; 144 } 145 146 static void sii8620_read_buf(struct sii8620 *ctx, u16 addr, u8 *buf, int len) 147 { 148 struct device *dev = ctx->dev; 149 struct i2c_client *client = to_i2c_client(dev); 150 u8 data = addr; 151 struct i2c_msg msg[] = { 152 { 153 .addr = sii8620_i2c_page[addr >> 8], 154 .flags = client->flags, 155 .len = 1, 156 .buf = &data 157 }, 158 { 159 .addr = sii8620_i2c_page[addr >> 8], 160 .flags = client->flags | I2C_M_RD, 161 .len = len, 162 .buf = buf 163 }, 164 }; 165 int ret; 166 167 if (ctx->error) 168 return; 169 170 ret = i2c_transfer(client->adapter, msg, 2); 171 dev_dbg(dev, "read at %04x: %*ph, %d\n", addr, len, buf, ret); 172 173 if (ret != 2) { 174 dev_err(dev, "Read at %#06x of %d bytes failed with code %d.\n", 175 addr, len, ret); 176 ctx->error = ret < 0 ? ret : -EIO; 177 } 178 } 179 180 static u8 sii8620_readb(struct sii8620 *ctx, u16 addr) 181 { 182 u8 ret; 183 184 sii8620_read_buf(ctx, addr, &ret, 1); 185 return ret; 186 } 187 188 static void sii8620_write_buf(struct sii8620 *ctx, u16 addr, const u8 *buf, 189 int len) 190 { 191 struct device *dev = ctx->dev; 192 struct i2c_client *client = to_i2c_client(dev); 193 u8 data[2]; 194 struct i2c_msg msg = { 195 .addr = sii8620_i2c_page[addr >> 8], 196 .flags = client->flags, 197 .len = len + 1, 198 }; 199 int ret; 200 201 if (ctx->error) 202 return; 203 204 if (len > 1) { 205 msg.buf = kmalloc(len + 1, GFP_KERNEL); 206 if (!msg.buf) { 207 ctx->error = -ENOMEM; 208 return; 209 } 210 memcpy(msg.buf + 1, buf, len); 211 } else { 212 msg.buf = data; 213 msg.buf[1] = *buf; 214 } 215 216 msg.buf[0] = addr; 217 218 ret = i2c_transfer(client->adapter, &msg, 1); 219 dev_dbg(dev, "write at %04x: %*ph, %d\n", addr, len, buf, ret); 220 221 if (ret != 1) { 222 dev_err(dev, "Write at %#06x of %*ph failed with code %d.\n", 223 addr, len, buf, ret); 224 ctx->error = ret ?: -EIO; 225 } 226 227 if (len > 1) 228 kfree(msg.buf); 229 } 230 231 #define sii8620_write(ctx, addr, arr...) \ 232 ({\ 233 u8 d[] = { arr }; \ 234 sii8620_write_buf(ctx, addr, d, ARRAY_SIZE(d)); \ 235 }) 236 237 static void __sii8620_write_seq(struct sii8620 *ctx, const u16 *seq, int len) 238 { 239 int i; 240 241 for (i = 0; i < len; i += 2) 242 sii8620_write(ctx, seq[i], seq[i + 1]); 243 } 244 245 #define sii8620_write_seq(ctx, seq...) \ 246 ({\ 247 const u16 d[] = { seq }; \ 248 __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \ 249 }) 250 251 #define sii8620_write_seq_static(ctx, seq...) \ 252 ({\ 253 static const u16 d[] = { seq }; \ 254 __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \ 255 }) 256 257 static void sii8620_setbits(struct sii8620 *ctx, u16 addr, u8 mask, u8 val) 258 { 259 val = (val & mask) | (sii8620_readb(ctx, addr) & ~mask); 260 sii8620_write(ctx, addr, val); 261 } 262 263 static inline bool sii8620_is_mhl3(struct sii8620 *ctx) 264 { 265 return ctx->mode >= CM_MHL3; 266 } 267 268 static void sii8620_mt_cleanup(struct sii8620 *ctx) 269 { 270 struct sii8620_mt_msg *msg, *n; 271 272 list_for_each_entry_safe(msg, n, &ctx->mt_queue, node) { 273 list_del(&msg->node); 274 kfree(msg); 275 } 276 ctx->mt_state = MT_STATE_READY; 277 } 278 279 static void sii8620_mt_work(struct sii8620 *ctx) 280 { 281 struct sii8620_mt_msg *msg; 282 283 if (ctx->error) 284 return; 285 if (ctx->mt_state == MT_STATE_BUSY || list_empty(&ctx->mt_queue)) 286 return; 287 288 if (ctx->mt_state == MT_STATE_DONE) { 289 ctx->mt_state = MT_STATE_READY; 290 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, 291 node); 292 list_del(&msg->node); 293 if (msg->recv) 294 msg->recv(ctx, msg); 295 if (msg->continuation) 296 msg->continuation(ctx, msg->ret); 297 kfree(msg); 298 } 299 300 if (ctx->mt_state != MT_STATE_READY || list_empty(&ctx->mt_queue)) 301 return; 302 303 ctx->mt_state = MT_STATE_BUSY; 304 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 305 if (msg->send) 306 msg->send(ctx, msg); 307 } 308 309 static void sii8620_enable_gen2_write_burst(struct sii8620 *ctx) 310 { 311 u8 ctrl = BIT_MDT_RCV_CTRL_MDT_RCV_EN; 312 313 if (ctx->gen2_write_burst) 314 return; 315 316 if (ctx->mode >= CM_MHL1) 317 ctrl |= BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN; 318 319 sii8620_write_seq(ctx, 320 REG_MDT_RCV_TIMEOUT, 100, 321 REG_MDT_RCV_CTRL, ctrl 322 ); 323 ctx->gen2_write_burst = 1; 324 } 325 326 static void sii8620_disable_gen2_write_burst(struct sii8620 *ctx) 327 { 328 if (!ctx->gen2_write_burst) 329 return; 330 331 sii8620_write_seq_static(ctx, 332 REG_MDT_XMIT_CTRL, 0, 333 REG_MDT_RCV_CTRL, 0 334 ); 335 ctx->gen2_write_burst = 0; 336 } 337 338 static void sii8620_start_gen2_write_burst(struct sii8620 *ctx) 339 { 340 sii8620_write_seq_static(ctx, 341 REG_MDT_INT_1_MASK, BIT_MDT_RCV_TIMEOUT 342 | BIT_MDT_RCV_SM_ABORT_PKT_RCVD | BIT_MDT_RCV_SM_ERROR 343 | BIT_MDT_XMIT_TIMEOUT | BIT_MDT_XMIT_SM_ABORT_PKT_RCVD 344 | BIT_MDT_XMIT_SM_ERROR, 345 REG_MDT_INT_0_MASK, BIT_MDT_XFIFO_EMPTY 346 | BIT_MDT_IDLE_AFTER_HAWB_DISABLE 347 | BIT_MDT_RFIFO_DATA_RDY 348 ); 349 sii8620_enable_gen2_write_burst(ctx); 350 } 351 352 static void sii8620_mt_msc_cmd_send(struct sii8620 *ctx, 353 struct sii8620_mt_msg *msg) 354 { 355 if (msg->reg[0] == MHL_SET_INT && 356 msg->reg[1] == MHL_INT_REG(RCHANGE) && 357 msg->reg[2] == MHL_INT_RC_FEAT_REQ) 358 sii8620_enable_gen2_write_burst(ctx); 359 else 360 sii8620_disable_gen2_write_burst(ctx); 361 362 switch (msg->reg[0]) { 363 case MHL_WRITE_STAT: 364 case MHL_SET_INT: 365 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg + 1, 2); 366 sii8620_write(ctx, REG_MSC_COMMAND_START, 367 BIT_MSC_COMMAND_START_WRITE_STAT); 368 break; 369 case MHL_MSC_MSG: 370 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg, 3); 371 sii8620_write(ctx, REG_MSC_COMMAND_START, 372 BIT_MSC_COMMAND_START_MSC_MSG); 373 break; 374 case MHL_READ_DEVCAP_REG: 375 case MHL_READ_XDEVCAP_REG: 376 sii8620_write(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg[1]); 377 sii8620_write(ctx, REG_MSC_COMMAND_START, 378 BIT_MSC_COMMAND_START_READ_DEVCAP); 379 break; 380 default: 381 dev_err(ctx->dev, "%s: command %#x not supported\n", __func__, 382 msg->reg[0]); 383 } 384 } 385 386 static struct sii8620_mt_msg *sii8620_mt_msg_new(struct sii8620 *ctx) 387 { 388 struct sii8620_mt_msg *msg = kzalloc(sizeof(*msg), GFP_KERNEL); 389 390 if (!msg) 391 ctx->error = -ENOMEM; 392 else 393 list_add_tail(&msg->node, &ctx->mt_queue); 394 395 return msg; 396 } 397 398 static void sii8620_mt_set_cont(struct sii8620 *ctx, sii8620_cb cont) 399 { 400 struct sii8620_mt_msg *msg; 401 402 if (ctx->error) 403 return; 404 405 if (list_empty(&ctx->mt_queue)) { 406 ctx->error = -EINVAL; 407 return; 408 } 409 msg = list_last_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 410 msg->continuation = cont; 411 } 412 413 static void sii8620_mt_msc_cmd(struct sii8620 *ctx, u8 cmd, u8 arg1, u8 arg2) 414 { 415 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 416 417 if (!msg) 418 return; 419 420 msg->reg[0] = cmd; 421 msg->reg[1] = arg1; 422 msg->reg[2] = arg2; 423 msg->send = sii8620_mt_msc_cmd_send; 424 } 425 426 static void sii8620_mt_write_stat(struct sii8620 *ctx, u8 reg, u8 val) 427 { 428 sii8620_mt_msc_cmd(ctx, MHL_WRITE_STAT, reg, val); 429 } 430 431 static inline void sii8620_mt_set_int(struct sii8620 *ctx, u8 irq, u8 mask) 432 { 433 sii8620_mt_msc_cmd(ctx, MHL_SET_INT, irq, mask); 434 } 435 436 static void sii8620_mt_msc_msg(struct sii8620 *ctx, u8 cmd, u8 data) 437 { 438 sii8620_mt_msc_cmd(ctx, MHL_MSC_MSG, cmd, data); 439 } 440 441 static void sii8620_mt_rap(struct sii8620 *ctx, u8 code) 442 { 443 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RAP, code); 444 } 445 446 static void sii8620_mt_rcpk(struct sii8620 *ctx, u8 code) 447 { 448 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPK, code); 449 } 450 451 static void sii8620_mt_rcpe(struct sii8620 *ctx, u8 code) 452 { 453 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPE, code); 454 } 455 456 static void sii8620_mt_read_devcap_send(struct sii8620 *ctx, 457 struct sii8620_mt_msg *msg) 458 { 459 u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP 460 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 461 | BIT_EDID_CTRL_EDID_MODE_EN; 462 463 if (msg->reg[0] == MHL_READ_XDEVCAP) 464 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN; 465 466 sii8620_write_seq(ctx, 467 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE, 468 REG_EDID_CTRL, ctrl, 469 REG_TPI_CBUS_START, BIT_TPI_CBUS_START_GET_DEVCAP_START 470 ); 471 } 472 473 /* copy src to dst and set changed bits in src */ 474 static void sii8620_update_array(u8 *dst, u8 *src, int count) 475 { 476 while (--count >= 0) { 477 *src ^= *dst; 478 *dst++ ^= *src++; 479 } 480 } 481 482 static void sii8620_sink_detected(struct sii8620 *ctx, int ret) 483 { 484 static const char * const sink_str[] = { 485 [SINK_NONE] = "NONE", 486 [SINK_HDMI] = "HDMI", 487 [SINK_DVI] = "DVI" 488 }; 489 490 char sink_name[20]; 491 struct device *dev = ctx->dev; 492 493 if (ret < 0) 494 return; 495 496 sii8620_fetch_edid(ctx); 497 if (!ctx->edid) { 498 dev_err(ctx->dev, "Cannot fetch EDID\n"); 499 sii8620_mhl_disconnected(ctx); 500 return; 501 } 502 503 if (drm_detect_hdmi_monitor(ctx->edid)) 504 ctx->sink_type = SINK_HDMI; 505 else 506 ctx->sink_type = SINK_DVI; 507 508 drm_edid_get_monitor_name(ctx->edid, sink_name, ARRAY_SIZE(sink_name)); 509 510 dev_info(dev, "detected sink(type: %s): %s\n", 511 sink_str[ctx->sink_type], sink_name); 512 } 513 514 static void sii8620_hsic_init(struct sii8620 *ctx) 515 { 516 if (!sii8620_is_mhl3(ctx)) 517 return; 518 519 sii8620_write(ctx, REG_FCGC, 520 BIT_FCGC_HSIC_HOSTMODE | BIT_FCGC_HSIC_ENABLE); 521 sii8620_setbits(ctx, REG_HRXCTRL3, 522 BIT_HRXCTRL3_HRX_STAY_RESET | BIT_HRXCTRL3_STATUS_EN, ~0); 523 sii8620_setbits(ctx, REG_TTXNUMB, MSK_TTXNUMB_TTX_NUMBPS, 4); 524 sii8620_setbits(ctx, REG_TRXCTRL, BIT_TRXCTRL_TRX_FROM_SE_COC, ~0); 525 sii8620_setbits(ctx, REG_HTXCTRL, BIT_HTXCTRL_HTX_DRVCONN1, 0); 526 sii8620_setbits(ctx, REG_KEEPER, MSK_KEEPER_MODE, VAL_KEEPER_MODE_HOST); 527 sii8620_write_seq_static(ctx, 528 REG_TDMLLCTL, 0, 529 REG_UTSRST, BIT_UTSRST_HRX_SRST | BIT_UTSRST_HTX_SRST | 530 BIT_UTSRST_KEEPER_SRST | BIT_UTSRST_FC_SRST, 531 REG_UTSRST, BIT_UTSRST_HRX_SRST | BIT_UTSRST_HTX_SRST, 532 REG_HRXINTL, 0xff, 533 REG_HRXINTH, 0xff, 534 REG_TTXINTL, 0xff, 535 REG_TTXINTH, 0xff, 536 REG_TRXINTL, 0xff, 537 REG_TRXINTH, 0xff, 538 REG_HTXINTL, 0xff, 539 REG_HTXINTH, 0xff, 540 REG_FCINTR0, 0xff, 541 REG_FCINTR1, 0xff, 542 REG_FCINTR2, 0xff, 543 REG_FCINTR3, 0xff, 544 REG_FCINTR4, 0xff, 545 REG_FCINTR5, 0xff, 546 REG_FCINTR6, 0xff, 547 REG_FCINTR7, 0xff 548 ); 549 } 550 551 static void sii8620_edid_read(struct sii8620 *ctx, int ret) 552 { 553 if (ret < 0) 554 return; 555 556 sii8620_set_upstream_edid(ctx); 557 sii8620_hsic_init(ctx); 558 sii8620_enable_hpd(ctx); 559 } 560 561 static void sii8620_mr_devcap(struct sii8620 *ctx) 562 { 563 u8 dcap[MHL_DCAP_SIZE]; 564 struct device *dev = ctx->dev; 565 566 sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, dcap, MHL_DCAP_SIZE); 567 if (ctx->error < 0) 568 return; 569 570 dev_info(dev, "detected dongle MHL %d.%d, ChipID %02x%02x:%02x%02x\n", 571 dcap[MHL_DCAP_MHL_VERSION] / 16, 572 dcap[MHL_DCAP_MHL_VERSION] % 16, 573 dcap[MHL_DCAP_ADOPTER_ID_H], dcap[MHL_DCAP_ADOPTER_ID_L], 574 dcap[MHL_DCAP_DEVICE_ID_H], dcap[MHL_DCAP_DEVICE_ID_L]); 575 sii8620_update_array(ctx->devcap, dcap, MHL_DCAP_SIZE); 576 } 577 578 static void sii8620_mr_xdevcap(struct sii8620 *ctx) 579 { 580 sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, ctx->xdevcap, 581 MHL_XDC_SIZE); 582 } 583 584 static void sii8620_mt_read_devcap_recv(struct sii8620 *ctx, 585 struct sii8620_mt_msg *msg) 586 { 587 u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP 588 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 589 | BIT_EDID_CTRL_EDID_MODE_EN; 590 591 if (msg->reg[0] == MHL_READ_XDEVCAP) 592 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN; 593 594 sii8620_write_seq(ctx, 595 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE | BIT_INTR9_EDID_DONE 596 | BIT_INTR9_EDID_ERROR, 597 REG_EDID_CTRL, ctrl, 598 REG_EDID_FIFO_ADDR, 0 599 ); 600 601 if (msg->reg[0] == MHL_READ_XDEVCAP) 602 sii8620_mr_xdevcap(ctx); 603 else 604 sii8620_mr_devcap(ctx); 605 } 606 607 static void sii8620_mt_read_devcap(struct sii8620 *ctx, bool xdevcap) 608 { 609 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 610 611 if (!msg) 612 return; 613 614 msg->reg[0] = xdevcap ? MHL_READ_XDEVCAP : MHL_READ_DEVCAP; 615 msg->send = sii8620_mt_read_devcap_send; 616 msg->recv = sii8620_mt_read_devcap_recv; 617 } 618 619 static void sii8620_mt_read_devcap_reg_recv(struct sii8620 *ctx, 620 struct sii8620_mt_msg *msg) 621 { 622 u8 reg = msg->reg[1] & 0x7f; 623 624 if (msg->reg[1] & 0x80) 625 ctx->xdevcap[reg] = msg->ret; 626 else 627 ctx->devcap[reg] = msg->ret; 628 } 629 630 static void sii8620_mt_read_devcap_reg(struct sii8620 *ctx, u8 reg) 631 { 632 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 633 634 if (!msg) 635 return; 636 637 msg->reg[0] = (reg & 0x80) ? MHL_READ_XDEVCAP_REG : MHL_READ_DEVCAP_REG; 638 msg->reg[1] = reg; 639 msg->send = sii8620_mt_msc_cmd_send; 640 msg->recv = sii8620_mt_read_devcap_reg_recv; 641 } 642 643 static inline void sii8620_mt_read_xdevcap_reg(struct sii8620 *ctx, u8 reg) 644 { 645 sii8620_mt_read_devcap_reg(ctx, reg | 0x80); 646 } 647 648 static void *sii8620_burst_get_tx_buf(struct sii8620 *ctx, int len) 649 { 650 u8 *buf = &ctx->burst.tx_buf[ctx->burst.tx_count]; 651 int size = len + 2; 652 653 if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) { 654 dev_err(ctx->dev, "TX-BLK buffer exhausted\n"); 655 ctx->error = -EINVAL; 656 return NULL; 657 } 658 659 ctx->burst.tx_count += size; 660 buf[1] = len; 661 662 return buf + 2; 663 } 664 665 static u8 *sii8620_burst_get_rx_buf(struct sii8620 *ctx, int len) 666 { 667 u8 *buf = &ctx->burst.rx_buf[ctx->burst.rx_count]; 668 int size = len + 1; 669 670 if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) { 671 dev_err(ctx->dev, "RX-BLK buffer exhausted\n"); 672 ctx->error = -EINVAL; 673 return NULL; 674 } 675 676 ctx->burst.rx_count += size; 677 buf[0] = len; 678 679 return buf + 1; 680 } 681 682 static void sii8620_burst_send(struct sii8620 *ctx) 683 { 684 int tx_left = ctx->burst.tx_count; 685 u8 *d = ctx->burst.tx_buf; 686 687 while (tx_left > 0) { 688 int len = d[1] + 2; 689 690 if (ctx->burst.r_count + len > ctx->burst.r_size) 691 break; 692 d[0] = min(ctx->burst.rx_ack, 255); 693 ctx->burst.rx_ack -= d[0]; 694 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, d, len); 695 ctx->burst.r_count += len; 696 tx_left -= len; 697 d += len; 698 } 699 700 ctx->burst.tx_count = tx_left; 701 702 while (ctx->burst.rx_ack > 0) { 703 u8 b[2] = { min(ctx->burst.rx_ack, 255), 0 }; 704 705 if (ctx->burst.r_count + 2 > ctx->burst.r_size) 706 break; 707 ctx->burst.rx_ack -= b[0]; 708 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, b, 2); 709 ctx->burst.r_count += 2; 710 } 711 } 712 713 static void sii8620_burst_receive(struct sii8620 *ctx) 714 { 715 u8 buf[3], *d; 716 int count; 717 718 sii8620_read_buf(ctx, REG_EMSCRFIFOBCNTL, buf, 2); 719 count = get_unaligned_le16(buf); 720 while (count > 0) { 721 int len = min(count, 3); 722 723 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, buf, len); 724 count -= len; 725 ctx->burst.rx_ack += len - 1; 726 ctx->burst.r_count -= buf[1]; 727 if (ctx->burst.r_count < 0) 728 ctx->burst.r_count = 0; 729 730 if (len < 3 || !buf[2]) 731 continue; 732 733 len = buf[2]; 734 d = sii8620_burst_get_rx_buf(ctx, len); 735 if (!d) 736 continue; 737 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, d, len); 738 count -= len; 739 ctx->burst.rx_ack += len; 740 } 741 } 742 743 static void sii8620_burst_tx_rbuf_info(struct sii8620 *ctx, int size) 744 { 745 struct mhl_burst_blk_rcv_buffer_info *d = 746 sii8620_burst_get_tx_buf(ctx, sizeof(*d)); 747 if (!d) 748 return; 749 750 d->id = cpu_to_be16(MHL_BURST_ID_BLK_RCV_BUFFER_INFO); 751 d->size = cpu_to_le16(size); 752 } 753 754 static u8 sii8620_checksum(void *ptr, int size) 755 { 756 u8 *d = ptr, sum = 0; 757 758 while (size--) 759 sum += *d++; 760 761 return sum; 762 } 763 764 static void sii8620_mhl_burst_hdr_set(struct mhl3_burst_header *h, 765 enum mhl_burst_id id) 766 { 767 h->id = cpu_to_be16(id); 768 h->total_entries = 1; 769 h->sequence_index = 1; 770 } 771 772 static void sii8620_burst_tx_bits_per_pixel_fmt(struct sii8620 *ctx, u8 fmt) 773 { 774 struct mhl_burst_bits_per_pixel_fmt *d; 775 const int size = sizeof(*d) + sizeof(d->desc[0]); 776 777 d = sii8620_burst_get_tx_buf(ctx, size); 778 if (!d) 779 return; 780 781 sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_BITS_PER_PIXEL_FMT); 782 d->num_entries = 1; 783 d->desc[0].stream_id = 0; 784 d->desc[0].pixel_format = fmt; 785 d->hdr.checksum -= sii8620_checksum(d, size); 786 } 787 788 static void sii8620_burst_rx_all(struct sii8620 *ctx) 789 { 790 u8 *d = ctx->burst.rx_buf; 791 int count = ctx->burst.rx_count; 792 793 while (count-- > 0) { 794 int len = *d++; 795 int id = get_unaligned_be16(&d[0]); 796 797 switch (id) { 798 case MHL_BURST_ID_BLK_RCV_BUFFER_INFO: 799 ctx->burst.r_size = get_unaligned_le16(&d[2]); 800 break; 801 default: 802 break; 803 } 804 count -= len; 805 d += len; 806 } 807 ctx->burst.rx_count = 0; 808 } 809 810 static void sii8620_fetch_edid(struct sii8620 *ctx) 811 { 812 u8 lm_ddc, ddc_cmd, int3, cbus; 813 unsigned long timeout; 814 int fetched, i; 815 int edid_len = EDID_LENGTH; 816 u8 *edid; 817 818 sii8620_readb(ctx, REG_CBUS_STATUS); 819 lm_ddc = sii8620_readb(ctx, REG_LM_DDC); 820 ddc_cmd = sii8620_readb(ctx, REG_DDC_CMD); 821 822 sii8620_write_seq(ctx, 823 REG_INTR9_MASK, 0, 824 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO, 825 REG_HDCP2X_POLL_CS, 0x71, 826 REG_HDCP2X_CTRL_0, BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX, 827 REG_LM_DDC, lm_ddc | BIT_LM_DDC_SW_TPI_EN_DISABLED, 828 ); 829 830 for (i = 0; i < 256; ++i) { 831 u8 ddc_stat = sii8620_readb(ctx, REG_DDC_STATUS); 832 833 if (!(ddc_stat & BIT_DDC_STATUS_DDC_I2C_IN_PROG)) 834 break; 835 sii8620_write(ctx, REG_DDC_STATUS, 836 BIT_DDC_STATUS_DDC_FIFO_EMPTY); 837 } 838 839 sii8620_write(ctx, REG_DDC_ADDR, 0x50 << 1); 840 841 edid = kmalloc(EDID_LENGTH, GFP_KERNEL); 842 if (!edid) { 843 ctx->error = -ENOMEM; 844 return; 845 } 846 847 #define FETCH_SIZE 16 848 for (fetched = 0; fetched < edid_len; fetched += FETCH_SIZE) { 849 sii8620_readb(ctx, REG_DDC_STATUS); 850 sii8620_write_seq(ctx, 851 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_ABORT, 852 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_CLEAR_FIFO, 853 REG_DDC_STATUS, BIT_DDC_STATUS_DDC_FIFO_EMPTY 854 ); 855 sii8620_write_seq(ctx, 856 REG_DDC_SEGM, fetched >> 8, 857 REG_DDC_OFFSET, fetched & 0xff, 858 REG_DDC_DIN_CNT1, FETCH_SIZE, 859 REG_DDC_DIN_CNT2, 0, 860 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_ENH_DDC_READ_NO_ACK 861 ); 862 863 int3 = 0; 864 timeout = jiffies + msecs_to_jiffies(200); 865 for (;;) { 866 cbus = sii8620_readb(ctx, REG_CBUS_STATUS); 867 if (~cbus & BIT_CBUS_STATUS_CBUS_CONNECTED) { 868 kfree(edid); 869 edid = NULL; 870 goto end; 871 } 872 if (int3 & BIT_DDC_CMD_DONE) { 873 if (sii8620_readb(ctx, REG_DDC_DOUT_CNT) 874 >= FETCH_SIZE) 875 break; 876 } else { 877 int3 = sii8620_readb(ctx, REG_INTR3); 878 } 879 if (time_is_before_jiffies(timeout)) { 880 ctx->error = -ETIMEDOUT; 881 dev_err(ctx->dev, "timeout during EDID read\n"); 882 kfree(edid); 883 edid = NULL; 884 goto end; 885 } 886 usleep_range(10, 20); 887 } 888 889 sii8620_read_buf(ctx, REG_DDC_DATA, edid + fetched, FETCH_SIZE); 890 if (fetched + FETCH_SIZE == EDID_LENGTH) { 891 u8 ext = ((struct edid *)edid)->extensions; 892 893 if (ext) { 894 u8 *new_edid; 895 896 edid_len += ext * EDID_LENGTH; 897 new_edid = krealloc(edid, edid_len, GFP_KERNEL); 898 if (!new_edid) { 899 kfree(edid); 900 ctx->error = -ENOMEM; 901 return; 902 } 903 edid = new_edid; 904 } 905 } 906 } 907 908 sii8620_write_seq(ctx, 909 REG_INTR3_MASK, BIT_DDC_CMD_DONE, 910 REG_LM_DDC, lm_ddc 911 ); 912 913 end: 914 kfree(ctx->edid); 915 ctx->edid = (struct edid *)edid; 916 } 917 918 static void sii8620_set_upstream_edid(struct sii8620 *ctx) 919 { 920 sii8620_setbits(ctx, REG_DPD, BIT_DPD_PDNRX12 | BIT_DPD_PDIDCK_N 921 | BIT_DPD_PD_MHL_CLK_N, 0xff); 922 923 sii8620_write_seq_static(ctx, 924 REG_RX_HDMI_CTRL3, 0x00, 925 REG_PKT_FILTER_0, 0xFF, 926 REG_PKT_FILTER_1, 0xFF, 927 REG_ALICE0_BW_I2C, 0x06 928 ); 929 930 sii8620_setbits(ctx, REG_RX_HDMI_CLR_BUFFER, 931 BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN, 0xff); 932 933 sii8620_write_seq_static(ctx, 934 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 935 | BIT_EDID_CTRL_EDID_MODE_EN, 936 REG_EDID_FIFO_ADDR, 0, 937 ); 938 939 sii8620_write_buf(ctx, REG_EDID_FIFO_WR_DATA, (u8 *)ctx->edid, 940 (ctx->edid->extensions + 1) * EDID_LENGTH); 941 942 sii8620_write_seq_static(ctx, 943 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID 944 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 945 | BIT_EDID_CTRL_EDID_MODE_EN, 946 REG_INTR5_MASK, BIT_INTR_SCDT_CHANGE, 947 REG_INTR9_MASK, 0 948 ); 949 } 950 951 static void sii8620_xtal_set_rate(struct sii8620 *ctx) 952 { 953 static const struct { 954 unsigned int rate; 955 u8 div; 956 u8 tp1; 957 } rates[] = { 958 { 19200, 0x04, 0x53 }, 959 { 20000, 0x04, 0x62 }, 960 { 24000, 0x05, 0x75 }, 961 { 30000, 0x06, 0x92 }, 962 { 38400, 0x0c, 0xbc }, 963 }; 964 unsigned long rate = clk_get_rate(ctx->clk_xtal) / 1000; 965 int i; 966 967 for (i = 0; i < ARRAY_SIZE(rates) - 1; ++i) 968 if (rate <= rates[i].rate) 969 break; 970 971 if (rate != rates[i].rate) 972 dev_err(ctx->dev, "xtal clock rate(%lukHz) not supported, setting MHL for %ukHz.\n", 973 rate, rates[i].rate); 974 975 sii8620_write(ctx, REG_DIV_CTL_MAIN, rates[i].div); 976 sii8620_write(ctx, REG_HDCP2X_TP1, rates[i].tp1); 977 } 978 979 static int sii8620_hw_on(struct sii8620 *ctx) 980 { 981 int ret; 982 983 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 984 if (ret) 985 return ret; 986 987 usleep_range(10000, 20000); 988 ret = clk_prepare_enable(ctx->clk_xtal); 989 if (ret) 990 return ret; 991 992 msleep(100); 993 gpiod_set_value(ctx->gpio_reset, 0); 994 msleep(100); 995 996 return 0; 997 } 998 999 static int sii8620_hw_off(struct sii8620 *ctx) 1000 { 1001 clk_disable_unprepare(ctx->clk_xtal); 1002 gpiod_set_value(ctx->gpio_reset, 1); 1003 return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 1004 } 1005 1006 static void sii8620_cbus_reset(struct sii8620 *ctx) 1007 { 1008 sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST 1009 | BIT_PWD_SRST_CBUS_RST_SW_EN); 1010 usleep_range(10000, 20000); 1011 sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN); 1012 } 1013 1014 static void sii8620_set_auto_zone(struct sii8620 *ctx) 1015 { 1016 if (ctx->mode != CM_MHL1) { 1017 sii8620_write_seq_static(ctx, 1018 REG_TX_ZONE_CTL1, 0x0, 1019 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 1020 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 1021 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE 1022 ); 1023 } else { 1024 sii8620_write_seq_static(ctx, 1025 REG_TX_ZONE_CTL1, VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE, 1026 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 1027 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE 1028 ); 1029 } 1030 } 1031 1032 static void sii8620_stop_video(struct sii8620 *ctx) 1033 { 1034 u8 uninitialized_var(val); 1035 1036 sii8620_write_seq_static(ctx, 1037 REG_TPI_INTR_EN, 0, 1038 REG_HDCP2X_INTR0_MASK, 0, 1039 REG_TPI_COPP_DATA2, 0, 1040 REG_TPI_INTR_ST0, ~0, 1041 ); 1042 1043 switch (ctx->sink_type) { 1044 case SINK_DVI: 1045 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN 1046 | BIT_TPI_SC_TPI_AV_MUTE; 1047 break; 1048 case SINK_HDMI: 1049 default: 1050 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN 1051 | BIT_TPI_SC_TPI_AV_MUTE 1052 | BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI; 1053 break; 1054 } 1055 1056 sii8620_write(ctx, REG_TPI_SC, val); 1057 } 1058 1059 static void sii8620_set_format(struct sii8620 *ctx) 1060 { 1061 u8 out_fmt; 1062 1063 if (sii8620_is_mhl3(ctx)) { 1064 sii8620_setbits(ctx, REG_M3_P0CTRL, 1065 BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED, 1066 ctx->use_packed_pixel ? ~0 : 0); 1067 } else { 1068 if (ctx->use_packed_pixel) 1069 sii8620_write_seq_static(ctx, 1070 REG_VID_MODE, BIT_VID_MODE_M1080P, 1071 REG_MHL_TOP_CTL, BIT_MHL_TOP_CTL_MHL_PP_SEL | 1, 1072 REG_MHLTX_CTL6, 0x60 1073 ); 1074 else 1075 sii8620_write_seq_static(ctx, 1076 REG_VID_MODE, 0, 1077 REG_MHL_TOP_CTL, 1, 1078 REG_MHLTX_CTL6, 0xa0 1079 ); 1080 } 1081 1082 if (ctx->use_packed_pixel) 1083 out_fmt = VAL_TPI_FORMAT(YCBCR422, FULL) | 1084 BIT_TPI_OUTPUT_CSCMODE709; 1085 else 1086 out_fmt = VAL_TPI_FORMAT(RGB, FULL); 1087 1088 sii8620_write_seq(ctx, 1089 REG_TPI_INPUT, VAL_TPI_FORMAT(RGB, FULL), 1090 REG_TPI_OUTPUT, out_fmt, 1091 ); 1092 } 1093 1094 static int mhl3_infoframe_init(struct mhl3_infoframe *frame) 1095 { 1096 memset(frame, 0, sizeof(*frame)); 1097 1098 frame->version = 3; 1099 frame->hev_format = -1; 1100 return 0; 1101 } 1102 1103 static ssize_t mhl3_infoframe_pack(struct mhl3_infoframe *frame, 1104 void *buffer, size_t size) 1105 { 1106 const int frm_len = HDMI_INFOFRAME_HEADER_SIZE + MHL3_INFOFRAME_SIZE; 1107 u8 *ptr = buffer; 1108 1109 if (size < frm_len) 1110 return -ENOSPC; 1111 1112 memset(buffer, 0, size); 1113 ptr[0] = HDMI_INFOFRAME_TYPE_VENDOR; 1114 ptr[1] = frame->version; 1115 ptr[2] = MHL3_INFOFRAME_SIZE; 1116 ptr[4] = MHL3_IEEE_OUI & 0xff; 1117 ptr[5] = (MHL3_IEEE_OUI >> 8) & 0xff; 1118 ptr[6] = (MHL3_IEEE_OUI >> 16) & 0xff; 1119 ptr[7] = frame->video_format & 0x3; 1120 ptr[7] |= (frame->format_type & 0x7) << 2; 1121 ptr[7] |= frame->sep_audio ? BIT(5) : 0; 1122 if (frame->hev_format >= 0) { 1123 ptr[9] = 1; 1124 ptr[10] = (frame->hev_format >> 8) & 0xff; 1125 ptr[11] = frame->hev_format & 0xff; 1126 } 1127 if (frame->av_delay) { 1128 bool sign = frame->av_delay < 0; 1129 int delay = sign ? -frame->av_delay : frame->av_delay; 1130 1131 ptr[12] = (delay >> 16) & 0xf; 1132 if (sign) 1133 ptr[12] |= BIT(4); 1134 ptr[13] = (delay >> 8) & 0xff; 1135 ptr[14] = delay & 0xff; 1136 } 1137 ptr[3] -= sii8620_checksum(buffer, frm_len); 1138 return frm_len; 1139 } 1140 1141 static void sii8620_set_infoframes(struct sii8620 *ctx) 1142 { 1143 struct mhl3_infoframe mhl_frm; 1144 union hdmi_infoframe frm; 1145 u8 buf[31]; 1146 int ret; 1147 1148 if (!sii8620_is_mhl3(ctx) || !ctx->use_packed_pixel) { 1149 sii8620_write(ctx, REG_TPI_SC, 1150 BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI); 1151 sii8620_write_buf(ctx, REG_TPI_AVI_CHSUM, ctx->avif + 3, 1152 ARRAY_SIZE(ctx->avif) - 3); 1153 sii8620_write(ctx, REG_PKT_FILTER_0, 1154 BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT | 1155 BIT_PKT_FILTER_0_DROP_MPEG_PKT | 1156 BIT_PKT_FILTER_0_DROP_GCP_PKT, 1157 BIT_PKT_FILTER_1_DROP_GEN_PKT); 1158 return; 1159 } 1160 1161 ret = hdmi_avi_infoframe_init(&frm.avi); 1162 frm.avi.colorspace = HDMI_COLORSPACE_YUV422; 1163 frm.avi.active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 1164 frm.avi.picture_aspect = HDMI_PICTURE_ASPECT_16_9; 1165 frm.avi.colorimetry = HDMI_COLORIMETRY_ITU_709; 1166 frm.avi.video_code = ctx->video_code; 1167 if (!ret) 1168 ret = hdmi_avi_infoframe_pack(&frm.avi, buf, ARRAY_SIZE(buf)); 1169 if (ret > 0) 1170 sii8620_write_buf(ctx, REG_TPI_AVI_CHSUM, buf + 3, ret - 3); 1171 sii8620_write(ctx, REG_PKT_FILTER_0, 1172 BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT | 1173 BIT_PKT_FILTER_0_DROP_MPEG_PKT | 1174 BIT_PKT_FILTER_0_DROP_AVI_PKT | 1175 BIT_PKT_FILTER_0_DROP_GCP_PKT, 1176 BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS | 1177 BIT_PKT_FILTER_1_DROP_GEN_PKT | 1178 BIT_PKT_FILTER_1_DROP_VSIF_PKT); 1179 1180 sii8620_write(ctx, REG_TPI_INFO_FSEL, BIT_TPI_INFO_FSEL_EN 1181 | BIT_TPI_INFO_FSEL_RPT | VAL_TPI_INFO_FSEL_VSI); 1182 ret = mhl3_infoframe_init(&mhl_frm); 1183 if (!ret) 1184 ret = mhl3_infoframe_pack(&mhl_frm, buf, ARRAY_SIZE(buf)); 1185 sii8620_write_buf(ctx, REG_TPI_INFO_B0, buf, ret); 1186 } 1187 1188 static void sii8620_start_video(struct sii8620 *ctx) 1189 { 1190 if (!sii8620_is_mhl3(ctx)) 1191 sii8620_stop_video(ctx); 1192 1193 if (ctx->sink_type == SINK_DVI && !sii8620_is_mhl3(ctx)) { 1194 sii8620_write(ctx, REG_RX_HDMI_CTRL2, 1195 VAL_RX_HDMI_CTRL2_DEFVAL); 1196 sii8620_write(ctx, REG_TPI_SC, 0); 1197 return; 1198 } 1199 1200 sii8620_write_seq_static(ctx, 1201 REG_RX_HDMI_CTRL2, VAL_RX_HDMI_CTRL2_DEFVAL 1202 | BIT_RX_HDMI_CTRL2_USE_AV_MUTE, 1203 REG_VID_OVRRD, BIT_VID_OVRRD_PP_AUTO_DISABLE 1204 | BIT_VID_OVRRD_M1080P_OVRRD); 1205 sii8620_set_format(ctx); 1206 1207 if (!sii8620_is_mhl3(ctx)) { 1208 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE), 1209 MHL_DST_LM_CLK_MODE_NORMAL | MHL_DST_LM_PATH_ENABLED); 1210 sii8620_set_auto_zone(ctx); 1211 } else { 1212 static const struct { 1213 int max_clk; 1214 u8 zone; 1215 u8 link_rate; 1216 u8 rrp_decode; 1217 } clk_spec[] = { 1218 { 150000, VAL_TX_ZONE_CTL3_TX_ZONE_1_5GBPS, 1219 MHL_XDS_LINK_RATE_1_5_GBPS, 0x38 }, 1220 { 300000, VAL_TX_ZONE_CTL3_TX_ZONE_3GBPS, 1221 MHL_XDS_LINK_RATE_3_0_GBPS, 0x40 }, 1222 { 600000, VAL_TX_ZONE_CTL3_TX_ZONE_6GBPS, 1223 MHL_XDS_LINK_RATE_6_0_GBPS, 0x40 }, 1224 }; 1225 u8 p0_ctrl = BIT_M3_P0CTRL_MHL3_P0_PORT_EN; 1226 int clk = ctx->pixel_clock * (ctx->use_packed_pixel ? 2 : 3); 1227 int i; 1228 1229 for (i = 0; i < ARRAY_SIZE(clk_spec) - 1; ++i) 1230 if (clk < clk_spec[i].max_clk) 1231 break; 1232 1233 if (100 * clk >= 98 * clk_spec[i].max_clk) 1234 p0_ctrl |= BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN; 1235 1236 sii8620_burst_tx_bits_per_pixel_fmt(ctx, ctx->use_packed_pixel); 1237 sii8620_burst_send(ctx); 1238 sii8620_write_seq(ctx, 1239 REG_MHL_DP_CTL0, 0xf0, 1240 REG_MHL3_TX_ZONE_CTL, clk_spec[i].zone); 1241 sii8620_setbits(ctx, REG_M3_P0CTRL, 1242 BIT_M3_P0CTRL_MHL3_P0_PORT_EN 1243 | BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN, p0_ctrl); 1244 sii8620_setbits(ctx, REG_M3_POSTM, MSK_M3_POSTM_RRP_DECODE, 1245 clk_spec[i].rrp_decode); 1246 sii8620_write_seq_static(ctx, 1247 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE 1248 | BIT_M3_CTRL_H2M_SWRST, 1249 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE 1250 ); 1251 sii8620_mt_write_stat(ctx, MHL_XDS_REG(AVLINK_MODE_CONTROL), 1252 clk_spec[i].link_rate); 1253 } 1254 1255 sii8620_set_infoframes(ctx); 1256 } 1257 1258 static void sii8620_disable_hpd(struct sii8620 *ctx) 1259 { 1260 sii8620_setbits(ctx, REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID, 0); 1261 sii8620_write_seq_static(ctx, 1262 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN, 1263 REG_INTR8_MASK, 0 1264 ); 1265 } 1266 1267 static void sii8620_enable_hpd(struct sii8620 *ctx) 1268 { 1269 sii8620_setbits(ctx, REG_TMDS_CSTAT_P3, 1270 BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS 1271 | BIT_TMDS_CSTAT_P3_CLR_AVI, ~0); 1272 sii8620_write_seq_static(ctx, 1273 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN 1274 | BIT_HPD_CTRL_HPD_HIGH, 1275 ); 1276 } 1277 1278 static void sii8620_mhl_discover(struct sii8620 *ctx) 1279 { 1280 sii8620_write_seq_static(ctx, 1281 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1282 | BIT_DISC_CTRL9_DISC_PULSE_PROCEED, 1283 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_5K, VAL_PUP_20K), 1284 REG_CBUS_DISC_INTR0_MASK, BIT_MHL3_EST_INT 1285 | BIT_MHL_EST_INT 1286 | BIT_NOT_MHL_EST_INT 1287 | BIT_CBUS_MHL3_DISCON_INT 1288 | BIT_CBUS_MHL12_DISCON_INT 1289 | BIT_RGND_READY_INT, 1290 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 1291 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 1292 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE, 1293 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE 1294 | BIT_MHL_DP_CTL0_TX_OE_OVR, 1295 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE, 1296 REG_MHL_DP_CTL1, 0xA2, 1297 REG_MHL_DP_CTL2, 0x03, 1298 REG_MHL_DP_CTL3, 0x35, 1299 REG_MHL_DP_CTL5, 0x02, 1300 REG_MHL_DP_CTL6, 0x02, 1301 REG_MHL_DP_CTL7, 0x03, 1302 REG_COC_CTLC, 0xFF, 1303 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 1304 | BIT_DPD_OSC_EN | BIT_DPD_PWRON_HSIC, 1305 REG_COC_INTR_MASK, BIT_COC_PLL_LOCK_STATUS_CHANGE 1306 | BIT_COC_CALIBRATION_DONE, 1307 REG_CBUS_INT_1_MASK, BIT_CBUS_MSC_ABORT_RCVD 1308 | BIT_CBUS_CMD_ABORT, 1309 REG_CBUS_INT_0_MASK, BIT_CBUS_MSC_MT_DONE 1310 | BIT_CBUS_HPD_CHG 1311 | BIT_CBUS_MSC_MR_WRITE_STAT 1312 | BIT_CBUS_MSC_MR_MSC_MSG 1313 | BIT_CBUS_MSC_MR_WRITE_BURST 1314 | BIT_CBUS_MSC_MR_SET_INT 1315 | BIT_CBUS_MSC_MT_DONE_NACK 1316 ); 1317 } 1318 1319 static void sii8620_peer_specific_init(struct sii8620 *ctx) 1320 { 1321 if (sii8620_is_mhl3(ctx)) 1322 sii8620_write_seq_static(ctx, 1323 REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD, 1324 REG_EMSCINTRMASK1, 1325 BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR 1326 ); 1327 else 1328 sii8620_write_seq_static(ctx, 1329 REG_HDCP2X_INTR0_MASK, 0x00, 1330 REG_EMSCINTRMASK1, 0x00, 1331 REG_HDCP2X_INTR0, 0xFF, 1332 REG_INTR1, 0xFF, 1333 REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD 1334 | BIT_SYS_CTRL1_TX_CTRL_HDMI 1335 ); 1336 } 1337 1338 #define SII8620_MHL_VERSION 0x32 1339 #define SII8620_SCRATCHPAD_SIZE 16 1340 #define SII8620_INT_STAT_SIZE 0x33 1341 1342 static void sii8620_set_dev_cap(struct sii8620 *ctx) 1343 { 1344 static const u8 devcap[MHL_DCAP_SIZE] = { 1345 [MHL_DCAP_MHL_VERSION] = SII8620_MHL_VERSION, 1346 [MHL_DCAP_CAT] = MHL_DCAP_CAT_SOURCE | MHL_DCAP_CAT_POWER, 1347 [MHL_DCAP_ADOPTER_ID_H] = 0x01, 1348 [MHL_DCAP_ADOPTER_ID_L] = 0x41, 1349 [MHL_DCAP_VID_LINK_MODE] = MHL_DCAP_VID_LINK_RGB444 1350 | MHL_DCAP_VID_LINK_PPIXEL 1351 | MHL_DCAP_VID_LINK_16BPP, 1352 [MHL_DCAP_AUD_LINK_MODE] = MHL_DCAP_AUD_LINK_2CH, 1353 [MHL_DCAP_VIDEO_TYPE] = MHL_DCAP_VT_GRAPHICS, 1354 [MHL_DCAP_LOG_DEV_MAP] = MHL_DCAP_LD_GUI, 1355 [MHL_DCAP_BANDWIDTH] = 0x0f, 1356 [MHL_DCAP_FEATURE_FLAG] = MHL_DCAP_FEATURE_RCP_SUPPORT 1357 | MHL_DCAP_FEATURE_RAP_SUPPORT 1358 | MHL_DCAP_FEATURE_SP_SUPPORT, 1359 [MHL_DCAP_SCRATCHPAD_SIZE] = SII8620_SCRATCHPAD_SIZE, 1360 [MHL_DCAP_INT_STAT_SIZE] = SII8620_INT_STAT_SIZE, 1361 }; 1362 static const u8 xdcap[MHL_XDC_SIZE] = { 1363 [MHL_XDC_ECBUS_SPEEDS] = MHL_XDC_ECBUS_S_075 1364 | MHL_XDC_ECBUS_S_8BIT, 1365 [MHL_XDC_TMDS_SPEEDS] = MHL_XDC_TMDS_150 1366 | MHL_XDC_TMDS_300 | MHL_XDC_TMDS_600, 1367 [MHL_XDC_ECBUS_ROLES] = MHL_XDC_DEV_HOST, 1368 [MHL_XDC_LOG_DEV_MAPX] = MHL_XDC_LD_PHONE, 1369 }; 1370 1371 sii8620_write_buf(ctx, REG_MHL_DEVCAP_0, devcap, ARRAY_SIZE(devcap)); 1372 sii8620_write_buf(ctx, REG_MHL_EXTDEVCAP_0, xdcap, ARRAY_SIZE(xdcap)); 1373 } 1374 1375 static void sii8620_mhl_init(struct sii8620 *ctx) 1376 { 1377 sii8620_write_seq_static(ctx, 1378 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1379 REG_CBUS_MSC_COMPAT_CTRL, 1380 BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN, 1381 ); 1382 1383 sii8620_peer_specific_init(ctx); 1384 1385 sii8620_disable_hpd(ctx); 1386 1387 sii8620_write_seq_static(ctx, 1388 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO, 1389 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1390 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1391 REG_TMDS0_CCTRL1, 0x90, 1392 REG_TMDS_CLK_EN, 0x01, 1393 REG_TMDS_CH_EN, 0x11, 1394 REG_BGR_BIAS, 0x87, 1395 REG_ALICE0_ZONE_CTRL, 0xE8, 1396 REG_ALICE0_MODE_CTRL, 0x04, 1397 ); 1398 sii8620_setbits(ctx, REG_LM_DDC, BIT_LM_DDC_SW_TPI_EN_DISABLED, 0); 1399 sii8620_write_seq_static(ctx, 1400 REG_TPI_HW_OPT3, 0x76, 1401 REG_TMDS_CCTRL, BIT_TMDS_CCTRL_TMDS_OE, 1402 REG_TPI_DTD_B2, 79, 1403 ); 1404 sii8620_set_dev_cap(ctx); 1405 sii8620_write_seq_static(ctx, 1406 REG_MDT_XMIT_TIMEOUT, 100, 1407 REG_MDT_XMIT_CTRL, 0x03, 1408 REG_MDT_XFIFO_STAT, 0x00, 1409 REG_MDT_RCV_TIMEOUT, 100, 1410 REG_CBUS_LINK_CTRL_8, 0x1D, 1411 ); 1412 1413 sii8620_start_gen2_write_burst(ctx); 1414 sii8620_write_seq_static(ctx, 1415 REG_BIST_CTRL, 0x00, 1416 REG_COC_CTL1, 0x10, 1417 REG_COC_CTL2, 0x18, 1418 REG_COC_CTLF, 0x07, 1419 REG_COC_CTL11, 0xF8, 1420 REG_COC_CTL17, 0x61, 1421 REG_COC_CTL18, 0x46, 1422 REG_COC_CTL19, 0x15, 1423 REG_COC_CTL1A, 0x01, 1424 REG_MHL_COC_CTL3, BIT_MHL_COC_CTL3_COC_AECHO_EN, 1425 REG_MHL_COC_CTL4, 0x2D, 1426 REG_MHL_COC_CTL5, 0xF9, 1427 REG_MSC_HEARTBEAT_CTRL, 0x27, 1428 ); 1429 sii8620_disable_gen2_write_burst(ctx); 1430 1431 sii8620_mt_write_stat(ctx, MHL_DST_REG(VERSION), SII8620_MHL_VERSION); 1432 sii8620_mt_write_stat(ctx, MHL_DST_REG(CONNECTED_RDY), 1433 MHL_DST_CONN_DCAP_RDY | MHL_DST_CONN_XDEVCAPP_SUPP 1434 | MHL_DST_CONN_POW_STAT); 1435 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), MHL_INT_RC_DCAP_CHG); 1436 } 1437 1438 static void sii8620_emsc_enable(struct sii8620 *ctx) 1439 { 1440 u8 reg; 1441 1442 sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_EMSC_EN 1443 | BIT_GENCTL_CLR_EMSC_RFIFO 1444 | BIT_GENCTL_CLR_EMSC_XFIFO, ~0); 1445 sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_CLR_EMSC_RFIFO 1446 | BIT_GENCTL_CLR_EMSC_XFIFO, 0); 1447 sii8620_setbits(ctx, REG_COMMECNT, BIT_COMMECNT_I2C_TO_EMSC_EN, ~0); 1448 reg = sii8620_readb(ctx, REG_EMSCINTR); 1449 sii8620_write(ctx, REG_EMSCINTR, reg); 1450 sii8620_write(ctx, REG_EMSCINTRMASK, BIT_EMSCINTR_SPI_DVLD); 1451 } 1452 1453 static int sii8620_wait_for_fsm_state(struct sii8620 *ctx, u8 state) 1454 { 1455 int i; 1456 1457 for (i = 0; i < 10; ++i) { 1458 u8 s = sii8620_readb(ctx, REG_COC_STAT_0); 1459 1460 if ((s & MSK_COC_STAT_0_FSM_STATE) == state) 1461 return 0; 1462 if (!(s & BIT_COC_STAT_0_PLL_LOCKED)) 1463 return -EBUSY; 1464 usleep_range(4000, 6000); 1465 } 1466 return -ETIMEDOUT; 1467 } 1468 1469 static void sii8620_set_mode(struct sii8620 *ctx, enum sii8620_mode mode) 1470 { 1471 int ret; 1472 1473 if (ctx->mode == mode) 1474 return; 1475 1476 switch (mode) { 1477 case CM_MHL1: 1478 sii8620_write_seq_static(ctx, 1479 REG_CBUS_MSC_COMPAT_CTRL, 0x02, 1480 REG_M3_CTRL, VAL_M3_CTRL_MHL1_2_VALUE, 1481 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 1482 | BIT_DPD_OSC_EN, 1483 REG_COC_INTR_MASK, 0 1484 ); 1485 ctx->mode = mode; 1486 break; 1487 case CM_MHL3: 1488 sii8620_write(ctx, REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE); 1489 ctx->mode = mode; 1490 return; 1491 case CM_ECBUS_S: 1492 sii8620_emsc_enable(ctx); 1493 sii8620_write_seq_static(ctx, 1494 REG_TTXSPINUMS, 4, 1495 REG_TRXSPINUMS, 4, 1496 REG_TTXHSICNUMS, 0x14, 1497 REG_TRXHSICNUMS, 0x14, 1498 REG_TTXTOTNUMS, 0x18, 1499 REG_TRXTOTNUMS, 0x18, 1500 REG_PWD_SRST, BIT_PWD_SRST_COC_DOC_RST 1501 | BIT_PWD_SRST_CBUS_RST_SW_EN, 1502 REG_MHL_COC_CTL1, 0xbd, 1503 REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN, 1504 REG_COC_CTLB, 0x01, 1505 REG_COC_CTL0, 0x5c, 1506 REG_COC_CTL14, 0x03, 1507 REG_COC_CTL15, 0x80, 1508 REG_MHL_DP_CTL6, BIT_MHL_DP_CTL6_DP_TAP1_SGN 1509 | BIT_MHL_DP_CTL6_DP_TAP1_EN 1510 | BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN, 1511 REG_MHL_DP_CTL8, 0x03 1512 ); 1513 ret = sii8620_wait_for_fsm_state(ctx, 0x03); 1514 sii8620_write_seq_static(ctx, 1515 REG_COC_CTL14, 0x00, 1516 REG_COC_CTL15, 0x80 1517 ); 1518 if (!ret) 1519 sii8620_write(ctx, REG_CBUS3_CNVT, 0x85); 1520 else 1521 sii8620_disconnect(ctx); 1522 return; 1523 case CM_DISCONNECTED: 1524 ctx->mode = mode; 1525 break; 1526 default: 1527 dev_err(ctx->dev, "%s mode %d not supported\n", __func__, mode); 1528 break; 1529 } 1530 1531 sii8620_set_auto_zone(ctx); 1532 1533 if (mode != CM_MHL1) 1534 return; 1535 1536 sii8620_write_seq_static(ctx, 1537 REG_MHL_DP_CTL0, 0xBC, 1538 REG_MHL_DP_CTL1, 0xBB, 1539 REG_MHL_DP_CTL3, 0x48, 1540 REG_MHL_DP_CTL5, 0x39, 1541 REG_MHL_DP_CTL2, 0x2A, 1542 REG_MHL_DP_CTL6, 0x2A, 1543 REG_MHL_DP_CTL7, 0x08 1544 ); 1545 } 1546 1547 static void sii8620_disconnect(struct sii8620 *ctx) 1548 { 1549 sii8620_disable_gen2_write_burst(ctx); 1550 sii8620_stop_video(ctx); 1551 msleep(100); 1552 sii8620_cbus_reset(ctx); 1553 sii8620_set_mode(ctx, CM_DISCONNECTED); 1554 sii8620_write_seq_static(ctx, 1555 REG_TX_ZONE_CTL1, 0, 1556 REG_MHL_PLL_CTL0, 0x07, 1557 REG_COC_CTL0, 0x40, 1558 REG_CBUS3_CNVT, 0x84, 1559 REG_COC_CTL14, 0x00, 1560 REG_COC_CTL0, 0x40, 1561 REG_HRXCTRL3, 0x07, 1562 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 1563 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 1564 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE, 1565 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE 1566 | BIT_MHL_DP_CTL0_TX_OE_OVR, 1567 REG_MHL_DP_CTL1, 0xBB, 1568 REG_MHL_DP_CTL3, 0x48, 1569 REG_MHL_DP_CTL5, 0x3F, 1570 REG_MHL_DP_CTL2, 0x2F, 1571 REG_MHL_DP_CTL6, 0x2A, 1572 REG_MHL_DP_CTL7, 0x03 1573 ); 1574 sii8620_disable_hpd(ctx); 1575 sii8620_write_seq_static(ctx, 1576 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE, 1577 REG_MHL_COC_CTL1, 0x07, 1578 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1579 REG_DISC_CTRL8, 0x00, 1580 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1581 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1582 REG_INT_CTRL, 0x00, 1583 REG_MSC_HEARTBEAT_CTRL, 0x27, 1584 REG_DISC_CTRL1, 0x25, 1585 REG_CBUS_DISC_INTR0, (u8)~BIT_RGND_READY_INT, 1586 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT, 1587 REG_MDT_INT_1, 0xff, 1588 REG_MDT_INT_1_MASK, 0x00, 1589 REG_MDT_INT_0, 0xff, 1590 REG_MDT_INT_0_MASK, 0x00, 1591 REG_COC_INTR, 0xff, 1592 REG_COC_INTR_MASK, 0x00, 1593 REG_TRXINTH, 0xff, 1594 REG_TRXINTMH, 0x00, 1595 REG_CBUS_INT_0, 0xff, 1596 REG_CBUS_INT_0_MASK, 0x00, 1597 REG_CBUS_INT_1, 0xff, 1598 REG_CBUS_INT_1_MASK, 0x00, 1599 REG_EMSCINTR, 0xff, 1600 REG_EMSCINTRMASK, 0x00, 1601 REG_EMSCINTR1, 0xff, 1602 REG_EMSCINTRMASK1, 0x00, 1603 REG_INTR8, 0xff, 1604 REG_INTR8_MASK, 0x00, 1605 REG_TPI_INTR_ST0, 0xff, 1606 REG_TPI_INTR_EN, 0x00, 1607 REG_HDCP2X_INTR0, 0xff, 1608 REG_HDCP2X_INTR0_MASK, 0x00, 1609 REG_INTR9, 0xff, 1610 REG_INTR9_MASK, 0x00, 1611 REG_INTR3, 0xff, 1612 REG_INTR3_MASK, 0x00, 1613 REG_INTR5, 0xff, 1614 REG_INTR5_MASK, 0x00, 1615 REG_INTR2, 0xff, 1616 REG_INTR2_MASK, 0x00, 1617 ); 1618 memset(ctx->stat, 0, sizeof(ctx->stat)); 1619 memset(ctx->xstat, 0, sizeof(ctx->xstat)); 1620 memset(ctx->devcap, 0, sizeof(ctx->devcap)); 1621 memset(ctx->xdevcap, 0, sizeof(ctx->xdevcap)); 1622 ctx->cbus_status = 0; 1623 ctx->sink_type = SINK_NONE; 1624 kfree(ctx->edid); 1625 ctx->edid = NULL; 1626 sii8620_mt_cleanup(ctx); 1627 } 1628 1629 static void sii8620_mhl_disconnected(struct sii8620 *ctx) 1630 { 1631 sii8620_write_seq_static(ctx, 1632 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1633 REG_CBUS_MSC_COMPAT_CTRL, 1634 BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN 1635 ); 1636 sii8620_disconnect(ctx); 1637 } 1638 1639 static void sii8620_irq_disc(struct sii8620 *ctx) 1640 { 1641 u8 stat = sii8620_readb(ctx, REG_CBUS_DISC_INTR0); 1642 1643 if (stat & VAL_CBUS_MHL_DISCON) 1644 sii8620_mhl_disconnected(ctx); 1645 1646 if (stat & BIT_RGND_READY_INT) { 1647 u8 stat2 = sii8620_readb(ctx, REG_DISC_STAT2); 1648 1649 if ((stat2 & MSK_DISC_STAT2_RGND) == VAL_RGND_1K) { 1650 sii8620_mhl_discover(ctx); 1651 } else { 1652 sii8620_write_seq_static(ctx, 1653 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1654 | BIT_DISC_CTRL9_NOMHL_EST 1655 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1656 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT 1657 | BIT_CBUS_MHL3_DISCON_INT 1658 | BIT_CBUS_MHL12_DISCON_INT 1659 | BIT_NOT_MHL_EST_INT 1660 ); 1661 } 1662 } 1663 if (stat & BIT_MHL_EST_INT) 1664 sii8620_mhl_init(ctx); 1665 1666 sii8620_write(ctx, REG_CBUS_DISC_INTR0, stat); 1667 } 1668 1669 static void sii8620_read_burst(struct sii8620 *ctx) 1670 { 1671 u8 buf[17]; 1672 1673 sii8620_read_buf(ctx, REG_MDT_RCV_READ_PORT, buf, ARRAY_SIZE(buf)); 1674 sii8620_write(ctx, REG_MDT_RCV_CTRL, BIT_MDT_RCV_CTRL_MDT_RCV_EN | 1675 BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN | 1676 BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR); 1677 sii8620_readb(ctx, REG_MDT_RFIFO_STAT); 1678 } 1679 1680 static void sii8620_irq_g2wb(struct sii8620 *ctx) 1681 { 1682 u8 stat = sii8620_readb(ctx, REG_MDT_INT_0); 1683 1684 if (stat & BIT_MDT_IDLE_AFTER_HAWB_DISABLE) 1685 if (sii8620_is_mhl3(ctx)) 1686 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), 1687 MHL_INT_RC_FEAT_COMPLETE); 1688 1689 if (stat & BIT_MDT_RFIFO_DATA_RDY) 1690 sii8620_read_burst(ctx); 1691 1692 if (stat & BIT_MDT_XFIFO_EMPTY) 1693 sii8620_write(ctx, REG_MDT_XMIT_CTRL, 0); 1694 1695 sii8620_write(ctx, REG_MDT_INT_0, stat); 1696 } 1697 1698 static void sii8620_status_dcap_ready(struct sii8620 *ctx) 1699 { 1700 enum sii8620_mode mode; 1701 1702 mode = ctx->stat[MHL_DST_VERSION] >= 0x30 ? CM_MHL3 : CM_MHL1; 1703 if (mode > ctx->mode) 1704 sii8620_set_mode(ctx, mode); 1705 sii8620_peer_specific_init(ctx); 1706 sii8620_write(ctx, REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE 1707 | BIT_INTR9_EDID_DONE | BIT_INTR9_EDID_ERROR); 1708 } 1709 1710 static void sii8620_status_changed_path(struct sii8620 *ctx) 1711 { 1712 if (ctx->stat[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED) { 1713 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE), 1714 MHL_DST_LM_CLK_MODE_NORMAL 1715 | MHL_DST_LM_PATH_ENABLED); 1716 if (!sii8620_is_mhl3(ctx)) 1717 sii8620_mt_read_devcap(ctx, false); 1718 sii8620_mt_set_cont(ctx, sii8620_sink_detected); 1719 } else { 1720 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE), 1721 MHL_DST_LM_CLK_MODE_NORMAL); 1722 } 1723 } 1724 1725 static void sii8620_msc_mr_write_stat(struct sii8620 *ctx) 1726 { 1727 u8 st[MHL_DST_SIZE], xst[MHL_XDS_SIZE]; 1728 1729 sii8620_read_buf(ctx, REG_MHL_STAT_0, st, MHL_DST_SIZE); 1730 sii8620_read_buf(ctx, REG_MHL_EXTSTAT_0, xst, MHL_XDS_SIZE); 1731 1732 sii8620_update_array(ctx->stat, st, MHL_DST_SIZE); 1733 sii8620_update_array(ctx->xstat, xst, MHL_XDS_SIZE); 1734 1735 if (ctx->stat[MHL_DST_CONNECTED_RDY] & MHL_DST_CONN_DCAP_RDY) 1736 sii8620_status_dcap_ready(ctx); 1737 1738 if (st[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED) 1739 sii8620_status_changed_path(ctx); 1740 } 1741 1742 static void sii8620_ecbus_up(struct sii8620 *ctx, int ret) 1743 { 1744 if (ret < 0) 1745 return; 1746 1747 sii8620_set_mode(ctx, CM_ECBUS_S); 1748 } 1749 1750 static void sii8620_got_ecbus_speed(struct sii8620 *ctx, int ret) 1751 { 1752 if (ret < 0) 1753 return; 1754 1755 sii8620_mt_write_stat(ctx, MHL_XDS_REG(CURR_ECBUS_MODE), 1756 MHL_XDS_ECBUS_S | MHL_XDS_SLOT_MODE_8BIT); 1757 sii8620_mt_rap(ctx, MHL_RAP_CBUS_MODE_UP); 1758 sii8620_mt_set_cont(ctx, sii8620_ecbus_up); 1759 } 1760 1761 static void sii8620_mhl_burst_emsc_support_set(struct mhl_burst_emsc_support *d, 1762 enum mhl_burst_id id) 1763 { 1764 sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_EMSC_SUPPORT); 1765 d->num_entries = 1; 1766 d->burst_id[0] = cpu_to_be16(id); 1767 } 1768 1769 static void sii8620_send_features(struct sii8620 *ctx) 1770 { 1771 u8 buf[16]; 1772 1773 sii8620_write(ctx, REG_MDT_XMIT_CTRL, BIT_MDT_XMIT_CTRL_EN 1774 | BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN); 1775 sii8620_mhl_burst_emsc_support_set((void *)buf, 1776 MHL_BURST_ID_HID_PAYLOAD); 1777 sii8620_write_buf(ctx, REG_MDT_XMIT_WRITE_PORT, buf, ARRAY_SIZE(buf)); 1778 } 1779 1780 static bool sii8620_rcp_consume(struct sii8620 *ctx, u8 scancode) 1781 { 1782 bool pressed = !(scancode & MHL_RCP_KEY_RELEASED_MASK); 1783 1784 scancode &= MHL_RCP_KEY_ID_MASK; 1785 1786 if (!ctx->rc_dev) { 1787 dev_dbg(ctx->dev, "RCP input device not initialized\n"); 1788 return false; 1789 } 1790 1791 if (pressed) 1792 rc_keydown(ctx->rc_dev, RC_PROTO_CEC, scancode, 0); 1793 else 1794 rc_keyup(ctx->rc_dev); 1795 1796 return true; 1797 } 1798 1799 static void sii8620_msc_mr_set_int(struct sii8620 *ctx) 1800 { 1801 u8 ints[MHL_INT_SIZE]; 1802 1803 sii8620_read_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE); 1804 sii8620_write_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE); 1805 1806 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_DCAP_CHG) { 1807 switch (ctx->mode) { 1808 case CM_MHL3: 1809 sii8620_mt_read_xdevcap_reg(ctx, MHL_XDC_ECBUS_SPEEDS); 1810 sii8620_mt_set_cont(ctx, sii8620_got_ecbus_speed); 1811 break; 1812 case CM_ECBUS_S: 1813 sii8620_mt_read_devcap(ctx, true); 1814 break; 1815 default: 1816 break; 1817 } 1818 } 1819 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_REQ) 1820 sii8620_send_features(ctx); 1821 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_COMPLETE) 1822 sii8620_edid_read(ctx, 0); 1823 } 1824 1825 static struct sii8620_mt_msg *sii8620_msc_msg_first(struct sii8620 *ctx) 1826 { 1827 struct device *dev = ctx->dev; 1828 1829 if (list_empty(&ctx->mt_queue)) { 1830 dev_err(dev, "unexpected MSC MT response\n"); 1831 return NULL; 1832 } 1833 1834 return list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 1835 } 1836 1837 static void sii8620_msc_mt_done(struct sii8620 *ctx) 1838 { 1839 struct sii8620_mt_msg *msg = sii8620_msc_msg_first(ctx); 1840 1841 if (!msg) 1842 return; 1843 1844 msg->ret = sii8620_readb(ctx, REG_MSC_MT_RCVD_DATA0); 1845 ctx->mt_state = MT_STATE_DONE; 1846 } 1847 1848 static void sii8620_msc_mr_msc_msg(struct sii8620 *ctx) 1849 { 1850 struct sii8620_mt_msg *msg; 1851 u8 buf[2]; 1852 1853 sii8620_read_buf(ctx, REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA, buf, 2); 1854 1855 switch (buf[0]) { 1856 case MHL_MSC_MSG_RAPK: 1857 msg = sii8620_msc_msg_first(ctx); 1858 if (!msg) 1859 return; 1860 msg->ret = buf[1]; 1861 ctx->mt_state = MT_STATE_DONE; 1862 break; 1863 case MHL_MSC_MSG_RCP: 1864 if (!sii8620_rcp_consume(ctx, buf[1])) 1865 sii8620_mt_rcpe(ctx, 1866 MHL_RCPE_STATUS_INEFFECTIVE_KEY_CODE); 1867 sii8620_mt_rcpk(ctx, buf[1]); 1868 break; 1869 default: 1870 dev_err(ctx->dev, "%s message type %d,%d not supported", 1871 __func__, buf[0], buf[1]); 1872 } 1873 } 1874 1875 static void sii8620_irq_msc(struct sii8620 *ctx) 1876 { 1877 u8 stat = sii8620_readb(ctx, REG_CBUS_INT_0); 1878 1879 if (stat & ~BIT_CBUS_HPD_CHG) 1880 sii8620_write(ctx, REG_CBUS_INT_0, stat & ~BIT_CBUS_HPD_CHG); 1881 1882 if (stat & BIT_CBUS_HPD_CHG) { 1883 u8 cbus_stat = sii8620_readb(ctx, REG_CBUS_STATUS); 1884 1885 if ((cbus_stat ^ ctx->cbus_status) & BIT_CBUS_STATUS_CBUS_HPD) { 1886 sii8620_write(ctx, REG_CBUS_INT_0, BIT_CBUS_HPD_CHG); 1887 } else { 1888 stat ^= BIT_CBUS_STATUS_CBUS_HPD; 1889 cbus_stat ^= BIT_CBUS_STATUS_CBUS_HPD; 1890 } 1891 ctx->cbus_status = cbus_stat; 1892 } 1893 1894 if (stat & BIT_CBUS_MSC_MR_WRITE_STAT) 1895 sii8620_msc_mr_write_stat(ctx); 1896 1897 if (stat & BIT_CBUS_MSC_MR_SET_INT) 1898 sii8620_msc_mr_set_int(ctx); 1899 1900 if (stat & BIT_CBUS_MSC_MT_DONE) 1901 sii8620_msc_mt_done(ctx); 1902 1903 if (stat & BIT_CBUS_MSC_MR_MSC_MSG) 1904 sii8620_msc_mr_msc_msg(ctx); 1905 } 1906 1907 static void sii8620_irq_coc(struct sii8620 *ctx) 1908 { 1909 u8 stat = sii8620_readb(ctx, REG_COC_INTR); 1910 1911 if (stat & BIT_COC_CALIBRATION_DONE) { 1912 u8 cstat = sii8620_readb(ctx, REG_COC_STAT_0); 1913 1914 cstat &= BIT_COC_STAT_0_PLL_LOCKED | MSK_COC_STAT_0_FSM_STATE; 1915 if (cstat == (BIT_COC_STAT_0_PLL_LOCKED | 0x02)) { 1916 sii8620_write_seq_static(ctx, 1917 REG_COC_CTLB, 0, 1918 REG_TRXINTMH, BIT_TDM_INTR_SYNC_DATA 1919 | BIT_TDM_INTR_SYNC_WAIT 1920 ); 1921 } 1922 } 1923 1924 sii8620_write(ctx, REG_COC_INTR, stat); 1925 } 1926 1927 static void sii8620_irq_merr(struct sii8620 *ctx) 1928 { 1929 u8 stat = sii8620_readb(ctx, REG_CBUS_INT_1); 1930 1931 sii8620_write(ctx, REG_CBUS_INT_1, stat); 1932 } 1933 1934 static void sii8620_irq_edid(struct sii8620 *ctx) 1935 { 1936 u8 stat = sii8620_readb(ctx, REG_INTR9); 1937 1938 sii8620_write(ctx, REG_INTR9, stat); 1939 1940 if (stat & BIT_INTR9_DEVCAP_DONE) 1941 ctx->mt_state = MT_STATE_DONE; 1942 } 1943 1944 static void sii8620_irq_scdt(struct sii8620 *ctx) 1945 { 1946 u8 stat = sii8620_readb(ctx, REG_INTR5); 1947 1948 if (stat & BIT_INTR_SCDT_CHANGE) { 1949 u8 cstat = sii8620_readb(ctx, REG_TMDS_CSTAT_P3); 1950 1951 if (cstat & BIT_TMDS_CSTAT_P3_SCDT) 1952 sii8620_start_video(ctx); 1953 } 1954 1955 sii8620_write(ctx, REG_INTR5, stat); 1956 } 1957 1958 static void sii8620_got_xdevcap(struct sii8620 *ctx, int ret) 1959 { 1960 if (ret < 0) 1961 return; 1962 1963 sii8620_mt_read_devcap(ctx, false); 1964 } 1965 1966 static void sii8620_irq_tdm(struct sii8620 *ctx) 1967 { 1968 u8 stat = sii8620_readb(ctx, REG_TRXINTH); 1969 u8 tdm = sii8620_readb(ctx, REG_TRXSTA2); 1970 1971 if ((tdm & MSK_TDM_SYNCHRONIZED) == VAL_TDM_SYNCHRONIZED) { 1972 ctx->mode = CM_ECBUS_S; 1973 ctx->burst.rx_ack = 0; 1974 ctx->burst.r_size = SII8620_BURST_BUF_LEN; 1975 sii8620_burst_tx_rbuf_info(ctx, SII8620_BURST_BUF_LEN); 1976 sii8620_mt_read_devcap(ctx, true); 1977 sii8620_mt_set_cont(ctx, sii8620_got_xdevcap); 1978 } else { 1979 sii8620_write_seq_static(ctx, 1980 REG_MHL_PLL_CTL2, 0, 1981 REG_MHL_PLL_CTL2, BIT_MHL_PLL_CTL2_CLKDETECT_EN 1982 ); 1983 } 1984 1985 sii8620_write(ctx, REG_TRXINTH, stat); 1986 } 1987 1988 static void sii8620_irq_block(struct sii8620 *ctx) 1989 { 1990 u8 stat = sii8620_readb(ctx, REG_EMSCINTR); 1991 1992 if (stat & BIT_EMSCINTR_SPI_DVLD) { 1993 u8 bstat = sii8620_readb(ctx, REG_SPIBURSTSTAT); 1994 1995 if (bstat & BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE) 1996 sii8620_burst_receive(ctx); 1997 } 1998 1999 sii8620_write(ctx, REG_EMSCINTR, stat); 2000 } 2001 2002 static void sii8620_irq_ddc(struct sii8620 *ctx) 2003 { 2004 u8 stat = sii8620_readb(ctx, REG_INTR3); 2005 2006 if (stat & BIT_DDC_CMD_DONE) { 2007 sii8620_write(ctx, REG_INTR3_MASK, 0); 2008 if (sii8620_is_mhl3(ctx)) 2009 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), 2010 MHL_INT_RC_FEAT_REQ); 2011 else 2012 sii8620_edid_read(ctx, 0); 2013 } 2014 sii8620_write(ctx, REG_INTR3, stat); 2015 } 2016 2017 /* endian agnostic, non-volatile version of test_bit */ 2018 static bool sii8620_test_bit(unsigned int nr, const u8 *addr) 2019 { 2020 return 1 & (addr[nr / BITS_PER_BYTE] >> (nr % BITS_PER_BYTE)); 2021 } 2022 2023 static irqreturn_t sii8620_irq_thread(int irq, void *data) 2024 { 2025 static const struct { 2026 int bit; 2027 void (*handler)(struct sii8620 *ctx); 2028 } irq_vec[] = { 2029 { BIT_FAST_INTR_STAT_DISC, sii8620_irq_disc }, 2030 { BIT_FAST_INTR_STAT_G2WB, sii8620_irq_g2wb }, 2031 { BIT_FAST_INTR_STAT_COC, sii8620_irq_coc }, 2032 { BIT_FAST_INTR_STAT_TDM, sii8620_irq_tdm }, 2033 { BIT_FAST_INTR_STAT_MSC, sii8620_irq_msc }, 2034 { BIT_FAST_INTR_STAT_MERR, sii8620_irq_merr }, 2035 { BIT_FAST_INTR_STAT_BLOCK, sii8620_irq_block }, 2036 { BIT_FAST_INTR_STAT_EDID, sii8620_irq_edid }, 2037 { BIT_FAST_INTR_STAT_DDC, sii8620_irq_ddc }, 2038 { BIT_FAST_INTR_STAT_SCDT, sii8620_irq_scdt }, 2039 }; 2040 struct sii8620 *ctx = data; 2041 u8 stats[LEN_FAST_INTR_STAT]; 2042 int i, ret; 2043 2044 mutex_lock(&ctx->lock); 2045 2046 sii8620_read_buf(ctx, REG_FAST_INTR_STAT, stats, ARRAY_SIZE(stats)); 2047 for (i = 0; i < ARRAY_SIZE(irq_vec); ++i) 2048 if (sii8620_test_bit(irq_vec[i].bit, stats)) 2049 irq_vec[i].handler(ctx); 2050 2051 sii8620_burst_rx_all(ctx); 2052 sii8620_mt_work(ctx); 2053 sii8620_burst_send(ctx); 2054 2055 ret = sii8620_clear_error(ctx); 2056 if (ret) { 2057 dev_err(ctx->dev, "Error during IRQ handling, %d.\n", ret); 2058 sii8620_mhl_disconnected(ctx); 2059 } 2060 mutex_unlock(&ctx->lock); 2061 2062 return IRQ_HANDLED; 2063 } 2064 2065 static void sii8620_cable_in(struct sii8620 *ctx) 2066 { 2067 struct device *dev = ctx->dev; 2068 u8 ver[5]; 2069 int ret; 2070 2071 ret = sii8620_hw_on(ctx); 2072 if (ret) { 2073 dev_err(dev, "Error powering on, %d.\n", ret); 2074 return; 2075 } 2076 2077 sii8620_read_buf(ctx, REG_VND_IDL, ver, ARRAY_SIZE(ver)); 2078 ret = sii8620_clear_error(ctx); 2079 if (ret) { 2080 dev_err(dev, "Error accessing I2C bus, %d.\n", ret); 2081 return; 2082 } 2083 2084 dev_info(dev, "ChipID %02x%02x:%02x%02x rev %02x.\n", ver[1], ver[0], 2085 ver[3], ver[2], ver[4]); 2086 2087 sii8620_write(ctx, REG_DPD, 2088 BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN); 2089 2090 sii8620_xtal_set_rate(ctx); 2091 sii8620_disconnect(ctx); 2092 2093 sii8620_write_seq_static(ctx, 2094 REG_MHL_CBUS_CTL0, VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONG 2095 | VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_734, 2096 REG_MHL_CBUS_CTL1, VAL_MHL_CBUS_CTL1_1115_OHM, 2097 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN, 2098 ); 2099 2100 ret = sii8620_clear_error(ctx); 2101 if (ret) { 2102 dev_err(dev, "Error accessing I2C bus, %d.\n", ret); 2103 return; 2104 } 2105 2106 enable_irq(to_i2c_client(ctx->dev)->irq); 2107 } 2108 2109 static void sii8620_init_rcp_input_dev(struct sii8620 *ctx) 2110 { 2111 struct rc_dev *rc_dev; 2112 int ret; 2113 2114 rc_dev = rc_allocate_device(RC_DRIVER_SCANCODE); 2115 if (!rc_dev) { 2116 dev_err(ctx->dev, "Failed to allocate RC device\n"); 2117 ctx->error = -ENOMEM; 2118 return; 2119 } 2120 2121 rc_dev->input_phys = "sii8620/input0"; 2122 rc_dev->input_id.bustype = BUS_VIRTUAL; 2123 rc_dev->map_name = RC_MAP_CEC; 2124 rc_dev->allowed_protocols = RC_PROTO_BIT_CEC; 2125 rc_dev->driver_name = "sii8620"; 2126 rc_dev->device_name = "sii8620"; 2127 2128 ret = rc_register_device(rc_dev); 2129 2130 if (ret) { 2131 dev_err(ctx->dev, "Failed to register RC device\n"); 2132 ctx->error = ret; 2133 rc_free_device(ctx->rc_dev); 2134 return; 2135 } 2136 ctx->rc_dev = rc_dev; 2137 } 2138 2139 static void sii8620_cable_out(struct sii8620 *ctx) 2140 { 2141 disable_irq(to_i2c_client(ctx->dev)->irq); 2142 sii8620_hw_off(ctx); 2143 } 2144 2145 static void sii8620_extcon_work(struct work_struct *work) 2146 { 2147 struct sii8620 *ctx = 2148 container_of(work, struct sii8620, extcon_wq); 2149 int state = extcon_get_state(ctx->extcon, EXTCON_DISP_MHL); 2150 2151 if (state == ctx->cable_state) 2152 return; 2153 2154 ctx->cable_state = state; 2155 2156 if (state > 0) 2157 sii8620_cable_in(ctx); 2158 else 2159 sii8620_cable_out(ctx); 2160 } 2161 2162 static int sii8620_extcon_notifier(struct notifier_block *self, 2163 unsigned long event, void *ptr) 2164 { 2165 struct sii8620 *ctx = 2166 container_of(self, struct sii8620, extcon_nb); 2167 2168 schedule_work(&ctx->extcon_wq); 2169 2170 return NOTIFY_DONE; 2171 } 2172 2173 static int sii8620_extcon_init(struct sii8620 *ctx) 2174 { 2175 struct extcon_dev *edev; 2176 struct device_node *musb, *muic; 2177 int ret; 2178 2179 /* get micro-USB connector node */ 2180 musb = of_graph_get_remote_node(ctx->dev->of_node, 1, -1); 2181 /* next get micro-USB Interface Controller node */ 2182 muic = of_get_next_parent(musb); 2183 2184 if (!muic) { 2185 dev_info(ctx->dev, "no extcon found, switching to 'always on' mode\n"); 2186 return 0; 2187 } 2188 2189 edev = extcon_find_edev_by_node(muic); 2190 of_node_put(muic); 2191 if (IS_ERR(edev)) { 2192 if (PTR_ERR(edev) == -EPROBE_DEFER) 2193 return -EPROBE_DEFER; 2194 dev_err(ctx->dev, "Invalid or missing extcon\n"); 2195 return PTR_ERR(edev); 2196 } 2197 2198 ctx->extcon = edev; 2199 ctx->extcon_nb.notifier_call = sii8620_extcon_notifier; 2200 INIT_WORK(&ctx->extcon_wq, sii8620_extcon_work); 2201 ret = extcon_register_notifier(edev, EXTCON_DISP_MHL, &ctx->extcon_nb); 2202 if (ret) { 2203 dev_err(ctx->dev, "failed to register notifier for MHL\n"); 2204 return ret; 2205 } 2206 2207 return 0; 2208 } 2209 2210 static inline struct sii8620 *bridge_to_sii8620(struct drm_bridge *bridge) 2211 { 2212 return container_of(bridge, struct sii8620, bridge); 2213 } 2214 2215 static int sii8620_attach(struct drm_bridge *bridge) 2216 { 2217 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2218 2219 sii8620_init_rcp_input_dev(ctx); 2220 2221 return sii8620_clear_error(ctx); 2222 } 2223 2224 static void sii8620_detach(struct drm_bridge *bridge) 2225 { 2226 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2227 2228 rc_unregister_device(ctx->rc_dev); 2229 } 2230 2231 static int sii8620_is_packing_required(struct sii8620 *ctx, 2232 const struct drm_display_mode *mode) 2233 { 2234 int max_pclk, max_pclk_pp_mode; 2235 2236 if (sii8620_is_mhl3(ctx)) { 2237 max_pclk = MHL3_MAX_PCLK; 2238 max_pclk_pp_mode = MHL3_MAX_PCLK_PP_MODE; 2239 } else { 2240 max_pclk = MHL1_MAX_PCLK; 2241 max_pclk_pp_mode = MHL1_MAX_PCLK_PP_MODE; 2242 } 2243 2244 if (mode->clock < max_pclk) 2245 return 0; 2246 else if (mode->clock < max_pclk_pp_mode) 2247 return 1; 2248 else 2249 return -1; 2250 } 2251 2252 static enum drm_mode_status sii8620_mode_valid(struct drm_bridge *bridge, 2253 const struct drm_display_mode *mode) 2254 { 2255 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2256 int pack_required = sii8620_is_packing_required(ctx, mode); 2257 bool can_pack = ctx->devcap[MHL_DCAP_VID_LINK_MODE] & 2258 MHL_DCAP_VID_LINK_PPIXEL; 2259 2260 switch (pack_required) { 2261 case 0: 2262 return MODE_OK; 2263 case 1: 2264 return (can_pack) ? MODE_OK : MODE_CLOCK_HIGH; 2265 default: 2266 return MODE_CLOCK_HIGH; 2267 } 2268 } 2269 2270 static bool sii8620_mode_fixup(struct drm_bridge *bridge, 2271 const struct drm_display_mode *mode, 2272 struct drm_display_mode *adjusted_mode) 2273 { 2274 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2275 2276 mutex_lock(&ctx->lock); 2277 2278 ctx->use_packed_pixel = sii8620_is_packing_required(ctx, adjusted_mode); 2279 ctx->video_code = drm_match_cea_mode(adjusted_mode); 2280 ctx->pixel_clock = adjusted_mode->clock; 2281 2282 mutex_unlock(&ctx->lock); 2283 2284 return true; 2285 } 2286 2287 static const struct drm_bridge_funcs sii8620_bridge_funcs = { 2288 .attach = sii8620_attach, 2289 .detach = sii8620_detach, 2290 .mode_fixup = sii8620_mode_fixup, 2291 .mode_valid = sii8620_mode_valid, 2292 }; 2293 2294 static int sii8620_probe(struct i2c_client *client, 2295 const struct i2c_device_id *id) 2296 { 2297 struct device *dev = &client->dev; 2298 struct sii8620 *ctx; 2299 int ret; 2300 2301 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 2302 if (!ctx) 2303 return -ENOMEM; 2304 2305 ctx->dev = dev; 2306 mutex_init(&ctx->lock); 2307 INIT_LIST_HEAD(&ctx->mt_queue); 2308 2309 ctx->clk_xtal = devm_clk_get(dev, "xtal"); 2310 if (IS_ERR(ctx->clk_xtal)) { 2311 dev_err(dev, "failed to get xtal clock from DT\n"); 2312 return PTR_ERR(ctx->clk_xtal); 2313 } 2314 2315 if (!client->irq) { 2316 dev_err(dev, "no irq provided\n"); 2317 return -EINVAL; 2318 } 2319 irq_set_status_flags(client->irq, IRQ_NOAUTOEN); 2320 ret = devm_request_threaded_irq(dev, client->irq, NULL, 2321 sii8620_irq_thread, 2322 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 2323 "sii8620", ctx); 2324 if (ret < 0) { 2325 dev_err(dev, "failed to install IRQ handler\n"); 2326 return ret; 2327 } 2328 2329 ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); 2330 if (IS_ERR(ctx->gpio_reset)) { 2331 dev_err(dev, "failed to get reset gpio from DT\n"); 2332 return PTR_ERR(ctx->gpio_reset); 2333 } 2334 2335 ctx->supplies[0].supply = "cvcc10"; 2336 ctx->supplies[1].supply = "iovcc18"; 2337 ret = devm_regulator_bulk_get(dev, 2, ctx->supplies); 2338 if (ret) 2339 return ret; 2340 2341 ret = sii8620_extcon_init(ctx); 2342 if (ret < 0) { 2343 dev_err(ctx->dev, "failed to initialize EXTCON\n"); 2344 return ret; 2345 } 2346 2347 i2c_set_clientdata(client, ctx); 2348 2349 ctx->bridge.funcs = &sii8620_bridge_funcs; 2350 ctx->bridge.of_node = dev->of_node; 2351 drm_bridge_add(&ctx->bridge); 2352 2353 if (!ctx->extcon) 2354 sii8620_cable_in(ctx); 2355 2356 return 0; 2357 } 2358 2359 static int sii8620_remove(struct i2c_client *client) 2360 { 2361 struct sii8620 *ctx = i2c_get_clientdata(client); 2362 2363 if (ctx->extcon) { 2364 extcon_unregister_notifier(ctx->extcon, EXTCON_DISP_MHL, 2365 &ctx->extcon_nb); 2366 flush_work(&ctx->extcon_wq); 2367 if (ctx->cable_state > 0) 2368 sii8620_cable_out(ctx); 2369 } else { 2370 sii8620_cable_out(ctx); 2371 } 2372 drm_bridge_remove(&ctx->bridge); 2373 2374 return 0; 2375 } 2376 2377 static const struct of_device_id sii8620_dt_match[] = { 2378 { .compatible = "sil,sii8620" }, 2379 { }, 2380 }; 2381 MODULE_DEVICE_TABLE(of, sii8620_dt_match); 2382 2383 static const struct i2c_device_id sii8620_id[] = { 2384 { "sii8620", 0 }, 2385 { }, 2386 }; 2387 2388 MODULE_DEVICE_TABLE(i2c, sii8620_id); 2389 static struct i2c_driver sii8620_driver = { 2390 .driver = { 2391 .name = "sii8620", 2392 .of_match_table = of_match_ptr(sii8620_dt_match), 2393 }, 2394 .probe = sii8620_probe, 2395 .remove = sii8620_remove, 2396 .id_table = sii8620_id, 2397 }; 2398 2399 module_i2c_driver(sii8620_driver); 2400 MODULE_LICENSE("GPL v2"); 2401