1 /* 2 * Silicon Image SiI8620 HDMI/MHL bridge driver 3 * 4 * Copyright (C) 2015, Samsung Electronics Co., Ltd. 5 * Andrzej Hajda <a.hajda@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <asm/unaligned.h> 13 14 #include <drm/bridge/mhl.h> 15 #include <drm/drm_crtc.h> 16 #include <drm/drm_edid.h> 17 #include <drm/drm_encoder.h> 18 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/extcon.h> 22 #include <linux/gpio/consumer.h> 23 #include <linux/i2c.h> 24 #include <linux/interrupt.h> 25 #include <linux/irq.h> 26 #include <linux/kernel.h> 27 #include <linux/list.h> 28 #include <linux/module.h> 29 #include <linux/mutex.h> 30 #include <linux/of_graph.h> 31 #include <linux/regulator/consumer.h> 32 #include <linux/slab.h> 33 34 #include <media/rc-core.h> 35 36 #include "sil-sii8620.h" 37 38 #define SII8620_BURST_BUF_LEN 288 39 #define VAL_RX_HDMI_CTRL2_DEFVAL VAL_RX_HDMI_CTRL2_IDLE_CNT(3) 40 41 #define MHL1_MAX_PCLK 75000 42 #define MHL1_MAX_PCLK_PP_MODE 150000 43 #define MHL3_MAX_PCLK 200000 44 #define MHL3_MAX_PCLK_PP_MODE 300000 45 46 enum sii8620_mode { 47 CM_DISCONNECTED, 48 CM_DISCOVERY, 49 CM_MHL1, 50 CM_MHL3, 51 CM_ECBUS_S 52 }; 53 54 enum sii8620_sink_type { 55 SINK_NONE, 56 SINK_HDMI, 57 SINK_DVI 58 }; 59 60 enum sii8620_mt_state { 61 MT_STATE_READY, 62 MT_STATE_BUSY, 63 MT_STATE_DONE 64 }; 65 66 struct sii8620 { 67 struct drm_bridge bridge; 68 struct device *dev; 69 struct rc_dev *rc_dev; 70 struct clk *clk_xtal; 71 struct gpio_desc *gpio_reset; 72 struct gpio_desc *gpio_int; 73 struct regulator_bulk_data supplies[2]; 74 struct mutex lock; /* context lock, protects fields below */ 75 int error; 76 unsigned int use_packed_pixel:1; 77 enum sii8620_mode mode; 78 enum sii8620_sink_type sink_type; 79 u8 cbus_status; 80 u8 stat[MHL_DST_SIZE]; 81 u8 xstat[MHL_XDS_SIZE]; 82 u8 devcap[MHL_DCAP_SIZE]; 83 u8 xdevcap[MHL_XDC_SIZE]; 84 bool feature_complete; 85 bool devcap_read; 86 bool sink_detected; 87 struct edid *edid; 88 unsigned int gen2_write_burst:1; 89 enum sii8620_mt_state mt_state; 90 struct extcon_dev *extcon; 91 struct notifier_block extcon_nb; 92 struct work_struct extcon_wq; 93 int cable_state; 94 struct list_head mt_queue; 95 struct { 96 int r_size; 97 int r_count; 98 int rx_ack; 99 int rx_count; 100 u8 rx_buf[32]; 101 int tx_count; 102 u8 tx_buf[32]; 103 } burst; 104 }; 105 106 struct sii8620_mt_msg; 107 108 typedef void (*sii8620_mt_msg_cb)(struct sii8620 *ctx, 109 struct sii8620_mt_msg *msg); 110 111 typedef void (*sii8620_cb)(struct sii8620 *ctx, int ret); 112 113 struct sii8620_mt_msg { 114 struct list_head node; 115 u8 reg[4]; 116 u8 ret; 117 sii8620_mt_msg_cb send; 118 sii8620_mt_msg_cb recv; 119 sii8620_cb continuation; 120 }; 121 122 static const u8 sii8620_i2c_page[] = { 123 0x39, /* Main System */ 124 0x3d, /* TDM and HSIC */ 125 0x49, /* TMDS Receiver, MHL EDID */ 126 0x4d, /* eMSC, HDCP, HSIC */ 127 0x5d, /* MHL Spec */ 128 0x64, /* MHL CBUS */ 129 0x59, /* Hardware TPI (Transmitter Programming Interface) */ 130 0x61, /* eCBUS-S, eCBUS-D */ 131 }; 132 133 static void sii8620_fetch_edid(struct sii8620 *ctx); 134 static void sii8620_set_upstream_edid(struct sii8620 *ctx); 135 static void sii8620_enable_hpd(struct sii8620 *ctx); 136 static void sii8620_mhl_disconnected(struct sii8620 *ctx); 137 static void sii8620_disconnect(struct sii8620 *ctx); 138 139 static int sii8620_clear_error(struct sii8620 *ctx) 140 { 141 int ret = ctx->error; 142 143 ctx->error = 0; 144 return ret; 145 } 146 147 static void sii8620_read_buf(struct sii8620 *ctx, u16 addr, u8 *buf, int len) 148 { 149 struct device *dev = ctx->dev; 150 struct i2c_client *client = to_i2c_client(dev); 151 u8 data = addr; 152 struct i2c_msg msg[] = { 153 { 154 .addr = sii8620_i2c_page[addr >> 8], 155 .flags = client->flags, 156 .len = 1, 157 .buf = &data 158 }, 159 { 160 .addr = sii8620_i2c_page[addr >> 8], 161 .flags = client->flags | I2C_M_RD, 162 .len = len, 163 .buf = buf 164 }, 165 }; 166 int ret; 167 168 if (ctx->error) 169 return; 170 171 ret = i2c_transfer(client->adapter, msg, 2); 172 dev_dbg(dev, "read at %04x: %*ph, %d\n", addr, len, buf, ret); 173 174 if (ret != 2) { 175 dev_err(dev, "Read at %#06x of %d bytes failed with code %d.\n", 176 addr, len, ret); 177 ctx->error = ret < 0 ? ret : -EIO; 178 } 179 } 180 181 static u8 sii8620_readb(struct sii8620 *ctx, u16 addr) 182 { 183 u8 ret; 184 185 sii8620_read_buf(ctx, addr, &ret, 1); 186 return ret; 187 } 188 189 static void sii8620_write_buf(struct sii8620 *ctx, u16 addr, const u8 *buf, 190 int len) 191 { 192 struct device *dev = ctx->dev; 193 struct i2c_client *client = to_i2c_client(dev); 194 u8 data[2]; 195 struct i2c_msg msg = { 196 .addr = sii8620_i2c_page[addr >> 8], 197 .flags = client->flags, 198 .len = len + 1, 199 }; 200 int ret; 201 202 if (ctx->error) 203 return; 204 205 if (len > 1) { 206 msg.buf = kmalloc(len + 1, GFP_KERNEL); 207 if (!msg.buf) { 208 ctx->error = -ENOMEM; 209 return; 210 } 211 memcpy(msg.buf + 1, buf, len); 212 } else { 213 msg.buf = data; 214 msg.buf[1] = *buf; 215 } 216 217 msg.buf[0] = addr; 218 219 ret = i2c_transfer(client->adapter, &msg, 1); 220 dev_dbg(dev, "write at %04x: %*ph, %d\n", addr, len, buf, ret); 221 222 if (ret != 1) { 223 dev_err(dev, "Write at %#06x of %*ph failed with code %d.\n", 224 addr, len, buf, ret); 225 ctx->error = ret ?: -EIO; 226 } 227 228 if (len > 1) 229 kfree(msg.buf); 230 } 231 232 #define sii8620_write(ctx, addr, arr...) \ 233 ({\ 234 u8 d[] = { arr }; \ 235 sii8620_write_buf(ctx, addr, d, ARRAY_SIZE(d)); \ 236 }) 237 238 static void __sii8620_write_seq(struct sii8620 *ctx, const u16 *seq, int len) 239 { 240 int i; 241 242 for (i = 0; i < len; i += 2) 243 sii8620_write(ctx, seq[i], seq[i + 1]); 244 } 245 246 #define sii8620_write_seq(ctx, seq...) \ 247 ({\ 248 const u16 d[] = { seq }; \ 249 __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \ 250 }) 251 252 #define sii8620_write_seq_static(ctx, seq...) \ 253 ({\ 254 static const u16 d[] = { seq }; \ 255 __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \ 256 }) 257 258 static void sii8620_setbits(struct sii8620 *ctx, u16 addr, u8 mask, u8 val) 259 { 260 val = (val & mask) | (sii8620_readb(ctx, addr) & ~mask); 261 sii8620_write(ctx, addr, val); 262 } 263 264 static inline bool sii8620_is_mhl3(struct sii8620 *ctx) 265 { 266 return ctx->mode >= CM_MHL3; 267 } 268 269 static void sii8620_mt_cleanup(struct sii8620 *ctx) 270 { 271 struct sii8620_mt_msg *msg, *n; 272 273 list_for_each_entry_safe(msg, n, &ctx->mt_queue, node) { 274 list_del(&msg->node); 275 kfree(msg); 276 } 277 ctx->mt_state = MT_STATE_READY; 278 } 279 280 static void sii8620_mt_work(struct sii8620 *ctx) 281 { 282 struct sii8620_mt_msg *msg; 283 284 if (ctx->error) 285 return; 286 if (ctx->mt_state == MT_STATE_BUSY || list_empty(&ctx->mt_queue)) 287 return; 288 289 if (ctx->mt_state == MT_STATE_DONE) { 290 ctx->mt_state = MT_STATE_READY; 291 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, 292 node); 293 list_del(&msg->node); 294 if (msg->recv) 295 msg->recv(ctx, msg); 296 if (msg->continuation) 297 msg->continuation(ctx, msg->ret); 298 kfree(msg); 299 } 300 301 if (ctx->mt_state != MT_STATE_READY || list_empty(&ctx->mt_queue)) 302 return; 303 304 ctx->mt_state = MT_STATE_BUSY; 305 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 306 if (msg->send) 307 msg->send(ctx, msg); 308 } 309 310 static void sii8620_enable_gen2_write_burst(struct sii8620 *ctx) 311 { 312 u8 ctrl = BIT_MDT_RCV_CTRL_MDT_RCV_EN; 313 314 if (ctx->gen2_write_burst) 315 return; 316 317 if (ctx->mode >= CM_MHL1) 318 ctrl |= BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN; 319 320 sii8620_write_seq(ctx, 321 REG_MDT_RCV_TIMEOUT, 100, 322 REG_MDT_RCV_CTRL, ctrl 323 ); 324 ctx->gen2_write_burst = 1; 325 } 326 327 static void sii8620_disable_gen2_write_burst(struct sii8620 *ctx) 328 { 329 if (!ctx->gen2_write_burst) 330 return; 331 332 sii8620_write_seq_static(ctx, 333 REG_MDT_XMIT_CTRL, 0, 334 REG_MDT_RCV_CTRL, 0 335 ); 336 ctx->gen2_write_burst = 0; 337 } 338 339 static void sii8620_start_gen2_write_burst(struct sii8620 *ctx) 340 { 341 sii8620_write_seq_static(ctx, 342 REG_MDT_INT_1_MASK, BIT_MDT_RCV_TIMEOUT 343 | BIT_MDT_RCV_SM_ABORT_PKT_RCVD | BIT_MDT_RCV_SM_ERROR 344 | BIT_MDT_XMIT_TIMEOUT | BIT_MDT_XMIT_SM_ABORT_PKT_RCVD 345 | BIT_MDT_XMIT_SM_ERROR, 346 REG_MDT_INT_0_MASK, BIT_MDT_XFIFO_EMPTY 347 | BIT_MDT_IDLE_AFTER_HAWB_DISABLE 348 | BIT_MDT_RFIFO_DATA_RDY 349 ); 350 sii8620_enable_gen2_write_burst(ctx); 351 } 352 353 static void sii8620_mt_msc_cmd_send(struct sii8620 *ctx, 354 struct sii8620_mt_msg *msg) 355 { 356 if (msg->reg[0] == MHL_SET_INT && 357 msg->reg[1] == MHL_INT_REG(RCHANGE) && 358 msg->reg[2] == MHL_INT_RC_FEAT_REQ) 359 sii8620_enable_gen2_write_burst(ctx); 360 else 361 sii8620_disable_gen2_write_burst(ctx); 362 363 switch (msg->reg[0]) { 364 case MHL_WRITE_STAT: 365 case MHL_SET_INT: 366 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg + 1, 2); 367 sii8620_write(ctx, REG_MSC_COMMAND_START, 368 BIT_MSC_COMMAND_START_WRITE_STAT); 369 break; 370 case MHL_MSC_MSG: 371 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg, 3); 372 sii8620_write(ctx, REG_MSC_COMMAND_START, 373 BIT_MSC_COMMAND_START_MSC_MSG); 374 break; 375 case MHL_READ_DEVCAP_REG: 376 case MHL_READ_XDEVCAP_REG: 377 sii8620_write(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg[1]); 378 sii8620_write(ctx, REG_MSC_COMMAND_START, 379 BIT_MSC_COMMAND_START_READ_DEVCAP); 380 break; 381 default: 382 dev_err(ctx->dev, "%s: command %#x not supported\n", __func__, 383 msg->reg[0]); 384 } 385 } 386 387 static struct sii8620_mt_msg *sii8620_mt_msg_new(struct sii8620 *ctx) 388 { 389 struct sii8620_mt_msg *msg = kzalloc(sizeof(*msg), GFP_KERNEL); 390 391 if (!msg) 392 ctx->error = -ENOMEM; 393 else 394 list_add_tail(&msg->node, &ctx->mt_queue); 395 396 return msg; 397 } 398 399 static void sii8620_mt_set_cont(struct sii8620 *ctx, sii8620_cb cont) 400 { 401 struct sii8620_mt_msg *msg; 402 403 if (ctx->error) 404 return; 405 406 if (list_empty(&ctx->mt_queue)) { 407 ctx->error = -EINVAL; 408 return; 409 } 410 msg = list_last_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 411 msg->continuation = cont; 412 } 413 414 static void sii8620_mt_msc_cmd(struct sii8620 *ctx, u8 cmd, u8 arg1, u8 arg2) 415 { 416 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 417 418 if (!msg) 419 return; 420 421 msg->reg[0] = cmd; 422 msg->reg[1] = arg1; 423 msg->reg[2] = arg2; 424 msg->send = sii8620_mt_msc_cmd_send; 425 } 426 427 static void sii8620_mt_write_stat(struct sii8620 *ctx, u8 reg, u8 val) 428 { 429 sii8620_mt_msc_cmd(ctx, MHL_WRITE_STAT, reg, val); 430 } 431 432 static inline void sii8620_mt_set_int(struct sii8620 *ctx, u8 irq, u8 mask) 433 { 434 sii8620_mt_msc_cmd(ctx, MHL_SET_INT, irq, mask); 435 } 436 437 static void sii8620_mt_msc_msg(struct sii8620 *ctx, u8 cmd, u8 data) 438 { 439 sii8620_mt_msc_cmd(ctx, MHL_MSC_MSG, cmd, data); 440 } 441 442 static void sii8620_mt_rap(struct sii8620 *ctx, u8 code) 443 { 444 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RAP, code); 445 } 446 447 static void sii8620_mt_rcpk(struct sii8620 *ctx, u8 code) 448 { 449 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPK, code); 450 } 451 452 static void sii8620_mt_rcpe(struct sii8620 *ctx, u8 code) 453 { 454 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPE, code); 455 } 456 457 static void sii8620_mt_read_devcap_send(struct sii8620 *ctx, 458 struct sii8620_mt_msg *msg) 459 { 460 u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP 461 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 462 | BIT_EDID_CTRL_EDID_MODE_EN; 463 464 if (msg->reg[0] == MHL_READ_XDEVCAP) 465 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN; 466 467 sii8620_write_seq(ctx, 468 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE, 469 REG_EDID_CTRL, ctrl, 470 REG_TPI_CBUS_START, BIT_TPI_CBUS_START_GET_DEVCAP_START 471 ); 472 } 473 474 /* copy src to dst and set changed bits in src */ 475 static void sii8620_update_array(u8 *dst, u8 *src, int count) 476 { 477 while (--count >= 0) { 478 *src ^= *dst; 479 *dst++ ^= *src++; 480 } 481 } 482 483 static void sii8620_identify_sink(struct sii8620 *ctx) 484 { 485 static const char * const sink_str[] = { 486 [SINK_NONE] = "NONE", 487 [SINK_HDMI] = "HDMI", 488 [SINK_DVI] = "DVI" 489 }; 490 491 char sink_name[20]; 492 struct device *dev = ctx->dev; 493 494 if (!ctx->sink_detected || !ctx->devcap_read) 495 return; 496 497 sii8620_fetch_edid(ctx); 498 if (!ctx->edid) { 499 dev_err(ctx->dev, "Cannot fetch EDID\n"); 500 sii8620_mhl_disconnected(ctx); 501 return; 502 } 503 sii8620_set_upstream_edid(ctx); 504 505 if (drm_detect_hdmi_monitor(ctx->edid)) 506 ctx->sink_type = SINK_HDMI; 507 else 508 ctx->sink_type = SINK_DVI; 509 510 drm_edid_get_monitor_name(ctx->edid, sink_name, ARRAY_SIZE(sink_name)); 511 512 dev_info(dev, "detected sink(type: %s): %s\n", 513 sink_str[ctx->sink_type], sink_name); 514 } 515 516 static void sii8620_mr_devcap(struct sii8620 *ctx) 517 { 518 u8 dcap[MHL_DCAP_SIZE]; 519 struct device *dev = ctx->dev; 520 521 sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, dcap, MHL_DCAP_SIZE); 522 if (ctx->error < 0) 523 return; 524 525 dev_info(dev, "detected dongle MHL %d.%d, ChipID %02x%02x:%02x%02x\n", 526 dcap[MHL_DCAP_MHL_VERSION] / 16, 527 dcap[MHL_DCAP_MHL_VERSION] % 16, 528 dcap[MHL_DCAP_ADOPTER_ID_H], dcap[MHL_DCAP_ADOPTER_ID_L], 529 dcap[MHL_DCAP_DEVICE_ID_H], dcap[MHL_DCAP_DEVICE_ID_L]); 530 sii8620_update_array(ctx->devcap, dcap, MHL_DCAP_SIZE); 531 ctx->devcap_read = true; 532 sii8620_identify_sink(ctx); 533 } 534 535 static void sii8620_mr_xdevcap(struct sii8620 *ctx) 536 { 537 sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, ctx->xdevcap, 538 MHL_XDC_SIZE); 539 } 540 541 static void sii8620_mt_read_devcap_recv(struct sii8620 *ctx, 542 struct sii8620_mt_msg *msg) 543 { 544 u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP 545 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 546 | BIT_EDID_CTRL_EDID_MODE_EN; 547 548 if (msg->reg[0] == MHL_READ_XDEVCAP) 549 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN; 550 551 sii8620_write_seq(ctx, 552 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE | BIT_INTR9_EDID_DONE 553 | BIT_INTR9_EDID_ERROR, 554 REG_EDID_CTRL, ctrl, 555 REG_EDID_FIFO_ADDR, 0 556 ); 557 558 if (msg->reg[0] == MHL_READ_XDEVCAP) 559 sii8620_mr_xdevcap(ctx); 560 else 561 sii8620_mr_devcap(ctx); 562 } 563 564 static void sii8620_mt_read_devcap(struct sii8620 *ctx, bool xdevcap) 565 { 566 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 567 568 if (!msg) 569 return; 570 571 msg->reg[0] = xdevcap ? MHL_READ_XDEVCAP : MHL_READ_DEVCAP; 572 msg->send = sii8620_mt_read_devcap_send; 573 msg->recv = sii8620_mt_read_devcap_recv; 574 } 575 576 static void sii8620_mt_read_devcap_reg_recv(struct sii8620 *ctx, 577 struct sii8620_mt_msg *msg) 578 { 579 u8 reg = msg->reg[1] & 0x7f; 580 581 if (msg->reg[1] & 0x80) 582 ctx->xdevcap[reg] = msg->ret; 583 else 584 ctx->devcap[reg] = msg->ret; 585 } 586 587 static void sii8620_mt_read_devcap_reg(struct sii8620 *ctx, u8 reg) 588 { 589 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 590 591 if (!msg) 592 return; 593 594 msg->reg[0] = (reg & 0x80) ? MHL_READ_XDEVCAP_REG : MHL_READ_DEVCAP_REG; 595 msg->reg[1] = reg; 596 msg->send = sii8620_mt_msc_cmd_send; 597 msg->recv = sii8620_mt_read_devcap_reg_recv; 598 } 599 600 static inline void sii8620_mt_read_xdevcap_reg(struct sii8620 *ctx, u8 reg) 601 { 602 sii8620_mt_read_devcap_reg(ctx, reg | 0x80); 603 } 604 605 static void *sii8620_burst_get_tx_buf(struct sii8620 *ctx, int len) 606 { 607 u8 *buf = &ctx->burst.tx_buf[ctx->burst.tx_count]; 608 int size = len + 2; 609 610 if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) { 611 dev_err(ctx->dev, "TX-BLK buffer exhausted\n"); 612 ctx->error = -EINVAL; 613 return NULL; 614 } 615 616 ctx->burst.tx_count += size; 617 buf[1] = len; 618 619 return buf + 2; 620 } 621 622 static u8 *sii8620_burst_get_rx_buf(struct sii8620 *ctx, int len) 623 { 624 u8 *buf = &ctx->burst.rx_buf[ctx->burst.rx_count]; 625 int size = len + 1; 626 627 if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) { 628 dev_err(ctx->dev, "RX-BLK buffer exhausted\n"); 629 ctx->error = -EINVAL; 630 return NULL; 631 } 632 633 ctx->burst.rx_count += size; 634 buf[0] = len; 635 636 return buf + 1; 637 } 638 639 static void sii8620_burst_send(struct sii8620 *ctx) 640 { 641 int tx_left = ctx->burst.tx_count; 642 u8 *d = ctx->burst.tx_buf; 643 644 while (tx_left > 0) { 645 int len = d[1] + 2; 646 647 if (ctx->burst.r_count + len > ctx->burst.r_size) 648 break; 649 d[0] = min(ctx->burst.rx_ack, 255); 650 ctx->burst.rx_ack -= d[0]; 651 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, d, len); 652 ctx->burst.r_count += len; 653 tx_left -= len; 654 d += len; 655 } 656 657 ctx->burst.tx_count = tx_left; 658 659 while (ctx->burst.rx_ack > 0) { 660 u8 b[2] = { min(ctx->burst.rx_ack, 255), 0 }; 661 662 if (ctx->burst.r_count + 2 > ctx->burst.r_size) 663 break; 664 ctx->burst.rx_ack -= b[0]; 665 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, b, 2); 666 ctx->burst.r_count += 2; 667 } 668 } 669 670 static void sii8620_burst_receive(struct sii8620 *ctx) 671 { 672 u8 buf[3], *d; 673 int count; 674 675 sii8620_read_buf(ctx, REG_EMSCRFIFOBCNTL, buf, 2); 676 count = get_unaligned_le16(buf); 677 while (count > 0) { 678 int len = min(count, 3); 679 680 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, buf, len); 681 count -= len; 682 ctx->burst.rx_ack += len - 1; 683 ctx->burst.r_count -= buf[1]; 684 if (ctx->burst.r_count < 0) 685 ctx->burst.r_count = 0; 686 687 if (len < 3 || !buf[2]) 688 continue; 689 690 len = buf[2]; 691 d = sii8620_burst_get_rx_buf(ctx, len); 692 if (!d) 693 continue; 694 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, d, len); 695 count -= len; 696 ctx->burst.rx_ack += len; 697 } 698 } 699 700 static void sii8620_burst_tx_rbuf_info(struct sii8620 *ctx, int size) 701 { 702 struct mhl_burst_blk_rcv_buffer_info *d = 703 sii8620_burst_get_tx_buf(ctx, sizeof(*d)); 704 if (!d) 705 return; 706 707 d->id = cpu_to_be16(MHL_BURST_ID_BLK_RCV_BUFFER_INFO); 708 d->size = cpu_to_le16(size); 709 } 710 711 static u8 sii8620_checksum(void *ptr, int size) 712 { 713 u8 *d = ptr, sum = 0; 714 715 while (size--) 716 sum += *d++; 717 718 return sum; 719 } 720 721 static void sii8620_mhl_burst_hdr_set(struct mhl3_burst_header *h, 722 enum mhl_burst_id id) 723 { 724 h->id = cpu_to_be16(id); 725 h->total_entries = 1; 726 h->sequence_index = 1; 727 } 728 729 static void sii8620_burst_tx_bits_per_pixel_fmt(struct sii8620 *ctx, u8 fmt) 730 { 731 struct mhl_burst_bits_per_pixel_fmt *d; 732 const int size = sizeof(*d) + sizeof(d->desc[0]); 733 734 d = sii8620_burst_get_tx_buf(ctx, size); 735 if (!d) 736 return; 737 738 sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_BITS_PER_PIXEL_FMT); 739 d->num_entries = 1; 740 d->desc[0].stream_id = 0; 741 d->desc[0].pixel_format = fmt; 742 d->hdr.checksum -= sii8620_checksum(d, size); 743 } 744 745 static void sii8620_burst_rx_all(struct sii8620 *ctx) 746 { 747 u8 *d = ctx->burst.rx_buf; 748 int count = ctx->burst.rx_count; 749 750 while (count-- > 0) { 751 int len = *d++; 752 int id = get_unaligned_be16(&d[0]); 753 754 switch (id) { 755 case MHL_BURST_ID_BLK_RCV_BUFFER_INFO: 756 ctx->burst.r_size = get_unaligned_le16(&d[2]); 757 break; 758 default: 759 break; 760 } 761 count -= len; 762 d += len; 763 } 764 ctx->burst.rx_count = 0; 765 } 766 767 static void sii8620_fetch_edid(struct sii8620 *ctx) 768 { 769 u8 lm_ddc, ddc_cmd, int3, cbus; 770 unsigned long timeout; 771 int fetched, i; 772 int edid_len = EDID_LENGTH; 773 u8 *edid; 774 775 sii8620_readb(ctx, REG_CBUS_STATUS); 776 lm_ddc = sii8620_readb(ctx, REG_LM_DDC); 777 ddc_cmd = sii8620_readb(ctx, REG_DDC_CMD); 778 779 sii8620_write_seq(ctx, 780 REG_INTR9_MASK, 0, 781 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO, 782 REG_HDCP2X_POLL_CS, 0x71, 783 REG_HDCP2X_CTRL_0, BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX, 784 REG_LM_DDC, lm_ddc | BIT_LM_DDC_SW_TPI_EN_DISABLED, 785 ); 786 787 for (i = 0; i < 256; ++i) { 788 u8 ddc_stat = sii8620_readb(ctx, REG_DDC_STATUS); 789 790 if (!(ddc_stat & BIT_DDC_STATUS_DDC_I2C_IN_PROG)) 791 break; 792 sii8620_write(ctx, REG_DDC_STATUS, 793 BIT_DDC_STATUS_DDC_FIFO_EMPTY); 794 } 795 796 sii8620_write(ctx, REG_DDC_ADDR, 0x50 << 1); 797 798 edid = kmalloc(EDID_LENGTH, GFP_KERNEL); 799 if (!edid) { 800 ctx->error = -ENOMEM; 801 return; 802 } 803 804 #define FETCH_SIZE 16 805 for (fetched = 0; fetched < edid_len; fetched += FETCH_SIZE) { 806 sii8620_readb(ctx, REG_DDC_STATUS); 807 sii8620_write_seq(ctx, 808 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_ABORT, 809 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_CLEAR_FIFO, 810 REG_DDC_STATUS, BIT_DDC_STATUS_DDC_FIFO_EMPTY 811 ); 812 sii8620_write_seq(ctx, 813 REG_DDC_SEGM, fetched >> 8, 814 REG_DDC_OFFSET, fetched & 0xff, 815 REG_DDC_DIN_CNT1, FETCH_SIZE, 816 REG_DDC_DIN_CNT2, 0, 817 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_ENH_DDC_READ_NO_ACK 818 ); 819 820 int3 = 0; 821 timeout = jiffies + msecs_to_jiffies(200); 822 for (;;) { 823 cbus = sii8620_readb(ctx, REG_CBUS_STATUS); 824 if (~cbus & BIT_CBUS_STATUS_CBUS_CONNECTED) { 825 kfree(edid); 826 edid = NULL; 827 goto end; 828 } 829 if (int3 & BIT_DDC_CMD_DONE) { 830 if (sii8620_readb(ctx, REG_DDC_DOUT_CNT) 831 >= FETCH_SIZE) 832 break; 833 } else { 834 int3 = sii8620_readb(ctx, REG_INTR3); 835 } 836 if (time_is_before_jiffies(timeout)) { 837 ctx->error = -ETIMEDOUT; 838 dev_err(ctx->dev, "timeout during EDID read\n"); 839 kfree(edid); 840 edid = NULL; 841 goto end; 842 } 843 usleep_range(10, 20); 844 } 845 846 sii8620_read_buf(ctx, REG_DDC_DATA, edid + fetched, FETCH_SIZE); 847 if (fetched + FETCH_SIZE == EDID_LENGTH) { 848 u8 ext = ((struct edid *)edid)->extensions; 849 850 if (ext) { 851 u8 *new_edid; 852 853 edid_len += ext * EDID_LENGTH; 854 new_edid = krealloc(edid, edid_len, GFP_KERNEL); 855 if (!new_edid) { 856 kfree(edid); 857 ctx->error = -ENOMEM; 858 return; 859 } 860 edid = new_edid; 861 } 862 } 863 } 864 865 sii8620_write_seq(ctx, 866 REG_INTR3_MASK, BIT_DDC_CMD_DONE, 867 REG_LM_DDC, lm_ddc 868 ); 869 870 end: 871 kfree(ctx->edid); 872 ctx->edid = (struct edid *)edid; 873 } 874 875 static void sii8620_set_upstream_edid(struct sii8620 *ctx) 876 { 877 sii8620_setbits(ctx, REG_DPD, BIT_DPD_PDNRX12 | BIT_DPD_PDIDCK_N 878 | BIT_DPD_PD_MHL_CLK_N, 0xff); 879 880 sii8620_write_seq_static(ctx, 881 REG_RX_HDMI_CTRL3, 0x00, 882 REG_PKT_FILTER_0, 0xFF, 883 REG_PKT_FILTER_1, 0xFF, 884 REG_ALICE0_BW_I2C, 0x06 885 ); 886 887 sii8620_setbits(ctx, REG_RX_HDMI_CLR_BUFFER, 888 BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN, 0xff); 889 890 sii8620_write_seq_static(ctx, 891 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 892 | BIT_EDID_CTRL_EDID_MODE_EN, 893 REG_EDID_FIFO_ADDR, 0, 894 ); 895 896 sii8620_write_buf(ctx, REG_EDID_FIFO_WR_DATA, (u8 *)ctx->edid, 897 (ctx->edid->extensions + 1) * EDID_LENGTH); 898 899 sii8620_write_seq_static(ctx, 900 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID 901 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 902 | BIT_EDID_CTRL_EDID_MODE_EN, 903 REG_INTR5_MASK, BIT_INTR_SCDT_CHANGE, 904 REG_INTR9_MASK, 0 905 ); 906 } 907 908 static void sii8620_xtal_set_rate(struct sii8620 *ctx) 909 { 910 static const struct { 911 unsigned int rate; 912 u8 div; 913 u8 tp1; 914 } rates[] = { 915 { 19200, 0x04, 0x53 }, 916 { 20000, 0x04, 0x62 }, 917 { 24000, 0x05, 0x75 }, 918 { 30000, 0x06, 0x92 }, 919 { 38400, 0x0c, 0xbc }, 920 }; 921 unsigned long rate = clk_get_rate(ctx->clk_xtal) / 1000; 922 int i; 923 924 for (i = 0; i < ARRAY_SIZE(rates) - 1; ++i) 925 if (rate <= rates[i].rate) 926 break; 927 928 if (rate != rates[i].rate) 929 dev_err(ctx->dev, "xtal clock rate(%lukHz) not supported, setting MHL for %ukHz.\n", 930 rate, rates[i].rate); 931 932 sii8620_write(ctx, REG_DIV_CTL_MAIN, rates[i].div); 933 sii8620_write(ctx, REG_HDCP2X_TP1, rates[i].tp1); 934 } 935 936 static int sii8620_hw_on(struct sii8620 *ctx) 937 { 938 int ret; 939 940 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 941 if (ret) 942 return ret; 943 944 usleep_range(10000, 20000); 945 ret = clk_prepare_enable(ctx->clk_xtal); 946 if (ret) 947 return ret; 948 949 msleep(100); 950 gpiod_set_value(ctx->gpio_reset, 0); 951 msleep(100); 952 953 return 0; 954 } 955 956 static int sii8620_hw_off(struct sii8620 *ctx) 957 { 958 clk_disable_unprepare(ctx->clk_xtal); 959 gpiod_set_value(ctx->gpio_reset, 1); 960 return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 961 } 962 963 static void sii8620_cbus_reset(struct sii8620 *ctx) 964 { 965 sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST 966 | BIT_PWD_SRST_CBUS_RST_SW_EN); 967 usleep_range(10000, 20000); 968 sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN); 969 } 970 971 static void sii8620_set_auto_zone(struct sii8620 *ctx) 972 { 973 if (ctx->mode != CM_MHL1) { 974 sii8620_write_seq_static(ctx, 975 REG_TX_ZONE_CTL1, 0x0, 976 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 977 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 978 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE 979 ); 980 } else { 981 sii8620_write_seq_static(ctx, 982 REG_TX_ZONE_CTL1, VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE, 983 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 984 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE 985 ); 986 } 987 } 988 989 static void sii8620_stop_video(struct sii8620 *ctx) 990 { 991 u8 uninitialized_var(val); 992 993 sii8620_write_seq_static(ctx, 994 REG_TPI_INTR_EN, 0, 995 REG_HDCP2X_INTR0_MASK, 0, 996 REG_TPI_COPP_DATA2, 0, 997 REG_TPI_INTR_ST0, ~0, 998 ); 999 1000 switch (ctx->sink_type) { 1001 case SINK_DVI: 1002 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN 1003 | BIT_TPI_SC_TPI_AV_MUTE; 1004 break; 1005 case SINK_HDMI: 1006 default: 1007 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN 1008 | BIT_TPI_SC_TPI_AV_MUTE 1009 | BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI; 1010 break; 1011 } 1012 1013 sii8620_write(ctx, REG_TPI_SC, val); 1014 } 1015 1016 static void sii8620_set_format(struct sii8620 *ctx) 1017 { 1018 u8 out_fmt; 1019 1020 if (sii8620_is_mhl3(ctx)) { 1021 sii8620_setbits(ctx, REG_M3_P0CTRL, 1022 BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED, 1023 ctx->use_packed_pixel ? ~0 : 0); 1024 } else { 1025 if (ctx->use_packed_pixel) { 1026 sii8620_write_seq_static(ctx, 1027 REG_VID_MODE, BIT_VID_MODE_M1080P, 1028 REG_MHL_TOP_CTL, BIT_MHL_TOP_CTL_MHL_PP_SEL | 1, 1029 REG_MHLTX_CTL6, 0x60 1030 ); 1031 } else { 1032 sii8620_write_seq_static(ctx, 1033 REG_VID_MODE, 0, 1034 REG_MHL_TOP_CTL, 1, 1035 REG_MHLTX_CTL6, 0xa0 1036 ); 1037 } 1038 } 1039 1040 if (ctx->use_packed_pixel) 1041 out_fmt = VAL_TPI_FORMAT(YCBCR422, FULL); 1042 else 1043 out_fmt = VAL_TPI_FORMAT(RGB, FULL); 1044 1045 sii8620_write_seq(ctx, 1046 REG_TPI_INPUT, VAL_TPI_FORMAT(RGB, FULL), 1047 REG_TPI_OUTPUT, out_fmt, 1048 ); 1049 } 1050 1051 static int mhl3_infoframe_init(struct mhl3_infoframe *frame) 1052 { 1053 memset(frame, 0, sizeof(*frame)); 1054 1055 frame->version = 3; 1056 frame->hev_format = -1; 1057 return 0; 1058 } 1059 1060 static ssize_t mhl3_infoframe_pack(struct mhl3_infoframe *frame, 1061 void *buffer, size_t size) 1062 { 1063 const int frm_len = HDMI_INFOFRAME_HEADER_SIZE + MHL3_INFOFRAME_SIZE; 1064 u8 *ptr = buffer; 1065 1066 if (size < frm_len) 1067 return -ENOSPC; 1068 1069 memset(buffer, 0, size); 1070 ptr[0] = HDMI_INFOFRAME_TYPE_VENDOR; 1071 ptr[1] = frame->version; 1072 ptr[2] = MHL3_INFOFRAME_SIZE; 1073 ptr[4] = MHL3_IEEE_OUI & 0xff; 1074 ptr[5] = (MHL3_IEEE_OUI >> 8) & 0xff; 1075 ptr[6] = (MHL3_IEEE_OUI >> 16) & 0xff; 1076 ptr[7] = frame->video_format & 0x3; 1077 ptr[7] |= (frame->format_type & 0x7) << 2; 1078 ptr[7] |= frame->sep_audio ? BIT(5) : 0; 1079 if (frame->hev_format >= 0) { 1080 ptr[9] = 1; 1081 ptr[10] = (frame->hev_format >> 8) & 0xff; 1082 ptr[11] = frame->hev_format & 0xff; 1083 } 1084 if (frame->av_delay) { 1085 bool sign = frame->av_delay < 0; 1086 int delay = sign ? -frame->av_delay : frame->av_delay; 1087 1088 ptr[12] = (delay >> 16) & 0xf; 1089 if (sign) 1090 ptr[12] |= BIT(4); 1091 ptr[13] = (delay >> 8) & 0xff; 1092 ptr[14] = delay & 0xff; 1093 } 1094 ptr[3] -= sii8620_checksum(buffer, frm_len); 1095 return frm_len; 1096 } 1097 1098 static void sii8620_set_infoframes(struct sii8620 *ctx, 1099 struct drm_display_mode *mode) 1100 { 1101 struct mhl3_infoframe mhl_frm; 1102 union hdmi_infoframe frm; 1103 u8 buf[31]; 1104 int ret; 1105 1106 ret = drm_hdmi_avi_infoframe_from_display_mode(&frm.avi, 1107 NULL, mode); 1108 if (ctx->use_packed_pixel) 1109 frm.avi.colorspace = HDMI_COLORSPACE_YUV422; 1110 1111 if (!ret) 1112 ret = hdmi_avi_infoframe_pack(&frm.avi, buf, ARRAY_SIZE(buf)); 1113 if (ret > 0) 1114 sii8620_write_buf(ctx, REG_TPI_AVI_CHSUM, buf + 3, ret - 3); 1115 1116 if (!sii8620_is_mhl3(ctx) || !ctx->use_packed_pixel) { 1117 sii8620_write(ctx, REG_TPI_SC, 1118 BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI); 1119 sii8620_write(ctx, REG_PKT_FILTER_0, 1120 BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT | 1121 BIT_PKT_FILTER_0_DROP_MPEG_PKT | 1122 BIT_PKT_FILTER_0_DROP_GCP_PKT, 1123 BIT_PKT_FILTER_1_DROP_GEN_PKT); 1124 return; 1125 } 1126 1127 sii8620_write(ctx, REG_PKT_FILTER_0, 1128 BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT | 1129 BIT_PKT_FILTER_0_DROP_MPEG_PKT | 1130 BIT_PKT_FILTER_0_DROP_AVI_PKT | 1131 BIT_PKT_FILTER_0_DROP_GCP_PKT, 1132 BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS | 1133 BIT_PKT_FILTER_1_DROP_GEN_PKT | 1134 BIT_PKT_FILTER_1_DROP_VSIF_PKT); 1135 1136 sii8620_write(ctx, REG_TPI_INFO_FSEL, BIT_TPI_INFO_FSEL_EN 1137 | BIT_TPI_INFO_FSEL_RPT | VAL_TPI_INFO_FSEL_VSI); 1138 ret = mhl3_infoframe_init(&mhl_frm); 1139 if (!ret) 1140 ret = mhl3_infoframe_pack(&mhl_frm, buf, ARRAY_SIZE(buf)); 1141 sii8620_write_buf(ctx, REG_TPI_INFO_B0, buf, ret); 1142 } 1143 1144 static void sii8620_start_video(struct sii8620 *ctx) 1145 { 1146 struct drm_display_mode *mode = 1147 &ctx->bridge.encoder->crtc->state->adjusted_mode; 1148 1149 if (!sii8620_is_mhl3(ctx)) 1150 sii8620_stop_video(ctx); 1151 1152 if (ctx->sink_type == SINK_DVI && !sii8620_is_mhl3(ctx)) { 1153 sii8620_write(ctx, REG_RX_HDMI_CTRL2, 1154 VAL_RX_HDMI_CTRL2_DEFVAL); 1155 sii8620_write(ctx, REG_TPI_SC, 0); 1156 return; 1157 } 1158 1159 sii8620_write_seq_static(ctx, 1160 REG_RX_HDMI_CTRL2, VAL_RX_HDMI_CTRL2_DEFVAL 1161 | BIT_RX_HDMI_CTRL2_USE_AV_MUTE, 1162 REG_VID_OVRRD, BIT_VID_OVRRD_PP_AUTO_DISABLE 1163 | BIT_VID_OVRRD_M1080P_OVRRD); 1164 sii8620_set_format(ctx); 1165 1166 if (!sii8620_is_mhl3(ctx)) { 1167 u8 link_mode = MHL_DST_LM_PATH_ENABLED; 1168 1169 if (ctx->use_packed_pixel) 1170 link_mode |= MHL_DST_LM_CLK_MODE_PACKED_PIXEL; 1171 else 1172 link_mode |= MHL_DST_LM_CLK_MODE_NORMAL; 1173 1174 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE), link_mode); 1175 sii8620_set_auto_zone(ctx); 1176 } else { 1177 static const struct { 1178 int max_clk; 1179 u8 zone; 1180 u8 link_rate; 1181 u8 rrp_decode; 1182 } clk_spec[] = { 1183 { 150000, VAL_TX_ZONE_CTL3_TX_ZONE_1_5GBPS, 1184 MHL_XDS_LINK_RATE_1_5_GBPS, 0x38 }, 1185 { 300000, VAL_TX_ZONE_CTL3_TX_ZONE_3GBPS, 1186 MHL_XDS_LINK_RATE_3_0_GBPS, 0x40 }, 1187 { 600000, VAL_TX_ZONE_CTL3_TX_ZONE_6GBPS, 1188 MHL_XDS_LINK_RATE_6_0_GBPS, 0x40 }, 1189 }; 1190 u8 p0_ctrl = BIT_M3_P0CTRL_MHL3_P0_PORT_EN; 1191 int clk = mode->clock * (ctx->use_packed_pixel ? 2 : 3); 1192 int i; 1193 1194 for (i = 0; i < ARRAY_SIZE(clk_spec) - 1; ++i) 1195 if (clk < clk_spec[i].max_clk) 1196 break; 1197 1198 if (100 * clk >= 98 * clk_spec[i].max_clk) 1199 p0_ctrl |= BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN; 1200 1201 sii8620_burst_tx_bits_per_pixel_fmt(ctx, ctx->use_packed_pixel); 1202 sii8620_burst_send(ctx); 1203 sii8620_write_seq(ctx, 1204 REG_MHL_DP_CTL0, 0xf0, 1205 REG_MHL3_TX_ZONE_CTL, clk_spec[i].zone); 1206 sii8620_setbits(ctx, REG_M3_P0CTRL, 1207 BIT_M3_P0CTRL_MHL3_P0_PORT_EN 1208 | BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN, p0_ctrl); 1209 sii8620_setbits(ctx, REG_M3_POSTM, MSK_M3_POSTM_RRP_DECODE, 1210 clk_spec[i].rrp_decode); 1211 sii8620_write_seq_static(ctx, 1212 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE 1213 | BIT_M3_CTRL_H2M_SWRST, 1214 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE 1215 ); 1216 sii8620_mt_write_stat(ctx, MHL_XDS_REG(AVLINK_MODE_CONTROL), 1217 clk_spec[i].link_rate); 1218 } 1219 1220 sii8620_set_infoframes(ctx, mode); 1221 } 1222 1223 static void sii8620_disable_hpd(struct sii8620 *ctx) 1224 { 1225 sii8620_setbits(ctx, REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID, 0); 1226 sii8620_write_seq_static(ctx, 1227 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN, 1228 REG_INTR8_MASK, 0 1229 ); 1230 } 1231 1232 static void sii8620_enable_hpd(struct sii8620 *ctx) 1233 { 1234 sii8620_setbits(ctx, REG_TMDS_CSTAT_P3, 1235 BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS 1236 | BIT_TMDS_CSTAT_P3_CLR_AVI, ~0); 1237 sii8620_write_seq_static(ctx, 1238 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN 1239 | BIT_HPD_CTRL_HPD_HIGH, 1240 ); 1241 } 1242 1243 static void sii8620_mhl_discover(struct sii8620 *ctx) 1244 { 1245 sii8620_write_seq_static(ctx, 1246 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1247 | BIT_DISC_CTRL9_DISC_PULSE_PROCEED, 1248 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_5K, VAL_PUP_20K), 1249 REG_CBUS_DISC_INTR0_MASK, BIT_MHL3_EST_INT 1250 | BIT_MHL_EST_INT 1251 | BIT_NOT_MHL_EST_INT 1252 | BIT_CBUS_MHL3_DISCON_INT 1253 | BIT_CBUS_MHL12_DISCON_INT 1254 | BIT_RGND_READY_INT, 1255 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 1256 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 1257 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE, 1258 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE 1259 | BIT_MHL_DP_CTL0_TX_OE_OVR, 1260 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE, 1261 REG_MHL_DP_CTL1, 0xA2, 1262 REG_MHL_DP_CTL2, 0x03, 1263 REG_MHL_DP_CTL3, 0x35, 1264 REG_MHL_DP_CTL5, 0x02, 1265 REG_MHL_DP_CTL6, 0x02, 1266 REG_MHL_DP_CTL7, 0x03, 1267 REG_COC_CTLC, 0xFF, 1268 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 1269 | BIT_DPD_OSC_EN | BIT_DPD_PWRON_HSIC, 1270 REG_COC_INTR_MASK, BIT_COC_PLL_LOCK_STATUS_CHANGE 1271 | BIT_COC_CALIBRATION_DONE, 1272 REG_CBUS_INT_1_MASK, BIT_CBUS_MSC_ABORT_RCVD 1273 | BIT_CBUS_CMD_ABORT, 1274 REG_CBUS_INT_0_MASK, BIT_CBUS_MSC_MT_DONE 1275 | BIT_CBUS_HPD_CHG 1276 | BIT_CBUS_MSC_MR_WRITE_STAT 1277 | BIT_CBUS_MSC_MR_MSC_MSG 1278 | BIT_CBUS_MSC_MR_WRITE_BURST 1279 | BIT_CBUS_MSC_MR_SET_INT 1280 | BIT_CBUS_MSC_MT_DONE_NACK 1281 ); 1282 } 1283 1284 static void sii8620_peer_specific_init(struct sii8620 *ctx) 1285 { 1286 if (sii8620_is_mhl3(ctx)) 1287 sii8620_write_seq_static(ctx, 1288 REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD, 1289 REG_EMSCINTRMASK1, 1290 BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR 1291 ); 1292 else 1293 sii8620_write_seq_static(ctx, 1294 REG_HDCP2X_INTR0_MASK, 0x00, 1295 REG_EMSCINTRMASK1, 0x00, 1296 REG_HDCP2X_INTR0, 0xFF, 1297 REG_INTR1, 0xFF, 1298 REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD 1299 | BIT_SYS_CTRL1_TX_CTRL_HDMI 1300 ); 1301 } 1302 1303 #define SII8620_MHL_VERSION 0x32 1304 #define SII8620_SCRATCHPAD_SIZE 16 1305 #define SII8620_INT_STAT_SIZE 0x33 1306 1307 static void sii8620_set_dev_cap(struct sii8620 *ctx) 1308 { 1309 static const u8 devcap[MHL_DCAP_SIZE] = { 1310 [MHL_DCAP_MHL_VERSION] = SII8620_MHL_VERSION, 1311 [MHL_DCAP_CAT] = MHL_DCAP_CAT_SOURCE | MHL_DCAP_CAT_POWER, 1312 [MHL_DCAP_ADOPTER_ID_H] = 0x01, 1313 [MHL_DCAP_ADOPTER_ID_L] = 0x41, 1314 [MHL_DCAP_VID_LINK_MODE] = MHL_DCAP_VID_LINK_RGB444 1315 | MHL_DCAP_VID_LINK_PPIXEL 1316 | MHL_DCAP_VID_LINK_16BPP, 1317 [MHL_DCAP_AUD_LINK_MODE] = MHL_DCAP_AUD_LINK_2CH, 1318 [MHL_DCAP_VIDEO_TYPE] = MHL_DCAP_VT_GRAPHICS, 1319 [MHL_DCAP_LOG_DEV_MAP] = MHL_DCAP_LD_GUI, 1320 [MHL_DCAP_BANDWIDTH] = 0x0f, 1321 [MHL_DCAP_FEATURE_FLAG] = MHL_DCAP_FEATURE_RCP_SUPPORT 1322 | MHL_DCAP_FEATURE_RAP_SUPPORT 1323 | MHL_DCAP_FEATURE_SP_SUPPORT, 1324 [MHL_DCAP_SCRATCHPAD_SIZE] = SII8620_SCRATCHPAD_SIZE, 1325 [MHL_DCAP_INT_STAT_SIZE] = SII8620_INT_STAT_SIZE, 1326 }; 1327 static const u8 xdcap[MHL_XDC_SIZE] = { 1328 [MHL_XDC_ECBUS_SPEEDS] = MHL_XDC_ECBUS_S_075 1329 | MHL_XDC_ECBUS_S_8BIT, 1330 [MHL_XDC_TMDS_SPEEDS] = MHL_XDC_TMDS_150 1331 | MHL_XDC_TMDS_300 | MHL_XDC_TMDS_600, 1332 [MHL_XDC_ECBUS_ROLES] = MHL_XDC_DEV_HOST, 1333 [MHL_XDC_LOG_DEV_MAPX] = MHL_XDC_LD_PHONE, 1334 }; 1335 1336 sii8620_write_buf(ctx, REG_MHL_DEVCAP_0, devcap, ARRAY_SIZE(devcap)); 1337 sii8620_write_buf(ctx, REG_MHL_EXTDEVCAP_0, xdcap, ARRAY_SIZE(xdcap)); 1338 } 1339 1340 static void sii8620_mhl_init(struct sii8620 *ctx) 1341 { 1342 sii8620_write_seq_static(ctx, 1343 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1344 REG_CBUS_MSC_COMPAT_CTRL, 1345 BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN, 1346 ); 1347 1348 sii8620_peer_specific_init(ctx); 1349 1350 sii8620_disable_hpd(ctx); 1351 1352 sii8620_write_seq_static(ctx, 1353 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO, 1354 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1355 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1356 REG_TMDS0_CCTRL1, 0x90, 1357 REG_TMDS_CLK_EN, 0x01, 1358 REG_TMDS_CH_EN, 0x11, 1359 REG_BGR_BIAS, 0x87, 1360 REG_ALICE0_ZONE_CTRL, 0xE8, 1361 REG_ALICE0_MODE_CTRL, 0x04, 1362 ); 1363 sii8620_setbits(ctx, REG_LM_DDC, BIT_LM_DDC_SW_TPI_EN_DISABLED, 0); 1364 sii8620_write_seq_static(ctx, 1365 REG_TPI_HW_OPT3, 0x76, 1366 REG_TMDS_CCTRL, BIT_TMDS_CCTRL_TMDS_OE, 1367 REG_TPI_DTD_B2, 79, 1368 ); 1369 sii8620_set_dev_cap(ctx); 1370 sii8620_write_seq_static(ctx, 1371 REG_MDT_XMIT_TIMEOUT, 100, 1372 REG_MDT_XMIT_CTRL, 0x03, 1373 REG_MDT_XFIFO_STAT, 0x00, 1374 REG_MDT_RCV_TIMEOUT, 100, 1375 REG_CBUS_LINK_CTRL_8, 0x1D, 1376 ); 1377 1378 sii8620_start_gen2_write_burst(ctx); 1379 sii8620_write_seq_static(ctx, 1380 REG_BIST_CTRL, 0x00, 1381 REG_COC_CTL1, 0x10, 1382 REG_COC_CTL2, 0x18, 1383 REG_COC_CTLF, 0x07, 1384 REG_COC_CTL11, 0xF8, 1385 REG_COC_CTL17, 0x61, 1386 REG_COC_CTL18, 0x46, 1387 REG_COC_CTL19, 0x15, 1388 REG_COC_CTL1A, 0x01, 1389 REG_MHL_COC_CTL3, BIT_MHL_COC_CTL3_COC_AECHO_EN, 1390 REG_MHL_COC_CTL4, 0x2D, 1391 REG_MHL_COC_CTL5, 0xF9, 1392 REG_MSC_HEARTBEAT_CTRL, 0x27, 1393 ); 1394 sii8620_disable_gen2_write_burst(ctx); 1395 1396 sii8620_mt_write_stat(ctx, MHL_DST_REG(VERSION), SII8620_MHL_VERSION); 1397 sii8620_mt_write_stat(ctx, MHL_DST_REG(CONNECTED_RDY), 1398 MHL_DST_CONN_DCAP_RDY | MHL_DST_CONN_XDEVCAPP_SUPP 1399 | MHL_DST_CONN_POW_STAT); 1400 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), MHL_INT_RC_DCAP_CHG); 1401 } 1402 1403 static void sii8620_emsc_enable(struct sii8620 *ctx) 1404 { 1405 u8 reg; 1406 1407 sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_EMSC_EN 1408 | BIT_GENCTL_CLR_EMSC_RFIFO 1409 | BIT_GENCTL_CLR_EMSC_XFIFO, ~0); 1410 sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_CLR_EMSC_RFIFO 1411 | BIT_GENCTL_CLR_EMSC_XFIFO, 0); 1412 sii8620_setbits(ctx, REG_COMMECNT, BIT_COMMECNT_I2C_TO_EMSC_EN, ~0); 1413 reg = sii8620_readb(ctx, REG_EMSCINTR); 1414 sii8620_write(ctx, REG_EMSCINTR, reg); 1415 sii8620_write(ctx, REG_EMSCINTRMASK, BIT_EMSCINTR_SPI_DVLD); 1416 } 1417 1418 static int sii8620_wait_for_fsm_state(struct sii8620 *ctx, u8 state) 1419 { 1420 int i; 1421 1422 for (i = 0; i < 10; ++i) { 1423 u8 s = sii8620_readb(ctx, REG_COC_STAT_0); 1424 1425 if ((s & MSK_COC_STAT_0_FSM_STATE) == state) 1426 return 0; 1427 if (!(s & BIT_COC_STAT_0_PLL_LOCKED)) 1428 return -EBUSY; 1429 usleep_range(4000, 6000); 1430 } 1431 return -ETIMEDOUT; 1432 } 1433 1434 static void sii8620_set_mode(struct sii8620 *ctx, enum sii8620_mode mode) 1435 { 1436 int ret; 1437 1438 if (ctx->mode == mode) 1439 return; 1440 1441 switch (mode) { 1442 case CM_MHL1: 1443 sii8620_write_seq_static(ctx, 1444 REG_CBUS_MSC_COMPAT_CTRL, 0x02, 1445 REG_M3_CTRL, VAL_M3_CTRL_MHL1_2_VALUE, 1446 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 1447 | BIT_DPD_OSC_EN, 1448 REG_COC_INTR_MASK, 0 1449 ); 1450 ctx->mode = mode; 1451 break; 1452 case CM_MHL3: 1453 sii8620_write(ctx, REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE); 1454 ctx->mode = mode; 1455 return; 1456 case CM_ECBUS_S: 1457 sii8620_emsc_enable(ctx); 1458 sii8620_write_seq_static(ctx, 1459 REG_TTXSPINUMS, 4, 1460 REG_TRXSPINUMS, 4, 1461 REG_TTXHSICNUMS, 0x14, 1462 REG_TRXHSICNUMS, 0x14, 1463 REG_TTXTOTNUMS, 0x18, 1464 REG_TRXTOTNUMS, 0x18, 1465 REG_PWD_SRST, BIT_PWD_SRST_COC_DOC_RST 1466 | BIT_PWD_SRST_CBUS_RST_SW_EN, 1467 REG_MHL_COC_CTL1, 0xbd, 1468 REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN, 1469 REG_COC_CTLB, 0x01, 1470 REG_COC_CTL0, 0x5c, 1471 REG_COC_CTL14, 0x03, 1472 REG_COC_CTL15, 0x80, 1473 REG_MHL_DP_CTL6, BIT_MHL_DP_CTL6_DP_TAP1_SGN 1474 | BIT_MHL_DP_CTL6_DP_TAP1_EN 1475 | BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN, 1476 REG_MHL_DP_CTL8, 0x03 1477 ); 1478 ret = sii8620_wait_for_fsm_state(ctx, 0x03); 1479 sii8620_write_seq_static(ctx, 1480 REG_COC_CTL14, 0x00, 1481 REG_COC_CTL15, 0x80 1482 ); 1483 if (!ret) 1484 sii8620_write(ctx, REG_CBUS3_CNVT, 0x85); 1485 else 1486 sii8620_disconnect(ctx); 1487 return; 1488 case CM_DISCONNECTED: 1489 ctx->mode = mode; 1490 break; 1491 default: 1492 dev_err(ctx->dev, "%s mode %d not supported\n", __func__, mode); 1493 break; 1494 } 1495 1496 sii8620_set_auto_zone(ctx); 1497 1498 if (mode != CM_MHL1) 1499 return; 1500 1501 sii8620_write_seq_static(ctx, 1502 REG_MHL_DP_CTL0, 0xBC, 1503 REG_MHL_DP_CTL1, 0xBB, 1504 REG_MHL_DP_CTL3, 0x48, 1505 REG_MHL_DP_CTL5, 0x39, 1506 REG_MHL_DP_CTL2, 0x2A, 1507 REG_MHL_DP_CTL6, 0x2A, 1508 REG_MHL_DP_CTL7, 0x08 1509 ); 1510 } 1511 1512 static void sii8620_hpd_unplugged(struct sii8620 *ctx) 1513 { 1514 sii8620_disable_hpd(ctx); 1515 ctx->sink_type = SINK_NONE; 1516 ctx->sink_detected = false; 1517 ctx->feature_complete = false; 1518 kfree(ctx->edid); 1519 ctx->edid = NULL; 1520 } 1521 1522 static void sii8620_disconnect(struct sii8620 *ctx) 1523 { 1524 sii8620_disable_gen2_write_burst(ctx); 1525 sii8620_stop_video(ctx); 1526 msleep(100); 1527 sii8620_cbus_reset(ctx); 1528 sii8620_set_mode(ctx, CM_DISCONNECTED); 1529 sii8620_write_seq_static(ctx, 1530 REG_TX_ZONE_CTL1, 0, 1531 REG_MHL_PLL_CTL0, 0x07, 1532 REG_COC_CTL0, 0x40, 1533 REG_CBUS3_CNVT, 0x84, 1534 REG_COC_CTL14, 0x00, 1535 REG_COC_CTL0, 0x40, 1536 REG_HRXCTRL3, 0x07, 1537 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 1538 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 1539 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE, 1540 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE 1541 | BIT_MHL_DP_CTL0_TX_OE_OVR, 1542 REG_MHL_DP_CTL1, 0xBB, 1543 REG_MHL_DP_CTL3, 0x48, 1544 REG_MHL_DP_CTL5, 0x3F, 1545 REG_MHL_DP_CTL2, 0x2F, 1546 REG_MHL_DP_CTL6, 0x2A, 1547 REG_MHL_DP_CTL7, 0x03 1548 ); 1549 sii8620_hpd_unplugged(ctx); 1550 sii8620_write_seq_static(ctx, 1551 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE, 1552 REG_MHL_COC_CTL1, 0x07, 1553 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1554 REG_DISC_CTRL8, 0x00, 1555 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1556 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1557 REG_INT_CTRL, 0x00, 1558 REG_MSC_HEARTBEAT_CTRL, 0x27, 1559 REG_DISC_CTRL1, 0x25, 1560 REG_CBUS_DISC_INTR0, (u8)~BIT_RGND_READY_INT, 1561 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT, 1562 REG_MDT_INT_1, 0xff, 1563 REG_MDT_INT_1_MASK, 0x00, 1564 REG_MDT_INT_0, 0xff, 1565 REG_MDT_INT_0_MASK, 0x00, 1566 REG_COC_INTR, 0xff, 1567 REG_COC_INTR_MASK, 0x00, 1568 REG_TRXINTH, 0xff, 1569 REG_TRXINTMH, 0x00, 1570 REG_CBUS_INT_0, 0xff, 1571 REG_CBUS_INT_0_MASK, 0x00, 1572 REG_CBUS_INT_1, 0xff, 1573 REG_CBUS_INT_1_MASK, 0x00, 1574 REG_EMSCINTR, 0xff, 1575 REG_EMSCINTRMASK, 0x00, 1576 REG_EMSCINTR1, 0xff, 1577 REG_EMSCINTRMASK1, 0x00, 1578 REG_INTR8, 0xff, 1579 REG_INTR8_MASK, 0x00, 1580 REG_TPI_INTR_ST0, 0xff, 1581 REG_TPI_INTR_EN, 0x00, 1582 REG_HDCP2X_INTR0, 0xff, 1583 REG_HDCP2X_INTR0_MASK, 0x00, 1584 REG_INTR9, 0xff, 1585 REG_INTR9_MASK, 0x00, 1586 REG_INTR3, 0xff, 1587 REG_INTR3_MASK, 0x00, 1588 REG_INTR5, 0xff, 1589 REG_INTR5_MASK, 0x00, 1590 REG_INTR2, 0xff, 1591 REG_INTR2_MASK, 0x00, 1592 ); 1593 memset(ctx->stat, 0, sizeof(ctx->stat)); 1594 memset(ctx->xstat, 0, sizeof(ctx->xstat)); 1595 memset(ctx->devcap, 0, sizeof(ctx->devcap)); 1596 memset(ctx->xdevcap, 0, sizeof(ctx->xdevcap)); 1597 ctx->devcap_read = false; 1598 ctx->cbus_status = 0; 1599 sii8620_mt_cleanup(ctx); 1600 } 1601 1602 static void sii8620_mhl_disconnected(struct sii8620 *ctx) 1603 { 1604 sii8620_write_seq_static(ctx, 1605 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1606 REG_CBUS_MSC_COMPAT_CTRL, 1607 BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN 1608 ); 1609 sii8620_disconnect(ctx); 1610 } 1611 1612 static void sii8620_irq_disc(struct sii8620 *ctx) 1613 { 1614 u8 stat = sii8620_readb(ctx, REG_CBUS_DISC_INTR0); 1615 1616 if (stat & VAL_CBUS_MHL_DISCON) 1617 sii8620_mhl_disconnected(ctx); 1618 1619 if (stat & BIT_RGND_READY_INT) { 1620 u8 stat2 = sii8620_readb(ctx, REG_DISC_STAT2); 1621 1622 if ((stat2 & MSK_DISC_STAT2_RGND) == VAL_RGND_1K) { 1623 sii8620_mhl_discover(ctx); 1624 } else { 1625 sii8620_write_seq_static(ctx, 1626 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1627 | BIT_DISC_CTRL9_NOMHL_EST 1628 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1629 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT 1630 | BIT_CBUS_MHL3_DISCON_INT 1631 | BIT_CBUS_MHL12_DISCON_INT 1632 | BIT_NOT_MHL_EST_INT 1633 ); 1634 } 1635 } 1636 if (stat & BIT_MHL_EST_INT) 1637 sii8620_mhl_init(ctx); 1638 1639 sii8620_write(ctx, REG_CBUS_DISC_INTR0, stat); 1640 } 1641 1642 static void sii8620_read_burst(struct sii8620 *ctx) 1643 { 1644 u8 buf[17]; 1645 1646 sii8620_read_buf(ctx, REG_MDT_RCV_READ_PORT, buf, ARRAY_SIZE(buf)); 1647 sii8620_write(ctx, REG_MDT_RCV_CTRL, BIT_MDT_RCV_CTRL_MDT_RCV_EN | 1648 BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN | 1649 BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR); 1650 sii8620_readb(ctx, REG_MDT_RFIFO_STAT); 1651 } 1652 1653 static void sii8620_irq_g2wb(struct sii8620 *ctx) 1654 { 1655 u8 stat = sii8620_readb(ctx, REG_MDT_INT_0); 1656 1657 if (stat & BIT_MDT_IDLE_AFTER_HAWB_DISABLE) 1658 if (sii8620_is_mhl3(ctx)) 1659 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), 1660 MHL_INT_RC_FEAT_COMPLETE); 1661 1662 if (stat & BIT_MDT_RFIFO_DATA_RDY) 1663 sii8620_read_burst(ctx); 1664 1665 if (stat & BIT_MDT_XFIFO_EMPTY) 1666 sii8620_write(ctx, REG_MDT_XMIT_CTRL, 0); 1667 1668 sii8620_write(ctx, REG_MDT_INT_0, stat); 1669 } 1670 1671 static void sii8620_status_dcap_ready(struct sii8620 *ctx) 1672 { 1673 enum sii8620_mode mode; 1674 1675 mode = ctx->stat[MHL_DST_VERSION] >= 0x30 ? CM_MHL3 : CM_MHL1; 1676 if (mode > ctx->mode) 1677 sii8620_set_mode(ctx, mode); 1678 sii8620_peer_specific_init(ctx); 1679 sii8620_write(ctx, REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE 1680 | BIT_INTR9_EDID_DONE | BIT_INTR9_EDID_ERROR); 1681 } 1682 1683 static void sii8620_status_changed_path(struct sii8620 *ctx) 1684 { 1685 u8 link_mode; 1686 1687 if (ctx->use_packed_pixel) 1688 link_mode = MHL_DST_LM_CLK_MODE_PACKED_PIXEL; 1689 else 1690 link_mode = MHL_DST_LM_CLK_MODE_NORMAL; 1691 1692 if (ctx->stat[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED) 1693 link_mode |= MHL_DST_LM_PATH_ENABLED; 1694 1695 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE), 1696 link_mode); 1697 } 1698 1699 static void sii8620_msc_mr_write_stat(struct sii8620 *ctx) 1700 { 1701 u8 st[MHL_DST_SIZE], xst[MHL_XDS_SIZE]; 1702 1703 sii8620_read_buf(ctx, REG_MHL_STAT_0, st, MHL_DST_SIZE); 1704 sii8620_read_buf(ctx, REG_MHL_EXTSTAT_0, xst, MHL_XDS_SIZE); 1705 1706 sii8620_update_array(ctx->stat, st, MHL_DST_SIZE); 1707 sii8620_update_array(ctx->xstat, xst, MHL_XDS_SIZE); 1708 1709 if (ctx->stat[MHL_DST_CONNECTED_RDY] & st[MHL_DST_CONNECTED_RDY] & 1710 MHL_DST_CONN_DCAP_RDY) { 1711 sii8620_status_dcap_ready(ctx); 1712 1713 if (!sii8620_is_mhl3(ctx)) 1714 sii8620_mt_read_devcap(ctx, false); 1715 } 1716 1717 if (st[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED) 1718 sii8620_status_changed_path(ctx); 1719 } 1720 1721 static void sii8620_ecbus_up(struct sii8620 *ctx, int ret) 1722 { 1723 if (ret < 0) 1724 return; 1725 1726 sii8620_set_mode(ctx, CM_ECBUS_S); 1727 } 1728 1729 static void sii8620_got_ecbus_speed(struct sii8620 *ctx, int ret) 1730 { 1731 if (ret < 0) 1732 return; 1733 1734 sii8620_mt_write_stat(ctx, MHL_XDS_REG(CURR_ECBUS_MODE), 1735 MHL_XDS_ECBUS_S | MHL_XDS_SLOT_MODE_8BIT); 1736 sii8620_mt_rap(ctx, MHL_RAP_CBUS_MODE_UP); 1737 sii8620_mt_set_cont(ctx, sii8620_ecbus_up); 1738 } 1739 1740 static void sii8620_mhl_burst_emsc_support_set(struct mhl_burst_emsc_support *d, 1741 enum mhl_burst_id id) 1742 { 1743 sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_EMSC_SUPPORT); 1744 d->num_entries = 1; 1745 d->burst_id[0] = cpu_to_be16(id); 1746 } 1747 1748 static void sii8620_send_features(struct sii8620 *ctx) 1749 { 1750 u8 buf[16]; 1751 1752 sii8620_write(ctx, REG_MDT_XMIT_CTRL, BIT_MDT_XMIT_CTRL_EN 1753 | BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN); 1754 sii8620_mhl_burst_emsc_support_set((void *)buf, 1755 MHL_BURST_ID_HID_PAYLOAD); 1756 sii8620_write_buf(ctx, REG_MDT_XMIT_WRITE_PORT, buf, ARRAY_SIZE(buf)); 1757 } 1758 1759 static bool sii8620_rcp_consume(struct sii8620 *ctx, u8 scancode) 1760 { 1761 bool pressed = !(scancode & MHL_RCP_KEY_RELEASED_MASK); 1762 1763 scancode &= MHL_RCP_KEY_ID_MASK; 1764 1765 if (!ctx->rc_dev) { 1766 dev_dbg(ctx->dev, "RCP input device not initialized\n"); 1767 return false; 1768 } 1769 1770 if (pressed) 1771 rc_keydown(ctx->rc_dev, RC_PROTO_CEC, scancode, 0); 1772 else 1773 rc_keyup(ctx->rc_dev); 1774 1775 return true; 1776 } 1777 1778 static void sii8620_msc_mr_set_int(struct sii8620 *ctx) 1779 { 1780 u8 ints[MHL_INT_SIZE]; 1781 1782 sii8620_read_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE); 1783 sii8620_write_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE); 1784 1785 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_DCAP_CHG) { 1786 switch (ctx->mode) { 1787 case CM_MHL3: 1788 sii8620_mt_read_xdevcap_reg(ctx, MHL_XDC_ECBUS_SPEEDS); 1789 sii8620_mt_set_cont(ctx, sii8620_got_ecbus_speed); 1790 break; 1791 case CM_ECBUS_S: 1792 sii8620_mt_read_devcap(ctx, true); 1793 break; 1794 default: 1795 break; 1796 } 1797 } 1798 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_REQ) 1799 sii8620_send_features(ctx); 1800 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_COMPLETE) { 1801 ctx->feature_complete = true; 1802 if (ctx->edid) 1803 sii8620_enable_hpd(ctx); 1804 } 1805 } 1806 1807 static struct sii8620_mt_msg *sii8620_msc_msg_first(struct sii8620 *ctx) 1808 { 1809 struct device *dev = ctx->dev; 1810 1811 if (list_empty(&ctx->mt_queue)) { 1812 dev_err(dev, "unexpected MSC MT response\n"); 1813 return NULL; 1814 } 1815 1816 return list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 1817 } 1818 1819 static void sii8620_msc_mt_done(struct sii8620 *ctx) 1820 { 1821 struct sii8620_mt_msg *msg = sii8620_msc_msg_first(ctx); 1822 1823 if (!msg) 1824 return; 1825 1826 msg->ret = sii8620_readb(ctx, REG_MSC_MT_RCVD_DATA0); 1827 ctx->mt_state = MT_STATE_DONE; 1828 } 1829 1830 static void sii8620_msc_mr_msc_msg(struct sii8620 *ctx) 1831 { 1832 struct sii8620_mt_msg *msg; 1833 u8 buf[2]; 1834 1835 sii8620_read_buf(ctx, REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA, buf, 2); 1836 1837 switch (buf[0]) { 1838 case MHL_MSC_MSG_RAPK: 1839 msg = sii8620_msc_msg_first(ctx); 1840 if (!msg) 1841 return; 1842 msg->ret = buf[1]; 1843 ctx->mt_state = MT_STATE_DONE; 1844 break; 1845 case MHL_MSC_MSG_RCP: 1846 if (!sii8620_rcp_consume(ctx, buf[1])) 1847 sii8620_mt_rcpe(ctx, 1848 MHL_RCPE_STATUS_INEFFECTIVE_KEY_CODE); 1849 sii8620_mt_rcpk(ctx, buf[1]); 1850 break; 1851 default: 1852 dev_err(ctx->dev, "%s message type %d,%d not supported", 1853 __func__, buf[0], buf[1]); 1854 } 1855 } 1856 1857 static void sii8620_irq_msc(struct sii8620 *ctx) 1858 { 1859 u8 stat = sii8620_readb(ctx, REG_CBUS_INT_0); 1860 1861 if (stat & ~BIT_CBUS_HPD_CHG) 1862 sii8620_write(ctx, REG_CBUS_INT_0, stat & ~BIT_CBUS_HPD_CHG); 1863 1864 if (stat & BIT_CBUS_HPD_CHG) { 1865 u8 cbus_stat = sii8620_readb(ctx, REG_CBUS_STATUS); 1866 1867 if ((cbus_stat ^ ctx->cbus_status) & BIT_CBUS_STATUS_CBUS_HPD) { 1868 sii8620_write(ctx, REG_CBUS_INT_0, BIT_CBUS_HPD_CHG); 1869 } else { 1870 stat ^= BIT_CBUS_STATUS_CBUS_HPD; 1871 cbus_stat ^= BIT_CBUS_STATUS_CBUS_HPD; 1872 } 1873 ctx->cbus_status = cbus_stat; 1874 } 1875 1876 if (stat & BIT_CBUS_MSC_MR_WRITE_STAT) 1877 sii8620_msc_mr_write_stat(ctx); 1878 1879 if (stat & BIT_CBUS_HPD_CHG) { 1880 if (ctx->cbus_status & BIT_CBUS_STATUS_CBUS_HPD) { 1881 ctx->sink_detected = true; 1882 sii8620_identify_sink(ctx); 1883 } else { 1884 sii8620_hpd_unplugged(ctx); 1885 } 1886 } 1887 1888 if (stat & BIT_CBUS_MSC_MR_SET_INT) 1889 sii8620_msc_mr_set_int(ctx); 1890 1891 if (stat & BIT_CBUS_MSC_MT_DONE) 1892 sii8620_msc_mt_done(ctx); 1893 1894 if (stat & BIT_CBUS_MSC_MR_MSC_MSG) 1895 sii8620_msc_mr_msc_msg(ctx); 1896 } 1897 1898 static void sii8620_irq_coc(struct sii8620 *ctx) 1899 { 1900 u8 stat = sii8620_readb(ctx, REG_COC_INTR); 1901 1902 if (stat & BIT_COC_CALIBRATION_DONE) { 1903 u8 cstat = sii8620_readb(ctx, REG_COC_STAT_0); 1904 1905 cstat &= BIT_COC_STAT_0_PLL_LOCKED | MSK_COC_STAT_0_FSM_STATE; 1906 if (cstat == (BIT_COC_STAT_0_PLL_LOCKED | 0x02)) { 1907 sii8620_write_seq_static(ctx, 1908 REG_COC_CTLB, 0, 1909 REG_TRXINTMH, BIT_TDM_INTR_SYNC_DATA 1910 | BIT_TDM_INTR_SYNC_WAIT 1911 ); 1912 } 1913 } 1914 1915 sii8620_write(ctx, REG_COC_INTR, stat); 1916 } 1917 1918 static void sii8620_irq_merr(struct sii8620 *ctx) 1919 { 1920 u8 stat = sii8620_readb(ctx, REG_CBUS_INT_1); 1921 1922 sii8620_write(ctx, REG_CBUS_INT_1, stat); 1923 } 1924 1925 static void sii8620_irq_edid(struct sii8620 *ctx) 1926 { 1927 u8 stat = sii8620_readb(ctx, REG_INTR9); 1928 1929 sii8620_write(ctx, REG_INTR9, stat); 1930 1931 if (stat & BIT_INTR9_DEVCAP_DONE) 1932 ctx->mt_state = MT_STATE_DONE; 1933 } 1934 1935 static void sii8620_irq_scdt(struct sii8620 *ctx) 1936 { 1937 u8 stat = sii8620_readb(ctx, REG_INTR5); 1938 1939 if (stat & BIT_INTR_SCDT_CHANGE) { 1940 u8 cstat = sii8620_readb(ctx, REG_TMDS_CSTAT_P3); 1941 1942 if (cstat & BIT_TMDS_CSTAT_P3_SCDT) 1943 sii8620_start_video(ctx); 1944 } 1945 1946 sii8620_write(ctx, REG_INTR5, stat); 1947 } 1948 1949 static void sii8620_got_xdevcap(struct sii8620 *ctx, int ret) 1950 { 1951 if (ret < 0) 1952 return; 1953 1954 sii8620_mt_read_devcap(ctx, false); 1955 } 1956 1957 static void sii8620_irq_tdm(struct sii8620 *ctx) 1958 { 1959 u8 stat = sii8620_readb(ctx, REG_TRXINTH); 1960 u8 tdm = sii8620_readb(ctx, REG_TRXSTA2); 1961 1962 if ((tdm & MSK_TDM_SYNCHRONIZED) == VAL_TDM_SYNCHRONIZED) { 1963 ctx->mode = CM_ECBUS_S; 1964 ctx->burst.rx_ack = 0; 1965 ctx->burst.r_size = SII8620_BURST_BUF_LEN; 1966 sii8620_burst_tx_rbuf_info(ctx, SII8620_BURST_BUF_LEN); 1967 sii8620_mt_read_devcap(ctx, true); 1968 sii8620_mt_set_cont(ctx, sii8620_got_xdevcap); 1969 } else { 1970 sii8620_write_seq_static(ctx, 1971 REG_MHL_PLL_CTL2, 0, 1972 REG_MHL_PLL_CTL2, BIT_MHL_PLL_CTL2_CLKDETECT_EN 1973 ); 1974 } 1975 1976 sii8620_write(ctx, REG_TRXINTH, stat); 1977 } 1978 1979 static void sii8620_irq_block(struct sii8620 *ctx) 1980 { 1981 u8 stat = sii8620_readb(ctx, REG_EMSCINTR); 1982 1983 if (stat & BIT_EMSCINTR_SPI_DVLD) { 1984 u8 bstat = sii8620_readb(ctx, REG_SPIBURSTSTAT); 1985 1986 if (bstat & BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE) 1987 sii8620_burst_receive(ctx); 1988 } 1989 1990 sii8620_write(ctx, REG_EMSCINTR, stat); 1991 } 1992 1993 static void sii8620_irq_ddc(struct sii8620 *ctx) 1994 { 1995 u8 stat = sii8620_readb(ctx, REG_INTR3); 1996 1997 if (stat & BIT_DDC_CMD_DONE) { 1998 sii8620_write(ctx, REG_INTR3_MASK, 0); 1999 if (sii8620_is_mhl3(ctx) && !ctx->feature_complete) 2000 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), 2001 MHL_INT_RC_FEAT_REQ); 2002 else 2003 sii8620_enable_hpd(ctx); 2004 } 2005 sii8620_write(ctx, REG_INTR3, stat); 2006 } 2007 2008 /* endian agnostic, non-volatile version of test_bit */ 2009 static bool sii8620_test_bit(unsigned int nr, const u8 *addr) 2010 { 2011 return 1 & (addr[nr / BITS_PER_BYTE] >> (nr % BITS_PER_BYTE)); 2012 } 2013 2014 static irqreturn_t sii8620_irq_thread(int irq, void *data) 2015 { 2016 static const struct { 2017 int bit; 2018 void (*handler)(struct sii8620 *ctx); 2019 } irq_vec[] = { 2020 { BIT_FAST_INTR_STAT_DISC, sii8620_irq_disc }, 2021 { BIT_FAST_INTR_STAT_G2WB, sii8620_irq_g2wb }, 2022 { BIT_FAST_INTR_STAT_COC, sii8620_irq_coc }, 2023 { BIT_FAST_INTR_STAT_TDM, sii8620_irq_tdm }, 2024 { BIT_FAST_INTR_STAT_MSC, sii8620_irq_msc }, 2025 { BIT_FAST_INTR_STAT_MERR, sii8620_irq_merr }, 2026 { BIT_FAST_INTR_STAT_BLOCK, sii8620_irq_block }, 2027 { BIT_FAST_INTR_STAT_EDID, sii8620_irq_edid }, 2028 { BIT_FAST_INTR_STAT_DDC, sii8620_irq_ddc }, 2029 { BIT_FAST_INTR_STAT_SCDT, sii8620_irq_scdt }, 2030 }; 2031 struct sii8620 *ctx = data; 2032 u8 stats[LEN_FAST_INTR_STAT]; 2033 int i, ret; 2034 2035 mutex_lock(&ctx->lock); 2036 2037 sii8620_read_buf(ctx, REG_FAST_INTR_STAT, stats, ARRAY_SIZE(stats)); 2038 for (i = 0; i < ARRAY_SIZE(irq_vec); ++i) 2039 if (sii8620_test_bit(irq_vec[i].bit, stats)) 2040 irq_vec[i].handler(ctx); 2041 2042 sii8620_burst_rx_all(ctx); 2043 sii8620_mt_work(ctx); 2044 sii8620_burst_send(ctx); 2045 2046 ret = sii8620_clear_error(ctx); 2047 if (ret) { 2048 dev_err(ctx->dev, "Error during IRQ handling, %d.\n", ret); 2049 sii8620_mhl_disconnected(ctx); 2050 } 2051 mutex_unlock(&ctx->lock); 2052 2053 return IRQ_HANDLED; 2054 } 2055 2056 static void sii8620_cable_in(struct sii8620 *ctx) 2057 { 2058 struct device *dev = ctx->dev; 2059 u8 ver[5]; 2060 int ret; 2061 2062 ret = sii8620_hw_on(ctx); 2063 if (ret) { 2064 dev_err(dev, "Error powering on, %d.\n", ret); 2065 return; 2066 } 2067 2068 sii8620_read_buf(ctx, REG_VND_IDL, ver, ARRAY_SIZE(ver)); 2069 ret = sii8620_clear_error(ctx); 2070 if (ret) { 2071 dev_err(dev, "Error accessing I2C bus, %d.\n", ret); 2072 return; 2073 } 2074 2075 dev_info(dev, "ChipID %02x%02x:%02x%02x rev %02x.\n", ver[1], ver[0], 2076 ver[3], ver[2], ver[4]); 2077 2078 sii8620_write(ctx, REG_DPD, 2079 BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN); 2080 2081 sii8620_xtal_set_rate(ctx); 2082 sii8620_disconnect(ctx); 2083 2084 sii8620_write_seq_static(ctx, 2085 REG_MHL_CBUS_CTL0, VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONG 2086 | VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_734, 2087 REG_MHL_CBUS_CTL1, VAL_MHL_CBUS_CTL1_1115_OHM, 2088 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN, 2089 ); 2090 2091 ret = sii8620_clear_error(ctx); 2092 if (ret) { 2093 dev_err(dev, "Error accessing I2C bus, %d.\n", ret); 2094 return; 2095 } 2096 2097 enable_irq(to_i2c_client(ctx->dev)->irq); 2098 } 2099 2100 static void sii8620_init_rcp_input_dev(struct sii8620 *ctx) 2101 { 2102 struct rc_dev *rc_dev; 2103 int ret; 2104 2105 rc_dev = rc_allocate_device(RC_DRIVER_SCANCODE); 2106 if (!rc_dev) { 2107 dev_err(ctx->dev, "Failed to allocate RC device\n"); 2108 ctx->error = -ENOMEM; 2109 return; 2110 } 2111 2112 rc_dev->input_phys = "sii8620/input0"; 2113 rc_dev->input_id.bustype = BUS_VIRTUAL; 2114 rc_dev->map_name = RC_MAP_CEC; 2115 rc_dev->allowed_protocols = RC_PROTO_BIT_CEC; 2116 rc_dev->driver_name = "sii8620"; 2117 rc_dev->device_name = "sii8620"; 2118 2119 ret = rc_register_device(rc_dev); 2120 2121 if (ret) { 2122 dev_err(ctx->dev, "Failed to register RC device\n"); 2123 ctx->error = ret; 2124 rc_free_device(ctx->rc_dev); 2125 return; 2126 } 2127 ctx->rc_dev = rc_dev; 2128 } 2129 2130 static void sii8620_cable_out(struct sii8620 *ctx) 2131 { 2132 disable_irq(to_i2c_client(ctx->dev)->irq); 2133 sii8620_hw_off(ctx); 2134 } 2135 2136 static void sii8620_extcon_work(struct work_struct *work) 2137 { 2138 struct sii8620 *ctx = 2139 container_of(work, struct sii8620, extcon_wq); 2140 int state = extcon_get_state(ctx->extcon, EXTCON_DISP_MHL); 2141 2142 if (state == ctx->cable_state) 2143 return; 2144 2145 ctx->cable_state = state; 2146 2147 if (state > 0) 2148 sii8620_cable_in(ctx); 2149 else 2150 sii8620_cable_out(ctx); 2151 } 2152 2153 static int sii8620_extcon_notifier(struct notifier_block *self, 2154 unsigned long event, void *ptr) 2155 { 2156 struct sii8620 *ctx = 2157 container_of(self, struct sii8620, extcon_nb); 2158 2159 schedule_work(&ctx->extcon_wq); 2160 2161 return NOTIFY_DONE; 2162 } 2163 2164 static int sii8620_extcon_init(struct sii8620 *ctx) 2165 { 2166 struct extcon_dev *edev; 2167 struct device_node *musb, *muic; 2168 int ret; 2169 2170 /* get micro-USB connector node */ 2171 musb = of_graph_get_remote_node(ctx->dev->of_node, 1, -1); 2172 /* next get micro-USB Interface Controller node */ 2173 muic = of_get_next_parent(musb); 2174 2175 if (!muic) { 2176 dev_info(ctx->dev, "no extcon found, switching to 'always on' mode\n"); 2177 return 0; 2178 } 2179 2180 edev = extcon_find_edev_by_node(muic); 2181 of_node_put(muic); 2182 if (IS_ERR(edev)) { 2183 if (PTR_ERR(edev) == -EPROBE_DEFER) 2184 return -EPROBE_DEFER; 2185 dev_err(ctx->dev, "Invalid or missing extcon\n"); 2186 return PTR_ERR(edev); 2187 } 2188 2189 ctx->extcon = edev; 2190 ctx->extcon_nb.notifier_call = sii8620_extcon_notifier; 2191 INIT_WORK(&ctx->extcon_wq, sii8620_extcon_work); 2192 ret = extcon_register_notifier(edev, EXTCON_DISP_MHL, &ctx->extcon_nb); 2193 if (ret) { 2194 dev_err(ctx->dev, "failed to register notifier for MHL\n"); 2195 return ret; 2196 } 2197 2198 return 0; 2199 } 2200 2201 static inline struct sii8620 *bridge_to_sii8620(struct drm_bridge *bridge) 2202 { 2203 return container_of(bridge, struct sii8620, bridge); 2204 } 2205 2206 static int sii8620_attach(struct drm_bridge *bridge) 2207 { 2208 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2209 2210 sii8620_init_rcp_input_dev(ctx); 2211 2212 return sii8620_clear_error(ctx); 2213 } 2214 2215 static void sii8620_detach(struct drm_bridge *bridge) 2216 { 2217 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2218 2219 rc_unregister_device(ctx->rc_dev); 2220 } 2221 2222 static int sii8620_is_packing_required(struct sii8620 *ctx, 2223 const struct drm_display_mode *mode) 2224 { 2225 int max_pclk, max_pclk_pp_mode; 2226 2227 if (sii8620_is_mhl3(ctx)) { 2228 max_pclk = MHL3_MAX_PCLK; 2229 max_pclk_pp_mode = MHL3_MAX_PCLK_PP_MODE; 2230 } else { 2231 max_pclk = MHL1_MAX_PCLK; 2232 max_pclk_pp_mode = MHL1_MAX_PCLK_PP_MODE; 2233 } 2234 2235 if (mode->clock < max_pclk) 2236 return 0; 2237 else if (mode->clock < max_pclk_pp_mode) 2238 return 1; 2239 else 2240 return -1; 2241 } 2242 2243 static enum drm_mode_status sii8620_mode_valid(struct drm_bridge *bridge, 2244 const struct drm_display_mode *mode) 2245 { 2246 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2247 int pack_required = sii8620_is_packing_required(ctx, mode); 2248 bool can_pack = ctx->devcap[MHL_DCAP_VID_LINK_MODE] & 2249 MHL_DCAP_VID_LINK_PPIXEL; 2250 2251 switch (pack_required) { 2252 case 0: 2253 return MODE_OK; 2254 case 1: 2255 return (can_pack) ? MODE_OK : MODE_CLOCK_HIGH; 2256 default: 2257 return MODE_CLOCK_HIGH; 2258 } 2259 } 2260 2261 static bool sii8620_mode_fixup(struct drm_bridge *bridge, 2262 const struct drm_display_mode *mode, 2263 struct drm_display_mode *adjusted_mode) 2264 { 2265 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2266 2267 mutex_lock(&ctx->lock); 2268 2269 ctx->use_packed_pixel = sii8620_is_packing_required(ctx, adjusted_mode); 2270 2271 mutex_unlock(&ctx->lock); 2272 2273 return true; 2274 } 2275 2276 static const struct drm_bridge_funcs sii8620_bridge_funcs = { 2277 .attach = sii8620_attach, 2278 .detach = sii8620_detach, 2279 .mode_fixup = sii8620_mode_fixup, 2280 .mode_valid = sii8620_mode_valid, 2281 }; 2282 2283 static int sii8620_probe(struct i2c_client *client, 2284 const struct i2c_device_id *id) 2285 { 2286 struct device *dev = &client->dev; 2287 struct sii8620 *ctx; 2288 int ret; 2289 2290 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 2291 if (!ctx) 2292 return -ENOMEM; 2293 2294 ctx->dev = dev; 2295 mutex_init(&ctx->lock); 2296 INIT_LIST_HEAD(&ctx->mt_queue); 2297 2298 ctx->clk_xtal = devm_clk_get(dev, "xtal"); 2299 if (IS_ERR(ctx->clk_xtal)) { 2300 dev_err(dev, "failed to get xtal clock from DT\n"); 2301 return PTR_ERR(ctx->clk_xtal); 2302 } 2303 2304 if (!client->irq) { 2305 dev_err(dev, "no irq provided\n"); 2306 return -EINVAL; 2307 } 2308 irq_set_status_flags(client->irq, IRQ_NOAUTOEN); 2309 ret = devm_request_threaded_irq(dev, client->irq, NULL, 2310 sii8620_irq_thread, 2311 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 2312 "sii8620", ctx); 2313 if (ret < 0) { 2314 dev_err(dev, "failed to install IRQ handler\n"); 2315 return ret; 2316 } 2317 2318 ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); 2319 if (IS_ERR(ctx->gpio_reset)) { 2320 dev_err(dev, "failed to get reset gpio from DT\n"); 2321 return PTR_ERR(ctx->gpio_reset); 2322 } 2323 2324 ctx->supplies[0].supply = "cvcc10"; 2325 ctx->supplies[1].supply = "iovcc18"; 2326 ret = devm_regulator_bulk_get(dev, 2, ctx->supplies); 2327 if (ret) 2328 return ret; 2329 2330 ret = sii8620_extcon_init(ctx); 2331 if (ret < 0) { 2332 dev_err(ctx->dev, "failed to initialize EXTCON\n"); 2333 return ret; 2334 } 2335 2336 i2c_set_clientdata(client, ctx); 2337 2338 ctx->bridge.funcs = &sii8620_bridge_funcs; 2339 ctx->bridge.of_node = dev->of_node; 2340 drm_bridge_add(&ctx->bridge); 2341 2342 if (!ctx->extcon) 2343 sii8620_cable_in(ctx); 2344 2345 return 0; 2346 } 2347 2348 static int sii8620_remove(struct i2c_client *client) 2349 { 2350 struct sii8620 *ctx = i2c_get_clientdata(client); 2351 2352 if (ctx->extcon) { 2353 extcon_unregister_notifier(ctx->extcon, EXTCON_DISP_MHL, 2354 &ctx->extcon_nb); 2355 flush_work(&ctx->extcon_wq); 2356 if (ctx->cable_state > 0) 2357 sii8620_cable_out(ctx); 2358 } else { 2359 sii8620_cable_out(ctx); 2360 } 2361 drm_bridge_remove(&ctx->bridge); 2362 2363 return 0; 2364 } 2365 2366 static const struct of_device_id sii8620_dt_match[] = { 2367 { .compatible = "sil,sii8620" }, 2368 { }, 2369 }; 2370 MODULE_DEVICE_TABLE(of, sii8620_dt_match); 2371 2372 static const struct i2c_device_id sii8620_id[] = { 2373 { "sii8620", 0 }, 2374 { }, 2375 }; 2376 2377 MODULE_DEVICE_TABLE(i2c, sii8620_id); 2378 static struct i2c_driver sii8620_driver = { 2379 .driver = { 2380 .name = "sii8620", 2381 .of_match_table = of_match_ptr(sii8620_dt_match), 2382 }, 2383 .probe = sii8620_probe, 2384 .remove = sii8620_remove, 2385 .id_table = sii8620_id, 2386 }; 2387 2388 module_i2c_driver(sii8620_driver); 2389 MODULE_LICENSE("GPL v2"); 2390