1 /* 2 * Silicon Image SiI8620 HDMI/MHL bridge driver 3 * 4 * Copyright (C) 2015, Samsung Electronics Co., Ltd. 5 * Andrzej Hajda <a.hajda@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <asm/unaligned.h> 13 14 #include <drm/bridge/mhl.h> 15 #include <drm/drm_crtc.h> 16 #include <drm/drm_edid.h> 17 18 #include <linux/clk.h> 19 #include <linux/delay.h> 20 #include <linux/extcon.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/i2c.h> 23 #include <linux/interrupt.h> 24 #include <linux/irq.h> 25 #include <linux/kernel.h> 26 #include <linux/list.h> 27 #include <linux/module.h> 28 #include <linux/mutex.h> 29 #include <linux/of_graph.h> 30 #include <linux/regulator/consumer.h> 31 #include <linux/slab.h> 32 33 #include <media/rc-core.h> 34 35 #include "sil-sii8620.h" 36 37 #define SII8620_BURST_BUF_LEN 288 38 #define VAL_RX_HDMI_CTRL2_DEFVAL VAL_RX_HDMI_CTRL2_IDLE_CNT(3) 39 40 #define MHL1_MAX_PCLK 75000 41 #define MHL1_MAX_PCLK_PP_MODE 150000 42 #define MHL3_MAX_PCLK 200000 43 #define MHL3_MAX_PCLK_PP_MODE 300000 44 45 enum sii8620_mode { 46 CM_DISCONNECTED, 47 CM_DISCOVERY, 48 CM_MHL1, 49 CM_MHL3, 50 CM_ECBUS_S 51 }; 52 53 enum sii8620_sink_type { 54 SINK_NONE, 55 SINK_HDMI, 56 SINK_DVI 57 }; 58 59 enum sii8620_mt_state { 60 MT_STATE_READY, 61 MT_STATE_BUSY, 62 MT_STATE_DONE 63 }; 64 65 struct sii8620 { 66 struct drm_bridge bridge; 67 struct device *dev; 68 struct rc_dev *rc_dev; 69 struct clk *clk_xtal; 70 struct gpio_desc *gpio_reset; 71 struct gpio_desc *gpio_int; 72 struct regulator_bulk_data supplies[2]; 73 struct mutex lock; /* context lock, protects fields below */ 74 int error; 75 int pixel_clock; 76 unsigned int use_packed_pixel:1; 77 int video_code; 78 enum sii8620_mode mode; 79 enum sii8620_sink_type sink_type; 80 u8 cbus_status; 81 u8 stat[MHL_DST_SIZE]; 82 u8 xstat[MHL_XDS_SIZE]; 83 u8 devcap[MHL_DCAP_SIZE]; 84 u8 xdevcap[MHL_XDC_SIZE]; 85 u8 avif[HDMI_INFOFRAME_SIZE(AVI)]; 86 struct edid *edid; 87 unsigned int gen2_write_burst:1; 88 enum sii8620_mt_state mt_state; 89 struct extcon_dev *extcon; 90 struct notifier_block extcon_nb; 91 struct work_struct extcon_wq; 92 int cable_state; 93 struct list_head mt_queue; 94 struct { 95 int r_size; 96 int r_count; 97 int rx_ack; 98 int rx_count; 99 u8 rx_buf[32]; 100 int tx_count; 101 u8 tx_buf[32]; 102 } burst; 103 }; 104 105 struct sii8620_mt_msg; 106 107 typedef void (*sii8620_mt_msg_cb)(struct sii8620 *ctx, 108 struct sii8620_mt_msg *msg); 109 110 typedef void (*sii8620_cb)(struct sii8620 *ctx, int ret); 111 112 struct sii8620_mt_msg { 113 struct list_head node; 114 u8 reg[4]; 115 u8 ret; 116 sii8620_mt_msg_cb send; 117 sii8620_mt_msg_cb recv; 118 sii8620_cb continuation; 119 }; 120 121 static const u8 sii8620_i2c_page[] = { 122 0x39, /* Main System */ 123 0x3d, /* TDM and HSIC */ 124 0x49, /* TMDS Receiver, MHL EDID */ 125 0x4d, /* eMSC, HDCP, HSIC */ 126 0x5d, /* MHL Spec */ 127 0x64, /* MHL CBUS */ 128 0x59, /* Hardware TPI (Transmitter Programming Interface) */ 129 0x61, /* eCBUS-S, eCBUS-D */ 130 }; 131 132 static void sii8620_fetch_edid(struct sii8620 *ctx); 133 static void sii8620_set_upstream_edid(struct sii8620 *ctx); 134 static void sii8620_enable_hpd(struct sii8620 *ctx); 135 static void sii8620_mhl_disconnected(struct sii8620 *ctx); 136 static void sii8620_disconnect(struct sii8620 *ctx); 137 138 static int sii8620_clear_error(struct sii8620 *ctx) 139 { 140 int ret = ctx->error; 141 142 ctx->error = 0; 143 return ret; 144 } 145 146 static void sii8620_read_buf(struct sii8620 *ctx, u16 addr, u8 *buf, int len) 147 { 148 struct device *dev = ctx->dev; 149 struct i2c_client *client = to_i2c_client(dev); 150 u8 data = addr; 151 struct i2c_msg msg[] = { 152 { 153 .addr = sii8620_i2c_page[addr >> 8], 154 .flags = client->flags, 155 .len = 1, 156 .buf = &data 157 }, 158 { 159 .addr = sii8620_i2c_page[addr >> 8], 160 .flags = client->flags | I2C_M_RD, 161 .len = len, 162 .buf = buf 163 }, 164 }; 165 int ret; 166 167 if (ctx->error) 168 return; 169 170 ret = i2c_transfer(client->adapter, msg, 2); 171 dev_dbg(dev, "read at %04x: %*ph, %d\n", addr, len, buf, ret); 172 173 if (ret != 2) { 174 dev_err(dev, "Read at %#06x of %d bytes failed with code %d.\n", 175 addr, len, ret); 176 ctx->error = ret < 0 ? ret : -EIO; 177 } 178 } 179 180 static u8 sii8620_readb(struct sii8620 *ctx, u16 addr) 181 { 182 u8 ret; 183 184 sii8620_read_buf(ctx, addr, &ret, 1); 185 return ret; 186 } 187 188 static void sii8620_write_buf(struct sii8620 *ctx, u16 addr, const u8 *buf, 189 int len) 190 { 191 struct device *dev = ctx->dev; 192 struct i2c_client *client = to_i2c_client(dev); 193 u8 data[2]; 194 struct i2c_msg msg = { 195 .addr = sii8620_i2c_page[addr >> 8], 196 .flags = client->flags, 197 .len = len + 1, 198 }; 199 int ret; 200 201 if (ctx->error) 202 return; 203 204 if (len > 1) { 205 msg.buf = kmalloc(len + 1, GFP_KERNEL); 206 if (!msg.buf) { 207 ctx->error = -ENOMEM; 208 return; 209 } 210 memcpy(msg.buf + 1, buf, len); 211 } else { 212 msg.buf = data; 213 msg.buf[1] = *buf; 214 } 215 216 msg.buf[0] = addr; 217 218 ret = i2c_transfer(client->adapter, &msg, 1); 219 dev_dbg(dev, "write at %04x: %*ph, %d\n", addr, len, buf, ret); 220 221 if (ret != 1) { 222 dev_err(dev, "Write at %#06x of %*ph failed with code %d.\n", 223 addr, len, buf, ret); 224 ctx->error = ret ?: -EIO; 225 } 226 227 if (len > 1) 228 kfree(msg.buf); 229 } 230 231 #define sii8620_write(ctx, addr, arr...) \ 232 ({\ 233 u8 d[] = { arr }; \ 234 sii8620_write_buf(ctx, addr, d, ARRAY_SIZE(d)); \ 235 }) 236 237 static void __sii8620_write_seq(struct sii8620 *ctx, const u16 *seq, int len) 238 { 239 int i; 240 241 for (i = 0; i < len; i += 2) 242 sii8620_write(ctx, seq[i], seq[i + 1]); 243 } 244 245 #define sii8620_write_seq(ctx, seq...) \ 246 ({\ 247 const u16 d[] = { seq }; \ 248 __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \ 249 }) 250 251 #define sii8620_write_seq_static(ctx, seq...) \ 252 ({\ 253 static const u16 d[] = { seq }; \ 254 __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \ 255 }) 256 257 static void sii8620_setbits(struct sii8620 *ctx, u16 addr, u8 mask, u8 val) 258 { 259 val = (val & mask) | (sii8620_readb(ctx, addr) & ~mask); 260 sii8620_write(ctx, addr, val); 261 } 262 263 static inline bool sii8620_is_mhl3(struct sii8620 *ctx) 264 { 265 return ctx->mode >= CM_MHL3; 266 } 267 268 static void sii8620_mt_cleanup(struct sii8620 *ctx) 269 { 270 struct sii8620_mt_msg *msg, *n; 271 272 list_for_each_entry_safe(msg, n, &ctx->mt_queue, node) { 273 list_del(&msg->node); 274 kfree(msg); 275 } 276 ctx->mt_state = MT_STATE_READY; 277 } 278 279 static void sii8620_mt_work(struct sii8620 *ctx) 280 { 281 struct sii8620_mt_msg *msg; 282 283 if (ctx->error) 284 return; 285 if (ctx->mt_state == MT_STATE_BUSY || list_empty(&ctx->mt_queue)) 286 return; 287 288 if (ctx->mt_state == MT_STATE_DONE) { 289 ctx->mt_state = MT_STATE_READY; 290 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, 291 node); 292 list_del(&msg->node); 293 if (msg->recv) 294 msg->recv(ctx, msg); 295 if (msg->continuation) 296 msg->continuation(ctx, msg->ret); 297 kfree(msg); 298 } 299 300 if (ctx->mt_state != MT_STATE_READY || list_empty(&ctx->mt_queue)) 301 return; 302 303 ctx->mt_state = MT_STATE_BUSY; 304 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 305 if (msg->send) 306 msg->send(ctx, msg); 307 } 308 309 static void sii8620_enable_gen2_write_burst(struct sii8620 *ctx) 310 { 311 u8 ctrl = BIT_MDT_RCV_CTRL_MDT_RCV_EN; 312 313 if (ctx->gen2_write_burst) 314 return; 315 316 if (ctx->mode >= CM_MHL1) 317 ctrl |= BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN; 318 319 sii8620_write_seq(ctx, 320 REG_MDT_RCV_TIMEOUT, 100, 321 REG_MDT_RCV_CTRL, ctrl 322 ); 323 ctx->gen2_write_burst = 1; 324 } 325 326 static void sii8620_disable_gen2_write_burst(struct sii8620 *ctx) 327 { 328 if (!ctx->gen2_write_burst) 329 return; 330 331 sii8620_write_seq_static(ctx, 332 REG_MDT_XMIT_CTRL, 0, 333 REG_MDT_RCV_CTRL, 0 334 ); 335 ctx->gen2_write_burst = 0; 336 } 337 338 static void sii8620_start_gen2_write_burst(struct sii8620 *ctx) 339 { 340 sii8620_write_seq_static(ctx, 341 REG_MDT_INT_1_MASK, BIT_MDT_RCV_TIMEOUT 342 | BIT_MDT_RCV_SM_ABORT_PKT_RCVD | BIT_MDT_RCV_SM_ERROR 343 | BIT_MDT_XMIT_TIMEOUT | BIT_MDT_XMIT_SM_ABORT_PKT_RCVD 344 | BIT_MDT_XMIT_SM_ERROR, 345 REG_MDT_INT_0_MASK, BIT_MDT_XFIFO_EMPTY 346 | BIT_MDT_IDLE_AFTER_HAWB_DISABLE 347 | BIT_MDT_RFIFO_DATA_RDY 348 ); 349 sii8620_enable_gen2_write_burst(ctx); 350 } 351 352 static void sii8620_mt_msc_cmd_send(struct sii8620 *ctx, 353 struct sii8620_mt_msg *msg) 354 { 355 if (msg->reg[0] == MHL_SET_INT && 356 msg->reg[1] == MHL_INT_REG(RCHANGE) && 357 msg->reg[2] == MHL_INT_RC_FEAT_REQ) 358 sii8620_enable_gen2_write_burst(ctx); 359 else 360 sii8620_disable_gen2_write_burst(ctx); 361 362 switch (msg->reg[0]) { 363 case MHL_WRITE_STAT: 364 case MHL_SET_INT: 365 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg + 1, 2); 366 sii8620_write(ctx, REG_MSC_COMMAND_START, 367 BIT_MSC_COMMAND_START_WRITE_STAT); 368 break; 369 case MHL_MSC_MSG: 370 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg, 3); 371 sii8620_write(ctx, REG_MSC_COMMAND_START, 372 BIT_MSC_COMMAND_START_MSC_MSG); 373 break; 374 case MHL_READ_DEVCAP_REG: 375 case MHL_READ_XDEVCAP_REG: 376 sii8620_write(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg[1]); 377 sii8620_write(ctx, REG_MSC_COMMAND_START, 378 BIT_MSC_COMMAND_START_READ_DEVCAP); 379 break; 380 default: 381 dev_err(ctx->dev, "%s: command %#x not supported\n", __func__, 382 msg->reg[0]); 383 } 384 } 385 386 static struct sii8620_mt_msg *sii8620_mt_msg_new(struct sii8620 *ctx) 387 { 388 struct sii8620_mt_msg *msg = kzalloc(sizeof(*msg), GFP_KERNEL); 389 390 if (!msg) 391 ctx->error = -ENOMEM; 392 else 393 list_add_tail(&msg->node, &ctx->mt_queue); 394 395 return msg; 396 } 397 398 static void sii8620_mt_set_cont(struct sii8620 *ctx, sii8620_cb cont) 399 { 400 struct sii8620_mt_msg *msg; 401 402 if (ctx->error) 403 return; 404 405 if (list_empty(&ctx->mt_queue)) { 406 ctx->error = -EINVAL; 407 return; 408 } 409 msg = list_last_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 410 msg->continuation = cont; 411 } 412 413 static void sii8620_mt_msc_cmd(struct sii8620 *ctx, u8 cmd, u8 arg1, u8 arg2) 414 { 415 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 416 417 if (!msg) 418 return; 419 420 msg->reg[0] = cmd; 421 msg->reg[1] = arg1; 422 msg->reg[2] = arg2; 423 msg->send = sii8620_mt_msc_cmd_send; 424 } 425 426 static void sii8620_mt_write_stat(struct sii8620 *ctx, u8 reg, u8 val) 427 { 428 sii8620_mt_msc_cmd(ctx, MHL_WRITE_STAT, reg, val); 429 } 430 431 static inline void sii8620_mt_set_int(struct sii8620 *ctx, u8 irq, u8 mask) 432 { 433 sii8620_mt_msc_cmd(ctx, MHL_SET_INT, irq, mask); 434 } 435 436 static void sii8620_mt_msc_msg(struct sii8620 *ctx, u8 cmd, u8 data) 437 { 438 sii8620_mt_msc_cmd(ctx, MHL_MSC_MSG, cmd, data); 439 } 440 441 static void sii8620_mt_rap(struct sii8620 *ctx, u8 code) 442 { 443 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RAP, code); 444 } 445 446 static void sii8620_mt_rcpk(struct sii8620 *ctx, u8 code) 447 { 448 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPK, code); 449 } 450 451 static void sii8620_mt_rcpe(struct sii8620 *ctx, u8 code) 452 { 453 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPE, code); 454 } 455 456 static void sii8620_mt_read_devcap_send(struct sii8620 *ctx, 457 struct sii8620_mt_msg *msg) 458 { 459 u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP 460 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 461 | BIT_EDID_CTRL_EDID_MODE_EN; 462 463 if (msg->reg[0] == MHL_READ_XDEVCAP) 464 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN; 465 466 sii8620_write_seq(ctx, 467 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE, 468 REG_EDID_CTRL, ctrl, 469 REG_TPI_CBUS_START, BIT_TPI_CBUS_START_GET_DEVCAP_START 470 ); 471 } 472 473 /* copy src to dst and set changed bits in src */ 474 static void sii8620_update_array(u8 *dst, u8 *src, int count) 475 { 476 while (--count >= 0) { 477 *src ^= *dst; 478 *dst++ ^= *src++; 479 } 480 } 481 482 static void sii8620_sink_detected(struct sii8620 *ctx, int ret) 483 { 484 static const char * const sink_str[] = { 485 [SINK_NONE] = "NONE", 486 [SINK_HDMI] = "HDMI", 487 [SINK_DVI] = "DVI" 488 }; 489 490 char sink_name[20]; 491 struct device *dev = ctx->dev; 492 493 if (ret < 0) 494 return; 495 496 sii8620_fetch_edid(ctx); 497 if (!ctx->edid) { 498 dev_err(ctx->dev, "Cannot fetch EDID\n"); 499 sii8620_mhl_disconnected(ctx); 500 return; 501 } 502 503 if (drm_detect_hdmi_monitor(ctx->edid)) 504 ctx->sink_type = SINK_HDMI; 505 else 506 ctx->sink_type = SINK_DVI; 507 508 drm_edid_get_monitor_name(ctx->edid, sink_name, ARRAY_SIZE(sink_name)); 509 510 dev_info(dev, "detected sink(type: %s): %s\n", 511 sink_str[ctx->sink_type], sink_name); 512 } 513 514 static void sii8620_edid_read(struct sii8620 *ctx, int ret) 515 { 516 if (ret < 0) 517 return; 518 519 sii8620_set_upstream_edid(ctx); 520 sii8620_enable_hpd(ctx); 521 } 522 523 static void sii8620_mr_devcap(struct sii8620 *ctx) 524 { 525 u8 dcap[MHL_DCAP_SIZE]; 526 struct device *dev = ctx->dev; 527 528 sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, dcap, MHL_DCAP_SIZE); 529 if (ctx->error < 0) 530 return; 531 532 dev_info(dev, "detected dongle MHL %d.%d, ChipID %02x%02x:%02x%02x\n", 533 dcap[MHL_DCAP_MHL_VERSION] / 16, 534 dcap[MHL_DCAP_MHL_VERSION] % 16, 535 dcap[MHL_DCAP_ADOPTER_ID_H], dcap[MHL_DCAP_ADOPTER_ID_L], 536 dcap[MHL_DCAP_DEVICE_ID_H], dcap[MHL_DCAP_DEVICE_ID_L]); 537 sii8620_update_array(ctx->devcap, dcap, MHL_DCAP_SIZE); 538 } 539 540 static void sii8620_mr_xdevcap(struct sii8620 *ctx) 541 { 542 sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, ctx->xdevcap, 543 MHL_XDC_SIZE); 544 } 545 546 static void sii8620_mt_read_devcap_recv(struct sii8620 *ctx, 547 struct sii8620_mt_msg *msg) 548 { 549 u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP 550 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 551 | BIT_EDID_CTRL_EDID_MODE_EN; 552 553 if (msg->reg[0] == MHL_READ_XDEVCAP) 554 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN; 555 556 sii8620_write_seq(ctx, 557 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE | BIT_INTR9_EDID_DONE 558 | BIT_INTR9_EDID_ERROR, 559 REG_EDID_CTRL, ctrl, 560 REG_EDID_FIFO_ADDR, 0 561 ); 562 563 if (msg->reg[0] == MHL_READ_XDEVCAP) 564 sii8620_mr_xdevcap(ctx); 565 else 566 sii8620_mr_devcap(ctx); 567 } 568 569 static void sii8620_mt_read_devcap(struct sii8620 *ctx, bool xdevcap) 570 { 571 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 572 573 if (!msg) 574 return; 575 576 msg->reg[0] = xdevcap ? MHL_READ_XDEVCAP : MHL_READ_DEVCAP; 577 msg->send = sii8620_mt_read_devcap_send; 578 msg->recv = sii8620_mt_read_devcap_recv; 579 } 580 581 static void sii8620_mt_read_devcap_reg_recv(struct sii8620 *ctx, 582 struct sii8620_mt_msg *msg) 583 { 584 u8 reg = msg->reg[1] & 0x7f; 585 586 if (msg->reg[1] & 0x80) 587 ctx->xdevcap[reg] = msg->ret; 588 else 589 ctx->devcap[reg] = msg->ret; 590 } 591 592 static void sii8620_mt_read_devcap_reg(struct sii8620 *ctx, u8 reg) 593 { 594 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 595 596 if (!msg) 597 return; 598 599 msg->reg[0] = (reg & 0x80) ? MHL_READ_XDEVCAP_REG : MHL_READ_DEVCAP_REG; 600 msg->reg[1] = reg; 601 msg->send = sii8620_mt_msc_cmd_send; 602 msg->recv = sii8620_mt_read_devcap_reg_recv; 603 } 604 605 static inline void sii8620_mt_read_xdevcap_reg(struct sii8620 *ctx, u8 reg) 606 { 607 sii8620_mt_read_devcap_reg(ctx, reg | 0x80); 608 } 609 610 static void *sii8620_burst_get_tx_buf(struct sii8620 *ctx, int len) 611 { 612 u8 *buf = &ctx->burst.tx_buf[ctx->burst.tx_count]; 613 int size = len + 2; 614 615 if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) { 616 dev_err(ctx->dev, "TX-BLK buffer exhausted\n"); 617 ctx->error = -EINVAL; 618 return NULL; 619 } 620 621 ctx->burst.tx_count += size; 622 buf[1] = len; 623 624 return buf + 2; 625 } 626 627 static u8 *sii8620_burst_get_rx_buf(struct sii8620 *ctx, int len) 628 { 629 u8 *buf = &ctx->burst.rx_buf[ctx->burst.rx_count]; 630 int size = len + 1; 631 632 if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) { 633 dev_err(ctx->dev, "RX-BLK buffer exhausted\n"); 634 ctx->error = -EINVAL; 635 return NULL; 636 } 637 638 ctx->burst.rx_count += size; 639 buf[0] = len; 640 641 return buf + 1; 642 } 643 644 static void sii8620_burst_send(struct sii8620 *ctx) 645 { 646 int tx_left = ctx->burst.tx_count; 647 u8 *d = ctx->burst.tx_buf; 648 649 while (tx_left > 0) { 650 int len = d[1] + 2; 651 652 if (ctx->burst.r_count + len > ctx->burst.r_size) 653 break; 654 d[0] = min(ctx->burst.rx_ack, 255); 655 ctx->burst.rx_ack -= d[0]; 656 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, d, len); 657 ctx->burst.r_count += len; 658 tx_left -= len; 659 d += len; 660 } 661 662 ctx->burst.tx_count = tx_left; 663 664 while (ctx->burst.rx_ack > 0) { 665 u8 b[2] = { min(ctx->burst.rx_ack, 255), 0 }; 666 667 if (ctx->burst.r_count + 2 > ctx->burst.r_size) 668 break; 669 ctx->burst.rx_ack -= b[0]; 670 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, b, 2); 671 ctx->burst.r_count += 2; 672 } 673 } 674 675 static void sii8620_burst_receive(struct sii8620 *ctx) 676 { 677 u8 buf[3], *d; 678 int count; 679 680 sii8620_read_buf(ctx, REG_EMSCRFIFOBCNTL, buf, 2); 681 count = get_unaligned_le16(buf); 682 while (count > 0) { 683 int len = min(count, 3); 684 685 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, buf, len); 686 count -= len; 687 ctx->burst.rx_ack += len - 1; 688 ctx->burst.r_count -= buf[1]; 689 if (ctx->burst.r_count < 0) 690 ctx->burst.r_count = 0; 691 692 if (len < 3 || !buf[2]) 693 continue; 694 695 len = buf[2]; 696 d = sii8620_burst_get_rx_buf(ctx, len); 697 if (!d) 698 continue; 699 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, d, len); 700 count -= len; 701 ctx->burst.rx_ack += len; 702 } 703 } 704 705 static void sii8620_burst_tx_rbuf_info(struct sii8620 *ctx, int size) 706 { 707 struct mhl_burst_blk_rcv_buffer_info *d = 708 sii8620_burst_get_tx_buf(ctx, sizeof(*d)); 709 if (!d) 710 return; 711 712 d->id = cpu_to_be16(MHL_BURST_ID_BLK_RCV_BUFFER_INFO); 713 d->size = cpu_to_le16(size); 714 } 715 716 static u8 sii8620_checksum(void *ptr, int size) 717 { 718 u8 *d = ptr, sum = 0; 719 720 while (size--) 721 sum += *d++; 722 723 return sum; 724 } 725 726 static void sii8620_mhl_burst_hdr_set(struct mhl3_burst_header *h, 727 enum mhl_burst_id id) 728 { 729 h->id = cpu_to_be16(id); 730 h->total_entries = 1; 731 h->sequence_index = 1; 732 } 733 734 static void sii8620_burst_tx_bits_per_pixel_fmt(struct sii8620 *ctx, u8 fmt) 735 { 736 struct mhl_burst_bits_per_pixel_fmt *d; 737 const int size = sizeof(*d) + sizeof(d->desc[0]); 738 739 d = sii8620_burst_get_tx_buf(ctx, size); 740 if (!d) 741 return; 742 743 sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_BITS_PER_PIXEL_FMT); 744 d->num_entries = 1; 745 d->desc[0].stream_id = 0; 746 d->desc[0].pixel_format = fmt; 747 d->hdr.checksum -= sii8620_checksum(d, size); 748 } 749 750 static void sii8620_burst_rx_all(struct sii8620 *ctx) 751 { 752 u8 *d = ctx->burst.rx_buf; 753 int count = ctx->burst.rx_count; 754 755 while (count-- > 0) { 756 int len = *d++; 757 int id = get_unaligned_be16(&d[0]); 758 759 switch (id) { 760 case MHL_BURST_ID_BLK_RCV_BUFFER_INFO: 761 ctx->burst.r_size = get_unaligned_le16(&d[2]); 762 break; 763 default: 764 break; 765 } 766 count -= len; 767 d += len; 768 } 769 ctx->burst.rx_count = 0; 770 } 771 772 static void sii8620_fetch_edid(struct sii8620 *ctx) 773 { 774 u8 lm_ddc, ddc_cmd, int3, cbus; 775 unsigned long timeout; 776 int fetched, i; 777 int edid_len = EDID_LENGTH; 778 u8 *edid; 779 780 sii8620_readb(ctx, REG_CBUS_STATUS); 781 lm_ddc = sii8620_readb(ctx, REG_LM_DDC); 782 ddc_cmd = sii8620_readb(ctx, REG_DDC_CMD); 783 784 sii8620_write_seq(ctx, 785 REG_INTR9_MASK, 0, 786 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO, 787 REG_HDCP2X_POLL_CS, 0x71, 788 REG_HDCP2X_CTRL_0, BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX, 789 REG_LM_DDC, lm_ddc | BIT_LM_DDC_SW_TPI_EN_DISABLED, 790 ); 791 792 for (i = 0; i < 256; ++i) { 793 u8 ddc_stat = sii8620_readb(ctx, REG_DDC_STATUS); 794 795 if (!(ddc_stat & BIT_DDC_STATUS_DDC_I2C_IN_PROG)) 796 break; 797 sii8620_write(ctx, REG_DDC_STATUS, 798 BIT_DDC_STATUS_DDC_FIFO_EMPTY); 799 } 800 801 sii8620_write(ctx, REG_DDC_ADDR, 0x50 << 1); 802 803 edid = kmalloc(EDID_LENGTH, GFP_KERNEL); 804 if (!edid) { 805 ctx->error = -ENOMEM; 806 return; 807 } 808 809 #define FETCH_SIZE 16 810 for (fetched = 0; fetched < edid_len; fetched += FETCH_SIZE) { 811 sii8620_readb(ctx, REG_DDC_STATUS); 812 sii8620_write_seq(ctx, 813 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_ABORT, 814 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_CLEAR_FIFO, 815 REG_DDC_STATUS, BIT_DDC_STATUS_DDC_FIFO_EMPTY 816 ); 817 sii8620_write_seq(ctx, 818 REG_DDC_SEGM, fetched >> 8, 819 REG_DDC_OFFSET, fetched & 0xff, 820 REG_DDC_DIN_CNT1, FETCH_SIZE, 821 REG_DDC_DIN_CNT2, 0, 822 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_ENH_DDC_READ_NO_ACK 823 ); 824 825 int3 = 0; 826 timeout = jiffies + msecs_to_jiffies(200); 827 for (;;) { 828 cbus = sii8620_readb(ctx, REG_CBUS_STATUS); 829 if (~cbus & BIT_CBUS_STATUS_CBUS_CONNECTED) { 830 kfree(edid); 831 edid = NULL; 832 goto end; 833 } 834 if (int3 & BIT_DDC_CMD_DONE) { 835 if (sii8620_readb(ctx, REG_DDC_DOUT_CNT) 836 >= FETCH_SIZE) 837 break; 838 } else { 839 int3 = sii8620_readb(ctx, REG_INTR3); 840 } 841 if (time_is_before_jiffies(timeout)) { 842 ctx->error = -ETIMEDOUT; 843 dev_err(ctx->dev, "timeout during EDID read\n"); 844 kfree(edid); 845 edid = NULL; 846 goto end; 847 } 848 usleep_range(10, 20); 849 } 850 851 sii8620_read_buf(ctx, REG_DDC_DATA, edid + fetched, FETCH_SIZE); 852 if (fetched + FETCH_SIZE == EDID_LENGTH) { 853 u8 ext = ((struct edid *)edid)->extensions; 854 855 if (ext) { 856 u8 *new_edid; 857 858 edid_len += ext * EDID_LENGTH; 859 new_edid = krealloc(edid, edid_len, GFP_KERNEL); 860 if (!new_edid) { 861 kfree(edid); 862 ctx->error = -ENOMEM; 863 return; 864 } 865 edid = new_edid; 866 } 867 } 868 } 869 870 sii8620_write_seq(ctx, 871 REG_INTR3_MASK, BIT_DDC_CMD_DONE, 872 REG_LM_DDC, lm_ddc 873 ); 874 875 end: 876 kfree(ctx->edid); 877 ctx->edid = (struct edid *)edid; 878 } 879 880 static void sii8620_set_upstream_edid(struct sii8620 *ctx) 881 { 882 sii8620_setbits(ctx, REG_DPD, BIT_DPD_PDNRX12 | BIT_DPD_PDIDCK_N 883 | BIT_DPD_PD_MHL_CLK_N, 0xff); 884 885 sii8620_write_seq_static(ctx, 886 REG_RX_HDMI_CTRL3, 0x00, 887 REG_PKT_FILTER_0, 0xFF, 888 REG_PKT_FILTER_1, 0xFF, 889 REG_ALICE0_BW_I2C, 0x06 890 ); 891 892 sii8620_setbits(ctx, REG_RX_HDMI_CLR_BUFFER, 893 BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN, 0xff); 894 895 sii8620_write_seq_static(ctx, 896 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 897 | BIT_EDID_CTRL_EDID_MODE_EN, 898 REG_EDID_FIFO_ADDR, 0, 899 ); 900 901 sii8620_write_buf(ctx, REG_EDID_FIFO_WR_DATA, (u8 *)ctx->edid, 902 (ctx->edid->extensions + 1) * EDID_LENGTH); 903 904 sii8620_write_seq_static(ctx, 905 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID 906 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 907 | BIT_EDID_CTRL_EDID_MODE_EN, 908 REG_INTR5_MASK, BIT_INTR_SCDT_CHANGE, 909 REG_INTR9_MASK, 0 910 ); 911 } 912 913 static void sii8620_xtal_set_rate(struct sii8620 *ctx) 914 { 915 static const struct { 916 unsigned int rate; 917 u8 div; 918 u8 tp1; 919 } rates[] = { 920 { 19200, 0x04, 0x53 }, 921 { 20000, 0x04, 0x62 }, 922 { 24000, 0x05, 0x75 }, 923 { 30000, 0x06, 0x92 }, 924 { 38400, 0x0c, 0xbc }, 925 }; 926 unsigned long rate = clk_get_rate(ctx->clk_xtal) / 1000; 927 int i; 928 929 for (i = 0; i < ARRAY_SIZE(rates) - 1; ++i) 930 if (rate <= rates[i].rate) 931 break; 932 933 if (rate != rates[i].rate) 934 dev_err(ctx->dev, "xtal clock rate(%lukHz) not supported, setting MHL for %ukHz.\n", 935 rate, rates[i].rate); 936 937 sii8620_write(ctx, REG_DIV_CTL_MAIN, rates[i].div); 938 sii8620_write(ctx, REG_HDCP2X_TP1, rates[i].tp1); 939 } 940 941 static int sii8620_hw_on(struct sii8620 *ctx) 942 { 943 int ret; 944 945 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 946 if (ret) 947 return ret; 948 949 usleep_range(10000, 20000); 950 ret = clk_prepare_enable(ctx->clk_xtal); 951 if (ret) 952 return ret; 953 954 msleep(100); 955 gpiod_set_value(ctx->gpio_reset, 0); 956 msleep(100); 957 958 return 0; 959 } 960 961 static int sii8620_hw_off(struct sii8620 *ctx) 962 { 963 clk_disable_unprepare(ctx->clk_xtal); 964 gpiod_set_value(ctx->gpio_reset, 1); 965 return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 966 } 967 968 static void sii8620_cbus_reset(struct sii8620 *ctx) 969 { 970 sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST 971 | BIT_PWD_SRST_CBUS_RST_SW_EN); 972 usleep_range(10000, 20000); 973 sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN); 974 } 975 976 static void sii8620_set_auto_zone(struct sii8620 *ctx) 977 { 978 if (ctx->mode != CM_MHL1) { 979 sii8620_write_seq_static(ctx, 980 REG_TX_ZONE_CTL1, 0x0, 981 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 982 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 983 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE 984 ); 985 } else { 986 sii8620_write_seq_static(ctx, 987 REG_TX_ZONE_CTL1, VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE, 988 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 989 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE 990 ); 991 } 992 } 993 994 static void sii8620_stop_video(struct sii8620 *ctx) 995 { 996 u8 uninitialized_var(val); 997 998 sii8620_write_seq_static(ctx, 999 REG_TPI_INTR_EN, 0, 1000 REG_HDCP2X_INTR0_MASK, 0, 1001 REG_TPI_COPP_DATA2, 0, 1002 REG_TPI_INTR_ST0, ~0, 1003 ); 1004 1005 switch (ctx->sink_type) { 1006 case SINK_DVI: 1007 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN 1008 | BIT_TPI_SC_TPI_AV_MUTE; 1009 break; 1010 case SINK_HDMI: 1011 default: 1012 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN 1013 | BIT_TPI_SC_TPI_AV_MUTE 1014 | BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI; 1015 break; 1016 } 1017 1018 sii8620_write(ctx, REG_TPI_SC, val); 1019 } 1020 1021 static void sii8620_set_format(struct sii8620 *ctx) 1022 { 1023 u8 out_fmt; 1024 1025 if (sii8620_is_mhl3(ctx)) { 1026 sii8620_setbits(ctx, REG_M3_P0CTRL, 1027 BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED, 1028 ctx->use_packed_pixel ? ~0 : 0); 1029 } else { 1030 if (ctx->use_packed_pixel) 1031 sii8620_write_seq_static(ctx, 1032 REG_VID_MODE, BIT_VID_MODE_M1080P, 1033 REG_MHL_TOP_CTL, BIT_MHL_TOP_CTL_MHL_PP_SEL | 1, 1034 REG_MHLTX_CTL6, 0x60 1035 ); 1036 else 1037 sii8620_write_seq_static(ctx, 1038 REG_VID_MODE, 0, 1039 REG_MHL_TOP_CTL, 1, 1040 REG_MHLTX_CTL6, 0xa0 1041 ); 1042 } 1043 1044 if (ctx->use_packed_pixel) 1045 out_fmt = VAL_TPI_FORMAT(YCBCR422, FULL) | 1046 BIT_TPI_OUTPUT_CSCMODE709; 1047 else 1048 out_fmt = VAL_TPI_FORMAT(RGB, FULL); 1049 1050 sii8620_write_seq(ctx, 1051 REG_TPI_INPUT, VAL_TPI_FORMAT(RGB, FULL), 1052 REG_TPI_OUTPUT, out_fmt, 1053 ); 1054 } 1055 1056 static int mhl3_infoframe_init(struct mhl3_infoframe *frame) 1057 { 1058 memset(frame, 0, sizeof(*frame)); 1059 1060 frame->version = 3; 1061 frame->hev_format = -1; 1062 return 0; 1063 } 1064 1065 static ssize_t mhl3_infoframe_pack(struct mhl3_infoframe *frame, 1066 void *buffer, size_t size) 1067 { 1068 const int frm_len = HDMI_INFOFRAME_HEADER_SIZE + MHL3_INFOFRAME_SIZE; 1069 u8 *ptr = buffer; 1070 1071 if (size < frm_len) 1072 return -ENOSPC; 1073 1074 memset(buffer, 0, size); 1075 ptr[0] = HDMI_INFOFRAME_TYPE_VENDOR; 1076 ptr[1] = frame->version; 1077 ptr[2] = MHL3_INFOFRAME_SIZE; 1078 ptr[4] = MHL3_IEEE_OUI & 0xff; 1079 ptr[5] = (MHL3_IEEE_OUI >> 8) & 0xff; 1080 ptr[6] = (MHL3_IEEE_OUI >> 16) & 0xff; 1081 ptr[7] = frame->video_format & 0x3; 1082 ptr[7] |= (frame->format_type & 0x7) << 2; 1083 ptr[7] |= frame->sep_audio ? BIT(5) : 0; 1084 if (frame->hev_format >= 0) { 1085 ptr[9] = 1; 1086 ptr[10] = (frame->hev_format >> 8) & 0xff; 1087 ptr[11] = frame->hev_format & 0xff; 1088 } 1089 if (frame->av_delay) { 1090 bool sign = frame->av_delay < 0; 1091 int delay = sign ? -frame->av_delay : frame->av_delay; 1092 1093 ptr[12] = (delay >> 16) & 0xf; 1094 if (sign) 1095 ptr[12] |= BIT(4); 1096 ptr[13] = (delay >> 8) & 0xff; 1097 ptr[14] = delay & 0xff; 1098 } 1099 ptr[3] -= sii8620_checksum(buffer, frm_len); 1100 return frm_len; 1101 } 1102 1103 static void sii8620_set_infoframes(struct sii8620 *ctx) 1104 { 1105 struct mhl3_infoframe mhl_frm; 1106 union hdmi_infoframe frm; 1107 u8 buf[31]; 1108 int ret; 1109 1110 if (!sii8620_is_mhl3(ctx) || !ctx->use_packed_pixel) { 1111 sii8620_write(ctx, REG_TPI_SC, 1112 BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI); 1113 sii8620_write_buf(ctx, REG_TPI_AVI_CHSUM, ctx->avif + 3, 1114 ARRAY_SIZE(ctx->avif) - 3); 1115 sii8620_write(ctx, REG_PKT_FILTER_0, 1116 BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT | 1117 BIT_PKT_FILTER_0_DROP_MPEG_PKT | 1118 BIT_PKT_FILTER_0_DROP_GCP_PKT, 1119 BIT_PKT_FILTER_1_DROP_GEN_PKT); 1120 return; 1121 } 1122 1123 ret = hdmi_avi_infoframe_init(&frm.avi); 1124 frm.avi.colorspace = HDMI_COLORSPACE_YUV422; 1125 frm.avi.active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 1126 frm.avi.picture_aspect = HDMI_PICTURE_ASPECT_16_9; 1127 frm.avi.colorimetry = HDMI_COLORIMETRY_ITU_709; 1128 frm.avi.video_code = ctx->video_code; 1129 if (!ret) 1130 ret = hdmi_avi_infoframe_pack(&frm.avi, buf, ARRAY_SIZE(buf)); 1131 if (ret > 0) 1132 sii8620_write_buf(ctx, REG_TPI_AVI_CHSUM, buf + 3, ret - 3); 1133 sii8620_write(ctx, REG_PKT_FILTER_0, 1134 BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT | 1135 BIT_PKT_FILTER_0_DROP_MPEG_PKT | 1136 BIT_PKT_FILTER_0_DROP_AVI_PKT | 1137 BIT_PKT_FILTER_0_DROP_GCP_PKT, 1138 BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS | 1139 BIT_PKT_FILTER_1_DROP_GEN_PKT | 1140 BIT_PKT_FILTER_1_DROP_VSIF_PKT); 1141 1142 sii8620_write(ctx, REG_TPI_INFO_FSEL, BIT_TPI_INFO_FSEL_EN 1143 | BIT_TPI_INFO_FSEL_RPT | VAL_TPI_INFO_FSEL_VSI); 1144 ret = mhl3_infoframe_init(&mhl_frm); 1145 if (!ret) 1146 ret = mhl3_infoframe_pack(&mhl_frm, buf, ARRAY_SIZE(buf)); 1147 sii8620_write_buf(ctx, REG_TPI_INFO_B0, buf, ret); 1148 } 1149 1150 static void sii8620_start_video(struct sii8620 *ctx) 1151 { 1152 if (!sii8620_is_mhl3(ctx)) 1153 sii8620_stop_video(ctx); 1154 1155 if (ctx->sink_type == SINK_DVI && !sii8620_is_mhl3(ctx)) { 1156 sii8620_write(ctx, REG_RX_HDMI_CTRL2, 1157 VAL_RX_HDMI_CTRL2_DEFVAL); 1158 sii8620_write(ctx, REG_TPI_SC, 0); 1159 return; 1160 } 1161 1162 sii8620_write_seq_static(ctx, 1163 REG_RX_HDMI_CTRL2, VAL_RX_HDMI_CTRL2_DEFVAL 1164 | BIT_RX_HDMI_CTRL2_USE_AV_MUTE, 1165 REG_VID_OVRRD, BIT_VID_OVRRD_PP_AUTO_DISABLE 1166 | BIT_VID_OVRRD_M1080P_OVRRD); 1167 sii8620_set_format(ctx); 1168 1169 if (!sii8620_is_mhl3(ctx)) { 1170 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE), 1171 MHL_DST_LM_CLK_MODE_NORMAL | MHL_DST_LM_PATH_ENABLED); 1172 sii8620_set_auto_zone(ctx); 1173 } else { 1174 static const struct { 1175 int max_clk; 1176 u8 zone; 1177 u8 link_rate; 1178 u8 rrp_decode; 1179 } clk_spec[] = { 1180 { 150000, VAL_TX_ZONE_CTL3_TX_ZONE_1_5GBPS, 1181 MHL_XDS_LINK_RATE_1_5_GBPS, 0x38 }, 1182 { 300000, VAL_TX_ZONE_CTL3_TX_ZONE_3GBPS, 1183 MHL_XDS_LINK_RATE_3_0_GBPS, 0x40 }, 1184 { 600000, VAL_TX_ZONE_CTL3_TX_ZONE_6GBPS, 1185 MHL_XDS_LINK_RATE_6_0_GBPS, 0x40 }, 1186 }; 1187 u8 p0_ctrl = BIT_M3_P0CTRL_MHL3_P0_PORT_EN; 1188 int clk = ctx->pixel_clock * (ctx->use_packed_pixel ? 2 : 3); 1189 int i; 1190 1191 for (i = 0; i < ARRAY_SIZE(clk_spec) - 1; ++i) 1192 if (clk < clk_spec[i].max_clk) 1193 break; 1194 1195 if (100 * clk >= 98 * clk_spec[i].max_clk) 1196 p0_ctrl |= BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN; 1197 1198 sii8620_burst_tx_bits_per_pixel_fmt(ctx, ctx->use_packed_pixel); 1199 sii8620_burst_send(ctx); 1200 sii8620_write_seq(ctx, 1201 REG_MHL_DP_CTL0, 0xf0, 1202 REG_MHL3_TX_ZONE_CTL, clk_spec[i].zone); 1203 sii8620_setbits(ctx, REG_M3_P0CTRL, 1204 BIT_M3_P0CTRL_MHL3_P0_PORT_EN 1205 | BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN, p0_ctrl); 1206 sii8620_setbits(ctx, REG_M3_POSTM, MSK_M3_POSTM_RRP_DECODE, 1207 clk_spec[i].rrp_decode); 1208 sii8620_write_seq_static(ctx, 1209 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE 1210 | BIT_M3_CTRL_H2M_SWRST, 1211 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE 1212 ); 1213 sii8620_mt_write_stat(ctx, MHL_XDS_REG(AVLINK_MODE_CONTROL), 1214 clk_spec[i].link_rate); 1215 } 1216 1217 sii8620_set_infoframes(ctx); 1218 } 1219 1220 static void sii8620_disable_hpd(struct sii8620 *ctx) 1221 { 1222 sii8620_setbits(ctx, REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID, 0); 1223 sii8620_write_seq_static(ctx, 1224 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN, 1225 REG_INTR8_MASK, 0 1226 ); 1227 } 1228 1229 static void sii8620_enable_hpd(struct sii8620 *ctx) 1230 { 1231 sii8620_setbits(ctx, REG_TMDS_CSTAT_P3, 1232 BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS 1233 | BIT_TMDS_CSTAT_P3_CLR_AVI, ~0); 1234 sii8620_write_seq_static(ctx, 1235 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN 1236 | BIT_HPD_CTRL_HPD_HIGH, 1237 ); 1238 } 1239 1240 static void sii8620_mhl_discover(struct sii8620 *ctx) 1241 { 1242 sii8620_write_seq_static(ctx, 1243 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1244 | BIT_DISC_CTRL9_DISC_PULSE_PROCEED, 1245 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_5K, VAL_PUP_20K), 1246 REG_CBUS_DISC_INTR0_MASK, BIT_MHL3_EST_INT 1247 | BIT_MHL_EST_INT 1248 | BIT_NOT_MHL_EST_INT 1249 | BIT_CBUS_MHL3_DISCON_INT 1250 | BIT_CBUS_MHL12_DISCON_INT 1251 | BIT_RGND_READY_INT, 1252 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 1253 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 1254 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE, 1255 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE 1256 | BIT_MHL_DP_CTL0_TX_OE_OVR, 1257 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE, 1258 REG_MHL_DP_CTL1, 0xA2, 1259 REG_MHL_DP_CTL2, 0x03, 1260 REG_MHL_DP_CTL3, 0x35, 1261 REG_MHL_DP_CTL5, 0x02, 1262 REG_MHL_DP_CTL6, 0x02, 1263 REG_MHL_DP_CTL7, 0x03, 1264 REG_COC_CTLC, 0xFF, 1265 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 1266 | BIT_DPD_OSC_EN | BIT_DPD_PWRON_HSIC, 1267 REG_COC_INTR_MASK, BIT_COC_PLL_LOCK_STATUS_CHANGE 1268 | BIT_COC_CALIBRATION_DONE, 1269 REG_CBUS_INT_1_MASK, BIT_CBUS_MSC_ABORT_RCVD 1270 | BIT_CBUS_CMD_ABORT, 1271 REG_CBUS_INT_0_MASK, BIT_CBUS_MSC_MT_DONE 1272 | BIT_CBUS_HPD_CHG 1273 | BIT_CBUS_MSC_MR_WRITE_STAT 1274 | BIT_CBUS_MSC_MR_MSC_MSG 1275 | BIT_CBUS_MSC_MR_WRITE_BURST 1276 | BIT_CBUS_MSC_MR_SET_INT 1277 | BIT_CBUS_MSC_MT_DONE_NACK 1278 ); 1279 } 1280 1281 static void sii8620_peer_specific_init(struct sii8620 *ctx) 1282 { 1283 if (sii8620_is_mhl3(ctx)) 1284 sii8620_write_seq_static(ctx, 1285 REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD, 1286 REG_EMSCINTRMASK1, 1287 BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR 1288 ); 1289 else 1290 sii8620_write_seq_static(ctx, 1291 REG_HDCP2X_INTR0_MASK, 0x00, 1292 REG_EMSCINTRMASK1, 0x00, 1293 REG_HDCP2X_INTR0, 0xFF, 1294 REG_INTR1, 0xFF, 1295 REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD 1296 | BIT_SYS_CTRL1_TX_CTRL_HDMI 1297 ); 1298 } 1299 1300 #define SII8620_MHL_VERSION 0x32 1301 #define SII8620_SCRATCHPAD_SIZE 16 1302 #define SII8620_INT_STAT_SIZE 0x33 1303 1304 static void sii8620_set_dev_cap(struct sii8620 *ctx) 1305 { 1306 static const u8 devcap[MHL_DCAP_SIZE] = { 1307 [MHL_DCAP_MHL_VERSION] = SII8620_MHL_VERSION, 1308 [MHL_DCAP_CAT] = MHL_DCAP_CAT_SOURCE | MHL_DCAP_CAT_POWER, 1309 [MHL_DCAP_ADOPTER_ID_H] = 0x01, 1310 [MHL_DCAP_ADOPTER_ID_L] = 0x41, 1311 [MHL_DCAP_VID_LINK_MODE] = MHL_DCAP_VID_LINK_RGB444 1312 | MHL_DCAP_VID_LINK_PPIXEL 1313 | MHL_DCAP_VID_LINK_16BPP, 1314 [MHL_DCAP_AUD_LINK_MODE] = MHL_DCAP_AUD_LINK_2CH, 1315 [MHL_DCAP_VIDEO_TYPE] = MHL_DCAP_VT_GRAPHICS, 1316 [MHL_DCAP_LOG_DEV_MAP] = MHL_DCAP_LD_GUI, 1317 [MHL_DCAP_BANDWIDTH] = 0x0f, 1318 [MHL_DCAP_FEATURE_FLAG] = MHL_DCAP_FEATURE_RCP_SUPPORT 1319 | MHL_DCAP_FEATURE_RAP_SUPPORT 1320 | MHL_DCAP_FEATURE_SP_SUPPORT, 1321 [MHL_DCAP_SCRATCHPAD_SIZE] = SII8620_SCRATCHPAD_SIZE, 1322 [MHL_DCAP_INT_STAT_SIZE] = SII8620_INT_STAT_SIZE, 1323 }; 1324 static const u8 xdcap[MHL_XDC_SIZE] = { 1325 [MHL_XDC_ECBUS_SPEEDS] = MHL_XDC_ECBUS_S_075 1326 | MHL_XDC_ECBUS_S_8BIT, 1327 [MHL_XDC_TMDS_SPEEDS] = MHL_XDC_TMDS_150 1328 | MHL_XDC_TMDS_300 | MHL_XDC_TMDS_600, 1329 [MHL_XDC_ECBUS_ROLES] = MHL_XDC_DEV_HOST, 1330 [MHL_XDC_LOG_DEV_MAPX] = MHL_XDC_LD_PHONE, 1331 }; 1332 1333 sii8620_write_buf(ctx, REG_MHL_DEVCAP_0, devcap, ARRAY_SIZE(devcap)); 1334 sii8620_write_buf(ctx, REG_MHL_EXTDEVCAP_0, xdcap, ARRAY_SIZE(xdcap)); 1335 } 1336 1337 static void sii8620_mhl_init(struct sii8620 *ctx) 1338 { 1339 sii8620_write_seq_static(ctx, 1340 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1341 REG_CBUS_MSC_COMPAT_CTRL, 1342 BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN, 1343 ); 1344 1345 sii8620_peer_specific_init(ctx); 1346 1347 sii8620_disable_hpd(ctx); 1348 1349 sii8620_write_seq_static(ctx, 1350 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO, 1351 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1352 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1353 REG_TMDS0_CCTRL1, 0x90, 1354 REG_TMDS_CLK_EN, 0x01, 1355 REG_TMDS_CH_EN, 0x11, 1356 REG_BGR_BIAS, 0x87, 1357 REG_ALICE0_ZONE_CTRL, 0xE8, 1358 REG_ALICE0_MODE_CTRL, 0x04, 1359 ); 1360 sii8620_setbits(ctx, REG_LM_DDC, BIT_LM_DDC_SW_TPI_EN_DISABLED, 0); 1361 sii8620_write_seq_static(ctx, 1362 REG_TPI_HW_OPT3, 0x76, 1363 REG_TMDS_CCTRL, BIT_TMDS_CCTRL_TMDS_OE, 1364 REG_TPI_DTD_B2, 79, 1365 ); 1366 sii8620_set_dev_cap(ctx); 1367 sii8620_write_seq_static(ctx, 1368 REG_MDT_XMIT_TIMEOUT, 100, 1369 REG_MDT_XMIT_CTRL, 0x03, 1370 REG_MDT_XFIFO_STAT, 0x00, 1371 REG_MDT_RCV_TIMEOUT, 100, 1372 REG_CBUS_LINK_CTRL_8, 0x1D, 1373 ); 1374 1375 sii8620_start_gen2_write_burst(ctx); 1376 sii8620_write_seq_static(ctx, 1377 REG_BIST_CTRL, 0x00, 1378 REG_COC_CTL1, 0x10, 1379 REG_COC_CTL2, 0x18, 1380 REG_COC_CTLF, 0x07, 1381 REG_COC_CTL11, 0xF8, 1382 REG_COC_CTL17, 0x61, 1383 REG_COC_CTL18, 0x46, 1384 REG_COC_CTL19, 0x15, 1385 REG_COC_CTL1A, 0x01, 1386 REG_MHL_COC_CTL3, BIT_MHL_COC_CTL3_COC_AECHO_EN, 1387 REG_MHL_COC_CTL4, 0x2D, 1388 REG_MHL_COC_CTL5, 0xF9, 1389 REG_MSC_HEARTBEAT_CTRL, 0x27, 1390 ); 1391 sii8620_disable_gen2_write_burst(ctx); 1392 1393 sii8620_mt_write_stat(ctx, MHL_DST_REG(VERSION), SII8620_MHL_VERSION); 1394 sii8620_mt_write_stat(ctx, MHL_DST_REG(CONNECTED_RDY), 1395 MHL_DST_CONN_DCAP_RDY | MHL_DST_CONN_XDEVCAPP_SUPP 1396 | MHL_DST_CONN_POW_STAT); 1397 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), MHL_INT_RC_DCAP_CHG); 1398 } 1399 1400 static void sii8620_emsc_enable(struct sii8620 *ctx) 1401 { 1402 u8 reg; 1403 1404 sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_EMSC_EN 1405 | BIT_GENCTL_CLR_EMSC_RFIFO 1406 | BIT_GENCTL_CLR_EMSC_XFIFO, ~0); 1407 sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_CLR_EMSC_RFIFO 1408 | BIT_GENCTL_CLR_EMSC_XFIFO, 0); 1409 sii8620_setbits(ctx, REG_COMMECNT, BIT_COMMECNT_I2C_TO_EMSC_EN, ~0); 1410 reg = sii8620_readb(ctx, REG_EMSCINTR); 1411 sii8620_write(ctx, REG_EMSCINTR, reg); 1412 sii8620_write(ctx, REG_EMSCINTRMASK, BIT_EMSCINTR_SPI_DVLD); 1413 } 1414 1415 static int sii8620_wait_for_fsm_state(struct sii8620 *ctx, u8 state) 1416 { 1417 int i; 1418 1419 for (i = 0; i < 10; ++i) { 1420 u8 s = sii8620_readb(ctx, REG_COC_STAT_0); 1421 1422 if ((s & MSK_COC_STAT_0_FSM_STATE) == state) 1423 return 0; 1424 if (!(s & BIT_COC_STAT_0_PLL_LOCKED)) 1425 return -EBUSY; 1426 usleep_range(4000, 6000); 1427 } 1428 return -ETIMEDOUT; 1429 } 1430 1431 static void sii8620_set_mode(struct sii8620 *ctx, enum sii8620_mode mode) 1432 { 1433 int ret; 1434 1435 if (ctx->mode == mode) 1436 return; 1437 1438 switch (mode) { 1439 case CM_MHL1: 1440 sii8620_write_seq_static(ctx, 1441 REG_CBUS_MSC_COMPAT_CTRL, 0x02, 1442 REG_M3_CTRL, VAL_M3_CTRL_MHL1_2_VALUE, 1443 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 1444 | BIT_DPD_OSC_EN, 1445 REG_COC_INTR_MASK, 0 1446 ); 1447 ctx->mode = mode; 1448 break; 1449 case CM_MHL3: 1450 sii8620_write(ctx, REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE); 1451 ctx->mode = mode; 1452 return; 1453 case CM_ECBUS_S: 1454 sii8620_emsc_enable(ctx); 1455 sii8620_write_seq_static(ctx, 1456 REG_TTXSPINUMS, 4, 1457 REG_TRXSPINUMS, 4, 1458 REG_TTXHSICNUMS, 0x14, 1459 REG_TRXHSICNUMS, 0x14, 1460 REG_TTXTOTNUMS, 0x18, 1461 REG_TRXTOTNUMS, 0x18, 1462 REG_PWD_SRST, BIT_PWD_SRST_COC_DOC_RST 1463 | BIT_PWD_SRST_CBUS_RST_SW_EN, 1464 REG_MHL_COC_CTL1, 0xbd, 1465 REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN, 1466 REG_COC_CTLB, 0x01, 1467 REG_COC_CTL0, 0x5c, 1468 REG_COC_CTL14, 0x03, 1469 REG_COC_CTL15, 0x80, 1470 REG_MHL_DP_CTL6, BIT_MHL_DP_CTL6_DP_TAP1_SGN 1471 | BIT_MHL_DP_CTL6_DP_TAP1_EN 1472 | BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN, 1473 REG_MHL_DP_CTL8, 0x03 1474 ); 1475 ret = sii8620_wait_for_fsm_state(ctx, 0x03); 1476 sii8620_write_seq_static(ctx, 1477 REG_COC_CTL14, 0x00, 1478 REG_COC_CTL15, 0x80 1479 ); 1480 if (!ret) 1481 sii8620_write(ctx, REG_CBUS3_CNVT, 0x85); 1482 else 1483 sii8620_disconnect(ctx); 1484 return; 1485 case CM_DISCONNECTED: 1486 ctx->mode = mode; 1487 break; 1488 default: 1489 dev_err(ctx->dev, "%s mode %d not supported\n", __func__, mode); 1490 break; 1491 } 1492 1493 sii8620_set_auto_zone(ctx); 1494 1495 if (mode != CM_MHL1) 1496 return; 1497 1498 sii8620_write_seq_static(ctx, 1499 REG_MHL_DP_CTL0, 0xBC, 1500 REG_MHL_DP_CTL1, 0xBB, 1501 REG_MHL_DP_CTL3, 0x48, 1502 REG_MHL_DP_CTL5, 0x39, 1503 REG_MHL_DP_CTL2, 0x2A, 1504 REG_MHL_DP_CTL6, 0x2A, 1505 REG_MHL_DP_CTL7, 0x08 1506 ); 1507 } 1508 1509 static void sii8620_disconnect(struct sii8620 *ctx) 1510 { 1511 sii8620_disable_gen2_write_burst(ctx); 1512 sii8620_stop_video(ctx); 1513 msleep(100); 1514 sii8620_cbus_reset(ctx); 1515 sii8620_set_mode(ctx, CM_DISCONNECTED); 1516 sii8620_write_seq_static(ctx, 1517 REG_TX_ZONE_CTL1, 0, 1518 REG_MHL_PLL_CTL0, 0x07, 1519 REG_COC_CTL0, 0x40, 1520 REG_CBUS3_CNVT, 0x84, 1521 REG_COC_CTL14, 0x00, 1522 REG_COC_CTL0, 0x40, 1523 REG_HRXCTRL3, 0x07, 1524 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 1525 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 1526 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE, 1527 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE 1528 | BIT_MHL_DP_CTL0_TX_OE_OVR, 1529 REG_MHL_DP_CTL1, 0xBB, 1530 REG_MHL_DP_CTL3, 0x48, 1531 REG_MHL_DP_CTL5, 0x3F, 1532 REG_MHL_DP_CTL2, 0x2F, 1533 REG_MHL_DP_CTL6, 0x2A, 1534 REG_MHL_DP_CTL7, 0x03 1535 ); 1536 sii8620_disable_hpd(ctx); 1537 sii8620_write_seq_static(ctx, 1538 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE, 1539 REG_MHL_COC_CTL1, 0x07, 1540 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1541 REG_DISC_CTRL8, 0x00, 1542 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1543 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1544 REG_INT_CTRL, 0x00, 1545 REG_MSC_HEARTBEAT_CTRL, 0x27, 1546 REG_DISC_CTRL1, 0x25, 1547 REG_CBUS_DISC_INTR0, (u8)~BIT_RGND_READY_INT, 1548 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT, 1549 REG_MDT_INT_1, 0xff, 1550 REG_MDT_INT_1_MASK, 0x00, 1551 REG_MDT_INT_0, 0xff, 1552 REG_MDT_INT_0_MASK, 0x00, 1553 REG_COC_INTR, 0xff, 1554 REG_COC_INTR_MASK, 0x00, 1555 REG_TRXINTH, 0xff, 1556 REG_TRXINTMH, 0x00, 1557 REG_CBUS_INT_0, 0xff, 1558 REG_CBUS_INT_0_MASK, 0x00, 1559 REG_CBUS_INT_1, 0xff, 1560 REG_CBUS_INT_1_MASK, 0x00, 1561 REG_EMSCINTR, 0xff, 1562 REG_EMSCINTRMASK, 0x00, 1563 REG_EMSCINTR1, 0xff, 1564 REG_EMSCINTRMASK1, 0x00, 1565 REG_INTR8, 0xff, 1566 REG_INTR8_MASK, 0x00, 1567 REG_TPI_INTR_ST0, 0xff, 1568 REG_TPI_INTR_EN, 0x00, 1569 REG_HDCP2X_INTR0, 0xff, 1570 REG_HDCP2X_INTR0_MASK, 0x00, 1571 REG_INTR9, 0xff, 1572 REG_INTR9_MASK, 0x00, 1573 REG_INTR3, 0xff, 1574 REG_INTR3_MASK, 0x00, 1575 REG_INTR5, 0xff, 1576 REG_INTR5_MASK, 0x00, 1577 REG_INTR2, 0xff, 1578 REG_INTR2_MASK, 0x00, 1579 ); 1580 memset(ctx->stat, 0, sizeof(ctx->stat)); 1581 memset(ctx->xstat, 0, sizeof(ctx->xstat)); 1582 memset(ctx->devcap, 0, sizeof(ctx->devcap)); 1583 memset(ctx->xdevcap, 0, sizeof(ctx->xdevcap)); 1584 ctx->cbus_status = 0; 1585 ctx->sink_type = SINK_NONE; 1586 kfree(ctx->edid); 1587 ctx->edid = NULL; 1588 sii8620_mt_cleanup(ctx); 1589 } 1590 1591 static void sii8620_mhl_disconnected(struct sii8620 *ctx) 1592 { 1593 sii8620_write_seq_static(ctx, 1594 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1595 REG_CBUS_MSC_COMPAT_CTRL, 1596 BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN 1597 ); 1598 sii8620_disconnect(ctx); 1599 } 1600 1601 static void sii8620_irq_disc(struct sii8620 *ctx) 1602 { 1603 u8 stat = sii8620_readb(ctx, REG_CBUS_DISC_INTR0); 1604 1605 if (stat & VAL_CBUS_MHL_DISCON) 1606 sii8620_mhl_disconnected(ctx); 1607 1608 if (stat & BIT_RGND_READY_INT) { 1609 u8 stat2 = sii8620_readb(ctx, REG_DISC_STAT2); 1610 1611 if ((stat2 & MSK_DISC_STAT2_RGND) == VAL_RGND_1K) { 1612 sii8620_mhl_discover(ctx); 1613 } else { 1614 sii8620_write_seq_static(ctx, 1615 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1616 | BIT_DISC_CTRL9_NOMHL_EST 1617 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1618 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT 1619 | BIT_CBUS_MHL3_DISCON_INT 1620 | BIT_CBUS_MHL12_DISCON_INT 1621 | BIT_NOT_MHL_EST_INT 1622 ); 1623 } 1624 } 1625 if (stat & BIT_MHL_EST_INT) 1626 sii8620_mhl_init(ctx); 1627 1628 sii8620_write(ctx, REG_CBUS_DISC_INTR0, stat); 1629 } 1630 1631 static void sii8620_read_burst(struct sii8620 *ctx) 1632 { 1633 u8 buf[17]; 1634 1635 sii8620_read_buf(ctx, REG_MDT_RCV_READ_PORT, buf, ARRAY_SIZE(buf)); 1636 sii8620_write(ctx, REG_MDT_RCV_CTRL, BIT_MDT_RCV_CTRL_MDT_RCV_EN | 1637 BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN | 1638 BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR); 1639 sii8620_readb(ctx, REG_MDT_RFIFO_STAT); 1640 } 1641 1642 static void sii8620_irq_g2wb(struct sii8620 *ctx) 1643 { 1644 u8 stat = sii8620_readb(ctx, REG_MDT_INT_0); 1645 1646 if (stat & BIT_MDT_IDLE_AFTER_HAWB_DISABLE) 1647 if (sii8620_is_mhl3(ctx)) 1648 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), 1649 MHL_INT_RC_FEAT_COMPLETE); 1650 1651 if (stat & BIT_MDT_RFIFO_DATA_RDY) 1652 sii8620_read_burst(ctx); 1653 1654 if (stat & BIT_MDT_XFIFO_EMPTY) 1655 sii8620_write(ctx, REG_MDT_XMIT_CTRL, 0); 1656 1657 sii8620_write(ctx, REG_MDT_INT_0, stat); 1658 } 1659 1660 static void sii8620_status_dcap_ready(struct sii8620 *ctx) 1661 { 1662 enum sii8620_mode mode; 1663 1664 mode = ctx->stat[MHL_DST_VERSION] >= 0x30 ? CM_MHL3 : CM_MHL1; 1665 if (mode > ctx->mode) 1666 sii8620_set_mode(ctx, mode); 1667 sii8620_peer_specific_init(ctx); 1668 sii8620_write(ctx, REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE 1669 | BIT_INTR9_EDID_DONE | BIT_INTR9_EDID_ERROR); 1670 } 1671 1672 static void sii8620_status_changed_path(struct sii8620 *ctx) 1673 { 1674 if (ctx->stat[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED) { 1675 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE), 1676 MHL_DST_LM_CLK_MODE_NORMAL 1677 | MHL_DST_LM_PATH_ENABLED); 1678 if (!sii8620_is_mhl3(ctx)) 1679 sii8620_mt_read_devcap(ctx, false); 1680 sii8620_mt_set_cont(ctx, sii8620_sink_detected); 1681 } else { 1682 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE), 1683 MHL_DST_LM_CLK_MODE_NORMAL); 1684 } 1685 } 1686 1687 static void sii8620_msc_mr_write_stat(struct sii8620 *ctx) 1688 { 1689 u8 st[MHL_DST_SIZE], xst[MHL_XDS_SIZE]; 1690 1691 sii8620_read_buf(ctx, REG_MHL_STAT_0, st, MHL_DST_SIZE); 1692 sii8620_read_buf(ctx, REG_MHL_EXTSTAT_0, xst, MHL_XDS_SIZE); 1693 1694 sii8620_update_array(ctx->stat, st, MHL_DST_SIZE); 1695 sii8620_update_array(ctx->xstat, xst, MHL_XDS_SIZE); 1696 1697 if (ctx->stat[MHL_DST_CONNECTED_RDY] & MHL_DST_CONN_DCAP_RDY) 1698 sii8620_status_dcap_ready(ctx); 1699 1700 if (st[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED) 1701 sii8620_status_changed_path(ctx); 1702 } 1703 1704 static void sii8620_ecbus_up(struct sii8620 *ctx, int ret) 1705 { 1706 if (ret < 0) 1707 return; 1708 1709 sii8620_set_mode(ctx, CM_ECBUS_S); 1710 } 1711 1712 static void sii8620_got_ecbus_speed(struct sii8620 *ctx, int ret) 1713 { 1714 if (ret < 0) 1715 return; 1716 1717 sii8620_mt_write_stat(ctx, MHL_XDS_REG(CURR_ECBUS_MODE), 1718 MHL_XDS_ECBUS_S | MHL_XDS_SLOT_MODE_8BIT); 1719 sii8620_mt_rap(ctx, MHL_RAP_CBUS_MODE_UP); 1720 sii8620_mt_set_cont(ctx, sii8620_ecbus_up); 1721 } 1722 1723 static void sii8620_mhl_burst_emsc_support_set(struct mhl_burst_emsc_support *d, 1724 enum mhl_burst_id id) 1725 { 1726 sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_EMSC_SUPPORT); 1727 d->num_entries = 1; 1728 d->burst_id[0] = cpu_to_be16(id); 1729 } 1730 1731 static void sii8620_send_features(struct sii8620 *ctx) 1732 { 1733 u8 buf[16]; 1734 1735 sii8620_write(ctx, REG_MDT_XMIT_CTRL, BIT_MDT_XMIT_CTRL_EN 1736 | BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN); 1737 sii8620_mhl_burst_emsc_support_set((void *)buf, 1738 MHL_BURST_ID_HID_PAYLOAD); 1739 sii8620_write_buf(ctx, REG_MDT_XMIT_WRITE_PORT, buf, ARRAY_SIZE(buf)); 1740 } 1741 1742 static bool sii8620_rcp_consume(struct sii8620 *ctx, u8 scancode) 1743 { 1744 bool pressed = !(scancode & MHL_RCP_KEY_RELEASED_MASK); 1745 1746 scancode &= MHL_RCP_KEY_ID_MASK; 1747 1748 if (!ctx->rc_dev) { 1749 dev_dbg(ctx->dev, "RCP input device not initialized\n"); 1750 return false; 1751 } 1752 1753 if (pressed) 1754 rc_keydown(ctx->rc_dev, RC_PROTO_CEC, scancode, 0); 1755 else 1756 rc_keyup(ctx->rc_dev); 1757 1758 return true; 1759 } 1760 1761 static void sii8620_msc_mr_set_int(struct sii8620 *ctx) 1762 { 1763 u8 ints[MHL_INT_SIZE]; 1764 1765 sii8620_read_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE); 1766 sii8620_write_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE); 1767 1768 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_DCAP_CHG) { 1769 switch (ctx->mode) { 1770 case CM_MHL3: 1771 sii8620_mt_read_xdevcap_reg(ctx, MHL_XDC_ECBUS_SPEEDS); 1772 sii8620_mt_set_cont(ctx, sii8620_got_ecbus_speed); 1773 break; 1774 case CM_ECBUS_S: 1775 sii8620_mt_read_devcap(ctx, true); 1776 break; 1777 default: 1778 break; 1779 } 1780 } 1781 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_REQ) 1782 sii8620_send_features(ctx); 1783 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_COMPLETE) 1784 sii8620_edid_read(ctx, 0); 1785 } 1786 1787 static struct sii8620_mt_msg *sii8620_msc_msg_first(struct sii8620 *ctx) 1788 { 1789 struct device *dev = ctx->dev; 1790 1791 if (list_empty(&ctx->mt_queue)) { 1792 dev_err(dev, "unexpected MSC MT response\n"); 1793 return NULL; 1794 } 1795 1796 return list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 1797 } 1798 1799 static void sii8620_msc_mt_done(struct sii8620 *ctx) 1800 { 1801 struct sii8620_mt_msg *msg = sii8620_msc_msg_first(ctx); 1802 1803 if (!msg) 1804 return; 1805 1806 msg->ret = sii8620_readb(ctx, REG_MSC_MT_RCVD_DATA0); 1807 ctx->mt_state = MT_STATE_DONE; 1808 } 1809 1810 static void sii8620_msc_mr_msc_msg(struct sii8620 *ctx) 1811 { 1812 struct sii8620_mt_msg *msg; 1813 u8 buf[2]; 1814 1815 sii8620_read_buf(ctx, REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA, buf, 2); 1816 1817 switch (buf[0]) { 1818 case MHL_MSC_MSG_RAPK: 1819 msg = sii8620_msc_msg_first(ctx); 1820 if (!msg) 1821 return; 1822 msg->ret = buf[1]; 1823 ctx->mt_state = MT_STATE_DONE; 1824 break; 1825 case MHL_MSC_MSG_RCP: 1826 if (!sii8620_rcp_consume(ctx, buf[1])) 1827 sii8620_mt_rcpe(ctx, 1828 MHL_RCPE_STATUS_INEFFECTIVE_KEY_CODE); 1829 sii8620_mt_rcpk(ctx, buf[1]); 1830 break; 1831 default: 1832 dev_err(ctx->dev, "%s message type %d,%d not supported", 1833 __func__, buf[0], buf[1]); 1834 } 1835 } 1836 1837 static void sii8620_irq_msc(struct sii8620 *ctx) 1838 { 1839 u8 stat = sii8620_readb(ctx, REG_CBUS_INT_0); 1840 1841 if (stat & ~BIT_CBUS_HPD_CHG) 1842 sii8620_write(ctx, REG_CBUS_INT_0, stat & ~BIT_CBUS_HPD_CHG); 1843 1844 if (stat & BIT_CBUS_HPD_CHG) { 1845 u8 cbus_stat = sii8620_readb(ctx, REG_CBUS_STATUS); 1846 1847 if ((cbus_stat ^ ctx->cbus_status) & BIT_CBUS_STATUS_CBUS_HPD) { 1848 sii8620_write(ctx, REG_CBUS_INT_0, BIT_CBUS_HPD_CHG); 1849 } else { 1850 stat ^= BIT_CBUS_STATUS_CBUS_HPD; 1851 cbus_stat ^= BIT_CBUS_STATUS_CBUS_HPD; 1852 } 1853 ctx->cbus_status = cbus_stat; 1854 } 1855 1856 if (stat & BIT_CBUS_MSC_MR_WRITE_STAT) 1857 sii8620_msc_mr_write_stat(ctx); 1858 1859 if (stat & BIT_CBUS_MSC_MR_SET_INT) 1860 sii8620_msc_mr_set_int(ctx); 1861 1862 if (stat & BIT_CBUS_MSC_MT_DONE) 1863 sii8620_msc_mt_done(ctx); 1864 1865 if (stat & BIT_CBUS_MSC_MR_MSC_MSG) 1866 sii8620_msc_mr_msc_msg(ctx); 1867 } 1868 1869 static void sii8620_irq_coc(struct sii8620 *ctx) 1870 { 1871 u8 stat = sii8620_readb(ctx, REG_COC_INTR); 1872 1873 if (stat & BIT_COC_CALIBRATION_DONE) { 1874 u8 cstat = sii8620_readb(ctx, REG_COC_STAT_0); 1875 1876 cstat &= BIT_COC_STAT_0_PLL_LOCKED | MSK_COC_STAT_0_FSM_STATE; 1877 if (cstat == (BIT_COC_STAT_0_PLL_LOCKED | 0x02)) { 1878 sii8620_write_seq_static(ctx, 1879 REG_COC_CTLB, 0, 1880 REG_TRXINTMH, BIT_TDM_INTR_SYNC_DATA 1881 | BIT_TDM_INTR_SYNC_WAIT 1882 ); 1883 } 1884 } 1885 1886 sii8620_write(ctx, REG_COC_INTR, stat); 1887 } 1888 1889 static void sii8620_irq_merr(struct sii8620 *ctx) 1890 { 1891 u8 stat = sii8620_readb(ctx, REG_CBUS_INT_1); 1892 1893 sii8620_write(ctx, REG_CBUS_INT_1, stat); 1894 } 1895 1896 static void sii8620_irq_edid(struct sii8620 *ctx) 1897 { 1898 u8 stat = sii8620_readb(ctx, REG_INTR9); 1899 1900 sii8620_write(ctx, REG_INTR9, stat); 1901 1902 if (stat & BIT_INTR9_DEVCAP_DONE) 1903 ctx->mt_state = MT_STATE_DONE; 1904 } 1905 1906 static void sii8620_irq_scdt(struct sii8620 *ctx) 1907 { 1908 u8 stat = sii8620_readb(ctx, REG_INTR5); 1909 1910 if (stat & BIT_INTR_SCDT_CHANGE) { 1911 u8 cstat = sii8620_readb(ctx, REG_TMDS_CSTAT_P3); 1912 1913 if (cstat & BIT_TMDS_CSTAT_P3_SCDT) 1914 sii8620_start_video(ctx); 1915 } 1916 1917 sii8620_write(ctx, REG_INTR5, stat); 1918 } 1919 1920 static void sii8620_got_xdevcap(struct sii8620 *ctx, int ret) 1921 { 1922 if (ret < 0) 1923 return; 1924 1925 sii8620_mt_read_devcap(ctx, false); 1926 } 1927 1928 static void sii8620_irq_tdm(struct sii8620 *ctx) 1929 { 1930 u8 stat = sii8620_readb(ctx, REG_TRXINTH); 1931 u8 tdm = sii8620_readb(ctx, REG_TRXSTA2); 1932 1933 if ((tdm & MSK_TDM_SYNCHRONIZED) == VAL_TDM_SYNCHRONIZED) { 1934 ctx->mode = CM_ECBUS_S; 1935 ctx->burst.rx_ack = 0; 1936 ctx->burst.r_size = SII8620_BURST_BUF_LEN; 1937 sii8620_burst_tx_rbuf_info(ctx, SII8620_BURST_BUF_LEN); 1938 sii8620_mt_read_devcap(ctx, true); 1939 sii8620_mt_set_cont(ctx, sii8620_got_xdevcap); 1940 } else { 1941 sii8620_write_seq_static(ctx, 1942 REG_MHL_PLL_CTL2, 0, 1943 REG_MHL_PLL_CTL2, BIT_MHL_PLL_CTL2_CLKDETECT_EN 1944 ); 1945 } 1946 1947 sii8620_write(ctx, REG_TRXINTH, stat); 1948 } 1949 1950 static void sii8620_irq_block(struct sii8620 *ctx) 1951 { 1952 u8 stat = sii8620_readb(ctx, REG_EMSCINTR); 1953 1954 if (stat & BIT_EMSCINTR_SPI_DVLD) { 1955 u8 bstat = sii8620_readb(ctx, REG_SPIBURSTSTAT); 1956 1957 if (bstat & BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE) 1958 sii8620_burst_receive(ctx); 1959 } 1960 1961 sii8620_write(ctx, REG_EMSCINTR, stat); 1962 } 1963 1964 static void sii8620_irq_ddc(struct sii8620 *ctx) 1965 { 1966 u8 stat = sii8620_readb(ctx, REG_INTR3); 1967 1968 if (stat & BIT_DDC_CMD_DONE) { 1969 sii8620_write(ctx, REG_INTR3_MASK, 0); 1970 if (sii8620_is_mhl3(ctx)) 1971 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), 1972 MHL_INT_RC_FEAT_REQ); 1973 else 1974 sii8620_edid_read(ctx, 0); 1975 } 1976 sii8620_write(ctx, REG_INTR3, stat); 1977 } 1978 1979 /* endian agnostic, non-volatile version of test_bit */ 1980 static bool sii8620_test_bit(unsigned int nr, const u8 *addr) 1981 { 1982 return 1 & (addr[nr / BITS_PER_BYTE] >> (nr % BITS_PER_BYTE)); 1983 } 1984 1985 static irqreturn_t sii8620_irq_thread(int irq, void *data) 1986 { 1987 static const struct { 1988 int bit; 1989 void (*handler)(struct sii8620 *ctx); 1990 } irq_vec[] = { 1991 { BIT_FAST_INTR_STAT_DISC, sii8620_irq_disc }, 1992 { BIT_FAST_INTR_STAT_G2WB, sii8620_irq_g2wb }, 1993 { BIT_FAST_INTR_STAT_COC, sii8620_irq_coc }, 1994 { BIT_FAST_INTR_STAT_TDM, sii8620_irq_tdm }, 1995 { BIT_FAST_INTR_STAT_MSC, sii8620_irq_msc }, 1996 { BIT_FAST_INTR_STAT_MERR, sii8620_irq_merr }, 1997 { BIT_FAST_INTR_STAT_BLOCK, sii8620_irq_block }, 1998 { BIT_FAST_INTR_STAT_EDID, sii8620_irq_edid }, 1999 { BIT_FAST_INTR_STAT_DDC, sii8620_irq_ddc }, 2000 { BIT_FAST_INTR_STAT_SCDT, sii8620_irq_scdt }, 2001 }; 2002 struct sii8620 *ctx = data; 2003 u8 stats[LEN_FAST_INTR_STAT]; 2004 int i, ret; 2005 2006 mutex_lock(&ctx->lock); 2007 2008 sii8620_read_buf(ctx, REG_FAST_INTR_STAT, stats, ARRAY_SIZE(stats)); 2009 for (i = 0; i < ARRAY_SIZE(irq_vec); ++i) 2010 if (sii8620_test_bit(irq_vec[i].bit, stats)) 2011 irq_vec[i].handler(ctx); 2012 2013 sii8620_burst_rx_all(ctx); 2014 sii8620_mt_work(ctx); 2015 sii8620_burst_send(ctx); 2016 2017 ret = sii8620_clear_error(ctx); 2018 if (ret) { 2019 dev_err(ctx->dev, "Error during IRQ handling, %d.\n", ret); 2020 sii8620_mhl_disconnected(ctx); 2021 } 2022 mutex_unlock(&ctx->lock); 2023 2024 return IRQ_HANDLED; 2025 } 2026 2027 static void sii8620_cable_in(struct sii8620 *ctx) 2028 { 2029 struct device *dev = ctx->dev; 2030 u8 ver[5]; 2031 int ret; 2032 2033 ret = sii8620_hw_on(ctx); 2034 if (ret) { 2035 dev_err(dev, "Error powering on, %d.\n", ret); 2036 return; 2037 } 2038 2039 sii8620_read_buf(ctx, REG_VND_IDL, ver, ARRAY_SIZE(ver)); 2040 ret = sii8620_clear_error(ctx); 2041 if (ret) { 2042 dev_err(dev, "Error accessing I2C bus, %d.\n", ret); 2043 return; 2044 } 2045 2046 dev_info(dev, "ChipID %02x%02x:%02x%02x rev %02x.\n", ver[1], ver[0], 2047 ver[3], ver[2], ver[4]); 2048 2049 sii8620_write(ctx, REG_DPD, 2050 BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN); 2051 2052 sii8620_xtal_set_rate(ctx); 2053 sii8620_disconnect(ctx); 2054 2055 sii8620_write_seq_static(ctx, 2056 REG_MHL_CBUS_CTL0, VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONG 2057 | VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_734, 2058 REG_MHL_CBUS_CTL1, VAL_MHL_CBUS_CTL1_1115_OHM, 2059 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN, 2060 ); 2061 2062 ret = sii8620_clear_error(ctx); 2063 if (ret) { 2064 dev_err(dev, "Error accessing I2C bus, %d.\n", ret); 2065 return; 2066 } 2067 2068 enable_irq(to_i2c_client(ctx->dev)->irq); 2069 } 2070 2071 static void sii8620_init_rcp_input_dev(struct sii8620 *ctx) 2072 { 2073 struct rc_dev *rc_dev; 2074 int ret; 2075 2076 rc_dev = rc_allocate_device(RC_DRIVER_SCANCODE); 2077 if (!rc_dev) { 2078 dev_err(ctx->dev, "Failed to allocate RC device\n"); 2079 ctx->error = -ENOMEM; 2080 return; 2081 } 2082 2083 rc_dev->input_phys = "sii8620/input0"; 2084 rc_dev->input_id.bustype = BUS_VIRTUAL; 2085 rc_dev->map_name = RC_MAP_CEC; 2086 rc_dev->allowed_protocols = RC_PROTO_BIT_CEC; 2087 rc_dev->driver_name = "sii8620"; 2088 rc_dev->device_name = "sii8620"; 2089 2090 ret = rc_register_device(rc_dev); 2091 2092 if (ret) { 2093 dev_err(ctx->dev, "Failed to register RC device\n"); 2094 ctx->error = ret; 2095 rc_free_device(ctx->rc_dev); 2096 return; 2097 } 2098 ctx->rc_dev = rc_dev; 2099 } 2100 2101 static void sii8620_cable_out(struct sii8620 *ctx) 2102 { 2103 disable_irq(to_i2c_client(ctx->dev)->irq); 2104 sii8620_hw_off(ctx); 2105 } 2106 2107 static void sii8620_extcon_work(struct work_struct *work) 2108 { 2109 struct sii8620 *ctx = 2110 container_of(work, struct sii8620, extcon_wq); 2111 int state = extcon_get_state(ctx->extcon, EXTCON_DISP_MHL); 2112 2113 if (state == ctx->cable_state) 2114 return; 2115 2116 ctx->cable_state = state; 2117 2118 if (state > 0) 2119 sii8620_cable_in(ctx); 2120 else 2121 sii8620_cable_out(ctx); 2122 } 2123 2124 static int sii8620_extcon_notifier(struct notifier_block *self, 2125 unsigned long event, void *ptr) 2126 { 2127 struct sii8620 *ctx = 2128 container_of(self, struct sii8620, extcon_nb); 2129 2130 schedule_work(&ctx->extcon_wq); 2131 2132 return NOTIFY_DONE; 2133 } 2134 2135 static int sii8620_extcon_init(struct sii8620 *ctx) 2136 { 2137 struct extcon_dev *edev; 2138 struct device_node *musb, *muic; 2139 int ret; 2140 2141 /* get micro-USB connector node */ 2142 musb = of_graph_get_remote_node(ctx->dev->of_node, 1, -1); 2143 /* next get micro-USB Interface Controller node */ 2144 muic = of_get_next_parent(musb); 2145 2146 if (!muic) { 2147 dev_info(ctx->dev, "no extcon found, switching to 'always on' mode\n"); 2148 return 0; 2149 } 2150 2151 edev = extcon_find_edev_by_node(muic); 2152 of_node_put(muic); 2153 if (IS_ERR(edev)) { 2154 if (PTR_ERR(edev) == -EPROBE_DEFER) 2155 return -EPROBE_DEFER; 2156 dev_err(ctx->dev, "Invalid or missing extcon\n"); 2157 return PTR_ERR(edev); 2158 } 2159 2160 ctx->extcon = edev; 2161 ctx->extcon_nb.notifier_call = sii8620_extcon_notifier; 2162 INIT_WORK(&ctx->extcon_wq, sii8620_extcon_work); 2163 ret = extcon_register_notifier(edev, EXTCON_DISP_MHL, &ctx->extcon_nb); 2164 if (ret) { 2165 dev_err(ctx->dev, "failed to register notifier for MHL\n"); 2166 return ret; 2167 } 2168 2169 return 0; 2170 } 2171 2172 static inline struct sii8620 *bridge_to_sii8620(struct drm_bridge *bridge) 2173 { 2174 return container_of(bridge, struct sii8620, bridge); 2175 } 2176 2177 static int sii8620_attach(struct drm_bridge *bridge) 2178 { 2179 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2180 2181 sii8620_init_rcp_input_dev(ctx); 2182 2183 return sii8620_clear_error(ctx); 2184 } 2185 2186 static void sii8620_detach(struct drm_bridge *bridge) 2187 { 2188 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2189 2190 rc_unregister_device(ctx->rc_dev); 2191 } 2192 2193 static int sii8620_is_packing_required(struct sii8620 *ctx, 2194 const struct drm_display_mode *mode) 2195 { 2196 int max_pclk, max_pclk_pp_mode; 2197 2198 if (sii8620_is_mhl3(ctx)) { 2199 max_pclk = MHL3_MAX_PCLK; 2200 max_pclk_pp_mode = MHL3_MAX_PCLK_PP_MODE; 2201 } else { 2202 max_pclk = MHL1_MAX_PCLK; 2203 max_pclk_pp_mode = MHL1_MAX_PCLK_PP_MODE; 2204 } 2205 2206 if (mode->clock < max_pclk) 2207 return 0; 2208 else if (mode->clock < max_pclk_pp_mode) 2209 return 1; 2210 else 2211 return -1; 2212 } 2213 2214 static enum drm_mode_status sii8620_mode_valid(struct drm_bridge *bridge, 2215 const struct drm_display_mode *mode) 2216 { 2217 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2218 int pack_required = sii8620_is_packing_required(ctx, mode); 2219 bool can_pack = ctx->devcap[MHL_DCAP_VID_LINK_MODE] & 2220 MHL_DCAP_VID_LINK_PPIXEL; 2221 2222 switch (pack_required) { 2223 case 0: 2224 return MODE_OK; 2225 case 1: 2226 return (can_pack) ? MODE_OK : MODE_CLOCK_HIGH; 2227 default: 2228 return MODE_CLOCK_HIGH; 2229 } 2230 } 2231 2232 static bool sii8620_mode_fixup(struct drm_bridge *bridge, 2233 const struct drm_display_mode *mode, 2234 struct drm_display_mode *adjusted_mode) 2235 { 2236 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2237 2238 mutex_lock(&ctx->lock); 2239 2240 ctx->use_packed_pixel = sii8620_is_packing_required(ctx, adjusted_mode); 2241 ctx->video_code = drm_match_cea_mode(adjusted_mode); 2242 ctx->pixel_clock = adjusted_mode->clock; 2243 2244 mutex_unlock(&ctx->lock); 2245 2246 return true; 2247 } 2248 2249 static const struct drm_bridge_funcs sii8620_bridge_funcs = { 2250 .attach = sii8620_attach, 2251 .detach = sii8620_detach, 2252 .mode_fixup = sii8620_mode_fixup, 2253 .mode_valid = sii8620_mode_valid, 2254 }; 2255 2256 static int sii8620_probe(struct i2c_client *client, 2257 const struct i2c_device_id *id) 2258 { 2259 struct device *dev = &client->dev; 2260 struct sii8620 *ctx; 2261 int ret; 2262 2263 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 2264 if (!ctx) 2265 return -ENOMEM; 2266 2267 ctx->dev = dev; 2268 mutex_init(&ctx->lock); 2269 INIT_LIST_HEAD(&ctx->mt_queue); 2270 2271 ctx->clk_xtal = devm_clk_get(dev, "xtal"); 2272 if (IS_ERR(ctx->clk_xtal)) { 2273 dev_err(dev, "failed to get xtal clock from DT\n"); 2274 return PTR_ERR(ctx->clk_xtal); 2275 } 2276 2277 if (!client->irq) { 2278 dev_err(dev, "no irq provided\n"); 2279 return -EINVAL; 2280 } 2281 irq_set_status_flags(client->irq, IRQ_NOAUTOEN); 2282 ret = devm_request_threaded_irq(dev, client->irq, NULL, 2283 sii8620_irq_thread, 2284 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 2285 "sii8620", ctx); 2286 if (ret < 0) { 2287 dev_err(dev, "failed to install IRQ handler\n"); 2288 return ret; 2289 } 2290 2291 ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); 2292 if (IS_ERR(ctx->gpio_reset)) { 2293 dev_err(dev, "failed to get reset gpio from DT\n"); 2294 return PTR_ERR(ctx->gpio_reset); 2295 } 2296 2297 ctx->supplies[0].supply = "cvcc10"; 2298 ctx->supplies[1].supply = "iovcc18"; 2299 ret = devm_regulator_bulk_get(dev, 2, ctx->supplies); 2300 if (ret) 2301 return ret; 2302 2303 ret = sii8620_extcon_init(ctx); 2304 if (ret < 0) { 2305 dev_err(ctx->dev, "failed to initialize EXTCON\n"); 2306 return ret; 2307 } 2308 2309 i2c_set_clientdata(client, ctx); 2310 2311 ctx->bridge.funcs = &sii8620_bridge_funcs; 2312 ctx->bridge.of_node = dev->of_node; 2313 drm_bridge_add(&ctx->bridge); 2314 2315 if (!ctx->extcon) 2316 sii8620_cable_in(ctx); 2317 2318 return 0; 2319 } 2320 2321 static int sii8620_remove(struct i2c_client *client) 2322 { 2323 struct sii8620 *ctx = i2c_get_clientdata(client); 2324 2325 if (ctx->extcon) { 2326 extcon_unregister_notifier(ctx->extcon, EXTCON_DISP_MHL, 2327 &ctx->extcon_nb); 2328 flush_work(&ctx->extcon_wq); 2329 if (ctx->cable_state > 0) 2330 sii8620_cable_out(ctx); 2331 } else { 2332 sii8620_cable_out(ctx); 2333 } 2334 drm_bridge_remove(&ctx->bridge); 2335 2336 return 0; 2337 } 2338 2339 static const struct of_device_id sii8620_dt_match[] = { 2340 { .compatible = "sil,sii8620" }, 2341 { }, 2342 }; 2343 MODULE_DEVICE_TABLE(of, sii8620_dt_match); 2344 2345 static const struct i2c_device_id sii8620_id[] = { 2346 { "sii8620", 0 }, 2347 { }, 2348 }; 2349 2350 MODULE_DEVICE_TABLE(i2c, sii8620_id); 2351 static struct i2c_driver sii8620_driver = { 2352 .driver = { 2353 .name = "sii8620", 2354 .of_match_table = of_match_ptr(sii8620_dt_match), 2355 }, 2356 .probe = sii8620_probe, 2357 .remove = sii8620_remove, 2358 .id_table = sii8620_id, 2359 }; 2360 2361 module_i2c_driver(sii8620_driver); 2362 MODULE_LICENSE("GPL v2"); 2363