1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Samsung MIPI DSIM bridge driver. 4 * 5 * Copyright (C) 2021 Amarula Solutions(India) 6 * Copyright (c) 2014 Samsung Electronics Co., Ltd 7 * Author: Jagan Teki <jagan@amarulasolutions.com> 8 * 9 * Based on exynos_drm_dsi from 10 * Tomasz Figa <t.figa@samsung.com> 11 */ 12 13 #include <asm/unaligned.h> 14 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/irq.h> 18 #include <linux/media-bus-format.h> 19 #include <linux/of.h> 20 #include <linux/phy/phy.h> 21 #include <linux/platform_device.h> 22 23 #include <video/mipi_display.h> 24 25 #include <drm/bridge/samsung-dsim.h> 26 #include <drm/drm_panel.h> 27 #include <drm/drm_print.h> 28 29 /* returns true iff both arguments logically differs */ 30 #define NEQV(a, b) (!(a) ^ !(b)) 31 32 /* DSIM_STATUS */ 33 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) 34 #define DSIM_STOP_STATE_CLK BIT(8) 35 #define DSIM_TX_READY_HS_CLK BIT(10) 36 #define DSIM_PLL_STABLE BIT(31) 37 38 /* DSIM_SWRST */ 39 #define DSIM_FUNCRST BIT(16) 40 #define DSIM_SWRST BIT(0) 41 42 /* DSIM_TIMEOUT */ 43 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) 44 #define DSIM_BTA_TIMEOUT(x) ((x) << 16) 45 46 /* DSIM_CLKCTRL */ 47 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) 48 #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) 49 #define DSIM_LANE_ESC_CLK_EN_CLK BIT(19) 50 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) 51 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) 52 #define DSIM_BYTE_CLKEN BIT(24) 53 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) 54 #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) 55 #define DSIM_PLL_BYPASS BIT(27) 56 #define DSIM_ESC_CLKEN BIT(28) 57 #define DSIM_TX_REQUEST_HSCLK BIT(31) 58 59 /* DSIM_CONFIG */ 60 #define DSIM_LANE_EN_CLK BIT(0) 61 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) 62 #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) 63 #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) 64 #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) 65 #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) 66 #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) 67 #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) 68 #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) 69 #define DSIM_SUB_VC (((x) & 0x3) << 16) 70 #define DSIM_MAIN_VC (((x) & 0x3) << 18) 71 #define DSIM_HSA_DISABLE_MODE BIT(20) 72 #define DSIM_HBP_DISABLE_MODE BIT(21) 73 #define DSIM_HFP_DISABLE_MODE BIT(22) 74 /* 75 * The i.MX 8M Mini Applications Processor Reference Manual, 76 * Rev. 3, 11/2020 Page 4091 77 * The i.MX 8M Nano Applications Processor Reference Manual, 78 * Rev. 2, 07/2022 Page 3058 79 * The i.MX 8M Plus Applications Processor Reference Manual, 80 * Rev. 1, 06/2021 Page 5436 81 * all claims this bit is 'HseDisableMode' with the definition 82 * 0 = Disables transfer 83 * 1 = Enables transfer 84 * 85 * This clearly states that HSE is not a disabled bit. 86 * 87 * The naming convention follows as per the manual and the 88 * driver logic is based on the MIPI_DSI_MODE_VIDEO_HSE flag. 89 */ 90 #define DSIM_HSE_DISABLE_MODE BIT(23) 91 #define DSIM_AUTO_MODE BIT(24) 92 #define DSIM_VIDEO_MODE BIT(25) 93 #define DSIM_BURST_MODE BIT(26) 94 #define DSIM_SYNC_INFORM BIT(27) 95 #define DSIM_EOT_DISABLE BIT(28) 96 #define DSIM_MFLUSH_VS BIT(29) 97 /* This flag is valid only for exynos3250/3472/5260/5430 */ 98 #define DSIM_CLKLANE_STOP BIT(30) 99 100 /* DSIM_ESCMODE */ 101 #define DSIM_TX_TRIGGER_RST BIT(4) 102 #define DSIM_TX_LPDT_LP BIT(6) 103 #define DSIM_CMD_LPDT_LP BIT(7) 104 #define DSIM_FORCE_BTA BIT(16) 105 #define DSIM_FORCE_STOP_STATE BIT(20) 106 #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) 107 #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) 108 109 /* DSIM_MDRESOL */ 110 #define DSIM_MAIN_STAND_BY BIT(31) 111 #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16) 112 #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0) 113 114 /* DSIM_MVPORCH */ 115 #define DSIM_CMD_ALLOW(x) ((x) << 28) 116 #define DSIM_STABLE_VFP(x) ((x) << 16) 117 #define DSIM_MAIN_VBP(x) ((x) << 0) 118 #define DSIM_CMD_ALLOW_MASK (0xf << 28) 119 #define DSIM_STABLE_VFP_MASK (0x7ff << 16) 120 #define DSIM_MAIN_VBP_MASK (0x7ff << 0) 121 122 /* DSIM_MHPORCH */ 123 #define DSIM_MAIN_HFP(x) ((x) << 16) 124 #define DSIM_MAIN_HBP(x) ((x) << 0) 125 #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) 126 #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) 127 128 /* DSIM_MSYNC */ 129 #define DSIM_MAIN_VSA(x) ((x) << 22) 130 #define DSIM_MAIN_HSA(x) ((x) << 0) 131 #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) 132 #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) 133 134 /* DSIM_SDRESOL */ 135 #define DSIM_SUB_STANDY(x) ((x) << 31) 136 #define DSIM_SUB_VRESOL(x) ((x) << 16) 137 #define DSIM_SUB_HRESOL(x) ((x) << 0) 138 #define DSIM_SUB_STANDY_MASK ((0x1) << 31) 139 #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) 140 #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) 141 142 /* DSIM_INTSRC */ 143 #define DSIM_INT_PLL_STABLE BIT(31) 144 #define DSIM_INT_SW_RST_RELEASE BIT(30) 145 #define DSIM_INT_SFR_FIFO_EMPTY BIT(29) 146 #define DSIM_INT_SFR_HDR_FIFO_EMPTY BIT(28) 147 #define DSIM_INT_BTA BIT(25) 148 #define DSIM_INT_FRAME_DONE BIT(24) 149 #define DSIM_INT_RX_TIMEOUT BIT(21) 150 #define DSIM_INT_BTA_TIMEOUT BIT(20) 151 #define DSIM_INT_RX_DONE BIT(18) 152 #define DSIM_INT_RX_TE BIT(17) 153 #define DSIM_INT_RX_ACK BIT(16) 154 #define DSIM_INT_RX_ECC_ERR BIT(15) 155 #define DSIM_INT_RX_CRC_ERR BIT(14) 156 157 /* DSIM_FIFOCTRL */ 158 #define DSIM_RX_DATA_FULL BIT(25) 159 #define DSIM_RX_DATA_EMPTY BIT(24) 160 #define DSIM_SFR_HEADER_FULL BIT(23) 161 #define DSIM_SFR_HEADER_EMPTY BIT(22) 162 #define DSIM_SFR_PAYLOAD_FULL BIT(21) 163 #define DSIM_SFR_PAYLOAD_EMPTY BIT(20) 164 #define DSIM_I80_HEADER_FULL BIT(19) 165 #define DSIM_I80_HEADER_EMPTY BIT(18) 166 #define DSIM_I80_PAYLOAD_FULL BIT(17) 167 #define DSIM_I80_PAYLOAD_EMPTY BIT(16) 168 #define DSIM_SD_HEADER_FULL BIT(15) 169 #define DSIM_SD_HEADER_EMPTY BIT(14) 170 #define DSIM_SD_PAYLOAD_FULL BIT(13) 171 #define DSIM_SD_PAYLOAD_EMPTY BIT(12) 172 #define DSIM_MD_HEADER_FULL BIT(11) 173 #define DSIM_MD_HEADER_EMPTY BIT(10) 174 #define DSIM_MD_PAYLOAD_FULL BIT(9) 175 #define DSIM_MD_PAYLOAD_EMPTY BIT(8) 176 #define DSIM_RX_FIFO BIT(4) 177 #define DSIM_SFR_FIFO BIT(3) 178 #define DSIM_I80_FIFO BIT(2) 179 #define DSIM_SD_FIFO BIT(1) 180 #define DSIM_MD_FIFO BIT(0) 181 182 /* DSIM_PHYACCHR */ 183 #define DSIM_AFC_EN BIT(14) 184 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) 185 186 /* DSIM_PLLCTRL */ 187 #define DSIM_PLL_DPDNSWAP_CLK (1 << 25) 188 #define DSIM_PLL_DPDNSWAP_DAT (1 << 24) 189 #define DSIM_FREQ_BAND(x) ((x) << 24) 190 #define DSIM_PLL_EN BIT(23) 191 #define DSIM_PLL_P(x, offset) ((x) << (offset)) 192 #define DSIM_PLL_M(x) ((x) << 4) 193 #define DSIM_PLL_S(x) ((x) << 1) 194 195 /* DSIM_PHYCTRL */ 196 #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) 197 #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP BIT(30) 198 #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP BIT(14) 199 200 /* DSIM_PHYTIMING */ 201 #define DSIM_PHYTIMING_LPX(x) ((x) << 8) 202 #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0) 203 204 /* DSIM_PHYTIMING1 */ 205 #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24) 206 #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16) 207 #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8) 208 #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0) 209 210 /* DSIM_PHYTIMING2 */ 211 #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16) 212 #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8) 213 #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0) 214 215 #define DSI_MAX_BUS_WIDTH 4 216 #define DSI_NUM_VIRTUAL_CHANNELS 4 217 #define DSI_TX_FIFO_SIZE 2048 218 #define DSI_RX_FIFO_SIZE 256 219 #define DSI_XFER_TIMEOUT_MS 100 220 #define DSI_RX_FIFO_EMPTY 0x30800002 221 222 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" 223 224 #define PS_TO_CYCLE(ps, hz) DIV64_U64_ROUND_CLOSEST(((ps) * (hz)), 1000000000000ULL) 225 226 static const char *const clk_names[5] = { 227 "bus_clk", 228 "sclk_mipi", 229 "phyclk_mipidphy0_bitclkdiv8", 230 "phyclk_mipidphy0_rxclkesc0", 231 "sclk_rgb_vclk_to_dsim0" 232 }; 233 234 enum samsung_dsim_transfer_type { 235 EXYNOS_DSI_TX, 236 EXYNOS_DSI_RX, 237 }; 238 239 enum reg_idx { 240 DSIM_STATUS_REG, /* Status register */ 241 DSIM_SWRST_REG, /* Software reset register */ 242 DSIM_CLKCTRL_REG, /* Clock control register */ 243 DSIM_TIMEOUT_REG, /* Time out register */ 244 DSIM_CONFIG_REG, /* Configuration register */ 245 DSIM_ESCMODE_REG, /* Escape mode register */ 246 DSIM_MDRESOL_REG, 247 DSIM_MVPORCH_REG, /* Main display Vporch register */ 248 DSIM_MHPORCH_REG, /* Main display Hporch register */ 249 DSIM_MSYNC_REG, /* Main display sync area register */ 250 DSIM_INTSRC_REG, /* Interrupt source register */ 251 DSIM_INTMSK_REG, /* Interrupt mask register */ 252 DSIM_PKTHDR_REG, /* Packet Header FIFO register */ 253 DSIM_PAYLOAD_REG, /* Payload FIFO register */ 254 DSIM_RXFIFO_REG, /* Read FIFO register */ 255 DSIM_FIFOCTRL_REG, /* FIFO status and control register */ 256 DSIM_PLLCTRL_REG, /* PLL control register */ 257 DSIM_PHYCTRL_REG, 258 DSIM_PHYTIMING_REG, 259 DSIM_PHYTIMING1_REG, 260 DSIM_PHYTIMING2_REG, 261 NUM_REGS 262 }; 263 264 static const unsigned int exynos_reg_ofs[] = { 265 [DSIM_STATUS_REG] = 0x00, 266 [DSIM_SWRST_REG] = 0x04, 267 [DSIM_CLKCTRL_REG] = 0x08, 268 [DSIM_TIMEOUT_REG] = 0x0c, 269 [DSIM_CONFIG_REG] = 0x10, 270 [DSIM_ESCMODE_REG] = 0x14, 271 [DSIM_MDRESOL_REG] = 0x18, 272 [DSIM_MVPORCH_REG] = 0x1c, 273 [DSIM_MHPORCH_REG] = 0x20, 274 [DSIM_MSYNC_REG] = 0x24, 275 [DSIM_INTSRC_REG] = 0x2c, 276 [DSIM_INTMSK_REG] = 0x30, 277 [DSIM_PKTHDR_REG] = 0x34, 278 [DSIM_PAYLOAD_REG] = 0x38, 279 [DSIM_RXFIFO_REG] = 0x3c, 280 [DSIM_FIFOCTRL_REG] = 0x44, 281 [DSIM_PLLCTRL_REG] = 0x4c, 282 [DSIM_PHYCTRL_REG] = 0x5c, 283 [DSIM_PHYTIMING_REG] = 0x64, 284 [DSIM_PHYTIMING1_REG] = 0x68, 285 [DSIM_PHYTIMING2_REG] = 0x6c, 286 }; 287 288 static const unsigned int exynos5433_reg_ofs[] = { 289 [DSIM_STATUS_REG] = 0x04, 290 [DSIM_SWRST_REG] = 0x0C, 291 [DSIM_CLKCTRL_REG] = 0x10, 292 [DSIM_TIMEOUT_REG] = 0x14, 293 [DSIM_CONFIG_REG] = 0x18, 294 [DSIM_ESCMODE_REG] = 0x1C, 295 [DSIM_MDRESOL_REG] = 0x20, 296 [DSIM_MVPORCH_REG] = 0x24, 297 [DSIM_MHPORCH_REG] = 0x28, 298 [DSIM_MSYNC_REG] = 0x2C, 299 [DSIM_INTSRC_REG] = 0x34, 300 [DSIM_INTMSK_REG] = 0x38, 301 [DSIM_PKTHDR_REG] = 0x3C, 302 [DSIM_PAYLOAD_REG] = 0x40, 303 [DSIM_RXFIFO_REG] = 0x44, 304 [DSIM_FIFOCTRL_REG] = 0x4C, 305 [DSIM_PLLCTRL_REG] = 0x94, 306 [DSIM_PHYCTRL_REG] = 0xA4, 307 [DSIM_PHYTIMING_REG] = 0xB4, 308 [DSIM_PHYTIMING1_REG] = 0xB8, 309 [DSIM_PHYTIMING2_REG] = 0xBC, 310 }; 311 312 enum reg_value_idx { 313 RESET_TYPE, 314 PLL_TIMER, 315 STOP_STATE_CNT, 316 PHYCTRL_ULPS_EXIT, 317 PHYCTRL_VREG_LP, 318 PHYCTRL_SLEW_UP, 319 PHYTIMING_LPX, 320 PHYTIMING_HS_EXIT, 321 PHYTIMING_CLK_PREPARE, 322 PHYTIMING_CLK_ZERO, 323 PHYTIMING_CLK_POST, 324 PHYTIMING_CLK_TRAIL, 325 PHYTIMING_HS_PREPARE, 326 PHYTIMING_HS_ZERO, 327 PHYTIMING_HS_TRAIL 328 }; 329 330 static const unsigned int reg_values[] = { 331 [RESET_TYPE] = DSIM_SWRST, 332 [PLL_TIMER] = 500, 333 [STOP_STATE_CNT] = 0xf, 334 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), 335 [PHYCTRL_VREG_LP] = 0, 336 [PHYCTRL_SLEW_UP] = 0, 337 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), 338 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), 339 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), 340 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), 341 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), 342 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), 343 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), 344 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), 345 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), 346 }; 347 348 static const unsigned int exynos5422_reg_values[] = { 349 [RESET_TYPE] = DSIM_SWRST, 350 [PLL_TIMER] = 500, 351 [STOP_STATE_CNT] = 0xf, 352 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), 353 [PHYCTRL_VREG_LP] = 0, 354 [PHYCTRL_SLEW_UP] = 0, 355 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08), 356 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d), 357 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 358 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30), 359 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 360 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a), 361 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c), 362 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11), 363 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d), 364 }; 365 366 static const unsigned int exynos5433_reg_values[] = { 367 [RESET_TYPE] = DSIM_FUNCRST, 368 [PLL_TIMER] = 22200, 369 [STOP_STATE_CNT] = 0xa, 370 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), 371 [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, 372 [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, 373 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), 374 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), 375 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 376 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), 377 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 378 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), 379 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), 380 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), 381 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), 382 }; 383 384 static const unsigned int imx8mm_dsim_reg_values[] = { 385 [RESET_TYPE] = DSIM_SWRST, 386 [PLL_TIMER] = 500, 387 [STOP_STATE_CNT] = 0xf, 388 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), 389 [PHYCTRL_VREG_LP] = 0, 390 [PHYCTRL_SLEW_UP] = 0, 391 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), 392 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), 393 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), 394 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x26), 395 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), 396 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), 397 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x08), 398 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), 399 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), 400 }; 401 402 static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { 403 .reg_ofs = exynos_reg_ofs, 404 .plltmr_reg = 0x50, 405 .has_freqband = 1, 406 .has_clklane_stop = 1, 407 .num_clks = 2, 408 .max_freq = 1000, 409 .wait_for_reset = 1, 410 .num_bits_resol = 11, 411 .pll_p_offset = 13, 412 .reg_values = reg_values, 413 .m_min = 41, 414 .m_max = 125, 415 .min_freq = 500, 416 .has_broken_fifoctrl_emptyhdr = 1, 417 }; 418 419 static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = { 420 .reg_ofs = exynos_reg_ofs, 421 .plltmr_reg = 0x50, 422 .has_freqband = 1, 423 .has_clklane_stop = 1, 424 .num_clks = 2, 425 .max_freq = 1000, 426 .wait_for_reset = 1, 427 .num_bits_resol = 11, 428 .pll_p_offset = 13, 429 .reg_values = reg_values, 430 .m_min = 41, 431 .m_max = 125, 432 .min_freq = 500, 433 .has_broken_fifoctrl_emptyhdr = 1, 434 }; 435 436 static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = { 437 .reg_ofs = exynos_reg_ofs, 438 .plltmr_reg = 0x58, 439 .num_clks = 2, 440 .max_freq = 1000, 441 .wait_for_reset = 1, 442 .num_bits_resol = 11, 443 .pll_p_offset = 13, 444 .reg_values = reg_values, 445 .m_min = 41, 446 .m_max = 125, 447 .min_freq = 500, 448 }; 449 450 static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = { 451 .reg_ofs = exynos5433_reg_ofs, 452 .plltmr_reg = 0xa0, 453 .has_clklane_stop = 1, 454 .num_clks = 5, 455 .max_freq = 1500, 456 .wait_for_reset = 0, 457 .num_bits_resol = 12, 458 .pll_p_offset = 13, 459 .reg_values = exynos5433_reg_values, 460 .m_min = 41, 461 .m_max = 125, 462 .min_freq = 500, 463 }; 464 465 static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { 466 .reg_ofs = exynos5433_reg_ofs, 467 .plltmr_reg = 0xa0, 468 .has_clklane_stop = 1, 469 .num_clks = 2, 470 .max_freq = 1500, 471 .wait_for_reset = 1, 472 .num_bits_resol = 12, 473 .pll_p_offset = 13, 474 .reg_values = exynos5422_reg_values, 475 .m_min = 41, 476 .m_max = 125, 477 .min_freq = 500, 478 }; 479 480 static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = { 481 .reg_ofs = exynos5433_reg_ofs, 482 .plltmr_reg = 0xa0, 483 .has_clklane_stop = 1, 484 .num_clks = 2, 485 .max_freq = 2100, 486 .wait_for_reset = 0, 487 .num_bits_resol = 12, 488 /* 489 * Unlike Exynos, PLL_P(PMS_P) offset 14 is used in i.MX8M Mini/Nano/Plus 490 * downstream driver - drivers/gpu/drm/bridge/sec-dsim.c 491 */ 492 .pll_p_offset = 14, 493 .reg_values = imx8mm_dsim_reg_values, 494 .m_min = 64, 495 .m_max = 1023, 496 .min_freq = 1050, 497 }; 498 499 static const struct samsung_dsim_driver_data * 500 samsung_dsim_types[DSIM_TYPE_COUNT] = { 501 [DSIM_TYPE_EXYNOS3250] = &exynos3_dsi_driver_data, 502 [DSIM_TYPE_EXYNOS4210] = &exynos4_dsi_driver_data, 503 [DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data, 504 [DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data, 505 [DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data, 506 [DSIM_TYPE_IMX8MM] = &imx8mm_dsi_driver_data, 507 [DSIM_TYPE_IMX8MP] = &imx8mm_dsi_driver_data, 508 }; 509 510 static inline struct samsung_dsim *host_to_dsi(struct mipi_dsi_host *h) 511 { 512 return container_of(h, struct samsung_dsim, dsi_host); 513 } 514 515 static inline struct samsung_dsim *bridge_to_dsi(struct drm_bridge *b) 516 { 517 return container_of(b, struct samsung_dsim, bridge); 518 } 519 520 static inline void samsung_dsim_write(struct samsung_dsim *dsi, 521 enum reg_idx idx, u32 val) 522 { 523 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 524 } 525 526 static inline u32 samsung_dsim_read(struct samsung_dsim *dsi, enum reg_idx idx) 527 { 528 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 529 } 530 531 static void samsung_dsim_wait_for_reset(struct samsung_dsim *dsi) 532 { 533 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) 534 return; 535 536 dev_err(dsi->dev, "timeout waiting for reset\n"); 537 } 538 539 static void samsung_dsim_reset(struct samsung_dsim *dsi) 540 { 541 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE]; 542 543 reinit_completion(&dsi->completed); 544 samsung_dsim_write(dsi, DSIM_SWRST_REG, reset_val); 545 } 546 547 #ifndef MHZ 548 #define MHZ (1000 * 1000) 549 #endif 550 551 static unsigned long samsung_dsim_pll_find_pms(struct samsung_dsim *dsi, 552 unsigned long fin, 553 unsigned long fout, 554 u8 *p, u16 *m, u8 *s) 555 { 556 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 557 unsigned long best_freq = 0; 558 u32 min_delta = 0xffffffff; 559 u8 p_min, p_max; 560 u8 _p, best_p; 561 u16 _m, best_m; 562 u8 _s, best_s; 563 564 p_min = DIV_ROUND_UP(fin, (12 * MHZ)); 565 p_max = fin / (6 * MHZ); 566 567 for (_p = p_min; _p <= p_max; ++_p) { 568 for (_s = 0; _s <= 5; ++_s) { 569 u64 tmp; 570 u32 delta; 571 572 tmp = (u64)fout * (_p << _s); 573 do_div(tmp, fin); 574 _m = tmp; 575 if (_m < driver_data->m_min || _m > driver_data->m_max) 576 continue; 577 578 tmp = (u64)_m * fin; 579 do_div(tmp, _p); 580 if (tmp < driver_data->min_freq * MHZ || 581 tmp > driver_data->max_freq * MHZ) 582 continue; 583 584 tmp = (u64)_m * fin; 585 do_div(tmp, _p << _s); 586 587 delta = abs(fout - tmp); 588 if (delta < min_delta) { 589 best_p = _p; 590 best_m = _m; 591 best_s = _s; 592 min_delta = delta; 593 best_freq = tmp; 594 } 595 } 596 } 597 598 if (best_freq) { 599 *p = best_p; 600 *m = best_m; 601 *s = best_s; 602 } 603 604 return best_freq; 605 } 606 607 static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, 608 unsigned long freq) 609 { 610 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 611 unsigned long fin, fout; 612 int timeout; 613 u8 p, s; 614 u16 m; 615 u32 reg; 616 617 fin = dsi->pll_clk_rate; 618 fout = samsung_dsim_pll_find_pms(dsi, fin, freq, &p, &m, &s); 619 if (!fout) { 620 dev_err(dsi->dev, 621 "failed to find PLL PMS for requested frequency\n"); 622 return 0; 623 } 624 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); 625 626 writel(driver_data->reg_values[PLL_TIMER], 627 dsi->reg_base + driver_data->plltmr_reg); 628 629 reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) | 630 DSIM_PLL_M(m) | DSIM_PLL_S(s); 631 632 if (driver_data->has_freqband) { 633 static const unsigned long freq_bands[] = { 634 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, 635 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, 636 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, 637 770 * MHZ, 870 * MHZ, 950 * MHZ, 638 }; 639 int band; 640 641 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) 642 if (fout < freq_bands[band]) 643 break; 644 645 dev_dbg(dsi->dev, "band %d\n", band); 646 647 reg |= DSIM_FREQ_BAND(band); 648 } 649 650 if (dsi->swap_dn_dp_clk) 651 reg |= DSIM_PLL_DPDNSWAP_CLK; 652 if (dsi->swap_dn_dp_data) 653 reg |= DSIM_PLL_DPDNSWAP_DAT; 654 655 samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg); 656 657 timeout = 1000; 658 do { 659 if (timeout-- == 0) { 660 dev_err(dsi->dev, "PLL failed to stabilize\n"); 661 return 0; 662 } 663 reg = samsung_dsim_read(dsi, DSIM_STATUS_REG); 664 } while ((reg & DSIM_PLL_STABLE) == 0); 665 666 dsi->hs_clock = fout; 667 668 return fout; 669 } 670 671 static int samsung_dsim_enable_clock(struct samsung_dsim *dsi) 672 { 673 unsigned long hs_clk, byte_clk, esc_clk, pix_clk; 674 unsigned long esc_div; 675 u32 reg; 676 struct drm_display_mode *m = &dsi->mode; 677 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 678 679 /* m->clock is in KHz */ 680 pix_clk = m->clock * 1000; 681 682 /* Use burst_clk_rate if available, otherwise use the pix_clk */ 683 if (dsi->burst_clk_rate) 684 hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); 685 else 686 hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->lanes)); 687 688 if (!hs_clk) { 689 dev_err(dsi->dev, "failed to configure DSI PLL\n"); 690 return -EFAULT; 691 } 692 693 byte_clk = hs_clk / 8; 694 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); 695 esc_clk = byte_clk / esc_div; 696 697 if (esc_clk > 20 * MHZ) { 698 ++esc_div; 699 esc_clk = byte_clk / esc_div; 700 } 701 702 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", 703 hs_clk, byte_clk, esc_clk); 704 705 reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG); 706 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK 707 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS 708 | DSIM_BYTE_CLK_SRC_MASK); 709 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN 710 | DSIM_ESC_PRESCALER(esc_div) 711 | DSIM_LANE_ESC_CLK_EN_CLK 712 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) 713 | DSIM_BYTE_CLK_SRC(0) 714 | DSIM_TX_REQUEST_HSCLK; 715 samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg); 716 717 return 0; 718 } 719 720 static void samsung_dsim_set_phy_ctrl(struct samsung_dsim *dsi) 721 { 722 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 723 const unsigned int *reg_values = driver_data->reg_values; 724 u32 reg; 725 struct phy_configure_opts_mipi_dphy cfg; 726 int clk_prepare, lpx, clk_zero, clk_post, clk_trail; 727 int hs_exit, hs_prepare, hs_zero, hs_trail; 728 unsigned long long byte_clock = dsi->hs_clock / 8; 729 730 if (driver_data->has_freqband) 731 return; 732 733 phy_mipi_dphy_get_default_config_for_hsclk(dsi->hs_clock, 734 dsi->lanes, &cfg); 735 736 /* 737 * TODO: 738 * The tech Applications Processor manuals for i.MX8M Mini, Nano, 739 * and Plus don't state what the definition of the PHYTIMING 740 * bits are beyond their address and bit position. 741 * After reviewing NXP's downstream code, it appears 742 * that the various PHYTIMING registers take the number 743 * of cycles and use various dividers on them. This 744 * calculation does not result in an exact match to the 745 * downstream code, but it is very close to the values 746 * generated by their lookup table, and it appears 747 * to sync at a variety of resolutions. If someone 748 * can get a more accurate mathematical equation needed 749 * for these registers, this should be updated. 750 */ 751 752 lpx = PS_TO_CYCLE(cfg.lpx, byte_clock); 753 hs_exit = PS_TO_CYCLE(cfg.hs_exit, byte_clock); 754 clk_prepare = PS_TO_CYCLE(cfg.clk_prepare, byte_clock); 755 clk_zero = PS_TO_CYCLE(cfg.clk_zero, byte_clock); 756 clk_post = PS_TO_CYCLE(cfg.clk_post, byte_clock); 757 clk_trail = PS_TO_CYCLE(cfg.clk_trail, byte_clock); 758 hs_prepare = PS_TO_CYCLE(cfg.hs_prepare, byte_clock); 759 hs_zero = PS_TO_CYCLE(cfg.hs_zero, byte_clock); 760 hs_trail = PS_TO_CYCLE(cfg.hs_trail, byte_clock); 761 762 /* B D-PHY: D-PHY Master & Slave Analog Block control */ 763 reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | 764 reg_values[PHYCTRL_SLEW_UP]; 765 766 samsung_dsim_write(dsi, DSIM_PHYCTRL_REG, reg); 767 768 /* 769 * T LPX: Transmitted length of any Low-Power state period 770 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS 771 * burst 772 */ 773 774 reg = DSIM_PHYTIMING_LPX(lpx) | DSIM_PHYTIMING_HS_EXIT(hs_exit); 775 776 samsung_dsim_write(dsi, DSIM_PHYTIMING_REG, reg); 777 778 /* 779 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00 780 * Line state immediately before the HS-0 Line state starting the 781 * HS transmission 782 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to 783 * transmitting the Clock. 784 * T CLK_POST: Time that the transmitter continues to send HS clock 785 * after the last associated Data Lane has transitioned to LP Mode 786 * Interval is defined as the period from the end of T HS-TRAIL to 787 * the beginning of T CLK-TRAIL 788 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after 789 * the last payload clock bit of a HS transmission burst 790 */ 791 792 reg = DSIM_PHYTIMING1_CLK_PREPARE(clk_prepare) | 793 DSIM_PHYTIMING1_CLK_ZERO(clk_zero) | 794 DSIM_PHYTIMING1_CLK_POST(clk_post) | 795 DSIM_PHYTIMING1_CLK_TRAIL(clk_trail); 796 797 samsung_dsim_write(dsi, DSIM_PHYTIMING1_REG, reg); 798 799 /* 800 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00 801 * Line state immediately before the HS-0 Line state starting the 802 * HS transmission 803 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to 804 * transmitting the Sync sequence. 805 * T HS-TRAIL: Time that the transmitter drives the flipped differential 806 * state after last payload data bit of a HS transmission burst 807 */ 808 809 reg = DSIM_PHYTIMING2_HS_PREPARE(hs_prepare) | 810 DSIM_PHYTIMING2_HS_ZERO(hs_zero) | 811 DSIM_PHYTIMING2_HS_TRAIL(hs_trail); 812 813 samsung_dsim_write(dsi, DSIM_PHYTIMING2_REG, reg); 814 } 815 816 static void samsung_dsim_disable_clock(struct samsung_dsim *dsi) 817 { 818 u32 reg; 819 820 reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG); 821 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK 822 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); 823 samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg); 824 825 reg = samsung_dsim_read(dsi, DSIM_PLLCTRL_REG); 826 reg &= ~DSIM_PLL_EN; 827 samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg); 828 } 829 830 static void samsung_dsim_enable_lane(struct samsung_dsim *dsi, u32 lane) 831 { 832 u32 reg = samsung_dsim_read(dsi, DSIM_CONFIG_REG); 833 834 reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | 835 DSIM_LANE_EN(lane)); 836 samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg); 837 } 838 839 static int samsung_dsim_init_link(struct samsung_dsim *dsi) 840 { 841 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 842 int timeout; 843 u32 reg; 844 u32 lanes_mask; 845 846 /* Initialize FIFO pointers */ 847 reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG); 848 reg &= ~0x1f; 849 samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg); 850 851 usleep_range(9000, 11000); 852 853 reg |= 0x1f; 854 samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg); 855 usleep_range(9000, 11000); 856 857 /* DSI configuration */ 858 reg = 0; 859 860 /* 861 * The first bit of mode_flags specifies display configuration. 862 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video 863 * mode, otherwise it will support command mode. 864 */ 865 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 866 reg |= DSIM_VIDEO_MODE; 867 868 /* 869 * The user manual describes that following bits are ignored in 870 * command mode. 871 */ 872 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)) 873 reg |= DSIM_MFLUSH_VS; 874 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 875 reg |= DSIM_SYNC_INFORM; 876 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 877 reg |= DSIM_BURST_MODE; 878 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) 879 reg |= DSIM_AUTO_MODE; 880 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) 881 reg |= DSIM_HSE_DISABLE_MODE; 882 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 883 reg |= DSIM_HFP_DISABLE_MODE; 884 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 885 reg |= DSIM_HBP_DISABLE_MODE; 886 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA) 887 reg |= DSIM_HSA_DISABLE_MODE; 888 } 889 890 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 891 reg |= DSIM_EOT_DISABLE; 892 893 switch (dsi->format) { 894 case MIPI_DSI_FMT_RGB888: 895 reg |= DSIM_MAIN_PIX_FORMAT_RGB888; 896 break; 897 case MIPI_DSI_FMT_RGB666: 898 reg |= DSIM_MAIN_PIX_FORMAT_RGB666; 899 break; 900 case MIPI_DSI_FMT_RGB666_PACKED: 901 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; 902 break; 903 case MIPI_DSI_FMT_RGB565: 904 reg |= DSIM_MAIN_PIX_FORMAT_RGB565; 905 break; 906 default: 907 dev_err(dsi->dev, "invalid pixel format\n"); 908 return -EINVAL; 909 } 910 911 /* 912 * Use non-continuous clock mode if the periparal wants and 913 * host controller supports 914 * 915 * In non-continous clock mode, host controller will turn off 916 * the HS clock between high-speed transmissions to reduce 917 * power consumption. 918 */ 919 if (driver_data->has_clklane_stop && 920 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 921 reg |= DSIM_CLKLANE_STOP; 922 samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg); 923 924 lanes_mask = BIT(dsi->lanes) - 1; 925 samsung_dsim_enable_lane(dsi, lanes_mask); 926 927 /* Check clock and data lane state are stop state */ 928 timeout = 100; 929 do { 930 if (timeout-- == 0) { 931 dev_err(dsi->dev, "waiting for bus lanes timed out\n"); 932 return -EFAULT; 933 } 934 935 reg = samsung_dsim_read(dsi, DSIM_STATUS_REG); 936 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) 937 != DSIM_STOP_STATE_DAT(lanes_mask)) 938 continue; 939 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); 940 941 reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG); 942 reg &= ~DSIM_STOP_STATE_CNT_MASK; 943 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); 944 945 if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) 946 reg |= DSIM_FORCE_STOP_STATE; 947 948 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg); 949 950 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); 951 samsung_dsim_write(dsi, DSIM_TIMEOUT_REG, reg); 952 953 return 0; 954 } 955 956 static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi) 957 { 958 struct drm_display_mode *m = &dsi->mode; 959 unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; 960 u32 reg; 961 962 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 963 int byte_clk_khz = dsi->hs_clock / 1000 / 8; 964 int hfp = (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock; 965 int hbp = (m->htotal - m->hsync_end) * byte_clk_khz / m->clock; 966 int hsa = (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock; 967 968 /* remove packet overhead when possible */ 969 hfp = max(hfp - 6, 0); 970 hbp = max(hbp - 6, 0); 971 hsa = max(hsa - 6, 0); 972 973 dev_dbg(dsi->dev, "calculated hfp: %u, hbp: %u, hsa: %u", 974 hfp, hbp, hsa); 975 976 reg = DSIM_CMD_ALLOW(0xf) 977 | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay) 978 | DSIM_MAIN_VBP(m->vtotal - m->vsync_end); 979 samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg); 980 981 reg = DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp); 982 samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg); 983 984 reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) 985 | DSIM_MAIN_HSA(hsa); 986 samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg); 987 } 988 reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) | 989 DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol); 990 991 samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg); 992 993 dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay); 994 } 995 996 static void samsung_dsim_set_display_enable(struct samsung_dsim *dsi, bool enable) 997 { 998 u32 reg; 999 1000 reg = samsung_dsim_read(dsi, DSIM_MDRESOL_REG); 1001 if (enable) 1002 reg |= DSIM_MAIN_STAND_BY; 1003 else 1004 reg &= ~DSIM_MAIN_STAND_BY; 1005 samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg); 1006 } 1007 1008 static int samsung_dsim_wait_for_hdr_fifo(struct samsung_dsim *dsi) 1009 { 1010 int timeout = 2000; 1011 1012 do { 1013 u32 reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG); 1014 1015 if (!dsi->driver_data->has_broken_fifoctrl_emptyhdr) { 1016 if (reg & DSIM_SFR_HEADER_EMPTY) 1017 return 0; 1018 } else { 1019 if (!(reg & DSIM_SFR_HEADER_FULL)) { 1020 /* 1021 * Wait a little bit, so the pending data can 1022 * actually leave the FIFO to avoid overflow. 1023 */ 1024 if (!cond_resched()) 1025 usleep_range(950, 1050); 1026 return 0; 1027 } 1028 } 1029 1030 if (!cond_resched()) 1031 usleep_range(950, 1050); 1032 } while (--timeout); 1033 1034 return -ETIMEDOUT; 1035 } 1036 1037 static void samsung_dsim_set_cmd_lpm(struct samsung_dsim *dsi, bool lpm) 1038 { 1039 u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG); 1040 1041 if (lpm) 1042 v |= DSIM_CMD_LPDT_LP; 1043 else 1044 v &= ~DSIM_CMD_LPDT_LP; 1045 1046 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v); 1047 } 1048 1049 static void samsung_dsim_force_bta(struct samsung_dsim *dsi) 1050 { 1051 u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG); 1052 1053 v |= DSIM_FORCE_BTA; 1054 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v); 1055 } 1056 1057 static void samsung_dsim_send_to_fifo(struct samsung_dsim *dsi, 1058 struct samsung_dsim_transfer *xfer) 1059 { 1060 struct device *dev = dsi->dev; 1061 struct mipi_dsi_packet *pkt = &xfer->packet; 1062 const u8 *payload = pkt->payload + xfer->tx_done; 1063 u16 length = pkt->payload_length - xfer->tx_done; 1064 bool first = !xfer->tx_done; 1065 u32 reg; 1066 1067 dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n", 1068 xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done); 1069 1070 if (length > DSI_TX_FIFO_SIZE) 1071 length = DSI_TX_FIFO_SIZE; 1072 1073 xfer->tx_done += length; 1074 1075 /* Send payload */ 1076 while (length >= 4) { 1077 reg = get_unaligned_le32(payload); 1078 samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg); 1079 payload += 4; 1080 length -= 4; 1081 } 1082 1083 reg = 0; 1084 switch (length) { 1085 case 3: 1086 reg |= payload[2] << 16; 1087 fallthrough; 1088 case 2: 1089 reg |= payload[1] << 8; 1090 fallthrough; 1091 case 1: 1092 reg |= payload[0]; 1093 samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg); 1094 break; 1095 } 1096 1097 /* Send packet header */ 1098 if (!first) 1099 return; 1100 1101 reg = get_unaligned_le32(pkt->header); 1102 if (samsung_dsim_wait_for_hdr_fifo(dsi)) { 1103 dev_err(dev, "waiting for header FIFO timed out\n"); 1104 return; 1105 } 1106 1107 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, 1108 dsi->state & DSIM_STATE_CMD_LPM)) { 1109 samsung_dsim_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); 1110 dsi->state ^= DSIM_STATE_CMD_LPM; 1111 } 1112 1113 samsung_dsim_write(dsi, DSIM_PKTHDR_REG, reg); 1114 1115 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) 1116 samsung_dsim_force_bta(dsi); 1117 } 1118 1119 static void samsung_dsim_read_from_fifo(struct samsung_dsim *dsi, 1120 struct samsung_dsim_transfer *xfer) 1121 { 1122 u8 *payload = xfer->rx_payload + xfer->rx_done; 1123 bool first = !xfer->rx_done; 1124 struct device *dev = dsi->dev; 1125 u16 length; 1126 u32 reg; 1127 1128 if (first) { 1129 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG); 1130 1131 switch (reg & 0x3f) { 1132 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 1133 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 1134 if (xfer->rx_len >= 2) { 1135 payload[1] = reg >> 16; 1136 ++xfer->rx_done; 1137 } 1138 fallthrough; 1139 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 1140 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 1141 payload[0] = reg >> 8; 1142 ++xfer->rx_done; 1143 xfer->rx_len = xfer->rx_done; 1144 xfer->result = 0; 1145 goto clear_fifo; 1146 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 1147 dev_err(dev, "DSI Error Report: 0x%04x\n", (reg >> 8) & 0xffff); 1148 xfer->result = 0; 1149 goto clear_fifo; 1150 } 1151 1152 length = (reg >> 8) & 0xffff; 1153 if (length > xfer->rx_len) { 1154 dev_err(dev, 1155 "response too long (%u > %u bytes), stripping\n", 1156 xfer->rx_len, length); 1157 length = xfer->rx_len; 1158 } else if (length < xfer->rx_len) { 1159 xfer->rx_len = length; 1160 } 1161 } 1162 1163 length = xfer->rx_len - xfer->rx_done; 1164 xfer->rx_done += length; 1165 1166 /* Receive payload */ 1167 while (length >= 4) { 1168 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG); 1169 payload[0] = (reg >> 0) & 0xff; 1170 payload[1] = (reg >> 8) & 0xff; 1171 payload[2] = (reg >> 16) & 0xff; 1172 payload[3] = (reg >> 24) & 0xff; 1173 payload += 4; 1174 length -= 4; 1175 } 1176 1177 if (length) { 1178 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG); 1179 switch (length) { 1180 case 3: 1181 payload[2] = (reg >> 16) & 0xff; 1182 fallthrough; 1183 case 2: 1184 payload[1] = (reg >> 8) & 0xff; 1185 fallthrough; 1186 case 1: 1187 payload[0] = reg & 0xff; 1188 } 1189 } 1190 1191 if (xfer->rx_done == xfer->rx_len) 1192 xfer->result = 0; 1193 1194 clear_fifo: 1195 length = DSI_RX_FIFO_SIZE / 4; 1196 do { 1197 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG); 1198 if (reg == DSI_RX_FIFO_EMPTY) 1199 break; 1200 } while (--length); 1201 } 1202 1203 static void samsung_dsim_transfer_start(struct samsung_dsim *dsi) 1204 { 1205 unsigned long flags; 1206 struct samsung_dsim_transfer *xfer; 1207 bool start = false; 1208 1209 again: 1210 spin_lock_irqsave(&dsi->transfer_lock, flags); 1211 1212 if (list_empty(&dsi->transfer_list)) { 1213 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1214 return; 1215 } 1216 1217 xfer = list_first_entry(&dsi->transfer_list, 1218 struct samsung_dsim_transfer, list); 1219 1220 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1221 1222 if (xfer->packet.payload_length && 1223 xfer->tx_done == xfer->packet.payload_length) 1224 /* waiting for RX */ 1225 return; 1226 1227 samsung_dsim_send_to_fifo(dsi, xfer); 1228 1229 if (xfer->packet.payload_length || xfer->rx_len) 1230 return; 1231 1232 xfer->result = 0; 1233 complete(&xfer->completed); 1234 1235 spin_lock_irqsave(&dsi->transfer_lock, flags); 1236 1237 list_del_init(&xfer->list); 1238 start = !list_empty(&dsi->transfer_list); 1239 1240 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1241 1242 if (start) 1243 goto again; 1244 } 1245 1246 static bool samsung_dsim_transfer_finish(struct samsung_dsim *dsi) 1247 { 1248 struct samsung_dsim_transfer *xfer; 1249 unsigned long flags; 1250 bool start = true; 1251 1252 spin_lock_irqsave(&dsi->transfer_lock, flags); 1253 1254 if (list_empty(&dsi->transfer_list)) { 1255 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1256 return false; 1257 } 1258 1259 xfer = list_first_entry(&dsi->transfer_list, 1260 struct samsung_dsim_transfer, list); 1261 1262 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1263 1264 dev_dbg(dsi->dev, 1265 "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n", 1266 xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len, 1267 xfer->rx_done); 1268 1269 if (xfer->tx_done != xfer->packet.payload_length) 1270 return true; 1271 1272 if (xfer->rx_done != xfer->rx_len) 1273 samsung_dsim_read_from_fifo(dsi, xfer); 1274 1275 if (xfer->rx_done != xfer->rx_len) 1276 return true; 1277 1278 spin_lock_irqsave(&dsi->transfer_lock, flags); 1279 1280 list_del_init(&xfer->list); 1281 start = !list_empty(&dsi->transfer_list); 1282 1283 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1284 1285 if (!xfer->rx_len) 1286 xfer->result = 0; 1287 complete(&xfer->completed); 1288 1289 return start; 1290 } 1291 1292 static void samsung_dsim_remove_transfer(struct samsung_dsim *dsi, 1293 struct samsung_dsim_transfer *xfer) 1294 { 1295 unsigned long flags; 1296 bool start; 1297 1298 spin_lock_irqsave(&dsi->transfer_lock, flags); 1299 1300 if (!list_empty(&dsi->transfer_list) && 1301 xfer == list_first_entry(&dsi->transfer_list, 1302 struct samsung_dsim_transfer, list)) { 1303 list_del_init(&xfer->list); 1304 start = !list_empty(&dsi->transfer_list); 1305 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1306 if (start) 1307 samsung_dsim_transfer_start(dsi); 1308 return; 1309 } 1310 1311 list_del_init(&xfer->list); 1312 1313 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1314 } 1315 1316 static int samsung_dsim_transfer(struct samsung_dsim *dsi, 1317 struct samsung_dsim_transfer *xfer) 1318 { 1319 unsigned long flags; 1320 bool stopped; 1321 1322 xfer->tx_done = 0; 1323 xfer->rx_done = 0; 1324 xfer->result = -ETIMEDOUT; 1325 init_completion(&xfer->completed); 1326 1327 spin_lock_irqsave(&dsi->transfer_lock, flags); 1328 1329 stopped = list_empty(&dsi->transfer_list); 1330 list_add_tail(&xfer->list, &dsi->transfer_list); 1331 1332 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1333 1334 if (stopped) 1335 samsung_dsim_transfer_start(dsi); 1336 1337 wait_for_completion_timeout(&xfer->completed, 1338 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); 1339 if (xfer->result == -ETIMEDOUT) { 1340 struct mipi_dsi_packet *pkt = &xfer->packet; 1341 1342 samsung_dsim_remove_transfer(dsi, xfer); 1343 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header, 1344 (int)pkt->payload_length, pkt->payload); 1345 return -ETIMEDOUT; 1346 } 1347 1348 /* Also covers hardware timeout condition */ 1349 return xfer->result; 1350 } 1351 1352 static irqreturn_t samsung_dsim_irq(int irq, void *dev_id) 1353 { 1354 struct samsung_dsim *dsi = dev_id; 1355 u32 status; 1356 1357 status = samsung_dsim_read(dsi, DSIM_INTSRC_REG); 1358 if (!status) { 1359 static unsigned long j; 1360 1361 if (printk_timed_ratelimit(&j, 500)) 1362 dev_warn(dsi->dev, "spurious interrupt\n"); 1363 return IRQ_HANDLED; 1364 } 1365 samsung_dsim_write(dsi, DSIM_INTSRC_REG, status); 1366 1367 if (status & DSIM_INT_SW_RST_RELEASE) { 1368 unsigned long mask = ~(DSIM_INT_RX_DONE | 1369 DSIM_INT_SFR_FIFO_EMPTY | 1370 DSIM_INT_SFR_HDR_FIFO_EMPTY | 1371 DSIM_INT_RX_ECC_ERR | 1372 DSIM_INT_SW_RST_RELEASE); 1373 samsung_dsim_write(dsi, DSIM_INTMSK_REG, mask); 1374 complete(&dsi->completed); 1375 return IRQ_HANDLED; 1376 } 1377 1378 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1379 DSIM_INT_PLL_STABLE))) 1380 return IRQ_HANDLED; 1381 1382 if (samsung_dsim_transfer_finish(dsi)) 1383 samsung_dsim_transfer_start(dsi); 1384 1385 return IRQ_HANDLED; 1386 } 1387 1388 static void samsung_dsim_enable_irq(struct samsung_dsim *dsi) 1389 { 1390 enable_irq(dsi->irq); 1391 1392 if (dsi->te_gpio) 1393 enable_irq(gpiod_to_irq(dsi->te_gpio)); 1394 } 1395 1396 static void samsung_dsim_disable_irq(struct samsung_dsim *dsi) 1397 { 1398 if (dsi->te_gpio) 1399 disable_irq(gpiod_to_irq(dsi->te_gpio)); 1400 1401 disable_irq(dsi->irq); 1402 } 1403 1404 static void samsung_dsim_set_stop_state(struct samsung_dsim *dsi, bool enable) 1405 { 1406 u32 reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG); 1407 1408 if (enable) 1409 reg |= DSIM_FORCE_STOP_STATE; 1410 else 1411 reg &= ~DSIM_FORCE_STOP_STATE; 1412 1413 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg); 1414 } 1415 1416 static int samsung_dsim_init(struct samsung_dsim *dsi) 1417 { 1418 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 1419 1420 if (dsi->state & DSIM_STATE_INITIALIZED) 1421 return 0; 1422 1423 samsung_dsim_reset(dsi); 1424 samsung_dsim_enable_irq(dsi); 1425 1426 if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) 1427 samsung_dsim_enable_lane(dsi, BIT(dsi->lanes) - 1); 1428 1429 samsung_dsim_enable_clock(dsi); 1430 if (driver_data->wait_for_reset) 1431 samsung_dsim_wait_for_reset(dsi); 1432 samsung_dsim_set_phy_ctrl(dsi); 1433 samsung_dsim_init_link(dsi); 1434 1435 dsi->state |= DSIM_STATE_INITIALIZED; 1436 1437 return 0; 1438 } 1439 1440 static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge, 1441 struct drm_bridge_state *old_bridge_state) 1442 { 1443 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1444 int ret; 1445 1446 if (dsi->state & DSIM_STATE_ENABLED) 1447 return; 1448 1449 ret = pm_runtime_resume_and_get(dsi->dev); 1450 if (ret < 0) { 1451 dev_err(dsi->dev, "failed to enable DSI device.\n"); 1452 return; 1453 } 1454 1455 dsi->state |= DSIM_STATE_ENABLED; 1456 1457 /* 1458 * For Exynos-DSIM the downstream bridge, or panel are expecting 1459 * the host initialization during DSI transfer. 1460 */ 1461 if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) { 1462 ret = samsung_dsim_init(dsi); 1463 if (ret) 1464 return; 1465 1466 samsung_dsim_set_display_mode(dsi); 1467 samsung_dsim_set_display_enable(dsi, true); 1468 } 1469 } 1470 1471 static void samsung_dsim_atomic_enable(struct drm_bridge *bridge, 1472 struct drm_bridge_state *old_bridge_state) 1473 { 1474 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1475 1476 if (samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) { 1477 samsung_dsim_set_display_mode(dsi); 1478 samsung_dsim_set_display_enable(dsi, true); 1479 } else { 1480 samsung_dsim_set_stop_state(dsi, false); 1481 } 1482 1483 dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE; 1484 } 1485 1486 static void samsung_dsim_atomic_disable(struct drm_bridge *bridge, 1487 struct drm_bridge_state *old_bridge_state) 1488 { 1489 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1490 1491 if (!(dsi->state & DSIM_STATE_ENABLED)) 1492 return; 1493 1494 if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) 1495 samsung_dsim_set_stop_state(dsi, true); 1496 1497 dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; 1498 } 1499 1500 static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge, 1501 struct drm_bridge_state *old_bridge_state) 1502 { 1503 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1504 1505 samsung_dsim_set_display_enable(dsi, false); 1506 1507 dsi->state &= ~DSIM_STATE_ENABLED; 1508 pm_runtime_put_sync(dsi->dev); 1509 } 1510 1511 /* 1512 * This pixel output formats list referenced from, 1513 * AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022 1514 * 3.7.4 Pixel formats 1515 * Table 14. DSI pixel packing formats 1516 */ 1517 static const u32 samsung_dsim_pixel_output_fmts[] = { 1518 MEDIA_BUS_FMT_YUYV10_1X20, 1519 MEDIA_BUS_FMT_YUYV12_1X24, 1520 MEDIA_BUS_FMT_UYVY8_1X16, 1521 MEDIA_BUS_FMT_RGB101010_1X30, 1522 MEDIA_BUS_FMT_RGB121212_1X36, 1523 MEDIA_BUS_FMT_RGB565_1X16, 1524 MEDIA_BUS_FMT_RGB666_1X18, 1525 MEDIA_BUS_FMT_RGB888_1X24, 1526 }; 1527 1528 static bool samsung_dsim_pixel_output_fmt_supported(u32 fmt) 1529 { 1530 int i; 1531 1532 if (fmt == MEDIA_BUS_FMT_FIXED) 1533 return false; 1534 1535 for (i = 0; i < ARRAY_SIZE(samsung_dsim_pixel_output_fmts); i++) { 1536 if (samsung_dsim_pixel_output_fmts[i] == fmt) 1537 return true; 1538 } 1539 1540 return false; 1541 } 1542 1543 static u32 * 1544 samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 1545 struct drm_bridge_state *bridge_state, 1546 struct drm_crtc_state *crtc_state, 1547 struct drm_connector_state *conn_state, 1548 u32 output_fmt, 1549 unsigned int *num_input_fmts) 1550 { 1551 u32 *input_fmts; 1552 1553 input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); 1554 if (!input_fmts) 1555 return NULL; 1556 1557 if (!samsung_dsim_pixel_output_fmt_supported(output_fmt)) 1558 /* 1559 * Some bridge/display drivers are still not able to pass the 1560 * correct format, so handle those pipelines by falling back 1561 * to the default format till the supported formats finalized. 1562 */ 1563 output_fmt = MEDIA_BUS_FMT_RGB888_1X24; 1564 1565 input_fmts[0] = output_fmt; 1566 *num_input_fmts = 1; 1567 1568 return input_fmts; 1569 } 1570 1571 static int samsung_dsim_atomic_check(struct drm_bridge *bridge, 1572 struct drm_bridge_state *bridge_state, 1573 struct drm_crtc_state *crtc_state, 1574 struct drm_connector_state *conn_state) 1575 { 1576 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1577 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 1578 1579 /* 1580 * The i.MX8M Mini/Nano glue logic between LCDIF and DSIM 1581 * inverts HS/VS/DE sync signals polarity, therefore, while 1582 * i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 1583 * 13.6.3.5.2 RGB interface 1584 * i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 1585 * 13.6.2.7.2 RGB interface 1586 * both claim "Vsync, Hsync, and VDEN are active high signals.", the 1587 * LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. 1588 * 1589 * The i.MX8M Plus glue logic between LCDIFv3 and DSIM does not 1590 * implement the same behavior, therefore LCDIFv3 must generate 1591 * HS/VS/DE signals active HIGH. 1592 */ 1593 if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) { 1594 adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); 1595 adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 1596 } else if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MP) { 1597 adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); 1598 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 1599 } 1600 1601 return 0; 1602 } 1603 1604 static void samsung_dsim_mode_set(struct drm_bridge *bridge, 1605 const struct drm_display_mode *mode, 1606 const struct drm_display_mode *adjusted_mode) 1607 { 1608 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1609 1610 drm_mode_copy(&dsi->mode, adjusted_mode); 1611 } 1612 1613 static int samsung_dsim_attach(struct drm_bridge *bridge, 1614 enum drm_bridge_attach_flags flags) 1615 { 1616 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1617 1618 return drm_bridge_attach(bridge->encoder, dsi->out_bridge, bridge, 1619 flags); 1620 } 1621 1622 static const struct drm_bridge_funcs samsung_dsim_bridge_funcs = { 1623 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1624 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1625 .atomic_reset = drm_atomic_helper_bridge_reset, 1626 .atomic_get_input_bus_fmts = samsung_dsim_atomic_get_input_bus_fmts, 1627 .atomic_check = samsung_dsim_atomic_check, 1628 .atomic_pre_enable = samsung_dsim_atomic_pre_enable, 1629 .atomic_enable = samsung_dsim_atomic_enable, 1630 .atomic_disable = samsung_dsim_atomic_disable, 1631 .atomic_post_disable = samsung_dsim_atomic_post_disable, 1632 .mode_set = samsung_dsim_mode_set, 1633 .attach = samsung_dsim_attach, 1634 }; 1635 1636 static irqreturn_t samsung_dsim_te_irq_handler(int irq, void *dev_id) 1637 { 1638 struct samsung_dsim *dsi = (struct samsung_dsim *)dev_id; 1639 const struct samsung_dsim_plat_data *pdata = dsi->plat_data; 1640 1641 if (pdata->host_ops && pdata->host_ops->te_irq_handler) 1642 return pdata->host_ops->te_irq_handler(dsi); 1643 1644 return IRQ_HANDLED; 1645 } 1646 1647 static int samsung_dsim_register_te_irq(struct samsung_dsim *dsi, struct device *dev) 1648 { 1649 int te_gpio_irq; 1650 int ret; 1651 1652 dsi->te_gpio = devm_gpiod_get_optional(dev, "te", GPIOD_IN); 1653 if (!dsi->te_gpio) 1654 return 0; 1655 else if (IS_ERR(dsi->te_gpio)) 1656 return dev_err_probe(dev, PTR_ERR(dsi->te_gpio), "failed to get te GPIO\n"); 1657 1658 te_gpio_irq = gpiod_to_irq(dsi->te_gpio); 1659 1660 ret = request_threaded_irq(te_gpio_irq, samsung_dsim_te_irq_handler, NULL, 1661 IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, "TE", dsi); 1662 if (ret) { 1663 dev_err(dsi->dev, "request interrupt failed with %d\n", ret); 1664 gpiod_put(dsi->te_gpio); 1665 return ret; 1666 } 1667 1668 return 0; 1669 } 1670 1671 static int samsung_dsim_host_attach(struct mipi_dsi_host *host, 1672 struct mipi_dsi_device *device) 1673 { 1674 struct samsung_dsim *dsi = host_to_dsi(host); 1675 const struct samsung_dsim_plat_data *pdata = dsi->plat_data; 1676 struct device *dev = dsi->dev; 1677 struct device_node *np = dev->of_node; 1678 struct device_node *remote; 1679 struct drm_panel *panel; 1680 int ret; 1681 1682 /* 1683 * Devices can also be child nodes when we also control that device 1684 * through the upstream device (ie, MIPI-DCS for a MIPI-DSI device). 1685 * 1686 * Lookup for a child node of the given parent that isn't either port 1687 * or ports. 1688 */ 1689 for_each_available_child_of_node(np, remote) { 1690 if (of_node_name_eq(remote, "port") || 1691 of_node_name_eq(remote, "ports")) 1692 continue; 1693 1694 goto of_find_panel_or_bridge; 1695 } 1696 1697 /* 1698 * of_graph_get_remote_node() produces a noisy error message if port 1699 * node isn't found and the absence of the port is a legit case here, 1700 * so at first we silently check whether graph presents in the 1701 * device-tree node. 1702 */ 1703 if (!of_graph_is_present(np)) 1704 return -ENODEV; 1705 1706 remote = of_graph_get_remote_node(np, 1, 0); 1707 1708 of_find_panel_or_bridge: 1709 if (!remote) 1710 return -ENODEV; 1711 1712 panel = of_drm_find_panel(remote); 1713 if (!IS_ERR(panel)) { 1714 dsi->out_bridge = devm_drm_panel_bridge_add(dev, panel); 1715 } else { 1716 dsi->out_bridge = of_drm_find_bridge(remote); 1717 if (!dsi->out_bridge) 1718 dsi->out_bridge = ERR_PTR(-EINVAL); 1719 } 1720 1721 of_node_put(remote); 1722 1723 if (IS_ERR(dsi->out_bridge)) { 1724 ret = PTR_ERR(dsi->out_bridge); 1725 DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n", ret); 1726 return ret; 1727 } 1728 1729 DRM_DEV_INFO(dev, "Attached %s device\n", device->name); 1730 1731 drm_bridge_add(&dsi->bridge); 1732 1733 /* 1734 * This is a temporary solution and should be made by more generic way. 1735 * 1736 * If attached panel device is for command mode one, dsi should register 1737 * TE interrupt handler. 1738 */ 1739 if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) { 1740 ret = samsung_dsim_register_te_irq(dsi, &device->dev); 1741 if (ret) 1742 return ret; 1743 } 1744 1745 if (pdata->host_ops && pdata->host_ops->attach) { 1746 ret = pdata->host_ops->attach(dsi, device); 1747 if (ret) 1748 return ret; 1749 } 1750 1751 dsi->lanes = device->lanes; 1752 dsi->format = device->format; 1753 dsi->mode_flags = device->mode_flags; 1754 1755 return 0; 1756 } 1757 1758 static void samsung_dsim_unregister_te_irq(struct samsung_dsim *dsi) 1759 { 1760 if (dsi->te_gpio) { 1761 free_irq(gpiod_to_irq(dsi->te_gpio), dsi); 1762 gpiod_put(dsi->te_gpio); 1763 } 1764 } 1765 1766 static int samsung_dsim_host_detach(struct mipi_dsi_host *host, 1767 struct mipi_dsi_device *device) 1768 { 1769 struct samsung_dsim *dsi = host_to_dsi(host); 1770 const struct samsung_dsim_plat_data *pdata = dsi->plat_data; 1771 1772 dsi->out_bridge = NULL; 1773 1774 if (pdata->host_ops && pdata->host_ops->detach) 1775 pdata->host_ops->detach(dsi, device); 1776 1777 samsung_dsim_unregister_te_irq(dsi); 1778 1779 drm_bridge_remove(&dsi->bridge); 1780 1781 return 0; 1782 } 1783 1784 static ssize_t samsung_dsim_host_transfer(struct mipi_dsi_host *host, 1785 const struct mipi_dsi_msg *msg) 1786 { 1787 struct samsung_dsim *dsi = host_to_dsi(host); 1788 struct samsung_dsim_transfer xfer; 1789 int ret; 1790 1791 if (!(dsi->state & DSIM_STATE_ENABLED)) 1792 return -EINVAL; 1793 1794 ret = samsung_dsim_init(dsi); 1795 if (ret) 1796 return ret; 1797 1798 samsung_dsim_set_stop_state(dsi, false); 1799 1800 ret = mipi_dsi_create_packet(&xfer.packet, msg); 1801 if (ret < 0) 1802 return ret; 1803 1804 xfer.rx_len = msg->rx_len; 1805 xfer.rx_payload = msg->rx_buf; 1806 xfer.flags = msg->flags; 1807 1808 ret = samsung_dsim_transfer(dsi, &xfer); 1809 return (ret < 0) ? ret : xfer.rx_done; 1810 } 1811 1812 static const struct mipi_dsi_host_ops samsung_dsim_ops = { 1813 .attach = samsung_dsim_host_attach, 1814 .detach = samsung_dsim_host_detach, 1815 .transfer = samsung_dsim_host_transfer, 1816 }; 1817 1818 static int samsung_dsim_of_read_u32(const struct device_node *np, 1819 const char *propname, u32 *out_value, bool optional) 1820 { 1821 int ret = of_property_read_u32(np, propname, out_value); 1822 1823 if (ret < 0 && !optional) 1824 pr_err("%pOF: failed to get '%s' property\n", np, propname); 1825 1826 return ret; 1827 } 1828 1829 static int samsung_dsim_parse_dt(struct samsung_dsim *dsi) 1830 { 1831 struct device *dev = dsi->dev; 1832 struct device_node *node = dev->of_node; 1833 u32 lane_polarities[5] = { 0 }; 1834 struct device_node *endpoint; 1835 int i, nr_lanes, ret; 1836 struct clk *pll_clk; 1837 1838 ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency", 1839 &dsi->pll_clk_rate, 1); 1840 /* If it doesn't exist, read it from the clock instead of failing */ 1841 if (ret < 0) { 1842 dev_dbg(dev, "Using sclk_mipi for pll clock frequency\n"); 1843 pll_clk = devm_clk_get(dev, "sclk_mipi"); 1844 if (!IS_ERR(pll_clk)) 1845 dsi->pll_clk_rate = clk_get_rate(pll_clk); 1846 else 1847 return PTR_ERR(pll_clk); 1848 } 1849 1850 /* If it doesn't exist, use pixel clock instead of failing */ 1851 ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency", 1852 &dsi->burst_clk_rate, 1); 1853 if (ret < 0) { 1854 dev_dbg(dev, "Using pixel clock for HS clock frequency\n"); 1855 dsi->burst_clk_rate = 0; 1856 } 1857 1858 ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency", 1859 &dsi->esc_clk_rate, 0); 1860 if (ret < 0) 1861 return ret; 1862 1863 endpoint = of_graph_get_endpoint_by_regs(node, 1, -1); 1864 nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes"); 1865 if (nr_lanes > 0 && nr_lanes <= 4) { 1866 /* Polarity 0 is clock lane, 1..4 are data lanes. */ 1867 of_property_read_u32_array(endpoint, "lane-polarities", 1868 lane_polarities, nr_lanes + 1); 1869 for (i = 1; i <= nr_lanes; i++) { 1870 if (lane_polarities[1] != lane_polarities[i]) 1871 DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match"); 1872 } 1873 if (lane_polarities[0]) 1874 dsi->swap_dn_dp_clk = true; 1875 if (lane_polarities[1]) 1876 dsi->swap_dn_dp_data = true; 1877 } 1878 1879 return 0; 1880 } 1881 1882 static int generic_dsim_register_host(struct samsung_dsim *dsi) 1883 { 1884 return mipi_dsi_host_register(&dsi->dsi_host); 1885 } 1886 1887 static void generic_dsim_unregister_host(struct samsung_dsim *dsi) 1888 { 1889 mipi_dsi_host_unregister(&dsi->dsi_host); 1890 } 1891 1892 static const struct samsung_dsim_host_ops generic_dsim_host_ops = { 1893 .register_host = generic_dsim_register_host, 1894 .unregister_host = generic_dsim_unregister_host, 1895 }; 1896 1897 static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_high = { 1898 .input_bus_flags = DRM_BUS_FLAG_DE_HIGH, 1899 }; 1900 1901 static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_low = { 1902 .input_bus_flags = DRM_BUS_FLAG_DE_LOW, 1903 }; 1904 1905 int samsung_dsim_probe(struct platform_device *pdev) 1906 { 1907 struct device *dev = &pdev->dev; 1908 struct samsung_dsim *dsi; 1909 int ret, i; 1910 1911 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1912 if (!dsi) 1913 return -ENOMEM; 1914 1915 init_completion(&dsi->completed); 1916 spin_lock_init(&dsi->transfer_lock); 1917 INIT_LIST_HEAD(&dsi->transfer_list); 1918 1919 dsi->dsi_host.ops = &samsung_dsim_ops; 1920 dsi->dsi_host.dev = dev; 1921 1922 dsi->dev = dev; 1923 dsi->plat_data = of_device_get_match_data(dev); 1924 dsi->driver_data = samsung_dsim_types[dsi->plat_data->hw_type]; 1925 1926 dsi->supplies[0].supply = "vddcore"; 1927 dsi->supplies[1].supply = "vddio"; 1928 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies), 1929 dsi->supplies); 1930 if (ret) 1931 return dev_err_probe(dev, ret, "failed to get regulators\n"); 1932 1933 dsi->clks = devm_kcalloc(dev, dsi->driver_data->num_clks, 1934 sizeof(*dsi->clks), GFP_KERNEL); 1935 if (!dsi->clks) 1936 return -ENOMEM; 1937 1938 for (i = 0; i < dsi->driver_data->num_clks; i++) { 1939 dsi->clks[i] = devm_clk_get(dev, clk_names[i]); 1940 if (IS_ERR(dsi->clks[i])) { 1941 if (strcmp(clk_names[i], "sclk_mipi") == 0) { 1942 dsi->clks[i] = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME); 1943 if (!IS_ERR(dsi->clks[i])) 1944 continue; 1945 } 1946 1947 dev_info(dev, "failed to get the clock: %s\n", clk_names[i]); 1948 return PTR_ERR(dsi->clks[i]); 1949 } 1950 } 1951 1952 dsi->reg_base = devm_platform_ioremap_resource(pdev, 0); 1953 if (IS_ERR(dsi->reg_base)) 1954 return PTR_ERR(dsi->reg_base); 1955 1956 dsi->phy = devm_phy_optional_get(dev, "dsim"); 1957 if (IS_ERR(dsi->phy)) { 1958 dev_info(dev, "failed to get dsim phy\n"); 1959 return PTR_ERR(dsi->phy); 1960 } 1961 1962 dsi->irq = platform_get_irq(pdev, 0); 1963 if (dsi->irq < 0) 1964 return dsi->irq; 1965 1966 ret = devm_request_threaded_irq(dev, dsi->irq, NULL, 1967 samsung_dsim_irq, 1968 IRQF_ONESHOT | IRQF_NO_AUTOEN, 1969 dev_name(dev), dsi); 1970 if (ret) { 1971 dev_err(dev, "failed to request dsi irq\n"); 1972 return ret; 1973 } 1974 1975 ret = samsung_dsim_parse_dt(dsi); 1976 if (ret) 1977 return ret; 1978 1979 platform_set_drvdata(pdev, dsi); 1980 1981 pm_runtime_enable(dev); 1982 1983 dsi->bridge.funcs = &samsung_dsim_bridge_funcs; 1984 dsi->bridge.of_node = dev->of_node; 1985 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; 1986 1987 /* DE_LOW: i.MX8M Mini/Nano LCDIF-DSIM glue logic inverts HS/VS/DE */ 1988 if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) 1989 dsi->bridge.timings = &samsung_dsim_bridge_timings_de_low; 1990 else 1991 dsi->bridge.timings = &samsung_dsim_bridge_timings_de_high; 1992 1993 if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->register_host) 1994 ret = dsi->plat_data->host_ops->register_host(dsi); 1995 1996 if (ret) 1997 goto err_disable_runtime; 1998 1999 return 0; 2000 2001 err_disable_runtime: 2002 pm_runtime_disable(dev); 2003 2004 return ret; 2005 } 2006 EXPORT_SYMBOL_GPL(samsung_dsim_probe); 2007 2008 int samsung_dsim_remove(struct platform_device *pdev) 2009 { 2010 struct samsung_dsim *dsi = platform_get_drvdata(pdev); 2011 2012 pm_runtime_disable(&pdev->dev); 2013 2014 if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->unregister_host) 2015 dsi->plat_data->host_ops->unregister_host(dsi); 2016 2017 return 0; 2018 } 2019 EXPORT_SYMBOL_GPL(samsung_dsim_remove); 2020 2021 static int __maybe_unused samsung_dsim_suspend(struct device *dev) 2022 { 2023 struct samsung_dsim *dsi = dev_get_drvdata(dev); 2024 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 2025 int ret, i; 2026 2027 usleep_range(10000, 20000); 2028 2029 if (dsi->state & DSIM_STATE_INITIALIZED) { 2030 dsi->state &= ~DSIM_STATE_INITIALIZED; 2031 2032 samsung_dsim_disable_clock(dsi); 2033 2034 samsung_dsim_disable_irq(dsi); 2035 } 2036 2037 dsi->state &= ~DSIM_STATE_CMD_LPM; 2038 2039 phy_power_off(dsi->phy); 2040 2041 for (i = driver_data->num_clks - 1; i > -1; i--) 2042 clk_disable_unprepare(dsi->clks[i]); 2043 2044 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 2045 if (ret < 0) 2046 dev_err(dsi->dev, "cannot disable regulators %d\n", ret); 2047 2048 return 0; 2049 } 2050 2051 static int __maybe_unused samsung_dsim_resume(struct device *dev) 2052 { 2053 struct samsung_dsim *dsi = dev_get_drvdata(dev); 2054 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 2055 int ret, i; 2056 2057 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 2058 if (ret < 0) { 2059 dev_err(dsi->dev, "cannot enable regulators %d\n", ret); 2060 return ret; 2061 } 2062 2063 for (i = 0; i < driver_data->num_clks; i++) { 2064 ret = clk_prepare_enable(dsi->clks[i]); 2065 if (ret < 0) 2066 goto err_clk; 2067 } 2068 2069 ret = phy_power_on(dsi->phy); 2070 if (ret < 0) { 2071 dev_err(dsi->dev, "cannot enable phy %d\n", ret); 2072 goto err_clk; 2073 } 2074 2075 return 0; 2076 2077 err_clk: 2078 while (--i > -1) 2079 clk_disable_unprepare(dsi->clks[i]); 2080 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 2081 2082 return ret; 2083 } 2084 2085 const struct dev_pm_ops samsung_dsim_pm_ops = { 2086 SET_RUNTIME_PM_OPS(samsung_dsim_suspend, samsung_dsim_resume, NULL) 2087 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2088 pm_runtime_force_resume) 2089 }; 2090 EXPORT_SYMBOL_GPL(samsung_dsim_pm_ops); 2091 2092 static const struct samsung_dsim_plat_data samsung_dsim_imx8mm_pdata = { 2093 .hw_type = DSIM_TYPE_IMX8MM, 2094 .host_ops = &generic_dsim_host_ops, 2095 }; 2096 2097 static const struct samsung_dsim_plat_data samsung_dsim_imx8mp_pdata = { 2098 .hw_type = DSIM_TYPE_IMX8MP, 2099 .host_ops = &generic_dsim_host_ops, 2100 }; 2101 2102 static const struct of_device_id samsung_dsim_of_match[] = { 2103 { 2104 .compatible = "fsl,imx8mm-mipi-dsim", 2105 .data = &samsung_dsim_imx8mm_pdata, 2106 }, 2107 { 2108 .compatible = "fsl,imx8mp-mipi-dsim", 2109 .data = &samsung_dsim_imx8mp_pdata, 2110 }, 2111 { /* sentinel. */ } 2112 }; 2113 MODULE_DEVICE_TABLE(of, samsung_dsim_of_match); 2114 2115 static struct platform_driver samsung_dsim_driver = { 2116 .probe = samsung_dsim_probe, 2117 .remove = samsung_dsim_remove, 2118 .driver = { 2119 .name = "samsung-dsim", 2120 .pm = &samsung_dsim_pm_ops, 2121 .of_match_table = samsung_dsim_of_match, 2122 }, 2123 }; 2124 2125 module_platform_driver(samsung_dsim_driver); 2126 2127 MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>"); 2128 MODULE_DESCRIPTION("Samsung MIPI DSIM controller bridge"); 2129 MODULE_LICENSE("GPL"); 2130