1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Samsung MIPI DSIM bridge driver.
4  *
5  * Copyright (C) 2021 Amarula Solutions(India)
6  * Copyright (c) 2014 Samsung Electronics Co., Ltd
7  * Author: Jagan Teki <jagan@amarulasolutions.com>
8  *
9  * Based on exynos_drm_dsi from
10  * Tomasz Figa <t.figa@samsung.com>
11  */
12 
13 #include <asm/unaligned.h>
14 
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/irq.h>
18 #include <linux/media-bus-format.h>
19 #include <linux/of.h>
20 #include <linux/phy/phy.h>
21 #include <linux/platform_device.h>
22 
23 #include <video/mipi_display.h>
24 
25 #include <drm/bridge/samsung-dsim.h>
26 #include <drm/drm_panel.h>
27 #include <drm/drm_print.h>
28 
29 /* returns true iff both arguments logically differs */
30 #define NEQV(a, b) (!(a) ^ !(b))
31 
32 /* DSIM_STATUS */
33 #define DSIM_STOP_STATE_DAT(x)		(((x) & 0xf) << 0)
34 #define DSIM_STOP_STATE_CLK		BIT(8)
35 #define DSIM_TX_READY_HS_CLK		BIT(10)
36 #define DSIM_PLL_STABLE			BIT(31)
37 
38 /* DSIM_SWRST */
39 #define DSIM_FUNCRST			BIT(16)
40 #define DSIM_SWRST			BIT(0)
41 
42 /* DSIM_TIMEOUT */
43 #define DSIM_LPDR_TIMEOUT(x)		((x) << 0)
44 #define DSIM_BTA_TIMEOUT(x)		((x) << 16)
45 
46 /* DSIM_CLKCTRL */
47 #define DSIM_ESC_PRESCALER(x)		(((x) & 0xffff) << 0)
48 #define DSIM_ESC_PRESCALER_MASK		(0xffff << 0)
49 #define DSIM_LANE_ESC_CLK_EN_CLK	BIT(19)
50 #define DSIM_LANE_ESC_CLK_EN_DATA(x)	(((x) & 0xf) << 20)
51 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK	(0xf << 20)
52 #define DSIM_BYTE_CLKEN			BIT(24)
53 #define DSIM_BYTE_CLK_SRC(x)		(((x) & 0x3) << 25)
54 #define DSIM_BYTE_CLK_SRC_MASK		(0x3 << 25)
55 #define DSIM_PLL_BYPASS			BIT(27)
56 #define DSIM_ESC_CLKEN			BIT(28)
57 #define DSIM_TX_REQUEST_HSCLK		BIT(31)
58 
59 /* DSIM_CONFIG */
60 #define DSIM_LANE_EN_CLK		BIT(0)
61 #define DSIM_LANE_EN(x)			(((x) & 0xf) << 1)
62 #define DSIM_NUM_OF_DATA_LANE(x)	(((x) & 0x3) << 5)
63 #define DSIM_SUB_PIX_FORMAT(x)		(((x) & 0x7) << 8)
64 #define DSIM_MAIN_PIX_FORMAT_MASK	(0x7 << 12)
65 #define DSIM_MAIN_PIX_FORMAT_RGB888	(0x7 << 12)
66 #define DSIM_MAIN_PIX_FORMAT_RGB666	(0x6 << 12)
67 #define DSIM_MAIN_PIX_FORMAT_RGB666_P	(0x5 << 12)
68 #define DSIM_MAIN_PIX_FORMAT_RGB565	(0x4 << 12)
69 #define DSIM_SUB_VC			(((x) & 0x3) << 16)
70 #define DSIM_MAIN_VC			(((x) & 0x3) << 18)
71 #define DSIM_HSA_DISABLE_MODE		BIT(20)
72 #define DSIM_HBP_DISABLE_MODE		BIT(21)
73 #define DSIM_HFP_DISABLE_MODE		BIT(22)
74 /*
75  * The i.MX 8M Mini Applications Processor Reference Manual,
76  * Rev. 3, 11/2020 Page 4091
77  * The i.MX 8M Nano Applications Processor Reference Manual,
78  * Rev. 2, 07/2022 Page 3058
79  * The i.MX 8M Plus Applications Processor Reference Manual,
80  * Rev. 1, 06/2021 Page 5436
81  * all claims this bit is 'HseDisableMode' with the definition
82  * 0 = Disables transfer
83  * 1 = Enables transfer
84  *
85  * This clearly states that HSE is not a disabled bit.
86  *
87  * The naming convention follows as per the manual and the
88  * driver logic is based on the MIPI_DSI_MODE_VIDEO_HSE flag.
89  */
90 #define DSIM_HSE_DISABLE_MODE		BIT(23)
91 #define DSIM_AUTO_MODE			BIT(24)
92 #define DSIM_VIDEO_MODE			BIT(25)
93 #define DSIM_BURST_MODE			BIT(26)
94 #define DSIM_SYNC_INFORM		BIT(27)
95 #define DSIM_EOT_DISABLE		BIT(28)
96 #define DSIM_MFLUSH_VS			BIT(29)
97 /* This flag is valid only for exynos3250/3472/5260/5430 */
98 #define DSIM_CLKLANE_STOP		BIT(30)
99 
100 /* DSIM_ESCMODE */
101 #define DSIM_TX_TRIGGER_RST		BIT(4)
102 #define DSIM_TX_LPDT_LP			BIT(6)
103 #define DSIM_CMD_LPDT_LP		BIT(7)
104 #define DSIM_FORCE_BTA			BIT(16)
105 #define DSIM_FORCE_STOP_STATE		BIT(20)
106 #define DSIM_STOP_STATE_CNT(x)		(((x) & 0x7ff) << 21)
107 #define DSIM_STOP_STATE_CNT_MASK	(0x7ff << 21)
108 
109 /* DSIM_MDRESOL */
110 #define DSIM_MAIN_STAND_BY		BIT(31)
111 #define DSIM_MAIN_VRESOL(x, num_bits)	(((x) & ((1 << (num_bits)) - 1)) << 16)
112 #define DSIM_MAIN_HRESOL(x, num_bits)	(((x) & ((1 << (num_bits)) - 1)) << 0)
113 
114 /* DSIM_MVPORCH */
115 #define DSIM_CMD_ALLOW(x)		((x) << 28)
116 #define DSIM_STABLE_VFP(x)		((x) << 16)
117 #define DSIM_MAIN_VBP(x)		((x) << 0)
118 #define DSIM_CMD_ALLOW_MASK		(0xf << 28)
119 #define DSIM_STABLE_VFP_MASK		(0x7ff << 16)
120 #define DSIM_MAIN_VBP_MASK		(0x7ff << 0)
121 
122 /* DSIM_MHPORCH */
123 #define DSIM_MAIN_HFP(x)		((x) << 16)
124 #define DSIM_MAIN_HBP(x)		((x) << 0)
125 #define DSIM_MAIN_HFP_MASK		((0xffff) << 16)
126 #define DSIM_MAIN_HBP_MASK		((0xffff) << 0)
127 
128 /* DSIM_MSYNC */
129 #define DSIM_MAIN_VSA(x)		((x) << 22)
130 #define DSIM_MAIN_HSA(x)		((x) << 0)
131 #define DSIM_MAIN_VSA_MASK		((0x3ff) << 22)
132 #define DSIM_MAIN_HSA_MASK		((0xffff) << 0)
133 
134 /* DSIM_SDRESOL */
135 #define DSIM_SUB_STANDY(x)		((x) << 31)
136 #define DSIM_SUB_VRESOL(x)		((x) << 16)
137 #define DSIM_SUB_HRESOL(x)		((x) << 0)
138 #define DSIM_SUB_STANDY_MASK		((0x1) << 31)
139 #define DSIM_SUB_VRESOL_MASK		((0x7ff) << 16)
140 #define DSIM_SUB_HRESOL_MASK		((0x7ff) << 0)
141 
142 /* DSIM_INTSRC */
143 #define DSIM_INT_PLL_STABLE		BIT(31)
144 #define DSIM_INT_SW_RST_RELEASE		BIT(30)
145 #define DSIM_INT_SFR_FIFO_EMPTY		BIT(29)
146 #define DSIM_INT_SFR_HDR_FIFO_EMPTY	BIT(28)
147 #define DSIM_INT_BTA			BIT(25)
148 #define DSIM_INT_FRAME_DONE		BIT(24)
149 #define DSIM_INT_RX_TIMEOUT		BIT(21)
150 #define DSIM_INT_BTA_TIMEOUT		BIT(20)
151 #define DSIM_INT_RX_DONE		BIT(18)
152 #define DSIM_INT_RX_TE			BIT(17)
153 #define DSIM_INT_RX_ACK			BIT(16)
154 #define DSIM_INT_RX_ECC_ERR		BIT(15)
155 #define DSIM_INT_RX_CRC_ERR		BIT(14)
156 
157 /* DSIM_FIFOCTRL */
158 #define DSIM_RX_DATA_FULL		BIT(25)
159 #define DSIM_RX_DATA_EMPTY		BIT(24)
160 #define DSIM_SFR_HEADER_FULL		BIT(23)
161 #define DSIM_SFR_HEADER_EMPTY		BIT(22)
162 #define DSIM_SFR_PAYLOAD_FULL		BIT(21)
163 #define DSIM_SFR_PAYLOAD_EMPTY		BIT(20)
164 #define DSIM_I80_HEADER_FULL		BIT(19)
165 #define DSIM_I80_HEADER_EMPTY		BIT(18)
166 #define DSIM_I80_PAYLOAD_FULL		BIT(17)
167 #define DSIM_I80_PAYLOAD_EMPTY		BIT(16)
168 #define DSIM_SD_HEADER_FULL		BIT(15)
169 #define DSIM_SD_HEADER_EMPTY		BIT(14)
170 #define DSIM_SD_PAYLOAD_FULL		BIT(13)
171 #define DSIM_SD_PAYLOAD_EMPTY		BIT(12)
172 #define DSIM_MD_HEADER_FULL		BIT(11)
173 #define DSIM_MD_HEADER_EMPTY		BIT(10)
174 #define DSIM_MD_PAYLOAD_FULL		BIT(9)
175 #define DSIM_MD_PAYLOAD_EMPTY		BIT(8)
176 #define DSIM_RX_FIFO			BIT(4)
177 #define DSIM_SFR_FIFO			BIT(3)
178 #define DSIM_I80_FIFO			BIT(2)
179 #define DSIM_SD_FIFO			BIT(1)
180 #define DSIM_MD_FIFO			BIT(0)
181 
182 /* DSIM_PHYACCHR */
183 #define DSIM_AFC_EN			BIT(14)
184 #define DSIM_AFC_CTL(x)			(((x) & 0x7) << 5)
185 
186 /* DSIM_PLLCTRL */
187 #define DSIM_PLL_DPDNSWAP_CLK		(1 << 25)
188 #define DSIM_PLL_DPDNSWAP_DAT		(1 << 24)
189 #define DSIM_FREQ_BAND(x)		((x) << 24)
190 #define DSIM_PLL_EN			BIT(23)
191 #define DSIM_PLL_P(x, offset)		((x) << (offset))
192 #define DSIM_PLL_M(x)			((x) << 4)
193 #define DSIM_PLL_S(x)			((x) << 1)
194 
195 /* DSIM_PHYCTRL */
196 #define DSIM_PHYCTRL_ULPS_EXIT(x)	(((x) & 0x1ff) << 0)
197 #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP	BIT(30)
198 #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP	BIT(14)
199 
200 /* DSIM_PHYTIMING */
201 #define DSIM_PHYTIMING_LPX(x)		((x) << 8)
202 #define DSIM_PHYTIMING_HS_EXIT(x)	((x) << 0)
203 
204 /* DSIM_PHYTIMING1 */
205 #define DSIM_PHYTIMING1_CLK_PREPARE(x)	((x) << 24)
206 #define DSIM_PHYTIMING1_CLK_ZERO(x)	((x) << 16)
207 #define DSIM_PHYTIMING1_CLK_POST(x)	((x) << 8)
208 #define DSIM_PHYTIMING1_CLK_TRAIL(x)	((x) << 0)
209 
210 /* DSIM_PHYTIMING2 */
211 #define DSIM_PHYTIMING2_HS_PREPARE(x)	((x) << 16)
212 #define DSIM_PHYTIMING2_HS_ZERO(x)	((x) << 8)
213 #define DSIM_PHYTIMING2_HS_TRAIL(x)	((x) << 0)
214 
215 #define DSI_MAX_BUS_WIDTH		4
216 #define DSI_NUM_VIRTUAL_CHANNELS	4
217 #define DSI_TX_FIFO_SIZE		2048
218 #define DSI_RX_FIFO_SIZE		256
219 #define DSI_XFER_TIMEOUT_MS		100
220 #define DSI_RX_FIFO_EMPTY		0x30800002
221 
222 #define OLD_SCLK_MIPI_CLK_NAME		"pll_clk"
223 
224 #define PS_TO_CYCLE(ps, hz) DIV64_U64_ROUND_CLOSEST(((ps) * (hz)), 1000000000000ULL)
225 
226 static const char *const clk_names[5] = {
227 	"bus_clk",
228 	"sclk_mipi",
229 	"phyclk_mipidphy0_bitclkdiv8",
230 	"phyclk_mipidphy0_rxclkesc0",
231 	"sclk_rgb_vclk_to_dsim0"
232 };
233 
234 enum samsung_dsim_transfer_type {
235 	EXYNOS_DSI_TX,
236 	EXYNOS_DSI_RX,
237 };
238 
239 enum reg_idx {
240 	DSIM_STATUS_REG,	/* Status register */
241 	DSIM_SWRST_REG,		/* Software reset register */
242 	DSIM_CLKCTRL_REG,	/* Clock control register */
243 	DSIM_TIMEOUT_REG,	/* Time out register */
244 	DSIM_CONFIG_REG,	/* Configuration register */
245 	DSIM_ESCMODE_REG,	/* Escape mode register */
246 	DSIM_MDRESOL_REG,
247 	DSIM_MVPORCH_REG,	/* Main display Vporch register */
248 	DSIM_MHPORCH_REG,	/* Main display Hporch register */
249 	DSIM_MSYNC_REG,		/* Main display sync area register */
250 	DSIM_INTSRC_REG,	/* Interrupt source register */
251 	DSIM_INTMSK_REG,	/* Interrupt mask register */
252 	DSIM_PKTHDR_REG,	/* Packet Header FIFO register */
253 	DSIM_PAYLOAD_REG,	/* Payload FIFO register */
254 	DSIM_RXFIFO_REG,	/* Read FIFO register */
255 	DSIM_FIFOCTRL_REG,	/* FIFO status and control register */
256 	DSIM_PLLCTRL_REG,	/* PLL control register */
257 	DSIM_PHYCTRL_REG,
258 	DSIM_PHYTIMING_REG,
259 	DSIM_PHYTIMING1_REG,
260 	DSIM_PHYTIMING2_REG,
261 	NUM_REGS
262 };
263 
264 static const unsigned int exynos_reg_ofs[] = {
265 	[DSIM_STATUS_REG] =  0x00,
266 	[DSIM_SWRST_REG] =  0x04,
267 	[DSIM_CLKCTRL_REG] =  0x08,
268 	[DSIM_TIMEOUT_REG] =  0x0c,
269 	[DSIM_CONFIG_REG] =  0x10,
270 	[DSIM_ESCMODE_REG] =  0x14,
271 	[DSIM_MDRESOL_REG] =  0x18,
272 	[DSIM_MVPORCH_REG] =  0x1c,
273 	[DSIM_MHPORCH_REG] =  0x20,
274 	[DSIM_MSYNC_REG] =  0x24,
275 	[DSIM_INTSRC_REG] =  0x2c,
276 	[DSIM_INTMSK_REG] =  0x30,
277 	[DSIM_PKTHDR_REG] =  0x34,
278 	[DSIM_PAYLOAD_REG] =  0x38,
279 	[DSIM_RXFIFO_REG] =  0x3c,
280 	[DSIM_FIFOCTRL_REG] =  0x44,
281 	[DSIM_PLLCTRL_REG] =  0x4c,
282 	[DSIM_PHYCTRL_REG] =  0x5c,
283 	[DSIM_PHYTIMING_REG] =  0x64,
284 	[DSIM_PHYTIMING1_REG] =  0x68,
285 	[DSIM_PHYTIMING2_REG] =  0x6c,
286 };
287 
288 static const unsigned int exynos5433_reg_ofs[] = {
289 	[DSIM_STATUS_REG] = 0x04,
290 	[DSIM_SWRST_REG] = 0x0C,
291 	[DSIM_CLKCTRL_REG] = 0x10,
292 	[DSIM_TIMEOUT_REG] = 0x14,
293 	[DSIM_CONFIG_REG] = 0x18,
294 	[DSIM_ESCMODE_REG] = 0x1C,
295 	[DSIM_MDRESOL_REG] = 0x20,
296 	[DSIM_MVPORCH_REG] = 0x24,
297 	[DSIM_MHPORCH_REG] = 0x28,
298 	[DSIM_MSYNC_REG] = 0x2C,
299 	[DSIM_INTSRC_REG] = 0x34,
300 	[DSIM_INTMSK_REG] = 0x38,
301 	[DSIM_PKTHDR_REG] = 0x3C,
302 	[DSIM_PAYLOAD_REG] = 0x40,
303 	[DSIM_RXFIFO_REG] = 0x44,
304 	[DSIM_FIFOCTRL_REG] = 0x4C,
305 	[DSIM_PLLCTRL_REG] = 0x94,
306 	[DSIM_PHYCTRL_REG] = 0xA4,
307 	[DSIM_PHYTIMING_REG] = 0xB4,
308 	[DSIM_PHYTIMING1_REG] = 0xB8,
309 	[DSIM_PHYTIMING2_REG] = 0xBC,
310 };
311 
312 enum reg_value_idx {
313 	RESET_TYPE,
314 	PLL_TIMER,
315 	STOP_STATE_CNT,
316 	PHYCTRL_ULPS_EXIT,
317 	PHYCTRL_VREG_LP,
318 	PHYCTRL_SLEW_UP,
319 	PHYTIMING_LPX,
320 	PHYTIMING_HS_EXIT,
321 	PHYTIMING_CLK_PREPARE,
322 	PHYTIMING_CLK_ZERO,
323 	PHYTIMING_CLK_POST,
324 	PHYTIMING_CLK_TRAIL,
325 	PHYTIMING_HS_PREPARE,
326 	PHYTIMING_HS_ZERO,
327 	PHYTIMING_HS_TRAIL
328 };
329 
330 static const unsigned int reg_values[] = {
331 	[RESET_TYPE] = DSIM_SWRST,
332 	[PLL_TIMER] = 500,
333 	[STOP_STATE_CNT] = 0xf,
334 	[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
335 	[PHYCTRL_VREG_LP] = 0,
336 	[PHYCTRL_SLEW_UP] = 0,
337 	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
338 	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
339 	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
340 	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
341 	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
342 	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
343 	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
344 	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
345 	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
346 };
347 
348 static const unsigned int exynos5422_reg_values[] = {
349 	[RESET_TYPE] = DSIM_SWRST,
350 	[PLL_TIMER] = 500,
351 	[STOP_STATE_CNT] = 0xf,
352 	[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
353 	[PHYCTRL_VREG_LP] = 0,
354 	[PHYCTRL_SLEW_UP] = 0,
355 	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08),
356 	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d),
357 	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
358 	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30),
359 	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
360 	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a),
361 	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c),
362 	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11),
363 	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
364 };
365 
366 static const unsigned int exynos5433_reg_values[] = {
367 	[RESET_TYPE] = DSIM_FUNCRST,
368 	[PLL_TIMER] = 22200,
369 	[STOP_STATE_CNT] = 0xa,
370 	[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190),
371 	[PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP,
372 	[PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP,
373 	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
374 	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
375 	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
376 	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d),
377 	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
378 	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
379 	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b),
380 	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10),
381 	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
382 };
383 
384 static const unsigned int imx8mm_dsim_reg_values[] = {
385 	[RESET_TYPE] = DSIM_SWRST,
386 	[PLL_TIMER] = 500,
387 	[STOP_STATE_CNT] = 0xf,
388 	[PHYCTRL_ULPS_EXIT] = 0,
389 	[PHYCTRL_VREG_LP] = 0,
390 	[PHYCTRL_SLEW_UP] = 0,
391 	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
392 	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
393 	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
394 	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x26),
395 	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
396 	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
397 	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x08),
398 	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
399 	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
400 };
401 
402 static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = {
403 	.reg_ofs = exynos_reg_ofs,
404 	.plltmr_reg = 0x50,
405 	.has_freqband = 1,
406 	.has_clklane_stop = 1,
407 	.num_clks = 2,
408 	.max_freq = 1000,
409 	.wait_for_reset = 1,
410 	.num_bits_resol = 11,
411 	.pll_p_offset = 13,
412 	.reg_values = reg_values,
413 	.m_min = 41,
414 	.m_max = 125,
415 	.min_freq = 500,
416 };
417 
418 static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = {
419 	.reg_ofs = exynos_reg_ofs,
420 	.plltmr_reg = 0x50,
421 	.has_freqband = 1,
422 	.has_clklane_stop = 1,
423 	.num_clks = 2,
424 	.max_freq = 1000,
425 	.wait_for_reset = 1,
426 	.num_bits_resol = 11,
427 	.pll_p_offset = 13,
428 	.reg_values = reg_values,
429 	.m_min = 41,
430 	.m_max = 125,
431 	.min_freq = 500,
432 };
433 
434 static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = {
435 	.reg_ofs = exynos_reg_ofs,
436 	.plltmr_reg = 0x58,
437 	.num_clks = 2,
438 	.max_freq = 1000,
439 	.wait_for_reset = 1,
440 	.num_bits_resol = 11,
441 	.pll_p_offset = 13,
442 	.reg_values = reg_values,
443 	.m_min = 41,
444 	.m_max = 125,
445 	.min_freq = 500,
446 };
447 
448 static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = {
449 	.reg_ofs = exynos5433_reg_ofs,
450 	.plltmr_reg = 0xa0,
451 	.has_clklane_stop = 1,
452 	.num_clks = 5,
453 	.max_freq = 1500,
454 	.wait_for_reset = 0,
455 	.num_bits_resol = 12,
456 	.pll_p_offset = 13,
457 	.reg_values = exynos5433_reg_values,
458 	.m_min = 41,
459 	.m_max = 125,
460 	.min_freq = 500,
461 };
462 
463 static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = {
464 	.reg_ofs = exynos5433_reg_ofs,
465 	.plltmr_reg = 0xa0,
466 	.has_clklane_stop = 1,
467 	.num_clks = 2,
468 	.max_freq = 1500,
469 	.wait_for_reset = 1,
470 	.num_bits_resol = 12,
471 	.pll_p_offset = 13,
472 	.reg_values = exynos5422_reg_values,
473 	.m_min = 41,
474 	.m_max = 125,
475 	.min_freq = 500,
476 };
477 
478 static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = {
479 	.reg_ofs = exynos5433_reg_ofs,
480 	.plltmr_reg = 0xa0,
481 	.has_clklane_stop = 1,
482 	.num_clks = 2,
483 	.max_freq = 2100,
484 	.wait_for_reset = 0,
485 	.num_bits_resol = 12,
486 	/*
487 	 * Unlike Exynos, PLL_P(PMS_P) offset 14 is used in i.MX8M Mini/Nano/Plus
488 	 * downstream driver - drivers/gpu/drm/bridge/sec-dsim.c
489 	 */
490 	.pll_p_offset = 14,
491 	.reg_values = imx8mm_dsim_reg_values,
492 	.m_min = 64,
493 	.m_max = 1023,
494 	.min_freq = 1050,
495 };
496 
497 static const struct samsung_dsim_driver_data *
498 samsung_dsim_types[DSIM_TYPE_COUNT] = {
499 	[DSIM_TYPE_EXYNOS3250] = &exynos3_dsi_driver_data,
500 	[DSIM_TYPE_EXYNOS4210] = &exynos4_dsi_driver_data,
501 	[DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data,
502 	[DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data,
503 	[DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data,
504 	[DSIM_TYPE_IMX8MM] = &imx8mm_dsi_driver_data,
505 	[DSIM_TYPE_IMX8MP] = &imx8mm_dsi_driver_data,
506 };
507 
508 static inline struct samsung_dsim *host_to_dsi(struct mipi_dsi_host *h)
509 {
510 	return container_of(h, struct samsung_dsim, dsi_host);
511 }
512 
513 static inline struct samsung_dsim *bridge_to_dsi(struct drm_bridge *b)
514 {
515 	return container_of(b, struct samsung_dsim, bridge);
516 }
517 
518 static inline void samsung_dsim_write(struct samsung_dsim *dsi,
519 				      enum reg_idx idx, u32 val)
520 {
521 	writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
522 }
523 
524 static inline u32 samsung_dsim_read(struct samsung_dsim *dsi, enum reg_idx idx)
525 {
526 	return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
527 }
528 
529 static void samsung_dsim_wait_for_reset(struct samsung_dsim *dsi)
530 {
531 	if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
532 		return;
533 
534 	dev_err(dsi->dev, "timeout waiting for reset\n");
535 }
536 
537 static void samsung_dsim_reset(struct samsung_dsim *dsi)
538 {
539 	u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];
540 
541 	reinit_completion(&dsi->completed);
542 	samsung_dsim_write(dsi, DSIM_SWRST_REG, reset_val);
543 }
544 
545 #ifndef MHZ
546 #define MHZ	(1000 * 1000)
547 #endif
548 
549 static unsigned long samsung_dsim_pll_find_pms(struct samsung_dsim *dsi,
550 					       unsigned long fin,
551 					       unsigned long fout,
552 					       u8 *p, u16 *m, u8 *s)
553 {
554 	const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
555 	unsigned long best_freq = 0;
556 	u32 min_delta = 0xffffffff;
557 	u8 p_min, p_max;
558 	u8 _p, best_p;
559 	u16 _m, best_m;
560 	u8 _s, best_s;
561 
562 	p_min = DIV_ROUND_UP(fin, (12 * MHZ));
563 	p_max = fin / (6 * MHZ);
564 
565 	for (_p = p_min; _p <= p_max; ++_p) {
566 		for (_s = 0; _s <= 5; ++_s) {
567 			u64 tmp;
568 			u32 delta;
569 
570 			tmp = (u64)fout * (_p << _s);
571 			do_div(tmp, fin);
572 			_m = tmp;
573 			if (_m < driver_data->m_min || _m > driver_data->m_max)
574 				continue;
575 
576 			tmp = (u64)_m * fin;
577 			do_div(tmp, _p);
578 			if (tmp < driver_data->min_freq  * MHZ ||
579 			    tmp > driver_data->max_freq * MHZ)
580 				continue;
581 
582 			tmp = (u64)_m * fin;
583 			do_div(tmp, _p << _s);
584 
585 			delta = abs(fout - tmp);
586 			if (delta < min_delta) {
587 				best_p = _p;
588 				best_m = _m;
589 				best_s = _s;
590 				min_delta = delta;
591 				best_freq = tmp;
592 			}
593 		}
594 	}
595 
596 	if (best_freq) {
597 		*p = best_p;
598 		*m = best_m;
599 		*s = best_s;
600 	}
601 
602 	return best_freq;
603 }
604 
605 static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
606 					  unsigned long freq)
607 {
608 	const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
609 	unsigned long fin, fout;
610 	int timeout;
611 	u8 p, s;
612 	u16 m;
613 	u32 reg;
614 
615 	fin = dsi->pll_clk_rate;
616 	fout = samsung_dsim_pll_find_pms(dsi, fin, freq, &p, &m, &s);
617 	if (!fout) {
618 		dev_err(dsi->dev,
619 			"failed to find PLL PMS for requested frequency\n");
620 		return 0;
621 	}
622 	dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
623 
624 	writel(driver_data->reg_values[PLL_TIMER],
625 	       dsi->reg_base + driver_data->plltmr_reg);
626 
627 	reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) |
628 	      DSIM_PLL_M(m) | DSIM_PLL_S(s);
629 
630 	if (driver_data->has_freqband) {
631 		static const unsigned long freq_bands[] = {
632 			100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
633 			270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
634 			510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
635 			770 * MHZ, 870 * MHZ, 950 * MHZ,
636 		};
637 		int band;
638 
639 		for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
640 			if (fout < freq_bands[band])
641 				break;
642 
643 		dev_dbg(dsi->dev, "band %d\n", band);
644 
645 		reg |= DSIM_FREQ_BAND(band);
646 	}
647 
648 	if (dsi->swap_dn_dp_clk)
649 		reg |= DSIM_PLL_DPDNSWAP_CLK;
650 	if (dsi->swap_dn_dp_data)
651 		reg |= DSIM_PLL_DPDNSWAP_DAT;
652 
653 	samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
654 
655 	timeout = 1000;
656 	do {
657 		if (timeout-- == 0) {
658 			dev_err(dsi->dev, "PLL failed to stabilize\n");
659 			return 0;
660 		}
661 		reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
662 	} while ((reg & DSIM_PLL_STABLE) == 0);
663 
664 	dsi->hs_clock = fout;
665 
666 	return fout;
667 }
668 
669 static int samsung_dsim_enable_clock(struct samsung_dsim *dsi)
670 {
671 	unsigned long hs_clk, byte_clk, esc_clk, pix_clk;
672 	unsigned long esc_div;
673 	u32 reg;
674 	struct drm_display_mode *m = &dsi->mode;
675 	int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
676 
677 	/* m->clock is in KHz */
678 	pix_clk = m->clock * 1000;
679 
680 	/* Use burst_clk_rate if available, otherwise use the pix_clk */
681 	if (dsi->burst_clk_rate)
682 		hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate);
683 	else
684 		hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->lanes));
685 
686 	if (!hs_clk) {
687 		dev_err(dsi->dev, "failed to configure DSI PLL\n");
688 		return -EFAULT;
689 	}
690 
691 	byte_clk = hs_clk / 8;
692 	esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
693 	esc_clk = byte_clk / esc_div;
694 
695 	if (esc_clk > 20 * MHZ) {
696 		++esc_div;
697 		esc_clk = byte_clk / esc_div;
698 	}
699 
700 	dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
701 		hs_clk, byte_clk, esc_clk);
702 
703 	reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG);
704 	reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
705 			| DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
706 			| DSIM_BYTE_CLK_SRC_MASK);
707 	reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
708 			| DSIM_ESC_PRESCALER(esc_div)
709 			| DSIM_LANE_ESC_CLK_EN_CLK
710 			| DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
711 			| DSIM_BYTE_CLK_SRC(0)
712 			| DSIM_TX_REQUEST_HSCLK;
713 	samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg);
714 
715 	return 0;
716 }
717 
718 static void samsung_dsim_set_phy_ctrl(struct samsung_dsim *dsi)
719 {
720 	const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
721 	const unsigned int *reg_values = driver_data->reg_values;
722 	u32 reg;
723 	struct phy_configure_opts_mipi_dphy cfg;
724 	int clk_prepare, lpx, clk_zero, clk_post, clk_trail;
725 	int hs_exit, hs_prepare, hs_zero, hs_trail;
726 	unsigned long long byte_clock = dsi->hs_clock / 8;
727 
728 	if (driver_data->has_freqband)
729 		return;
730 
731 	phy_mipi_dphy_get_default_config_for_hsclk(dsi->hs_clock,
732 						   dsi->lanes, &cfg);
733 
734 	/*
735 	 * TODO:
736 	 * The tech Applications Processor manuals for i.MX8M Mini, Nano,
737 	 * and Plus don't state what the definition of the PHYTIMING
738 	 * bits are beyond their address and bit position.
739 	 * After reviewing NXP's downstream code, it appears
740 	 * that the various PHYTIMING registers take the number
741 	 * of cycles and use various dividers on them.  This
742 	 * calculation does not result in an exact match to the
743 	 * downstream code, but it is very close to the values
744 	 * generated by their lookup table, and it appears
745 	 * to sync at a variety of resolutions. If someone
746 	 * can get a more accurate mathematical equation needed
747 	 * for these registers, this should be updated.
748 	 */
749 
750 	lpx = PS_TO_CYCLE(cfg.lpx, byte_clock);
751 	hs_exit = PS_TO_CYCLE(cfg.hs_exit, byte_clock);
752 	clk_prepare = PS_TO_CYCLE(cfg.clk_prepare, byte_clock);
753 	clk_zero = PS_TO_CYCLE(cfg.clk_zero, byte_clock);
754 	clk_post = PS_TO_CYCLE(cfg.clk_post, byte_clock);
755 	clk_trail = PS_TO_CYCLE(cfg.clk_trail, byte_clock);
756 	hs_prepare = PS_TO_CYCLE(cfg.hs_prepare, byte_clock);
757 	hs_zero = PS_TO_CYCLE(cfg.hs_zero, byte_clock);
758 	hs_trail = PS_TO_CYCLE(cfg.hs_trail, byte_clock);
759 
760 	/* B D-PHY: D-PHY Master & Slave Analog Block control */
761 	reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
762 		reg_values[PHYCTRL_SLEW_UP];
763 
764 	samsung_dsim_write(dsi, DSIM_PHYCTRL_REG, reg);
765 
766 	/*
767 	 * T LPX: Transmitted length of any Low-Power state period
768 	 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
769 	 *	burst
770 	 */
771 
772 	reg  = DSIM_PHYTIMING_LPX(lpx) | DSIM_PHYTIMING_HS_EXIT(hs_exit);
773 
774 	samsung_dsim_write(dsi, DSIM_PHYTIMING_REG, reg);
775 
776 	/*
777 	 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
778 	 *	Line state immediately before the HS-0 Line state starting the
779 	 *	HS transmission
780 	 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
781 	 *	transmitting the Clock.
782 	 * T CLK_POST: Time that the transmitter continues to send HS clock
783 	 *	after the last associated Data Lane has transitioned to LP Mode
784 	 *	Interval is defined as the period from the end of T HS-TRAIL to
785 	 *	the beginning of T CLK-TRAIL
786 	 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
787 	 *	the last payload clock bit of a HS transmission burst
788 	 */
789 
790 	reg = DSIM_PHYTIMING1_CLK_PREPARE(clk_prepare)	|
791 	      DSIM_PHYTIMING1_CLK_ZERO(clk_zero)	|
792 	      DSIM_PHYTIMING1_CLK_POST(clk_post)	|
793 	      DSIM_PHYTIMING1_CLK_TRAIL(clk_trail);
794 
795 	samsung_dsim_write(dsi, DSIM_PHYTIMING1_REG, reg);
796 
797 	/*
798 	 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
799 	 *	Line state immediately before the HS-0 Line state starting the
800 	 *	HS transmission
801 	 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
802 	 *	transmitting the Sync sequence.
803 	 * T HS-TRAIL: Time that the transmitter drives the flipped differential
804 	 *	state after last payload data bit of a HS transmission burst
805 	 */
806 
807 	reg = DSIM_PHYTIMING2_HS_PREPARE(hs_prepare) |
808 	      DSIM_PHYTIMING2_HS_ZERO(hs_zero) |
809 	      DSIM_PHYTIMING2_HS_TRAIL(hs_trail);
810 
811 	samsung_dsim_write(dsi, DSIM_PHYTIMING2_REG, reg);
812 }
813 
814 static void samsung_dsim_disable_clock(struct samsung_dsim *dsi)
815 {
816 	u32 reg;
817 
818 	reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG);
819 	reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
820 			| DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
821 	samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg);
822 
823 	reg = samsung_dsim_read(dsi, DSIM_PLLCTRL_REG);
824 	reg &= ~DSIM_PLL_EN;
825 	samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
826 }
827 
828 static void samsung_dsim_enable_lane(struct samsung_dsim *dsi, u32 lane)
829 {
830 	u32 reg = samsung_dsim_read(dsi, DSIM_CONFIG_REG);
831 
832 	reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
833 			DSIM_LANE_EN(lane));
834 	samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg);
835 }
836 
837 static int samsung_dsim_init_link(struct samsung_dsim *dsi)
838 {
839 	const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
840 	int timeout;
841 	u32 reg;
842 	u32 lanes_mask;
843 
844 	/* Initialize FIFO pointers */
845 	reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG);
846 	reg &= ~0x1f;
847 	samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg);
848 
849 	usleep_range(9000, 11000);
850 
851 	reg |= 0x1f;
852 	samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg);
853 	usleep_range(9000, 11000);
854 
855 	/* DSI configuration */
856 	reg = 0;
857 
858 	/*
859 	 * The first bit of mode_flags specifies display configuration.
860 	 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
861 	 * mode, otherwise it will support command mode.
862 	 */
863 	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
864 		reg |= DSIM_VIDEO_MODE;
865 
866 		/*
867 		 * The user manual describes that following bits are ignored in
868 		 * command mode.
869 		 */
870 		if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
871 			reg |= DSIM_MFLUSH_VS;
872 		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
873 			reg |= DSIM_SYNC_INFORM;
874 		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
875 			reg |= DSIM_BURST_MODE;
876 		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
877 			reg |= DSIM_AUTO_MODE;
878 		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
879 			reg |= DSIM_HSE_DISABLE_MODE;
880 		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP)
881 			reg |= DSIM_HFP_DISABLE_MODE;
882 		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP)
883 			reg |= DSIM_HBP_DISABLE_MODE;
884 		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA)
885 			reg |= DSIM_HSA_DISABLE_MODE;
886 	}
887 
888 	if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
889 		reg |= DSIM_EOT_DISABLE;
890 
891 	switch (dsi->format) {
892 	case MIPI_DSI_FMT_RGB888:
893 		reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
894 		break;
895 	case MIPI_DSI_FMT_RGB666:
896 		reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
897 		break;
898 	case MIPI_DSI_FMT_RGB666_PACKED:
899 		reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
900 		break;
901 	case MIPI_DSI_FMT_RGB565:
902 		reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
903 		break;
904 	default:
905 		dev_err(dsi->dev, "invalid pixel format\n");
906 		return -EINVAL;
907 	}
908 
909 	/*
910 	 * Use non-continuous clock mode if the periparal wants and
911 	 * host controller supports
912 	 *
913 	 * In non-continous clock mode, host controller will turn off
914 	 * the HS clock between high-speed transmissions to reduce
915 	 * power consumption.
916 	 */
917 	if (driver_data->has_clklane_stop &&
918 	    dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
919 		reg |= DSIM_CLKLANE_STOP;
920 	samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg);
921 
922 	lanes_mask = BIT(dsi->lanes) - 1;
923 	samsung_dsim_enable_lane(dsi, lanes_mask);
924 
925 	/* Check clock and data lane state are stop state */
926 	timeout = 100;
927 	do {
928 		if (timeout-- == 0) {
929 			dev_err(dsi->dev, "waiting for bus lanes timed out\n");
930 			return -EFAULT;
931 		}
932 
933 		reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
934 		if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
935 		    != DSIM_STOP_STATE_DAT(lanes_mask))
936 			continue;
937 	} while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
938 
939 	reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
940 	reg &= ~DSIM_STOP_STATE_CNT_MASK;
941 	reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
942 
943 	if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type))
944 		reg |= DSIM_FORCE_STOP_STATE;
945 
946 	samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg);
947 
948 	reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
949 	samsung_dsim_write(dsi, DSIM_TIMEOUT_REG, reg);
950 
951 	return 0;
952 }
953 
954 static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi)
955 {
956 	struct drm_display_mode *m = &dsi->mode;
957 	unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
958 	u32 reg;
959 
960 	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
961 		int byte_clk_khz = dsi->hs_clock / 1000 / 8;
962 		int hfp = (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock;
963 		int hbp = (m->htotal - m->hsync_end) * byte_clk_khz / m->clock;
964 		int hsa = (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock;
965 
966 		/* remove packet overhead when possible */
967 		hfp = max(hfp - 6, 0);
968 		hbp = max(hbp - 6, 0);
969 		hsa = max(hsa - 6, 0);
970 
971 		dev_dbg(dsi->dev, "calculated hfp: %u, hbp: %u, hsa: %u",
972 			hfp, hbp, hsa);
973 
974 		reg = DSIM_CMD_ALLOW(0xf)
975 			| DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)
976 			| DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
977 		samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg);
978 
979 		reg = DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp);
980 		samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg);
981 
982 		reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
983 			| DSIM_MAIN_HSA(hsa);
984 		samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg);
985 	}
986 	reg =  DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |
987 		DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol);
988 
989 	samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg);
990 
991 	dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay);
992 }
993 
994 static void samsung_dsim_set_display_enable(struct samsung_dsim *dsi, bool enable)
995 {
996 	u32 reg;
997 
998 	reg = samsung_dsim_read(dsi, DSIM_MDRESOL_REG);
999 	if (enable)
1000 		reg |= DSIM_MAIN_STAND_BY;
1001 	else
1002 		reg &= ~DSIM_MAIN_STAND_BY;
1003 	samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg);
1004 }
1005 
1006 static int samsung_dsim_wait_for_hdr_fifo(struct samsung_dsim *dsi)
1007 {
1008 	int timeout = 2000;
1009 
1010 	do {
1011 		u32 reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG);
1012 
1013 		if (reg & DSIM_SFR_HEADER_EMPTY)
1014 			return 0;
1015 
1016 		if (!cond_resched())
1017 			usleep_range(950, 1050);
1018 	} while (--timeout);
1019 
1020 	return -ETIMEDOUT;
1021 }
1022 
1023 static void samsung_dsim_set_cmd_lpm(struct samsung_dsim *dsi, bool lpm)
1024 {
1025 	u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
1026 
1027 	if (lpm)
1028 		v |= DSIM_CMD_LPDT_LP;
1029 	else
1030 		v &= ~DSIM_CMD_LPDT_LP;
1031 
1032 	samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v);
1033 }
1034 
1035 static void samsung_dsim_force_bta(struct samsung_dsim *dsi)
1036 {
1037 	u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
1038 
1039 	v |= DSIM_FORCE_BTA;
1040 	samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v);
1041 }
1042 
1043 static void samsung_dsim_send_to_fifo(struct samsung_dsim *dsi,
1044 				      struct samsung_dsim_transfer *xfer)
1045 {
1046 	struct device *dev = dsi->dev;
1047 	struct mipi_dsi_packet *pkt = &xfer->packet;
1048 	const u8 *payload = pkt->payload + xfer->tx_done;
1049 	u16 length = pkt->payload_length - xfer->tx_done;
1050 	bool first = !xfer->tx_done;
1051 	u32 reg;
1052 
1053 	dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n",
1054 		xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done);
1055 
1056 	if (length > DSI_TX_FIFO_SIZE)
1057 		length = DSI_TX_FIFO_SIZE;
1058 
1059 	xfer->tx_done += length;
1060 
1061 	/* Send payload */
1062 	while (length >= 4) {
1063 		reg = get_unaligned_le32(payload);
1064 		samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg);
1065 		payload += 4;
1066 		length -= 4;
1067 	}
1068 
1069 	reg = 0;
1070 	switch (length) {
1071 	case 3:
1072 		reg |= payload[2] << 16;
1073 		fallthrough;
1074 	case 2:
1075 		reg |= payload[1] << 8;
1076 		fallthrough;
1077 	case 1:
1078 		reg |= payload[0];
1079 		samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg);
1080 		break;
1081 	}
1082 
1083 	/* Send packet header */
1084 	if (!first)
1085 		return;
1086 
1087 	reg = get_unaligned_le32(pkt->header);
1088 	if (samsung_dsim_wait_for_hdr_fifo(dsi)) {
1089 		dev_err(dev, "waiting for header FIFO timed out\n");
1090 		return;
1091 	}
1092 
1093 	if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
1094 		 dsi->state & DSIM_STATE_CMD_LPM)) {
1095 		samsung_dsim_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
1096 		dsi->state ^= DSIM_STATE_CMD_LPM;
1097 	}
1098 
1099 	samsung_dsim_write(dsi, DSIM_PKTHDR_REG, reg);
1100 
1101 	if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
1102 		samsung_dsim_force_bta(dsi);
1103 }
1104 
1105 static void samsung_dsim_read_from_fifo(struct samsung_dsim *dsi,
1106 					struct samsung_dsim_transfer *xfer)
1107 {
1108 	u8 *payload = xfer->rx_payload + xfer->rx_done;
1109 	bool first = !xfer->rx_done;
1110 	struct device *dev = dsi->dev;
1111 	u16 length;
1112 	u32 reg;
1113 
1114 	if (first) {
1115 		reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1116 
1117 		switch (reg & 0x3f) {
1118 		case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1119 		case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1120 			if (xfer->rx_len >= 2) {
1121 				payload[1] = reg >> 16;
1122 				++xfer->rx_done;
1123 			}
1124 			fallthrough;
1125 		case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1126 		case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1127 			payload[0] = reg >> 8;
1128 			++xfer->rx_done;
1129 			xfer->rx_len = xfer->rx_done;
1130 			xfer->result = 0;
1131 			goto clear_fifo;
1132 		case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1133 			dev_err(dev, "DSI Error Report: 0x%04x\n", (reg >> 8) & 0xffff);
1134 			xfer->result = 0;
1135 			goto clear_fifo;
1136 		}
1137 
1138 		length = (reg >> 8) & 0xffff;
1139 		if (length > xfer->rx_len) {
1140 			dev_err(dev,
1141 				"response too long (%u > %u bytes), stripping\n",
1142 				xfer->rx_len, length);
1143 			length = xfer->rx_len;
1144 		} else if (length < xfer->rx_len) {
1145 			xfer->rx_len = length;
1146 		}
1147 	}
1148 
1149 	length = xfer->rx_len - xfer->rx_done;
1150 	xfer->rx_done += length;
1151 
1152 	/* Receive payload */
1153 	while (length >= 4) {
1154 		reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1155 		payload[0] = (reg >>  0) & 0xff;
1156 		payload[1] = (reg >>  8) & 0xff;
1157 		payload[2] = (reg >> 16) & 0xff;
1158 		payload[3] = (reg >> 24) & 0xff;
1159 		payload += 4;
1160 		length -= 4;
1161 	}
1162 
1163 	if (length) {
1164 		reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1165 		switch (length) {
1166 		case 3:
1167 			payload[2] = (reg >> 16) & 0xff;
1168 			fallthrough;
1169 		case 2:
1170 			payload[1] = (reg >> 8) & 0xff;
1171 			fallthrough;
1172 		case 1:
1173 			payload[0] = reg & 0xff;
1174 		}
1175 	}
1176 
1177 	if (xfer->rx_done == xfer->rx_len)
1178 		xfer->result = 0;
1179 
1180 clear_fifo:
1181 	length = DSI_RX_FIFO_SIZE / 4;
1182 	do {
1183 		reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1184 		if (reg == DSI_RX_FIFO_EMPTY)
1185 			break;
1186 	} while (--length);
1187 }
1188 
1189 static void samsung_dsim_transfer_start(struct samsung_dsim *dsi)
1190 {
1191 	unsigned long flags;
1192 	struct samsung_dsim_transfer *xfer;
1193 	bool start = false;
1194 
1195 again:
1196 	spin_lock_irqsave(&dsi->transfer_lock, flags);
1197 
1198 	if (list_empty(&dsi->transfer_list)) {
1199 		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1200 		return;
1201 	}
1202 
1203 	xfer = list_first_entry(&dsi->transfer_list,
1204 				struct samsung_dsim_transfer, list);
1205 
1206 	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1207 
1208 	if (xfer->packet.payload_length &&
1209 	    xfer->tx_done == xfer->packet.payload_length)
1210 		/* waiting for RX */
1211 		return;
1212 
1213 	samsung_dsim_send_to_fifo(dsi, xfer);
1214 
1215 	if (xfer->packet.payload_length || xfer->rx_len)
1216 		return;
1217 
1218 	xfer->result = 0;
1219 	complete(&xfer->completed);
1220 
1221 	spin_lock_irqsave(&dsi->transfer_lock, flags);
1222 
1223 	list_del_init(&xfer->list);
1224 	start = !list_empty(&dsi->transfer_list);
1225 
1226 	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1227 
1228 	if (start)
1229 		goto again;
1230 }
1231 
1232 static bool samsung_dsim_transfer_finish(struct samsung_dsim *dsi)
1233 {
1234 	struct samsung_dsim_transfer *xfer;
1235 	unsigned long flags;
1236 	bool start = true;
1237 
1238 	spin_lock_irqsave(&dsi->transfer_lock, flags);
1239 
1240 	if (list_empty(&dsi->transfer_list)) {
1241 		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1242 		return false;
1243 	}
1244 
1245 	xfer = list_first_entry(&dsi->transfer_list,
1246 				struct samsung_dsim_transfer, list);
1247 
1248 	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1249 
1250 	dev_dbg(dsi->dev,
1251 		"> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n",
1252 		xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len,
1253 		xfer->rx_done);
1254 
1255 	if (xfer->tx_done != xfer->packet.payload_length)
1256 		return true;
1257 
1258 	if (xfer->rx_done != xfer->rx_len)
1259 		samsung_dsim_read_from_fifo(dsi, xfer);
1260 
1261 	if (xfer->rx_done != xfer->rx_len)
1262 		return true;
1263 
1264 	spin_lock_irqsave(&dsi->transfer_lock, flags);
1265 
1266 	list_del_init(&xfer->list);
1267 	start = !list_empty(&dsi->transfer_list);
1268 
1269 	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1270 
1271 	if (!xfer->rx_len)
1272 		xfer->result = 0;
1273 	complete(&xfer->completed);
1274 
1275 	return start;
1276 }
1277 
1278 static void samsung_dsim_remove_transfer(struct samsung_dsim *dsi,
1279 					 struct samsung_dsim_transfer *xfer)
1280 {
1281 	unsigned long flags;
1282 	bool start;
1283 
1284 	spin_lock_irqsave(&dsi->transfer_lock, flags);
1285 
1286 	if (!list_empty(&dsi->transfer_list) &&
1287 	    xfer == list_first_entry(&dsi->transfer_list,
1288 				     struct samsung_dsim_transfer, list)) {
1289 		list_del_init(&xfer->list);
1290 		start = !list_empty(&dsi->transfer_list);
1291 		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1292 		if (start)
1293 			samsung_dsim_transfer_start(dsi);
1294 		return;
1295 	}
1296 
1297 	list_del_init(&xfer->list);
1298 
1299 	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1300 }
1301 
1302 static int samsung_dsim_transfer(struct samsung_dsim *dsi,
1303 				 struct samsung_dsim_transfer *xfer)
1304 {
1305 	unsigned long flags;
1306 	bool stopped;
1307 
1308 	xfer->tx_done = 0;
1309 	xfer->rx_done = 0;
1310 	xfer->result = -ETIMEDOUT;
1311 	init_completion(&xfer->completed);
1312 
1313 	spin_lock_irqsave(&dsi->transfer_lock, flags);
1314 
1315 	stopped = list_empty(&dsi->transfer_list);
1316 	list_add_tail(&xfer->list, &dsi->transfer_list);
1317 
1318 	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1319 
1320 	if (stopped)
1321 		samsung_dsim_transfer_start(dsi);
1322 
1323 	wait_for_completion_timeout(&xfer->completed,
1324 				    msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
1325 	if (xfer->result == -ETIMEDOUT) {
1326 		struct mipi_dsi_packet *pkt = &xfer->packet;
1327 
1328 		samsung_dsim_remove_transfer(dsi, xfer);
1329 		dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header,
1330 			(int)pkt->payload_length, pkt->payload);
1331 		return -ETIMEDOUT;
1332 	}
1333 
1334 	/* Also covers hardware timeout condition */
1335 	return xfer->result;
1336 }
1337 
1338 static irqreturn_t samsung_dsim_irq(int irq, void *dev_id)
1339 {
1340 	struct samsung_dsim *dsi = dev_id;
1341 	u32 status;
1342 
1343 	status = samsung_dsim_read(dsi, DSIM_INTSRC_REG);
1344 	if (!status) {
1345 		static unsigned long j;
1346 
1347 		if (printk_timed_ratelimit(&j, 500))
1348 			dev_warn(dsi->dev, "spurious interrupt\n");
1349 		return IRQ_HANDLED;
1350 	}
1351 	samsung_dsim_write(dsi, DSIM_INTSRC_REG, status);
1352 
1353 	if (status & DSIM_INT_SW_RST_RELEASE) {
1354 		unsigned long mask = ~(DSIM_INT_RX_DONE |
1355 				       DSIM_INT_SFR_FIFO_EMPTY |
1356 				       DSIM_INT_SFR_HDR_FIFO_EMPTY |
1357 				       DSIM_INT_RX_ECC_ERR |
1358 				       DSIM_INT_SW_RST_RELEASE);
1359 		samsung_dsim_write(dsi, DSIM_INTMSK_REG, mask);
1360 		complete(&dsi->completed);
1361 		return IRQ_HANDLED;
1362 	}
1363 
1364 	if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1365 			DSIM_INT_PLL_STABLE)))
1366 		return IRQ_HANDLED;
1367 
1368 	if (samsung_dsim_transfer_finish(dsi))
1369 		samsung_dsim_transfer_start(dsi);
1370 
1371 	return IRQ_HANDLED;
1372 }
1373 
1374 static void samsung_dsim_enable_irq(struct samsung_dsim *dsi)
1375 {
1376 	enable_irq(dsi->irq);
1377 
1378 	if (dsi->te_gpio)
1379 		enable_irq(gpiod_to_irq(dsi->te_gpio));
1380 }
1381 
1382 static void samsung_dsim_disable_irq(struct samsung_dsim *dsi)
1383 {
1384 	if (dsi->te_gpio)
1385 		disable_irq(gpiod_to_irq(dsi->te_gpio));
1386 
1387 	disable_irq(dsi->irq);
1388 }
1389 
1390 static void samsung_dsim_set_stop_state(struct samsung_dsim *dsi, bool enable)
1391 {
1392 	u32 reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
1393 
1394 	if (enable)
1395 		reg |= DSIM_FORCE_STOP_STATE;
1396 	else
1397 		reg &= ~DSIM_FORCE_STOP_STATE;
1398 
1399 	samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg);
1400 }
1401 
1402 static int samsung_dsim_init(struct samsung_dsim *dsi)
1403 {
1404 	const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
1405 
1406 	if (dsi->state & DSIM_STATE_INITIALIZED)
1407 		return 0;
1408 
1409 	samsung_dsim_reset(dsi);
1410 	samsung_dsim_enable_irq(dsi);
1411 
1412 	if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
1413 		samsung_dsim_enable_lane(dsi, BIT(dsi->lanes) - 1);
1414 
1415 	samsung_dsim_enable_clock(dsi);
1416 	if (driver_data->wait_for_reset)
1417 		samsung_dsim_wait_for_reset(dsi);
1418 	samsung_dsim_set_phy_ctrl(dsi);
1419 	samsung_dsim_init_link(dsi);
1420 
1421 	dsi->state |= DSIM_STATE_INITIALIZED;
1422 
1423 	return 0;
1424 }
1425 
1426 static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge,
1427 					   struct drm_bridge_state *old_bridge_state)
1428 {
1429 	struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1430 	int ret;
1431 
1432 	if (dsi->state & DSIM_STATE_ENABLED)
1433 		return;
1434 
1435 	ret = pm_runtime_resume_and_get(dsi->dev);
1436 	if (ret < 0) {
1437 		dev_err(dsi->dev, "failed to enable DSI device.\n");
1438 		return;
1439 	}
1440 
1441 	dsi->state |= DSIM_STATE_ENABLED;
1442 
1443 	/*
1444 	 * For Exynos-DSIM the downstream bridge, or panel are expecting
1445 	 * the host initialization during DSI transfer.
1446 	 */
1447 	if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) {
1448 		ret = samsung_dsim_init(dsi);
1449 		if (ret)
1450 			return;
1451 
1452 		samsung_dsim_set_display_mode(dsi);
1453 		samsung_dsim_set_display_enable(dsi, true);
1454 	}
1455 }
1456 
1457 static void samsung_dsim_atomic_enable(struct drm_bridge *bridge,
1458 				       struct drm_bridge_state *old_bridge_state)
1459 {
1460 	struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1461 
1462 	if (samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) {
1463 		samsung_dsim_set_display_mode(dsi);
1464 		samsung_dsim_set_display_enable(dsi, true);
1465 	} else {
1466 		samsung_dsim_set_stop_state(dsi, false);
1467 	}
1468 
1469 	dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
1470 }
1471 
1472 static void samsung_dsim_atomic_disable(struct drm_bridge *bridge,
1473 					struct drm_bridge_state *old_bridge_state)
1474 {
1475 	struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1476 
1477 	if (!(dsi->state & DSIM_STATE_ENABLED))
1478 		return;
1479 
1480 	if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type))
1481 		samsung_dsim_set_stop_state(dsi, true);
1482 
1483 	dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
1484 }
1485 
1486 static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
1487 					     struct drm_bridge_state *old_bridge_state)
1488 {
1489 	struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1490 
1491 	samsung_dsim_set_display_enable(dsi, false);
1492 
1493 	dsi->state &= ~DSIM_STATE_ENABLED;
1494 	pm_runtime_put_sync(dsi->dev);
1495 }
1496 
1497 /*
1498  * This pixel output formats list referenced from,
1499  * AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
1500  * 3.7.4 Pixel formats
1501  * Table 14. DSI pixel packing formats
1502  */
1503 static const u32 samsung_dsim_pixel_output_fmts[] = {
1504 	MEDIA_BUS_FMT_YUYV10_1X20,
1505 	MEDIA_BUS_FMT_YUYV12_1X24,
1506 	MEDIA_BUS_FMT_UYVY8_1X16,
1507 	MEDIA_BUS_FMT_RGB101010_1X30,
1508 	MEDIA_BUS_FMT_RGB121212_1X36,
1509 	MEDIA_BUS_FMT_RGB565_1X16,
1510 	MEDIA_BUS_FMT_RGB666_1X18,
1511 	MEDIA_BUS_FMT_RGB888_1X24,
1512 };
1513 
1514 static bool samsung_dsim_pixel_output_fmt_supported(u32 fmt)
1515 {
1516 	int i;
1517 
1518 	if (fmt == MEDIA_BUS_FMT_FIXED)
1519 		return false;
1520 
1521 	for (i = 0; i < ARRAY_SIZE(samsung_dsim_pixel_output_fmts); i++) {
1522 		if (samsung_dsim_pixel_output_fmts[i] == fmt)
1523 			return true;
1524 	}
1525 
1526 	return false;
1527 }
1528 
1529 static u32 *
1530 samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
1531 				       struct drm_bridge_state *bridge_state,
1532 				       struct drm_crtc_state *crtc_state,
1533 				       struct drm_connector_state *conn_state,
1534 				       u32 output_fmt,
1535 				       unsigned int *num_input_fmts)
1536 {
1537 	u32 *input_fmts;
1538 
1539 	input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
1540 	if (!input_fmts)
1541 		return NULL;
1542 
1543 	if (!samsung_dsim_pixel_output_fmt_supported(output_fmt))
1544 		/*
1545 		 * Some bridge/display drivers are still not able to pass the
1546 		 * correct format, so handle those pipelines by falling back
1547 		 * to the default format till the supported formats finalized.
1548 		 */
1549 		output_fmt = MEDIA_BUS_FMT_RGB888_1X24;
1550 
1551 	input_fmts[0] = output_fmt;
1552 	*num_input_fmts = 1;
1553 
1554 	return input_fmts;
1555 }
1556 
1557 static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
1558 				     struct drm_bridge_state *bridge_state,
1559 				     struct drm_crtc_state *crtc_state,
1560 				     struct drm_connector_state *conn_state)
1561 {
1562 	struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1563 	struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1564 
1565 	/*
1566 	 * The i.MX8M Mini/Nano glue logic between LCDIF and DSIM
1567 	 * inverts HS/VS/DE sync signals polarity, therefore, while
1568 	 * i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020
1569 	 * 13.6.3.5.2 RGB interface
1570 	 * i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022
1571 	 * 13.6.2.7.2 RGB interface
1572 	 * both claim "Vsync, Hsync, and VDEN are active high signals.", the
1573 	 * LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW.
1574 	 *
1575 	 * The i.MX8M Plus glue logic between LCDIFv3 and DSIM does not
1576 	 * implement the same behavior, therefore LCDIFv3 must generate
1577 	 * HS/VS/DE signals active HIGH.
1578 	 */
1579 	if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) {
1580 		adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1581 		adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1582 	} else if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MP) {
1583 		adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1584 		adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1585 	}
1586 
1587 	return 0;
1588 }
1589 
1590 static void samsung_dsim_mode_set(struct drm_bridge *bridge,
1591 				  const struct drm_display_mode *mode,
1592 				  const struct drm_display_mode *adjusted_mode)
1593 {
1594 	struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1595 
1596 	drm_mode_copy(&dsi->mode, adjusted_mode);
1597 }
1598 
1599 static int samsung_dsim_attach(struct drm_bridge *bridge,
1600 			       enum drm_bridge_attach_flags flags)
1601 {
1602 	struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1603 
1604 	return drm_bridge_attach(bridge->encoder, dsi->out_bridge, bridge,
1605 				 flags);
1606 }
1607 
1608 static const struct drm_bridge_funcs samsung_dsim_bridge_funcs = {
1609 	.atomic_duplicate_state		= drm_atomic_helper_bridge_duplicate_state,
1610 	.atomic_destroy_state		= drm_atomic_helper_bridge_destroy_state,
1611 	.atomic_reset			= drm_atomic_helper_bridge_reset,
1612 	.atomic_get_input_bus_fmts	= samsung_dsim_atomic_get_input_bus_fmts,
1613 	.atomic_check			= samsung_dsim_atomic_check,
1614 	.atomic_pre_enable		= samsung_dsim_atomic_pre_enable,
1615 	.atomic_enable			= samsung_dsim_atomic_enable,
1616 	.atomic_disable			= samsung_dsim_atomic_disable,
1617 	.atomic_post_disable		= samsung_dsim_atomic_post_disable,
1618 	.mode_set			= samsung_dsim_mode_set,
1619 	.attach				= samsung_dsim_attach,
1620 };
1621 
1622 static irqreturn_t samsung_dsim_te_irq_handler(int irq, void *dev_id)
1623 {
1624 	struct samsung_dsim *dsi = (struct samsung_dsim *)dev_id;
1625 	const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1626 
1627 	if (pdata->host_ops && pdata->host_ops->te_irq_handler)
1628 		return pdata->host_ops->te_irq_handler(dsi);
1629 
1630 	return IRQ_HANDLED;
1631 }
1632 
1633 static int samsung_dsim_register_te_irq(struct samsung_dsim *dsi, struct device *dev)
1634 {
1635 	int te_gpio_irq;
1636 	int ret;
1637 
1638 	dsi->te_gpio = devm_gpiod_get_optional(dev, "te", GPIOD_IN);
1639 	if (!dsi->te_gpio)
1640 		return 0;
1641 	else if (IS_ERR(dsi->te_gpio))
1642 		return dev_err_probe(dev, PTR_ERR(dsi->te_gpio), "failed to get te GPIO\n");
1643 
1644 	te_gpio_irq = gpiod_to_irq(dsi->te_gpio);
1645 
1646 	ret = request_threaded_irq(te_gpio_irq, samsung_dsim_te_irq_handler, NULL,
1647 				   IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, "TE", dsi);
1648 	if (ret) {
1649 		dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1650 		gpiod_put(dsi->te_gpio);
1651 		return ret;
1652 	}
1653 
1654 	return 0;
1655 }
1656 
1657 static int samsung_dsim_host_attach(struct mipi_dsi_host *host,
1658 				    struct mipi_dsi_device *device)
1659 {
1660 	struct samsung_dsim *dsi = host_to_dsi(host);
1661 	const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1662 	struct device *dev = dsi->dev;
1663 	struct device_node *np = dev->of_node;
1664 	struct device_node *remote;
1665 	struct drm_panel *panel;
1666 	int ret;
1667 
1668 	/*
1669 	 * Devices can also be child nodes when we also control that device
1670 	 * through the upstream device (ie, MIPI-DCS for a MIPI-DSI device).
1671 	 *
1672 	 * Lookup for a child node of the given parent that isn't either port
1673 	 * or ports.
1674 	 */
1675 	for_each_available_child_of_node(np, remote) {
1676 		if (of_node_name_eq(remote, "port") ||
1677 		    of_node_name_eq(remote, "ports"))
1678 			continue;
1679 
1680 		goto of_find_panel_or_bridge;
1681 	}
1682 
1683 	/*
1684 	 * of_graph_get_remote_node() produces a noisy error message if port
1685 	 * node isn't found and the absence of the port is a legit case here,
1686 	 * so at first we silently check whether graph presents in the
1687 	 * device-tree node.
1688 	 */
1689 	if (!of_graph_is_present(np))
1690 		return -ENODEV;
1691 
1692 	remote = of_graph_get_remote_node(np, 1, 0);
1693 
1694 of_find_panel_or_bridge:
1695 	if (!remote)
1696 		return -ENODEV;
1697 
1698 	panel = of_drm_find_panel(remote);
1699 	if (!IS_ERR(panel)) {
1700 		dsi->out_bridge = devm_drm_panel_bridge_add(dev, panel);
1701 	} else {
1702 		dsi->out_bridge = of_drm_find_bridge(remote);
1703 		if (!dsi->out_bridge)
1704 			dsi->out_bridge = ERR_PTR(-EINVAL);
1705 	}
1706 
1707 	of_node_put(remote);
1708 
1709 	if (IS_ERR(dsi->out_bridge)) {
1710 		ret = PTR_ERR(dsi->out_bridge);
1711 		DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n", ret);
1712 		return ret;
1713 	}
1714 
1715 	DRM_DEV_INFO(dev, "Attached %s device\n", device->name);
1716 
1717 	drm_bridge_add(&dsi->bridge);
1718 
1719 	/*
1720 	 * This is a temporary solution and should be made by more generic way.
1721 	 *
1722 	 * If attached panel device is for command mode one, dsi should register
1723 	 * TE interrupt handler.
1724 	 */
1725 	if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1726 		ret = samsung_dsim_register_te_irq(dsi, &device->dev);
1727 		if (ret)
1728 			return ret;
1729 	}
1730 
1731 	if (pdata->host_ops && pdata->host_ops->attach) {
1732 		ret = pdata->host_ops->attach(dsi, device);
1733 		if (ret)
1734 			return ret;
1735 	}
1736 
1737 	dsi->lanes = device->lanes;
1738 	dsi->format = device->format;
1739 	dsi->mode_flags = device->mode_flags;
1740 
1741 	return 0;
1742 }
1743 
1744 static void samsung_dsim_unregister_te_irq(struct samsung_dsim *dsi)
1745 {
1746 	if (dsi->te_gpio) {
1747 		free_irq(gpiod_to_irq(dsi->te_gpio), dsi);
1748 		gpiod_put(dsi->te_gpio);
1749 	}
1750 }
1751 
1752 static int samsung_dsim_host_detach(struct mipi_dsi_host *host,
1753 				    struct mipi_dsi_device *device)
1754 {
1755 	struct samsung_dsim *dsi = host_to_dsi(host);
1756 	const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1757 
1758 	dsi->out_bridge = NULL;
1759 
1760 	if (pdata->host_ops && pdata->host_ops->detach)
1761 		pdata->host_ops->detach(dsi, device);
1762 
1763 	samsung_dsim_unregister_te_irq(dsi);
1764 
1765 	drm_bridge_remove(&dsi->bridge);
1766 
1767 	return 0;
1768 }
1769 
1770 static ssize_t samsung_dsim_host_transfer(struct mipi_dsi_host *host,
1771 					  const struct mipi_dsi_msg *msg)
1772 {
1773 	struct samsung_dsim *dsi = host_to_dsi(host);
1774 	struct samsung_dsim_transfer xfer;
1775 	int ret;
1776 
1777 	if (!(dsi->state & DSIM_STATE_ENABLED))
1778 		return -EINVAL;
1779 
1780 	ret = samsung_dsim_init(dsi);
1781 	if (ret)
1782 		return ret;
1783 
1784 	samsung_dsim_set_stop_state(dsi, false);
1785 
1786 	ret = mipi_dsi_create_packet(&xfer.packet, msg);
1787 	if (ret < 0)
1788 		return ret;
1789 
1790 	xfer.rx_len = msg->rx_len;
1791 	xfer.rx_payload = msg->rx_buf;
1792 	xfer.flags = msg->flags;
1793 
1794 	ret = samsung_dsim_transfer(dsi, &xfer);
1795 	return (ret < 0) ? ret : xfer.rx_done;
1796 }
1797 
1798 static const struct mipi_dsi_host_ops samsung_dsim_ops = {
1799 	.attach = samsung_dsim_host_attach,
1800 	.detach = samsung_dsim_host_detach,
1801 	.transfer = samsung_dsim_host_transfer,
1802 };
1803 
1804 static int samsung_dsim_of_read_u32(const struct device_node *np,
1805 				    const char *propname, u32 *out_value, bool optional)
1806 {
1807 	int ret = of_property_read_u32(np, propname, out_value);
1808 
1809 	if (ret < 0 && !optional)
1810 		pr_err("%pOF: failed to get '%s' property\n", np, propname);
1811 
1812 	return ret;
1813 }
1814 
1815 static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
1816 {
1817 	struct device *dev = dsi->dev;
1818 	struct device_node *node = dev->of_node;
1819 	u32 lane_polarities[5] = { 0 };
1820 	struct device_node *endpoint;
1821 	int i, nr_lanes, ret;
1822 	struct clk *pll_clk;
1823 
1824 	ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
1825 				       &dsi->pll_clk_rate, 1);
1826 	/* If it doesn't exist, read it from the clock instead of failing */
1827 	if (ret < 0) {
1828 		dev_dbg(dev, "Using sclk_mipi for pll clock frequency\n");
1829 		pll_clk = devm_clk_get(dev, "sclk_mipi");
1830 		if (!IS_ERR(pll_clk))
1831 			dsi->pll_clk_rate = clk_get_rate(pll_clk);
1832 		else
1833 			return PTR_ERR(pll_clk);
1834 	}
1835 
1836 	/* If it doesn't exist, use pixel clock instead of failing */
1837 	ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency",
1838 				       &dsi->burst_clk_rate, 1);
1839 	if (ret < 0) {
1840 		dev_dbg(dev, "Using pixel clock for HS clock frequency\n");
1841 		dsi->burst_clk_rate = 0;
1842 	}
1843 
1844 	ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency",
1845 				       &dsi->esc_clk_rate, 0);
1846 	if (ret < 0)
1847 		return ret;
1848 
1849 	endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
1850 	nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
1851 	if (nr_lanes > 0 && nr_lanes <= 4) {
1852 		/* Polarity 0 is clock lane, 1..4 are data lanes. */
1853 		of_property_read_u32_array(endpoint, "lane-polarities",
1854 					   lane_polarities, nr_lanes + 1);
1855 		for (i = 1; i <= nr_lanes; i++) {
1856 			if (lane_polarities[1] != lane_polarities[i])
1857 				DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match");
1858 		}
1859 		if (lane_polarities[0])
1860 			dsi->swap_dn_dp_clk = true;
1861 		if (lane_polarities[1])
1862 			dsi->swap_dn_dp_data = true;
1863 	}
1864 
1865 	return 0;
1866 }
1867 
1868 static int generic_dsim_register_host(struct samsung_dsim *dsi)
1869 {
1870 	return mipi_dsi_host_register(&dsi->dsi_host);
1871 }
1872 
1873 static void generic_dsim_unregister_host(struct samsung_dsim *dsi)
1874 {
1875 	mipi_dsi_host_unregister(&dsi->dsi_host);
1876 }
1877 
1878 static const struct samsung_dsim_host_ops generic_dsim_host_ops = {
1879 	.register_host = generic_dsim_register_host,
1880 	.unregister_host = generic_dsim_unregister_host,
1881 };
1882 
1883 static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_high = {
1884 	.input_bus_flags = DRM_BUS_FLAG_DE_HIGH,
1885 };
1886 
1887 static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_low = {
1888 	.input_bus_flags = DRM_BUS_FLAG_DE_LOW,
1889 };
1890 
1891 int samsung_dsim_probe(struct platform_device *pdev)
1892 {
1893 	struct device *dev = &pdev->dev;
1894 	struct samsung_dsim *dsi;
1895 	int ret, i;
1896 
1897 	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1898 	if (!dsi)
1899 		return -ENOMEM;
1900 
1901 	init_completion(&dsi->completed);
1902 	spin_lock_init(&dsi->transfer_lock);
1903 	INIT_LIST_HEAD(&dsi->transfer_list);
1904 
1905 	dsi->dsi_host.ops = &samsung_dsim_ops;
1906 	dsi->dsi_host.dev = dev;
1907 
1908 	dsi->dev = dev;
1909 	dsi->plat_data = of_device_get_match_data(dev);
1910 	dsi->driver_data = samsung_dsim_types[dsi->plat_data->hw_type];
1911 
1912 	dsi->supplies[0].supply = "vddcore";
1913 	dsi->supplies[1].supply = "vddio";
1914 	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1915 				      dsi->supplies);
1916 	if (ret)
1917 		return dev_err_probe(dev, ret, "failed to get regulators\n");
1918 
1919 	dsi->clks = devm_kcalloc(dev, dsi->driver_data->num_clks,
1920 				 sizeof(*dsi->clks), GFP_KERNEL);
1921 	if (!dsi->clks)
1922 		return -ENOMEM;
1923 
1924 	for (i = 0; i < dsi->driver_data->num_clks; i++) {
1925 		dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
1926 		if (IS_ERR(dsi->clks[i])) {
1927 			if (strcmp(clk_names[i], "sclk_mipi") == 0) {
1928 				dsi->clks[i] = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME);
1929 				if (!IS_ERR(dsi->clks[i]))
1930 					continue;
1931 			}
1932 
1933 			dev_info(dev, "failed to get the clock: %s\n", clk_names[i]);
1934 			return PTR_ERR(dsi->clks[i]);
1935 		}
1936 	}
1937 
1938 	dsi->reg_base = devm_platform_ioremap_resource(pdev, 0);
1939 	if (IS_ERR(dsi->reg_base))
1940 		return PTR_ERR(dsi->reg_base);
1941 
1942 	dsi->phy = devm_phy_optional_get(dev, "dsim");
1943 	if (IS_ERR(dsi->phy)) {
1944 		dev_info(dev, "failed to get dsim phy\n");
1945 		return PTR_ERR(dsi->phy);
1946 	}
1947 
1948 	dsi->irq = platform_get_irq(pdev, 0);
1949 	if (dsi->irq < 0)
1950 		return dsi->irq;
1951 
1952 	ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
1953 					samsung_dsim_irq,
1954 					IRQF_ONESHOT | IRQF_NO_AUTOEN,
1955 					dev_name(dev), dsi);
1956 	if (ret) {
1957 		dev_err(dev, "failed to request dsi irq\n");
1958 		return ret;
1959 	}
1960 
1961 	ret = samsung_dsim_parse_dt(dsi);
1962 	if (ret)
1963 		return ret;
1964 
1965 	platform_set_drvdata(pdev, dsi);
1966 
1967 	pm_runtime_enable(dev);
1968 
1969 	dsi->bridge.funcs = &samsung_dsim_bridge_funcs;
1970 	dsi->bridge.of_node = dev->of_node;
1971 	dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
1972 
1973 	/* DE_LOW: i.MX8M Mini/Nano LCDIF-DSIM glue logic inverts HS/VS/DE */
1974 	if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM)
1975 		dsi->bridge.timings = &samsung_dsim_bridge_timings_de_low;
1976 	else
1977 		dsi->bridge.timings = &samsung_dsim_bridge_timings_de_high;
1978 
1979 	if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->register_host)
1980 		ret = dsi->plat_data->host_ops->register_host(dsi);
1981 
1982 	if (ret)
1983 		goto err_disable_runtime;
1984 
1985 	return 0;
1986 
1987 err_disable_runtime:
1988 	pm_runtime_disable(dev);
1989 
1990 	return ret;
1991 }
1992 EXPORT_SYMBOL_GPL(samsung_dsim_probe);
1993 
1994 int samsung_dsim_remove(struct platform_device *pdev)
1995 {
1996 	struct samsung_dsim *dsi = platform_get_drvdata(pdev);
1997 
1998 	pm_runtime_disable(&pdev->dev);
1999 
2000 	if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->unregister_host)
2001 		dsi->plat_data->host_ops->unregister_host(dsi);
2002 
2003 	return 0;
2004 }
2005 EXPORT_SYMBOL_GPL(samsung_dsim_remove);
2006 
2007 static int __maybe_unused samsung_dsim_suspend(struct device *dev)
2008 {
2009 	struct samsung_dsim *dsi = dev_get_drvdata(dev);
2010 	const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
2011 	int ret, i;
2012 
2013 	usleep_range(10000, 20000);
2014 
2015 	if (dsi->state & DSIM_STATE_INITIALIZED) {
2016 		dsi->state &= ~DSIM_STATE_INITIALIZED;
2017 
2018 		samsung_dsim_disable_clock(dsi);
2019 
2020 		samsung_dsim_disable_irq(dsi);
2021 	}
2022 
2023 	dsi->state &= ~DSIM_STATE_CMD_LPM;
2024 
2025 	phy_power_off(dsi->phy);
2026 
2027 	for (i = driver_data->num_clks - 1; i > -1; i--)
2028 		clk_disable_unprepare(dsi->clks[i]);
2029 
2030 	ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
2031 	if (ret < 0)
2032 		dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
2033 
2034 	return 0;
2035 }
2036 
2037 static int __maybe_unused samsung_dsim_resume(struct device *dev)
2038 {
2039 	struct samsung_dsim *dsi = dev_get_drvdata(dev);
2040 	const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
2041 	int ret, i;
2042 
2043 	ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
2044 	if (ret < 0) {
2045 		dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
2046 		return ret;
2047 	}
2048 
2049 	for (i = 0; i < driver_data->num_clks; i++) {
2050 		ret = clk_prepare_enable(dsi->clks[i]);
2051 		if (ret < 0)
2052 			goto err_clk;
2053 	}
2054 
2055 	ret = phy_power_on(dsi->phy);
2056 	if (ret < 0) {
2057 		dev_err(dsi->dev, "cannot enable phy %d\n", ret);
2058 		goto err_clk;
2059 	}
2060 
2061 	return 0;
2062 
2063 err_clk:
2064 	while (--i > -1)
2065 		clk_disable_unprepare(dsi->clks[i]);
2066 	regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
2067 
2068 	return ret;
2069 }
2070 
2071 const struct dev_pm_ops samsung_dsim_pm_ops = {
2072 	SET_RUNTIME_PM_OPS(samsung_dsim_suspend, samsung_dsim_resume, NULL)
2073 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2074 				pm_runtime_force_resume)
2075 };
2076 EXPORT_SYMBOL_GPL(samsung_dsim_pm_ops);
2077 
2078 static const struct samsung_dsim_plat_data samsung_dsim_imx8mm_pdata = {
2079 	.hw_type = DSIM_TYPE_IMX8MM,
2080 	.host_ops = &generic_dsim_host_ops,
2081 };
2082 
2083 static const struct samsung_dsim_plat_data samsung_dsim_imx8mp_pdata = {
2084 	.hw_type = DSIM_TYPE_IMX8MP,
2085 	.host_ops = &generic_dsim_host_ops,
2086 };
2087 
2088 static const struct of_device_id samsung_dsim_of_match[] = {
2089 	{
2090 		.compatible = "fsl,imx8mm-mipi-dsim",
2091 		.data = &samsung_dsim_imx8mm_pdata,
2092 	},
2093 	{
2094 		.compatible = "fsl,imx8mp-mipi-dsim",
2095 		.data = &samsung_dsim_imx8mp_pdata,
2096 	},
2097 	{ /* sentinel. */ }
2098 };
2099 MODULE_DEVICE_TABLE(of, samsung_dsim_of_match);
2100 
2101 static struct platform_driver samsung_dsim_driver = {
2102 	.probe = samsung_dsim_probe,
2103 	.remove = samsung_dsim_remove,
2104 	.driver = {
2105 		   .name = "samsung-dsim",
2106 		   .pm = &samsung_dsim_pm_ops,
2107 		   .of_match_table = samsung_dsim_of_match,
2108 	},
2109 };
2110 
2111 module_platform_driver(samsung_dsim_driver);
2112 
2113 MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
2114 MODULE_DESCRIPTION("Samsung MIPI DSIM controller bridge");
2115 MODULE_LICENSE("GPL");
2116