1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Samsung MIPI DSIM bridge driver.
4 *
5 * Copyright (C) 2021 Amarula Solutions(India)
6 * Copyright (c) 2014 Samsung Electronics Co., Ltd
7 * Author: Jagan Teki <jagan@amarulasolutions.com>
8 *
9 * Based on exynos_drm_dsi from
10 * Tomasz Figa <t.figa@samsung.com>
11 */
12
13 #include <asm/unaligned.h>
14
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/irq.h>
18 #include <linux/media-bus-format.h>
19 #include <linux/of.h>
20 #include <linux/phy/phy.h>
21 #include <linux/platform_device.h>
22
23 #include <video/mipi_display.h>
24
25 #include <drm/bridge/samsung-dsim.h>
26 #include <drm/drm_panel.h>
27 #include <drm/drm_print.h>
28
29 /* returns true iff both arguments logically differs */
30 #define NEQV(a, b) (!(a) ^ !(b))
31
32 /* DSIM_STATUS */
33 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
34 #define DSIM_STOP_STATE_CLK BIT(8)
35 #define DSIM_TX_READY_HS_CLK BIT(10)
36 #define DSIM_PLL_STABLE BIT(31)
37
38 /* DSIM_SWRST */
39 #define DSIM_FUNCRST BIT(16)
40 #define DSIM_SWRST BIT(0)
41
42 /* DSIM_TIMEOUT */
43 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0)
44 #define DSIM_BTA_TIMEOUT(x) ((x) << 16)
45
46 /* DSIM_CLKCTRL */
47 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0)
48 #define DSIM_ESC_PRESCALER_MASK (0xffff << 0)
49 #define DSIM_LANE_ESC_CLK_EN_CLK BIT(19)
50 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20)
51 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20)
52 #define DSIM_BYTE_CLKEN BIT(24)
53 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25)
54 #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25)
55 #define DSIM_PLL_BYPASS BIT(27)
56 #define DSIM_ESC_CLKEN BIT(28)
57 #define DSIM_TX_REQUEST_HSCLK BIT(31)
58
59 /* DSIM_CONFIG */
60 #define DSIM_LANE_EN_CLK BIT(0)
61 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1)
62 #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5)
63 #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8)
64 #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12)
65 #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12)
66 #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12)
67 #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12)
68 #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12)
69 #define DSIM_SUB_VC (((x) & 0x3) << 16)
70 #define DSIM_MAIN_VC (((x) & 0x3) << 18)
71 #define DSIM_HSA_DISABLE_MODE BIT(20)
72 #define DSIM_HBP_DISABLE_MODE BIT(21)
73 #define DSIM_HFP_DISABLE_MODE BIT(22)
74 /*
75 * The i.MX 8M Mini Applications Processor Reference Manual,
76 * Rev. 3, 11/2020 Page 4091
77 * The i.MX 8M Nano Applications Processor Reference Manual,
78 * Rev. 2, 07/2022 Page 3058
79 * The i.MX 8M Plus Applications Processor Reference Manual,
80 * Rev. 1, 06/2021 Page 5436
81 * all claims this bit is 'HseDisableMode' with the definition
82 * 0 = Disables transfer
83 * 1 = Enables transfer
84 *
85 * This clearly states that HSE is not a disabled bit.
86 *
87 * The naming convention follows as per the manual and the
88 * driver logic is based on the MIPI_DSI_MODE_VIDEO_HSE flag.
89 */
90 #define DSIM_HSE_DISABLE_MODE BIT(23)
91 #define DSIM_AUTO_MODE BIT(24)
92 #define DSIM_VIDEO_MODE BIT(25)
93 #define DSIM_BURST_MODE BIT(26)
94 #define DSIM_SYNC_INFORM BIT(27)
95 #define DSIM_EOT_DISABLE BIT(28)
96 #define DSIM_MFLUSH_VS BIT(29)
97 /* This flag is valid only for exynos3250/3472/5260/5430 */
98 #define DSIM_CLKLANE_STOP BIT(30)
99
100 /* DSIM_ESCMODE */
101 #define DSIM_TX_TRIGGER_RST BIT(4)
102 #define DSIM_TX_LPDT_LP BIT(6)
103 #define DSIM_CMD_LPDT_LP BIT(7)
104 #define DSIM_FORCE_BTA BIT(16)
105 #define DSIM_FORCE_STOP_STATE BIT(20)
106 #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21)
107 #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21)
108
109 /* DSIM_MDRESOL */
110 #define DSIM_MAIN_STAND_BY BIT(31)
111 #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16)
112 #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0)
113
114 /* DSIM_MVPORCH */
115 #define DSIM_CMD_ALLOW(x) ((x) << 28)
116 #define DSIM_STABLE_VFP(x) ((x) << 16)
117 #define DSIM_MAIN_VBP(x) ((x) << 0)
118 #define DSIM_CMD_ALLOW_MASK (0xf << 28)
119 #define DSIM_STABLE_VFP_MASK (0x7ff << 16)
120 #define DSIM_MAIN_VBP_MASK (0x7ff << 0)
121
122 /* DSIM_MHPORCH */
123 #define DSIM_MAIN_HFP(x) ((x) << 16)
124 #define DSIM_MAIN_HBP(x) ((x) << 0)
125 #define DSIM_MAIN_HFP_MASK ((0xffff) << 16)
126 #define DSIM_MAIN_HBP_MASK ((0xffff) << 0)
127
128 /* DSIM_MSYNC */
129 #define DSIM_MAIN_VSA(x) ((x) << 22)
130 #define DSIM_MAIN_HSA(x) ((x) << 0)
131 #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22)
132 #define DSIM_MAIN_HSA_MASK ((0xffff) << 0)
133
134 /* DSIM_SDRESOL */
135 #define DSIM_SUB_STANDY(x) ((x) << 31)
136 #define DSIM_SUB_VRESOL(x) ((x) << 16)
137 #define DSIM_SUB_HRESOL(x) ((x) << 0)
138 #define DSIM_SUB_STANDY_MASK ((0x1) << 31)
139 #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16)
140 #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0)
141
142 /* DSIM_INTSRC */
143 #define DSIM_INT_PLL_STABLE BIT(31)
144 #define DSIM_INT_SW_RST_RELEASE BIT(30)
145 #define DSIM_INT_SFR_FIFO_EMPTY BIT(29)
146 #define DSIM_INT_SFR_HDR_FIFO_EMPTY BIT(28)
147 #define DSIM_INT_BTA BIT(25)
148 #define DSIM_INT_FRAME_DONE BIT(24)
149 #define DSIM_INT_RX_TIMEOUT BIT(21)
150 #define DSIM_INT_BTA_TIMEOUT BIT(20)
151 #define DSIM_INT_RX_DONE BIT(18)
152 #define DSIM_INT_RX_TE BIT(17)
153 #define DSIM_INT_RX_ACK BIT(16)
154 #define DSIM_INT_RX_ECC_ERR BIT(15)
155 #define DSIM_INT_RX_CRC_ERR BIT(14)
156
157 /* DSIM_FIFOCTRL */
158 #define DSIM_RX_DATA_FULL BIT(25)
159 #define DSIM_RX_DATA_EMPTY BIT(24)
160 #define DSIM_SFR_HEADER_FULL BIT(23)
161 #define DSIM_SFR_HEADER_EMPTY BIT(22)
162 #define DSIM_SFR_PAYLOAD_FULL BIT(21)
163 #define DSIM_SFR_PAYLOAD_EMPTY BIT(20)
164 #define DSIM_I80_HEADER_FULL BIT(19)
165 #define DSIM_I80_HEADER_EMPTY BIT(18)
166 #define DSIM_I80_PAYLOAD_FULL BIT(17)
167 #define DSIM_I80_PAYLOAD_EMPTY BIT(16)
168 #define DSIM_SD_HEADER_FULL BIT(15)
169 #define DSIM_SD_HEADER_EMPTY BIT(14)
170 #define DSIM_SD_PAYLOAD_FULL BIT(13)
171 #define DSIM_SD_PAYLOAD_EMPTY BIT(12)
172 #define DSIM_MD_HEADER_FULL BIT(11)
173 #define DSIM_MD_HEADER_EMPTY BIT(10)
174 #define DSIM_MD_PAYLOAD_FULL BIT(9)
175 #define DSIM_MD_PAYLOAD_EMPTY BIT(8)
176 #define DSIM_RX_FIFO BIT(4)
177 #define DSIM_SFR_FIFO BIT(3)
178 #define DSIM_I80_FIFO BIT(2)
179 #define DSIM_SD_FIFO BIT(1)
180 #define DSIM_MD_FIFO BIT(0)
181
182 /* DSIM_PHYACCHR */
183 #define DSIM_AFC_EN BIT(14)
184 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
185
186 /* DSIM_PLLCTRL */
187 #define DSIM_PLL_DPDNSWAP_CLK (1 << 25)
188 #define DSIM_PLL_DPDNSWAP_DAT (1 << 24)
189 #define DSIM_FREQ_BAND(x) ((x) << 24)
190 #define DSIM_PLL_EN BIT(23)
191 #define DSIM_PLL_P(x, offset) ((x) << (offset))
192 #define DSIM_PLL_M(x) ((x) << 4)
193 #define DSIM_PLL_S(x) ((x) << 1)
194
195 /* DSIM_PHYCTRL */
196 #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0)
197 #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP BIT(30)
198 #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP BIT(14)
199
200 /* DSIM_PHYTIMING */
201 #define DSIM_PHYTIMING_LPX(x) ((x) << 8)
202 #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0)
203
204 /* DSIM_PHYTIMING1 */
205 #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
206 #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16)
207 #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8)
208 #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)
209
210 /* DSIM_PHYTIMING2 */
211 #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16)
212 #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
213 #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0)
214
215 #define DSI_MAX_BUS_WIDTH 4
216 #define DSI_NUM_VIRTUAL_CHANNELS 4
217 #define DSI_TX_FIFO_SIZE 2048
218 #define DSI_RX_FIFO_SIZE 256
219 #define DSI_XFER_TIMEOUT_MS 100
220 #define DSI_RX_FIFO_EMPTY 0x30800002
221
222 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
223
224 #define PS_TO_CYCLE(ps, hz) DIV64_U64_ROUND_CLOSEST(((ps) * (hz)), 1000000000000ULL)
225
226 static const char *const clk_names[5] = {
227 "bus_clk",
228 "sclk_mipi",
229 "phyclk_mipidphy0_bitclkdiv8",
230 "phyclk_mipidphy0_rxclkesc0",
231 "sclk_rgb_vclk_to_dsim0"
232 };
233
234 enum samsung_dsim_transfer_type {
235 EXYNOS_DSI_TX,
236 EXYNOS_DSI_RX,
237 };
238
239 enum reg_idx {
240 DSIM_STATUS_REG, /* Status register */
241 DSIM_SWRST_REG, /* Software reset register */
242 DSIM_CLKCTRL_REG, /* Clock control register */
243 DSIM_TIMEOUT_REG, /* Time out register */
244 DSIM_CONFIG_REG, /* Configuration register */
245 DSIM_ESCMODE_REG, /* Escape mode register */
246 DSIM_MDRESOL_REG,
247 DSIM_MVPORCH_REG, /* Main display Vporch register */
248 DSIM_MHPORCH_REG, /* Main display Hporch register */
249 DSIM_MSYNC_REG, /* Main display sync area register */
250 DSIM_INTSRC_REG, /* Interrupt source register */
251 DSIM_INTMSK_REG, /* Interrupt mask register */
252 DSIM_PKTHDR_REG, /* Packet Header FIFO register */
253 DSIM_PAYLOAD_REG, /* Payload FIFO register */
254 DSIM_RXFIFO_REG, /* Read FIFO register */
255 DSIM_FIFOCTRL_REG, /* FIFO status and control register */
256 DSIM_PLLCTRL_REG, /* PLL control register */
257 DSIM_PHYCTRL_REG,
258 DSIM_PHYTIMING_REG,
259 DSIM_PHYTIMING1_REG,
260 DSIM_PHYTIMING2_REG,
261 NUM_REGS
262 };
263
264 static const unsigned int exynos_reg_ofs[] = {
265 [DSIM_STATUS_REG] = 0x00,
266 [DSIM_SWRST_REG] = 0x04,
267 [DSIM_CLKCTRL_REG] = 0x08,
268 [DSIM_TIMEOUT_REG] = 0x0c,
269 [DSIM_CONFIG_REG] = 0x10,
270 [DSIM_ESCMODE_REG] = 0x14,
271 [DSIM_MDRESOL_REG] = 0x18,
272 [DSIM_MVPORCH_REG] = 0x1c,
273 [DSIM_MHPORCH_REG] = 0x20,
274 [DSIM_MSYNC_REG] = 0x24,
275 [DSIM_INTSRC_REG] = 0x2c,
276 [DSIM_INTMSK_REG] = 0x30,
277 [DSIM_PKTHDR_REG] = 0x34,
278 [DSIM_PAYLOAD_REG] = 0x38,
279 [DSIM_RXFIFO_REG] = 0x3c,
280 [DSIM_FIFOCTRL_REG] = 0x44,
281 [DSIM_PLLCTRL_REG] = 0x4c,
282 [DSIM_PHYCTRL_REG] = 0x5c,
283 [DSIM_PHYTIMING_REG] = 0x64,
284 [DSIM_PHYTIMING1_REG] = 0x68,
285 [DSIM_PHYTIMING2_REG] = 0x6c,
286 };
287
288 static const unsigned int exynos5433_reg_ofs[] = {
289 [DSIM_STATUS_REG] = 0x04,
290 [DSIM_SWRST_REG] = 0x0C,
291 [DSIM_CLKCTRL_REG] = 0x10,
292 [DSIM_TIMEOUT_REG] = 0x14,
293 [DSIM_CONFIG_REG] = 0x18,
294 [DSIM_ESCMODE_REG] = 0x1C,
295 [DSIM_MDRESOL_REG] = 0x20,
296 [DSIM_MVPORCH_REG] = 0x24,
297 [DSIM_MHPORCH_REG] = 0x28,
298 [DSIM_MSYNC_REG] = 0x2C,
299 [DSIM_INTSRC_REG] = 0x34,
300 [DSIM_INTMSK_REG] = 0x38,
301 [DSIM_PKTHDR_REG] = 0x3C,
302 [DSIM_PAYLOAD_REG] = 0x40,
303 [DSIM_RXFIFO_REG] = 0x44,
304 [DSIM_FIFOCTRL_REG] = 0x4C,
305 [DSIM_PLLCTRL_REG] = 0x94,
306 [DSIM_PHYCTRL_REG] = 0xA4,
307 [DSIM_PHYTIMING_REG] = 0xB4,
308 [DSIM_PHYTIMING1_REG] = 0xB8,
309 [DSIM_PHYTIMING2_REG] = 0xBC,
310 };
311
312 enum reg_value_idx {
313 RESET_TYPE,
314 PLL_TIMER,
315 STOP_STATE_CNT,
316 PHYCTRL_ULPS_EXIT,
317 PHYCTRL_VREG_LP,
318 PHYCTRL_SLEW_UP,
319 PHYTIMING_LPX,
320 PHYTIMING_HS_EXIT,
321 PHYTIMING_CLK_PREPARE,
322 PHYTIMING_CLK_ZERO,
323 PHYTIMING_CLK_POST,
324 PHYTIMING_CLK_TRAIL,
325 PHYTIMING_HS_PREPARE,
326 PHYTIMING_HS_ZERO,
327 PHYTIMING_HS_TRAIL
328 };
329
330 static const unsigned int reg_values[] = {
331 [RESET_TYPE] = DSIM_SWRST,
332 [PLL_TIMER] = 500,
333 [STOP_STATE_CNT] = 0xf,
334 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
335 [PHYCTRL_VREG_LP] = 0,
336 [PHYCTRL_SLEW_UP] = 0,
337 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
338 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
339 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
340 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
341 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
342 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
343 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
344 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
345 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
346 };
347
348 static const unsigned int exynos5422_reg_values[] = {
349 [RESET_TYPE] = DSIM_SWRST,
350 [PLL_TIMER] = 500,
351 [STOP_STATE_CNT] = 0xf,
352 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
353 [PHYCTRL_VREG_LP] = 0,
354 [PHYCTRL_SLEW_UP] = 0,
355 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08),
356 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d),
357 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
358 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30),
359 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
360 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a),
361 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c),
362 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11),
363 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
364 };
365
366 static const unsigned int exynos5433_reg_values[] = {
367 [RESET_TYPE] = DSIM_FUNCRST,
368 [PLL_TIMER] = 22200,
369 [STOP_STATE_CNT] = 0xa,
370 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190),
371 [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP,
372 [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP,
373 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
374 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
375 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
376 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d),
377 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
378 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
379 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b),
380 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10),
381 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
382 };
383
384 static const unsigned int imx8mm_dsim_reg_values[] = {
385 [RESET_TYPE] = DSIM_SWRST,
386 [PLL_TIMER] = 500,
387 [STOP_STATE_CNT] = 0xf,
388 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
389 [PHYCTRL_VREG_LP] = 0,
390 [PHYCTRL_SLEW_UP] = 0,
391 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
392 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
393 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
394 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x26),
395 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
396 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
397 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x08),
398 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
399 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
400 };
401
402 static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = {
403 .reg_ofs = exynos_reg_ofs,
404 .plltmr_reg = 0x50,
405 .has_freqband = 1,
406 .has_clklane_stop = 1,
407 .num_clks = 2,
408 .max_freq = 1000,
409 .wait_for_reset = 1,
410 .num_bits_resol = 11,
411 .pll_p_offset = 13,
412 .reg_values = reg_values,
413 .m_min = 41,
414 .m_max = 125,
415 .min_freq = 500,
416 .has_broken_fifoctrl_emptyhdr = 1,
417 };
418
419 static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = {
420 .reg_ofs = exynos_reg_ofs,
421 .plltmr_reg = 0x50,
422 .has_freqband = 1,
423 .has_clklane_stop = 1,
424 .num_clks = 2,
425 .max_freq = 1000,
426 .wait_for_reset = 1,
427 .num_bits_resol = 11,
428 .pll_p_offset = 13,
429 .reg_values = reg_values,
430 .m_min = 41,
431 .m_max = 125,
432 .min_freq = 500,
433 .has_broken_fifoctrl_emptyhdr = 1,
434 };
435
436 static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = {
437 .reg_ofs = exynos_reg_ofs,
438 .plltmr_reg = 0x58,
439 .num_clks = 2,
440 .max_freq = 1000,
441 .wait_for_reset = 1,
442 .num_bits_resol = 11,
443 .pll_p_offset = 13,
444 .reg_values = reg_values,
445 .m_min = 41,
446 .m_max = 125,
447 .min_freq = 500,
448 };
449
450 static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = {
451 .reg_ofs = exynos5433_reg_ofs,
452 .plltmr_reg = 0xa0,
453 .has_clklane_stop = 1,
454 .num_clks = 5,
455 .max_freq = 1500,
456 .wait_for_reset = 0,
457 .num_bits_resol = 12,
458 .pll_p_offset = 13,
459 .reg_values = exynos5433_reg_values,
460 .m_min = 41,
461 .m_max = 125,
462 .min_freq = 500,
463 };
464
465 static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = {
466 .reg_ofs = exynos5433_reg_ofs,
467 .plltmr_reg = 0xa0,
468 .has_clklane_stop = 1,
469 .num_clks = 2,
470 .max_freq = 1500,
471 .wait_for_reset = 1,
472 .num_bits_resol = 12,
473 .pll_p_offset = 13,
474 .reg_values = exynos5422_reg_values,
475 .m_min = 41,
476 .m_max = 125,
477 .min_freq = 500,
478 };
479
480 static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = {
481 .reg_ofs = exynos5433_reg_ofs,
482 .plltmr_reg = 0xa0,
483 .has_clklane_stop = 1,
484 .num_clks = 2,
485 .max_freq = 2100,
486 .wait_for_reset = 0,
487 .num_bits_resol = 12,
488 /*
489 * Unlike Exynos, PLL_P(PMS_P) offset 14 is used in i.MX8M Mini/Nano/Plus
490 * downstream driver - drivers/gpu/drm/bridge/sec-dsim.c
491 */
492 .pll_p_offset = 14,
493 .reg_values = imx8mm_dsim_reg_values,
494 .m_min = 64,
495 .m_max = 1023,
496 .min_freq = 1050,
497 };
498
499 static const struct samsung_dsim_driver_data *
500 samsung_dsim_types[DSIM_TYPE_COUNT] = {
501 [DSIM_TYPE_EXYNOS3250] = &exynos3_dsi_driver_data,
502 [DSIM_TYPE_EXYNOS4210] = &exynos4_dsi_driver_data,
503 [DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data,
504 [DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data,
505 [DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data,
506 [DSIM_TYPE_IMX8MM] = &imx8mm_dsi_driver_data,
507 [DSIM_TYPE_IMX8MP] = &imx8mm_dsi_driver_data,
508 };
509
host_to_dsi(struct mipi_dsi_host * h)510 static inline struct samsung_dsim *host_to_dsi(struct mipi_dsi_host *h)
511 {
512 return container_of(h, struct samsung_dsim, dsi_host);
513 }
514
bridge_to_dsi(struct drm_bridge * b)515 static inline struct samsung_dsim *bridge_to_dsi(struct drm_bridge *b)
516 {
517 return container_of(b, struct samsung_dsim, bridge);
518 }
519
samsung_dsim_write(struct samsung_dsim * dsi,enum reg_idx idx,u32 val)520 static inline void samsung_dsim_write(struct samsung_dsim *dsi,
521 enum reg_idx idx, u32 val)
522 {
523 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
524 }
525
samsung_dsim_read(struct samsung_dsim * dsi,enum reg_idx idx)526 static inline u32 samsung_dsim_read(struct samsung_dsim *dsi, enum reg_idx idx)
527 {
528 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
529 }
530
samsung_dsim_wait_for_reset(struct samsung_dsim * dsi)531 static void samsung_dsim_wait_for_reset(struct samsung_dsim *dsi)
532 {
533 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
534 return;
535
536 dev_err(dsi->dev, "timeout waiting for reset\n");
537 }
538
samsung_dsim_reset(struct samsung_dsim * dsi)539 static void samsung_dsim_reset(struct samsung_dsim *dsi)
540 {
541 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];
542
543 reinit_completion(&dsi->completed);
544 samsung_dsim_write(dsi, DSIM_SWRST_REG, reset_val);
545 }
546
547 #ifndef MHZ
548 #define MHZ (1000 * 1000)
549 #endif
550
samsung_dsim_pll_find_pms(struct samsung_dsim * dsi,unsigned long fin,unsigned long fout,u8 * p,u16 * m,u8 * s)551 static unsigned long samsung_dsim_pll_find_pms(struct samsung_dsim *dsi,
552 unsigned long fin,
553 unsigned long fout,
554 u8 *p, u16 *m, u8 *s)
555 {
556 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
557 unsigned long best_freq = 0;
558 u32 min_delta = 0xffffffff;
559 u8 p_min, p_max;
560 u8 _p, best_p;
561 u16 _m, best_m;
562 u8 _s, best_s;
563
564 p_min = DIV_ROUND_UP(fin, (12 * MHZ));
565 p_max = fin / (6 * MHZ);
566
567 for (_p = p_min; _p <= p_max; ++_p) {
568 for (_s = 0; _s <= 5; ++_s) {
569 u64 tmp;
570 u32 delta;
571
572 tmp = (u64)fout * (_p << _s);
573 do_div(tmp, fin);
574 _m = tmp;
575 if (_m < driver_data->m_min || _m > driver_data->m_max)
576 continue;
577
578 tmp = (u64)_m * fin;
579 do_div(tmp, _p);
580 if (tmp < driver_data->min_freq * MHZ ||
581 tmp > driver_data->max_freq * MHZ)
582 continue;
583
584 tmp = (u64)_m * fin;
585 do_div(tmp, _p << _s);
586
587 delta = abs(fout - tmp);
588 if (delta < min_delta) {
589 best_p = _p;
590 best_m = _m;
591 best_s = _s;
592 min_delta = delta;
593 best_freq = tmp;
594 }
595 }
596 }
597
598 if (best_freq) {
599 *p = best_p;
600 *m = best_m;
601 *s = best_s;
602 }
603
604 return best_freq;
605 }
606
samsung_dsim_set_pll(struct samsung_dsim * dsi,unsigned long freq)607 static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
608 unsigned long freq)
609 {
610 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
611 unsigned long fin, fout;
612 int timeout;
613 u8 p, s;
614 u16 m;
615 u32 reg;
616
617 fin = dsi->pll_clk_rate;
618 fout = samsung_dsim_pll_find_pms(dsi, fin, freq, &p, &m, &s);
619 if (!fout) {
620 dev_err(dsi->dev,
621 "failed to find PLL PMS for requested frequency\n");
622 return 0;
623 }
624 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
625
626 writel(driver_data->reg_values[PLL_TIMER],
627 dsi->reg_base + driver_data->plltmr_reg);
628
629 reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) |
630 DSIM_PLL_M(m) | DSIM_PLL_S(s);
631
632 if (driver_data->has_freqband) {
633 static const unsigned long freq_bands[] = {
634 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
635 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
636 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
637 770 * MHZ, 870 * MHZ, 950 * MHZ,
638 };
639 int band;
640
641 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
642 if (fout < freq_bands[band])
643 break;
644
645 dev_dbg(dsi->dev, "band %d\n", band);
646
647 reg |= DSIM_FREQ_BAND(band);
648 }
649
650 if (dsi->swap_dn_dp_clk)
651 reg |= DSIM_PLL_DPDNSWAP_CLK;
652 if (dsi->swap_dn_dp_data)
653 reg |= DSIM_PLL_DPDNSWAP_DAT;
654
655 samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
656
657 timeout = 1000;
658 do {
659 if (timeout-- == 0) {
660 dev_err(dsi->dev, "PLL failed to stabilize\n");
661 return 0;
662 }
663 reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
664 } while ((reg & DSIM_PLL_STABLE) == 0);
665
666 dsi->hs_clock = fout;
667
668 return fout;
669 }
670
samsung_dsim_enable_clock(struct samsung_dsim * dsi)671 static int samsung_dsim_enable_clock(struct samsung_dsim *dsi)
672 {
673 unsigned long hs_clk, byte_clk, esc_clk, pix_clk;
674 unsigned long esc_div;
675 u32 reg;
676 struct drm_display_mode *m = &dsi->mode;
677 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
678
679 /* m->clock is in KHz */
680 pix_clk = m->clock * 1000;
681
682 /* Use burst_clk_rate if available, otherwise use the pix_clk */
683 if (dsi->burst_clk_rate)
684 hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate);
685 else
686 hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->lanes));
687
688 if (!hs_clk) {
689 dev_err(dsi->dev, "failed to configure DSI PLL\n");
690 return -EFAULT;
691 }
692
693 byte_clk = hs_clk / 8;
694 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
695 esc_clk = byte_clk / esc_div;
696
697 if (esc_clk > 20 * MHZ) {
698 ++esc_div;
699 esc_clk = byte_clk / esc_div;
700 }
701
702 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
703 hs_clk, byte_clk, esc_clk);
704
705 reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG);
706 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
707 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
708 | DSIM_BYTE_CLK_SRC_MASK);
709 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
710 | DSIM_ESC_PRESCALER(esc_div)
711 | DSIM_LANE_ESC_CLK_EN_CLK
712 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
713 | DSIM_BYTE_CLK_SRC(0)
714 | DSIM_TX_REQUEST_HSCLK;
715 samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg);
716
717 return 0;
718 }
719
samsung_dsim_set_phy_ctrl(struct samsung_dsim * dsi)720 static void samsung_dsim_set_phy_ctrl(struct samsung_dsim *dsi)
721 {
722 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
723 const unsigned int *reg_values = driver_data->reg_values;
724 u32 reg;
725 struct phy_configure_opts_mipi_dphy cfg;
726 int clk_prepare, lpx, clk_zero, clk_post, clk_trail;
727 int hs_exit, hs_prepare, hs_zero, hs_trail;
728 unsigned long long byte_clock = dsi->hs_clock / 8;
729
730 if (driver_data->has_freqband)
731 return;
732
733 phy_mipi_dphy_get_default_config_for_hsclk(dsi->hs_clock,
734 dsi->lanes, &cfg);
735
736 /*
737 * TODO:
738 * The tech Applications Processor manuals for i.MX8M Mini, Nano,
739 * and Plus don't state what the definition of the PHYTIMING
740 * bits are beyond their address and bit position.
741 * After reviewing NXP's downstream code, it appears
742 * that the various PHYTIMING registers take the number
743 * of cycles and use various dividers on them. This
744 * calculation does not result in an exact match to the
745 * downstream code, but it is very close to the values
746 * generated by their lookup table, and it appears
747 * to sync at a variety of resolutions. If someone
748 * can get a more accurate mathematical equation needed
749 * for these registers, this should be updated.
750 */
751
752 lpx = PS_TO_CYCLE(cfg.lpx, byte_clock);
753 hs_exit = PS_TO_CYCLE(cfg.hs_exit, byte_clock);
754 clk_prepare = PS_TO_CYCLE(cfg.clk_prepare, byte_clock);
755 clk_zero = PS_TO_CYCLE(cfg.clk_zero, byte_clock);
756 clk_post = PS_TO_CYCLE(cfg.clk_post, byte_clock);
757 clk_trail = PS_TO_CYCLE(cfg.clk_trail, byte_clock);
758 hs_prepare = PS_TO_CYCLE(cfg.hs_prepare, byte_clock);
759 hs_zero = PS_TO_CYCLE(cfg.hs_zero, byte_clock);
760 hs_trail = PS_TO_CYCLE(cfg.hs_trail, byte_clock);
761
762 /* B D-PHY: D-PHY Master & Slave Analog Block control */
763 reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
764 reg_values[PHYCTRL_SLEW_UP];
765
766 samsung_dsim_write(dsi, DSIM_PHYCTRL_REG, reg);
767
768 /*
769 * T LPX: Transmitted length of any Low-Power state period
770 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
771 * burst
772 */
773
774 reg = DSIM_PHYTIMING_LPX(lpx) | DSIM_PHYTIMING_HS_EXIT(hs_exit);
775
776 samsung_dsim_write(dsi, DSIM_PHYTIMING_REG, reg);
777
778 /*
779 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
780 * Line state immediately before the HS-0 Line state starting the
781 * HS transmission
782 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
783 * transmitting the Clock.
784 * T CLK_POST: Time that the transmitter continues to send HS clock
785 * after the last associated Data Lane has transitioned to LP Mode
786 * Interval is defined as the period from the end of T HS-TRAIL to
787 * the beginning of T CLK-TRAIL
788 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
789 * the last payload clock bit of a HS transmission burst
790 */
791
792 reg = DSIM_PHYTIMING1_CLK_PREPARE(clk_prepare) |
793 DSIM_PHYTIMING1_CLK_ZERO(clk_zero) |
794 DSIM_PHYTIMING1_CLK_POST(clk_post) |
795 DSIM_PHYTIMING1_CLK_TRAIL(clk_trail);
796
797 samsung_dsim_write(dsi, DSIM_PHYTIMING1_REG, reg);
798
799 /*
800 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
801 * Line state immediately before the HS-0 Line state starting the
802 * HS transmission
803 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
804 * transmitting the Sync sequence.
805 * T HS-TRAIL: Time that the transmitter drives the flipped differential
806 * state after last payload data bit of a HS transmission burst
807 */
808
809 reg = DSIM_PHYTIMING2_HS_PREPARE(hs_prepare) |
810 DSIM_PHYTIMING2_HS_ZERO(hs_zero) |
811 DSIM_PHYTIMING2_HS_TRAIL(hs_trail);
812
813 samsung_dsim_write(dsi, DSIM_PHYTIMING2_REG, reg);
814 }
815
samsung_dsim_disable_clock(struct samsung_dsim * dsi)816 static void samsung_dsim_disable_clock(struct samsung_dsim *dsi)
817 {
818 u32 reg;
819
820 reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG);
821 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
822 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
823 samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg);
824
825 reg = samsung_dsim_read(dsi, DSIM_PLLCTRL_REG);
826 reg &= ~DSIM_PLL_EN;
827 samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
828 }
829
samsung_dsim_enable_lane(struct samsung_dsim * dsi,u32 lane)830 static void samsung_dsim_enable_lane(struct samsung_dsim *dsi, u32 lane)
831 {
832 u32 reg = samsung_dsim_read(dsi, DSIM_CONFIG_REG);
833
834 reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
835 DSIM_LANE_EN(lane));
836 samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg);
837 }
838
samsung_dsim_init_link(struct samsung_dsim * dsi)839 static int samsung_dsim_init_link(struct samsung_dsim *dsi)
840 {
841 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
842 int timeout;
843 u32 reg;
844 u32 lanes_mask;
845
846 /* Initialize FIFO pointers */
847 reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG);
848 reg &= ~0x1f;
849 samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg);
850
851 usleep_range(9000, 11000);
852
853 reg |= 0x1f;
854 samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg);
855 usleep_range(9000, 11000);
856
857 /* DSI configuration */
858 reg = 0;
859
860 /*
861 * The first bit of mode_flags specifies display configuration.
862 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
863 * mode, otherwise it will support command mode.
864 */
865 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
866 reg |= DSIM_VIDEO_MODE;
867
868 /*
869 * The user manual describes that following bits are ignored in
870 * command mode.
871 */
872 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
873 reg |= DSIM_MFLUSH_VS;
874 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
875 reg |= DSIM_SYNC_INFORM;
876 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
877 reg |= DSIM_BURST_MODE;
878 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
879 reg |= DSIM_AUTO_MODE;
880 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
881 reg |= DSIM_HSE_DISABLE_MODE;
882 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP)
883 reg |= DSIM_HFP_DISABLE_MODE;
884 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP)
885 reg |= DSIM_HBP_DISABLE_MODE;
886 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA)
887 reg |= DSIM_HSA_DISABLE_MODE;
888 }
889
890 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
891 reg |= DSIM_EOT_DISABLE;
892
893 switch (dsi->format) {
894 case MIPI_DSI_FMT_RGB888:
895 reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
896 break;
897 case MIPI_DSI_FMT_RGB666:
898 reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
899 break;
900 case MIPI_DSI_FMT_RGB666_PACKED:
901 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
902 break;
903 case MIPI_DSI_FMT_RGB565:
904 reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
905 break;
906 default:
907 dev_err(dsi->dev, "invalid pixel format\n");
908 return -EINVAL;
909 }
910
911 /*
912 * Use non-continuous clock mode if the periparal wants and
913 * host controller supports
914 *
915 * In non-continous clock mode, host controller will turn off
916 * the HS clock between high-speed transmissions to reduce
917 * power consumption.
918 */
919 if (driver_data->has_clklane_stop &&
920 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
921 reg |= DSIM_CLKLANE_STOP;
922 samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg);
923
924 lanes_mask = BIT(dsi->lanes) - 1;
925 samsung_dsim_enable_lane(dsi, lanes_mask);
926
927 /* Check clock and data lane state are stop state */
928 timeout = 100;
929 do {
930 if (timeout-- == 0) {
931 dev_err(dsi->dev, "waiting for bus lanes timed out\n");
932 return -EFAULT;
933 }
934
935 reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
936 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
937 != DSIM_STOP_STATE_DAT(lanes_mask))
938 continue;
939 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
940
941 reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
942 reg &= ~DSIM_STOP_STATE_CNT_MASK;
943 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
944 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg);
945
946 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
947 samsung_dsim_write(dsi, DSIM_TIMEOUT_REG, reg);
948
949 return 0;
950 }
951
samsung_dsim_set_display_mode(struct samsung_dsim * dsi)952 static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi)
953 {
954 struct drm_display_mode *m = &dsi->mode;
955 unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
956 u32 reg;
957
958 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
959 int byte_clk_khz = dsi->hs_clock / 1000 / 8;
960 int hfp = (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock;
961 int hbp = (m->htotal - m->hsync_end) * byte_clk_khz / m->clock;
962 int hsa = (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock;
963
964 /* remove packet overhead when possible */
965 hfp = max(hfp - 6, 0);
966 hbp = max(hbp - 6, 0);
967 hsa = max(hsa - 6, 0);
968
969 dev_dbg(dsi->dev, "calculated hfp: %u, hbp: %u, hsa: %u",
970 hfp, hbp, hsa);
971
972 reg = DSIM_CMD_ALLOW(0xf)
973 | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)
974 | DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
975 samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg);
976
977 reg = DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp);
978 samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg);
979
980 reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
981 | DSIM_MAIN_HSA(hsa);
982 samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg);
983 }
984 reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |
985 DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol);
986
987 samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg);
988
989 dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay);
990 }
991
samsung_dsim_set_display_enable(struct samsung_dsim * dsi,bool enable)992 static void samsung_dsim_set_display_enable(struct samsung_dsim *dsi, bool enable)
993 {
994 u32 reg;
995
996 reg = samsung_dsim_read(dsi, DSIM_MDRESOL_REG);
997 if (enable)
998 reg |= DSIM_MAIN_STAND_BY;
999 else
1000 reg &= ~DSIM_MAIN_STAND_BY;
1001 samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg);
1002 }
1003
samsung_dsim_wait_for_hdr_fifo(struct samsung_dsim * dsi)1004 static int samsung_dsim_wait_for_hdr_fifo(struct samsung_dsim *dsi)
1005 {
1006 int timeout = 2000;
1007
1008 do {
1009 u32 reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG);
1010
1011 if (!dsi->driver_data->has_broken_fifoctrl_emptyhdr) {
1012 if (reg & DSIM_SFR_HEADER_EMPTY)
1013 return 0;
1014 } else {
1015 if (!(reg & DSIM_SFR_HEADER_FULL)) {
1016 /*
1017 * Wait a little bit, so the pending data can
1018 * actually leave the FIFO to avoid overflow.
1019 */
1020 if (!cond_resched())
1021 usleep_range(950, 1050);
1022 return 0;
1023 }
1024 }
1025
1026 if (!cond_resched())
1027 usleep_range(950, 1050);
1028 } while (--timeout);
1029
1030 return -ETIMEDOUT;
1031 }
1032
samsung_dsim_set_cmd_lpm(struct samsung_dsim * dsi,bool lpm)1033 static void samsung_dsim_set_cmd_lpm(struct samsung_dsim *dsi, bool lpm)
1034 {
1035 u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
1036
1037 if (lpm)
1038 v |= DSIM_CMD_LPDT_LP;
1039 else
1040 v &= ~DSIM_CMD_LPDT_LP;
1041
1042 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v);
1043 }
1044
samsung_dsim_force_bta(struct samsung_dsim * dsi)1045 static void samsung_dsim_force_bta(struct samsung_dsim *dsi)
1046 {
1047 u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
1048
1049 v |= DSIM_FORCE_BTA;
1050 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v);
1051 }
1052
samsung_dsim_send_to_fifo(struct samsung_dsim * dsi,struct samsung_dsim_transfer * xfer)1053 static void samsung_dsim_send_to_fifo(struct samsung_dsim *dsi,
1054 struct samsung_dsim_transfer *xfer)
1055 {
1056 struct device *dev = dsi->dev;
1057 struct mipi_dsi_packet *pkt = &xfer->packet;
1058 const u8 *payload = pkt->payload + xfer->tx_done;
1059 u16 length = pkt->payload_length - xfer->tx_done;
1060 bool first = !xfer->tx_done;
1061 u32 reg;
1062
1063 dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n",
1064 xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done);
1065
1066 if (length > DSI_TX_FIFO_SIZE)
1067 length = DSI_TX_FIFO_SIZE;
1068
1069 xfer->tx_done += length;
1070
1071 /* Send payload */
1072 while (length >= 4) {
1073 reg = get_unaligned_le32(payload);
1074 samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg);
1075 payload += 4;
1076 length -= 4;
1077 }
1078
1079 reg = 0;
1080 switch (length) {
1081 case 3:
1082 reg |= payload[2] << 16;
1083 fallthrough;
1084 case 2:
1085 reg |= payload[1] << 8;
1086 fallthrough;
1087 case 1:
1088 reg |= payload[0];
1089 samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg);
1090 break;
1091 }
1092
1093 /* Send packet header */
1094 if (!first)
1095 return;
1096
1097 reg = get_unaligned_le32(pkt->header);
1098 if (samsung_dsim_wait_for_hdr_fifo(dsi)) {
1099 dev_err(dev, "waiting for header FIFO timed out\n");
1100 return;
1101 }
1102
1103 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
1104 dsi->state & DSIM_STATE_CMD_LPM)) {
1105 samsung_dsim_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
1106 dsi->state ^= DSIM_STATE_CMD_LPM;
1107 }
1108
1109 samsung_dsim_write(dsi, DSIM_PKTHDR_REG, reg);
1110
1111 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
1112 samsung_dsim_force_bta(dsi);
1113 }
1114
samsung_dsim_read_from_fifo(struct samsung_dsim * dsi,struct samsung_dsim_transfer * xfer)1115 static void samsung_dsim_read_from_fifo(struct samsung_dsim *dsi,
1116 struct samsung_dsim_transfer *xfer)
1117 {
1118 u8 *payload = xfer->rx_payload + xfer->rx_done;
1119 bool first = !xfer->rx_done;
1120 struct device *dev = dsi->dev;
1121 u16 length;
1122 u32 reg;
1123
1124 if (first) {
1125 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1126
1127 switch (reg & 0x3f) {
1128 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1129 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1130 if (xfer->rx_len >= 2) {
1131 payload[1] = reg >> 16;
1132 ++xfer->rx_done;
1133 }
1134 fallthrough;
1135 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1136 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1137 payload[0] = reg >> 8;
1138 ++xfer->rx_done;
1139 xfer->rx_len = xfer->rx_done;
1140 xfer->result = 0;
1141 goto clear_fifo;
1142 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1143 dev_err(dev, "DSI Error Report: 0x%04x\n", (reg >> 8) & 0xffff);
1144 xfer->result = 0;
1145 goto clear_fifo;
1146 }
1147
1148 length = (reg >> 8) & 0xffff;
1149 if (length > xfer->rx_len) {
1150 dev_err(dev,
1151 "response too long (%u > %u bytes), stripping\n",
1152 xfer->rx_len, length);
1153 length = xfer->rx_len;
1154 } else if (length < xfer->rx_len) {
1155 xfer->rx_len = length;
1156 }
1157 }
1158
1159 length = xfer->rx_len - xfer->rx_done;
1160 xfer->rx_done += length;
1161
1162 /* Receive payload */
1163 while (length >= 4) {
1164 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1165 payload[0] = (reg >> 0) & 0xff;
1166 payload[1] = (reg >> 8) & 0xff;
1167 payload[2] = (reg >> 16) & 0xff;
1168 payload[3] = (reg >> 24) & 0xff;
1169 payload += 4;
1170 length -= 4;
1171 }
1172
1173 if (length) {
1174 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1175 switch (length) {
1176 case 3:
1177 payload[2] = (reg >> 16) & 0xff;
1178 fallthrough;
1179 case 2:
1180 payload[1] = (reg >> 8) & 0xff;
1181 fallthrough;
1182 case 1:
1183 payload[0] = reg & 0xff;
1184 }
1185 }
1186
1187 if (xfer->rx_done == xfer->rx_len)
1188 xfer->result = 0;
1189
1190 clear_fifo:
1191 length = DSI_RX_FIFO_SIZE / 4;
1192 do {
1193 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1194 if (reg == DSI_RX_FIFO_EMPTY)
1195 break;
1196 } while (--length);
1197 }
1198
samsung_dsim_transfer_start(struct samsung_dsim * dsi)1199 static void samsung_dsim_transfer_start(struct samsung_dsim *dsi)
1200 {
1201 unsigned long flags;
1202 struct samsung_dsim_transfer *xfer;
1203 bool start = false;
1204
1205 again:
1206 spin_lock_irqsave(&dsi->transfer_lock, flags);
1207
1208 if (list_empty(&dsi->transfer_list)) {
1209 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1210 return;
1211 }
1212
1213 xfer = list_first_entry(&dsi->transfer_list,
1214 struct samsung_dsim_transfer, list);
1215
1216 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1217
1218 if (xfer->packet.payload_length &&
1219 xfer->tx_done == xfer->packet.payload_length)
1220 /* waiting for RX */
1221 return;
1222
1223 samsung_dsim_send_to_fifo(dsi, xfer);
1224
1225 if (xfer->packet.payload_length || xfer->rx_len)
1226 return;
1227
1228 xfer->result = 0;
1229 complete(&xfer->completed);
1230
1231 spin_lock_irqsave(&dsi->transfer_lock, flags);
1232
1233 list_del_init(&xfer->list);
1234 start = !list_empty(&dsi->transfer_list);
1235
1236 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1237
1238 if (start)
1239 goto again;
1240 }
1241
samsung_dsim_transfer_finish(struct samsung_dsim * dsi)1242 static bool samsung_dsim_transfer_finish(struct samsung_dsim *dsi)
1243 {
1244 struct samsung_dsim_transfer *xfer;
1245 unsigned long flags;
1246 bool start = true;
1247
1248 spin_lock_irqsave(&dsi->transfer_lock, flags);
1249
1250 if (list_empty(&dsi->transfer_list)) {
1251 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1252 return false;
1253 }
1254
1255 xfer = list_first_entry(&dsi->transfer_list,
1256 struct samsung_dsim_transfer, list);
1257
1258 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1259
1260 dev_dbg(dsi->dev,
1261 "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n",
1262 xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len,
1263 xfer->rx_done);
1264
1265 if (xfer->tx_done != xfer->packet.payload_length)
1266 return true;
1267
1268 if (xfer->rx_done != xfer->rx_len)
1269 samsung_dsim_read_from_fifo(dsi, xfer);
1270
1271 if (xfer->rx_done != xfer->rx_len)
1272 return true;
1273
1274 spin_lock_irqsave(&dsi->transfer_lock, flags);
1275
1276 list_del_init(&xfer->list);
1277 start = !list_empty(&dsi->transfer_list);
1278
1279 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1280
1281 if (!xfer->rx_len)
1282 xfer->result = 0;
1283 complete(&xfer->completed);
1284
1285 return start;
1286 }
1287
samsung_dsim_remove_transfer(struct samsung_dsim * dsi,struct samsung_dsim_transfer * xfer)1288 static void samsung_dsim_remove_transfer(struct samsung_dsim *dsi,
1289 struct samsung_dsim_transfer *xfer)
1290 {
1291 unsigned long flags;
1292 bool start;
1293
1294 spin_lock_irqsave(&dsi->transfer_lock, flags);
1295
1296 if (!list_empty(&dsi->transfer_list) &&
1297 xfer == list_first_entry(&dsi->transfer_list,
1298 struct samsung_dsim_transfer, list)) {
1299 list_del_init(&xfer->list);
1300 start = !list_empty(&dsi->transfer_list);
1301 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1302 if (start)
1303 samsung_dsim_transfer_start(dsi);
1304 return;
1305 }
1306
1307 list_del_init(&xfer->list);
1308
1309 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1310 }
1311
samsung_dsim_transfer(struct samsung_dsim * dsi,struct samsung_dsim_transfer * xfer)1312 static int samsung_dsim_transfer(struct samsung_dsim *dsi,
1313 struct samsung_dsim_transfer *xfer)
1314 {
1315 unsigned long flags;
1316 bool stopped;
1317
1318 xfer->tx_done = 0;
1319 xfer->rx_done = 0;
1320 xfer->result = -ETIMEDOUT;
1321 init_completion(&xfer->completed);
1322
1323 spin_lock_irqsave(&dsi->transfer_lock, flags);
1324
1325 stopped = list_empty(&dsi->transfer_list);
1326 list_add_tail(&xfer->list, &dsi->transfer_list);
1327
1328 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1329
1330 if (stopped)
1331 samsung_dsim_transfer_start(dsi);
1332
1333 wait_for_completion_timeout(&xfer->completed,
1334 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
1335 if (xfer->result == -ETIMEDOUT) {
1336 struct mipi_dsi_packet *pkt = &xfer->packet;
1337
1338 samsung_dsim_remove_transfer(dsi, xfer);
1339 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header,
1340 (int)pkt->payload_length, pkt->payload);
1341 return -ETIMEDOUT;
1342 }
1343
1344 /* Also covers hardware timeout condition */
1345 return xfer->result;
1346 }
1347
samsung_dsim_irq(int irq,void * dev_id)1348 static irqreturn_t samsung_dsim_irq(int irq, void *dev_id)
1349 {
1350 struct samsung_dsim *dsi = dev_id;
1351 u32 status;
1352
1353 status = samsung_dsim_read(dsi, DSIM_INTSRC_REG);
1354 if (!status) {
1355 static unsigned long j;
1356
1357 if (printk_timed_ratelimit(&j, 500))
1358 dev_warn(dsi->dev, "spurious interrupt\n");
1359 return IRQ_HANDLED;
1360 }
1361 samsung_dsim_write(dsi, DSIM_INTSRC_REG, status);
1362
1363 if (status & DSIM_INT_SW_RST_RELEASE) {
1364 unsigned long mask = ~(DSIM_INT_RX_DONE |
1365 DSIM_INT_SFR_FIFO_EMPTY |
1366 DSIM_INT_SFR_HDR_FIFO_EMPTY |
1367 DSIM_INT_RX_ECC_ERR |
1368 DSIM_INT_SW_RST_RELEASE);
1369 samsung_dsim_write(dsi, DSIM_INTMSK_REG, mask);
1370 complete(&dsi->completed);
1371 return IRQ_HANDLED;
1372 }
1373
1374 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1375 DSIM_INT_PLL_STABLE)))
1376 return IRQ_HANDLED;
1377
1378 if (samsung_dsim_transfer_finish(dsi))
1379 samsung_dsim_transfer_start(dsi);
1380
1381 return IRQ_HANDLED;
1382 }
1383
samsung_dsim_enable_irq(struct samsung_dsim * dsi)1384 static void samsung_dsim_enable_irq(struct samsung_dsim *dsi)
1385 {
1386 enable_irq(dsi->irq);
1387
1388 if (dsi->te_gpio)
1389 enable_irq(gpiod_to_irq(dsi->te_gpio));
1390 }
1391
samsung_dsim_disable_irq(struct samsung_dsim * dsi)1392 static void samsung_dsim_disable_irq(struct samsung_dsim *dsi)
1393 {
1394 if (dsi->te_gpio)
1395 disable_irq(gpiod_to_irq(dsi->te_gpio));
1396
1397 disable_irq(dsi->irq);
1398 }
1399
samsung_dsim_init(struct samsung_dsim * dsi)1400 static int samsung_dsim_init(struct samsung_dsim *dsi)
1401 {
1402 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
1403
1404 if (dsi->state & DSIM_STATE_INITIALIZED)
1405 return 0;
1406
1407 samsung_dsim_reset(dsi);
1408 samsung_dsim_enable_irq(dsi);
1409
1410 if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
1411 samsung_dsim_enable_lane(dsi, BIT(dsi->lanes) - 1);
1412
1413 samsung_dsim_enable_clock(dsi);
1414 if (driver_data->wait_for_reset)
1415 samsung_dsim_wait_for_reset(dsi);
1416 samsung_dsim_set_phy_ctrl(dsi);
1417 samsung_dsim_init_link(dsi);
1418
1419 dsi->state |= DSIM_STATE_INITIALIZED;
1420
1421 return 0;
1422 }
1423
samsung_dsim_atomic_pre_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1424 static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge,
1425 struct drm_bridge_state *old_bridge_state)
1426 {
1427 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1428 int ret;
1429
1430 if (dsi->state & DSIM_STATE_ENABLED)
1431 return;
1432
1433 ret = pm_runtime_resume_and_get(dsi->dev);
1434 if (ret < 0) {
1435 dev_err(dsi->dev, "failed to enable DSI device.\n");
1436 return;
1437 }
1438
1439 dsi->state |= DSIM_STATE_ENABLED;
1440
1441 /*
1442 * For Exynos-DSIM the downstream bridge, or panel are expecting
1443 * the host initialization during DSI transfer.
1444 */
1445 if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) {
1446 ret = samsung_dsim_init(dsi);
1447 if (ret)
1448 return;
1449 }
1450 }
1451
samsung_dsim_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1452 static void samsung_dsim_atomic_enable(struct drm_bridge *bridge,
1453 struct drm_bridge_state *old_bridge_state)
1454 {
1455 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1456
1457 samsung_dsim_set_display_mode(dsi);
1458 samsung_dsim_set_display_enable(dsi, true);
1459
1460 dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
1461 }
1462
samsung_dsim_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1463 static void samsung_dsim_atomic_disable(struct drm_bridge *bridge,
1464 struct drm_bridge_state *old_bridge_state)
1465 {
1466 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1467
1468 if (!(dsi->state & DSIM_STATE_ENABLED))
1469 return;
1470
1471 dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
1472 }
1473
samsung_dsim_atomic_post_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1474 static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
1475 struct drm_bridge_state *old_bridge_state)
1476 {
1477 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1478
1479 samsung_dsim_set_display_enable(dsi, false);
1480
1481 dsi->state &= ~DSIM_STATE_ENABLED;
1482 pm_runtime_put_sync(dsi->dev);
1483 }
1484
1485 /*
1486 * This pixel output formats list referenced from,
1487 * AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
1488 * 3.7.4 Pixel formats
1489 * Table 14. DSI pixel packing formats
1490 */
1491 static const u32 samsung_dsim_pixel_output_fmts[] = {
1492 MEDIA_BUS_FMT_YUYV10_1X20,
1493 MEDIA_BUS_FMT_YUYV12_1X24,
1494 MEDIA_BUS_FMT_UYVY8_1X16,
1495 MEDIA_BUS_FMT_RGB101010_1X30,
1496 MEDIA_BUS_FMT_RGB121212_1X36,
1497 MEDIA_BUS_FMT_RGB565_1X16,
1498 MEDIA_BUS_FMT_RGB666_1X18,
1499 MEDIA_BUS_FMT_RGB888_1X24,
1500 };
1501
samsung_dsim_pixel_output_fmt_supported(u32 fmt)1502 static bool samsung_dsim_pixel_output_fmt_supported(u32 fmt)
1503 {
1504 int i;
1505
1506 if (fmt == MEDIA_BUS_FMT_FIXED)
1507 return false;
1508
1509 for (i = 0; i < ARRAY_SIZE(samsung_dsim_pixel_output_fmts); i++) {
1510 if (samsung_dsim_pixel_output_fmts[i] == fmt)
1511 return true;
1512 }
1513
1514 return false;
1515 }
1516
1517 static u32 *
samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,u32 output_fmt,unsigned int * num_input_fmts)1518 samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
1519 struct drm_bridge_state *bridge_state,
1520 struct drm_crtc_state *crtc_state,
1521 struct drm_connector_state *conn_state,
1522 u32 output_fmt,
1523 unsigned int *num_input_fmts)
1524 {
1525 u32 *input_fmts;
1526
1527 input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
1528 if (!input_fmts)
1529 return NULL;
1530
1531 if (!samsung_dsim_pixel_output_fmt_supported(output_fmt))
1532 /*
1533 * Some bridge/display drivers are still not able to pass the
1534 * correct format, so handle those pipelines by falling back
1535 * to the default format till the supported formats finalized.
1536 */
1537 output_fmt = MEDIA_BUS_FMT_RGB888_1X24;
1538
1539 input_fmts[0] = output_fmt;
1540 *num_input_fmts = 1;
1541
1542 return input_fmts;
1543 }
1544
samsung_dsim_atomic_check(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1545 static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
1546 struct drm_bridge_state *bridge_state,
1547 struct drm_crtc_state *crtc_state,
1548 struct drm_connector_state *conn_state)
1549 {
1550 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1551 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1552
1553 /*
1554 * The i.MX8M Mini/Nano glue logic between LCDIF and DSIM
1555 * inverts HS/VS/DE sync signals polarity, therefore, while
1556 * i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020
1557 * 13.6.3.5.2 RGB interface
1558 * i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022
1559 * 13.6.2.7.2 RGB interface
1560 * both claim "Vsync, Hsync, and VDEN are active high signals.", the
1561 * LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW.
1562 *
1563 * The i.MX8M Plus glue logic between LCDIFv3 and DSIM does not
1564 * implement the same behavior, therefore LCDIFv3 must generate
1565 * HS/VS/DE signals active HIGH.
1566 */
1567 if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) {
1568 adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1569 adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1570 } else if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MP) {
1571 adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1572 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1573 }
1574
1575 return 0;
1576 }
1577
samsung_dsim_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * mode,const struct drm_display_mode * adjusted_mode)1578 static void samsung_dsim_mode_set(struct drm_bridge *bridge,
1579 const struct drm_display_mode *mode,
1580 const struct drm_display_mode *adjusted_mode)
1581 {
1582 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1583
1584 drm_mode_copy(&dsi->mode, adjusted_mode);
1585 }
1586
samsung_dsim_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)1587 static int samsung_dsim_attach(struct drm_bridge *bridge,
1588 enum drm_bridge_attach_flags flags)
1589 {
1590 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1591
1592 return drm_bridge_attach(bridge->encoder, dsi->out_bridge, bridge,
1593 flags);
1594 }
1595
1596 static const struct drm_bridge_funcs samsung_dsim_bridge_funcs = {
1597 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1598 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1599 .atomic_reset = drm_atomic_helper_bridge_reset,
1600 .atomic_get_input_bus_fmts = samsung_dsim_atomic_get_input_bus_fmts,
1601 .atomic_check = samsung_dsim_atomic_check,
1602 .atomic_pre_enable = samsung_dsim_atomic_pre_enable,
1603 .atomic_enable = samsung_dsim_atomic_enable,
1604 .atomic_disable = samsung_dsim_atomic_disable,
1605 .atomic_post_disable = samsung_dsim_atomic_post_disable,
1606 .mode_set = samsung_dsim_mode_set,
1607 .attach = samsung_dsim_attach,
1608 };
1609
samsung_dsim_te_irq_handler(int irq,void * dev_id)1610 static irqreturn_t samsung_dsim_te_irq_handler(int irq, void *dev_id)
1611 {
1612 struct samsung_dsim *dsi = (struct samsung_dsim *)dev_id;
1613 const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1614
1615 if (pdata->host_ops && pdata->host_ops->te_irq_handler)
1616 return pdata->host_ops->te_irq_handler(dsi);
1617
1618 return IRQ_HANDLED;
1619 }
1620
samsung_dsim_register_te_irq(struct samsung_dsim * dsi,struct device * dev)1621 static int samsung_dsim_register_te_irq(struct samsung_dsim *dsi, struct device *dev)
1622 {
1623 int te_gpio_irq;
1624 int ret;
1625
1626 dsi->te_gpio = devm_gpiod_get_optional(dev, "te", GPIOD_IN);
1627 if (!dsi->te_gpio)
1628 return 0;
1629 else if (IS_ERR(dsi->te_gpio))
1630 return dev_err_probe(dev, PTR_ERR(dsi->te_gpio), "failed to get te GPIO\n");
1631
1632 te_gpio_irq = gpiod_to_irq(dsi->te_gpio);
1633
1634 ret = request_threaded_irq(te_gpio_irq, samsung_dsim_te_irq_handler, NULL,
1635 IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, "TE", dsi);
1636 if (ret) {
1637 dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1638 gpiod_put(dsi->te_gpio);
1639 return ret;
1640 }
1641
1642 return 0;
1643 }
1644
samsung_dsim_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1645 static int samsung_dsim_host_attach(struct mipi_dsi_host *host,
1646 struct mipi_dsi_device *device)
1647 {
1648 struct samsung_dsim *dsi = host_to_dsi(host);
1649 const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1650 struct device *dev = dsi->dev;
1651 struct device_node *np = dev->of_node;
1652 struct device_node *remote;
1653 struct drm_panel *panel;
1654 int ret;
1655
1656 /*
1657 * Devices can also be child nodes when we also control that device
1658 * through the upstream device (ie, MIPI-DCS for a MIPI-DSI device).
1659 *
1660 * Lookup for a child node of the given parent that isn't either port
1661 * or ports.
1662 */
1663 for_each_available_child_of_node(np, remote) {
1664 if (of_node_name_eq(remote, "port") ||
1665 of_node_name_eq(remote, "ports"))
1666 continue;
1667
1668 goto of_find_panel_or_bridge;
1669 }
1670
1671 /*
1672 * of_graph_get_remote_node() produces a noisy error message if port
1673 * node isn't found and the absence of the port is a legit case here,
1674 * so at first we silently check whether graph presents in the
1675 * device-tree node.
1676 */
1677 if (!of_graph_is_present(np))
1678 return -ENODEV;
1679
1680 remote = of_graph_get_remote_node(np, 1, 0);
1681
1682 of_find_panel_or_bridge:
1683 if (!remote)
1684 return -ENODEV;
1685
1686 panel = of_drm_find_panel(remote);
1687 if (!IS_ERR(panel)) {
1688 dsi->out_bridge = devm_drm_panel_bridge_add(dev, panel);
1689 } else {
1690 dsi->out_bridge = of_drm_find_bridge(remote);
1691 if (!dsi->out_bridge)
1692 dsi->out_bridge = ERR_PTR(-EINVAL);
1693 }
1694
1695 of_node_put(remote);
1696
1697 if (IS_ERR(dsi->out_bridge)) {
1698 ret = PTR_ERR(dsi->out_bridge);
1699 DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n", ret);
1700 return ret;
1701 }
1702
1703 DRM_DEV_INFO(dev, "Attached %s device\n", device->name);
1704
1705 drm_bridge_add(&dsi->bridge);
1706
1707 /*
1708 * This is a temporary solution and should be made by more generic way.
1709 *
1710 * If attached panel device is for command mode one, dsi should register
1711 * TE interrupt handler.
1712 */
1713 if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1714 ret = samsung_dsim_register_te_irq(dsi, &device->dev);
1715 if (ret)
1716 return ret;
1717 }
1718
1719 if (pdata->host_ops && pdata->host_ops->attach) {
1720 ret = pdata->host_ops->attach(dsi, device);
1721 if (ret)
1722 return ret;
1723 }
1724
1725 dsi->lanes = device->lanes;
1726 dsi->format = device->format;
1727 dsi->mode_flags = device->mode_flags;
1728
1729 return 0;
1730 }
1731
samsung_dsim_unregister_te_irq(struct samsung_dsim * dsi)1732 static void samsung_dsim_unregister_te_irq(struct samsung_dsim *dsi)
1733 {
1734 if (dsi->te_gpio) {
1735 free_irq(gpiod_to_irq(dsi->te_gpio), dsi);
1736 gpiod_put(dsi->te_gpio);
1737 }
1738 }
1739
samsung_dsim_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1740 static int samsung_dsim_host_detach(struct mipi_dsi_host *host,
1741 struct mipi_dsi_device *device)
1742 {
1743 struct samsung_dsim *dsi = host_to_dsi(host);
1744 const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1745
1746 dsi->out_bridge = NULL;
1747
1748 if (pdata->host_ops && pdata->host_ops->detach)
1749 pdata->host_ops->detach(dsi, device);
1750
1751 samsung_dsim_unregister_te_irq(dsi);
1752
1753 drm_bridge_remove(&dsi->bridge);
1754
1755 return 0;
1756 }
1757
samsung_dsim_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)1758 static ssize_t samsung_dsim_host_transfer(struct mipi_dsi_host *host,
1759 const struct mipi_dsi_msg *msg)
1760 {
1761 struct samsung_dsim *dsi = host_to_dsi(host);
1762 struct samsung_dsim_transfer xfer;
1763 int ret;
1764
1765 if (!(dsi->state & DSIM_STATE_ENABLED))
1766 return -EINVAL;
1767
1768 ret = samsung_dsim_init(dsi);
1769 if (ret)
1770 return ret;
1771
1772 ret = mipi_dsi_create_packet(&xfer.packet, msg);
1773 if (ret < 0)
1774 return ret;
1775
1776 xfer.rx_len = msg->rx_len;
1777 xfer.rx_payload = msg->rx_buf;
1778 xfer.flags = msg->flags;
1779
1780 ret = samsung_dsim_transfer(dsi, &xfer);
1781 return (ret < 0) ? ret : xfer.rx_done;
1782 }
1783
1784 static const struct mipi_dsi_host_ops samsung_dsim_ops = {
1785 .attach = samsung_dsim_host_attach,
1786 .detach = samsung_dsim_host_detach,
1787 .transfer = samsung_dsim_host_transfer,
1788 };
1789
samsung_dsim_of_read_u32(const struct device_node * np,const char * propname,u32 * out_value,bool optional)1790 static int samsung_dsim_of_read_u32(const struct device_node *np,
1791 const char *propname, u32 *out_value, bool optional)
1792 {
1793 int ret = of_property_read_u32(np, propname, out_value);
1794
1795 if (ret < 0 && !optional)
1796 pr_err("%pOF: failed to get '%s' property\n", np, propname);
1797
1798 return ret;
1799 }
1800
samsung_dsim_parse_dt(struct samsung_dsim * dsi)1801 static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
1802 {
1803 struct device *dev = dsi->dev;
1804 struct device_node *node = dev->of_node;
1805 u32 lane_polarities[5] = { 0 };
1806 struct device_node *endpoint;
1807 int i, nr_lanes, ret;
1808 struct clk *pll_clk;
1809
1810 ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
1811 &dsi->pll_clk_rate, 1);
1812 /* If it doesn't exist, read it from the clock instead of failing */
1813 if (ret < 0) {
1814 dev_dbg(dev, "Using sclk_mipi for pll clock frequency\n");
1815 pll_clk = devm_clk_get(dev, "sclk_mipi");
1816 if (!IS_ERR(pll_clk))
1817 dsi->pll_clk_rate = clk_get_rate(pll_clk);
1818 else
1819 return PTR_ERR(pll_clk);
1820 }
1821
1822 /* If it doesn't exist, use pixel clock instead of failing */
1823 ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency",
1824 &dsi->burst_clk_rate, 1);
1825 if (ret < 0) {
1826 dev_dbg(dev, "Using pixel clock for HS clock frequency\n");
1827 dsi->burst_clk_rate = 0;
1828 }
1829
1830 ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency",
1831 &dsi->esc_clk_rate, 0);
1832 if (ret < 0)
1833 return ret;
1834
1835 endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
1836 nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
1837 if (nr_lanes > 0 && nr_lanes <= 4) {
1838 /* Polarity 0 is clock lane, 1..4 are data lanes. */
1839 of_property_read_u32_array(endpoint, "lane-polarities",
1840 lane_polarities, nr_lanes + 1);
1841 for (i = 1; i <= nr_lanes; i++) {
1842 if (lane_polarities[1] != lane_polarities[i])
1843 DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match");
1844 }
1845 if (lane_polarities[0])
1846 dsi->swap_dn_dp_clk = true;
1847 if (lane_polarities[1])
1848 dsi->swap_dn_dp_data = true;
1849 }
1850
1851 return 0;
1852 }
1853
generic_dsim_register_host(struct samsung_dsim * dsi)1854 static int generic_dsim_register_host(struct samsung_dsim *dsi)
1855 {
1856 return mipi_dsi_host_register(&dsi->dsi_host);
1857 }
1858
generic_dsim_unregister_host(struct samsung_dsim * dsi)1859 static void generic_dsim_unregister_host(struct samsung_dsim *dsi)
1860 {
1861 mipi_dsi_host_unregister(&dsi->dsi_host);
1862 }
1863
1864 static const struct samsung_dsim_host_ops generic_dsim_host_ops = {
1865 .register_host = generic_dsim_register_host,
1866 .unregister_host = generic_dsim_unregister_host,
1867 };
1868
1869 static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_high = {
1870 .input_bus_flags = DRM_BUS_FLAG_DE_HIGH,
1871 };
1872
1873 static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_low = {
1874 .input_bus_flags = DRM_BUS_FLAG_DE_LOW,
1875 };
1876
samsung_dsim_probe(struct platform_device * pdev)1877 int samsung_dsim_probe(struct platform_device *pdev)
1878 {
1879 struct device *dev = &pdev->dev;
1880 struct samsung_dsim *dsi;
1881 int ret, i;
1882
1883 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1884 if (!dsi)
1885 return -ENOMEM;
1886
1887 init_completion(&dsi->completed);
1888 spin_lock_init(&dsi->transfer_lock);
1889 INIT_LIST_HEAD(&dsi->transfer_list);
1890
1891 dsi->dsi_host.ops = &samsung_dsim_ops;
1892 dsi->dsi_host.dev = dev;
1893
1894 dsi->dev = dev;
1895 dsi->plat_data = of_device_get_match_data(dev);
1896 dsi->driver_data = samsung_dsim_types[dsi->plat_data->hw_type];
1897
1898 dsi->supplies[0].supply = "vddcore";
1899 dsi->supplies[1].supply = "vddio";
1900 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1901 dsi->supplies);
1902 if (ret)
1903 return dev_err_probe(dev, ret, "failed to get regulators\n");
1904
1905 dsi->clks = devm_kcalloc(dev, dsi->driver_data->num_clks,
1906 sizeof(*dsi->clks), GFP_KERNEL);
1907 if (!dsi->clks)
1908 return -ENOMEM;
1909
1910 for (i = 0; i < dsi->driver_data->num_clks; i++) {
1911 dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
1912 if (IS_ERR(dsi->clks[i])) {
1913 if (strcmp(clk_names[i], "sclk_mipi") == 0) {
1914 dsi->clks[i] = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME);
1915 if (!IS_ERR(dsi->clks[i]))
1916 continue;
1917 }
1918
1919 dev_info(dev, "failed to get the clock: %s\n", clk_names[i]);
1920 return PTR_ERR(dsi->clks[i]);
1921 }
1922 }
1923
1924 dsi->reg_base = devm_platform_ioremap_resource(pdev, 0);
1925 if (IS_ERR(dsi->reg_base))
1926 return PTR_ERR(dsi->reg_base);
1927
1928 dsi->phy = devm_phy_optional_get(dev, "dsim");
1929 if (IS_ERR(dsi->phy)) {
1930 dev_info(dev, "failed to get dsim phy\n");
1931 return PTR_ERR(dsi->phy);
1932 }
1933
1934 dsi->irq = platform_get_irq(pdev, 0);
1935 if (dsi->irq < 0)
1936 return dsi->irq;
1937
1938 ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
1939 samsung_dsim_irq,
1940 IRQF_ONESHOT | IRQF_NO_AUTOEN,
1941 dev_name(dev), dsi);
1942 if (ret) {
1943 dev_err(dev, "failed to request dsi irq\n");
1944 return ret;
1945 }
1946
1947 ret = samsung_dsim_parse_dt(dsi);
1948 if (ret)
1949 return ret;
1950
1951 platform_set_drvdata(pdev, dsi);
1952
1953 pm_runtime_enable(dev);
1954
1955 dsi->bridge.funcs = &samsung_dsim_bridge_funcs;
1956 dsi->bridge.of_node = dev->of_node;
1957 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
1958
1959 /* DE_LOW: i.MX8M Mini/Nano LCDIF-DSIM glue logic inverts HS/VS/DE */
1960 if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM)
1961 dsi->bridge.timings = &samsung_dsim_bridge_timings_de_low;
1962 else
1963 dsi->bridge.timings = &samsung_dsim_bridge_timings_de_high;
1964
1965 if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->register_host)
1966 ret = dsi->plat_data->host_ops->register_host(dsi);
1967
1968 if (ret)
1969 goto err_disable_runtime;
1970
1971 return 0;
1972
1973 err_disable_runtime:
1974 pm_runtime_disable(dev);
1975
1976 return ret;
1977 }
1978 EXPORT_SYMBOL_GPL(samsung_dsim_probe);
1979
samsung_dsim_remove(struct platform_device * pdev)1980 int samsung_dsim_remove(struct platform_device *pdev)
1981 {
1982 struct samsung_dsim *dsi = platform_get_drvdata(pdev);
1983
1984 pm_runtime_disable(&pdev->dev);
1985
1986 if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->unregister_host)
1987 dsi->plat_data->host_ops->unregister_host(dsi);
1988
1989 return 0;
1990 }
1991 EXPORT_SYMBOL_GPL(samsung_dsim_remove);
1992
samsung_dsim_suspend(struct device * dev)1993 static int __maybe_unused samsung_dsim_suspend(struct device *dev)
1994 {
1995 struct samsung_dsim *dsi = dev_get_drvdata(dev);
1996 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
1997 int ret, i;
1998
1999 usleep_range(10000, 20000);
2000
2001 if (dsi->state & DSIM_STATE_INITIALIZED) {
2002 dsi->state &= ~DSIM_STATE_INITIALIZED;
2003
2004 samsung_dsim_disable_clock(dsi);
2005
2006 samsung_dsim_disable_irq(dsi);
2007 }
2008
2009 dsi->state &= ~DSIM_STATE_CMD_LPM;
2010
2011 phy_power_off(dsi->phy);
2012
2013 for (i = driver_data->num_clks - 1; i > -1; i--)
2014 clk_disable_unprepare(dsi->clks[i]);
2015
2016 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
2017 if (ret < 0)
2018 dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
2019
2020 return 0;
2021 }
2022
samsung_dsim_resume(struct device * dev)2023 static int __maybe_unused samsung_dsim_resume(struct device *dev)
2024 {
2025 struct samsung_dsim *dsi = dev_get_drvdata(dev);
2026 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
2027 int ret, i;
2028
2029 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
2030 if (ret < 0) {
2031 dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
2032 return ret;
2033 }
2034
2035 for (i = 0; i < driver_data->num_clks; i++) {
2036 ret = clk_prepare_enable(dsi->clks[i]);
2037 if (ret < 0)
2038 goto err_clk;
2039 }
2040
2041 ret = phy_power_on(dsi->phy);
2042 if (ret < 0) {
2043 dev_err(dsi->dev, "cannot enable phy %d\n", ret);
2044 goto err_clk;
2045 }
2046
2047 return 0;
2048
2049 err_clk:
2050 while (--i > -1)
2051 clk_disable_unprepare(dsi->clks[i]);
2052 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
2053
2054 return ret;
2055 }
2056
2057 const struct dev_pm_ops samsung_dsim_pm_ops = {
2058 SET_RUNTIME_PM_OPS(samsung_dsim_suspend, samsung_dsim_resume, NULL)
2059 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2060 pm_runtime_force_resume)
2061 };
2062 EXPORT_SYMBOL_GPL(samsung_dsim_pm_ops);
2063
2064 static const struct samsung_dsim_plat_data samsung_dsim_imx8mm_pdata = {
2065 .hw_type = DSIM_TYPE_IMX8MM,
2066 .host_ops = &generic_dsim_host_ops,
2067 };
2068
2069 static const struct samsung_dsim_plat_data samsung_dsim_imx8mp_pdata = {
2070 .hw_type = DSIM_TYPE_IMX8MP,
2071 .host_ops = &generic_dsim_host_ops,
2072 };
2073
2074 static const struct of_device_id samsung_dsim_of_match[] = {
2075 {
2076 .compatible = "fsl,imx8mm-mipi-dsim",
2077 .data = &samsung_dsim_imx8mm_pdata,
2078 },
2079 {
2080 .compatible = "fsl,imx8mp-mipi-dsim",
2081 .data = &samsung_dsim_imx8mp_pdata,
2082 },
2083 { /* sentinel. */ }
2084 };
2085 MODULE_DEVICE_TABLE(of, samsung_dsim_of_match);
2086
2087 static struct platform_driver samsung_dsim_driver = {
2088 .probe = samsung_dsim_probe,
2089 .remove = samsung_dsim_remove,
2090 .driver = {
2091 .name = "samsung-dsim",
2092 .pm = &samsung_dsim_pm_ops,
2093 .of_match_table = samsung_dsim_of_match,
2094 },
2095 };
2096
2097 module_platform_driver(samsung_dsim_driver);
2098
2099 MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
2100 MODULE_DESCRIPTION("Samsung MIPI DSIM controller bridge");
2101 MODULE_LICENSE("GPL");
2102