1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016 MediaTek Inc. 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/err.h> 8 #include <linux/gpio/consumer.h> 9 #include <linux/i2c.h> 10 #include <linux/module.h> 11 #include <linux/of_graph.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <linux/regulator/consumer.h> 15 16 #include <drm/display/drm_dp_aux_bus.h> 17 #include <drm/display/drm_dp_helper.h> 18 #include <drm/drm_bridge.h> 19 #include <drm/drm_edid.h> 20 #include <drm/drm_mipi_dsi.h> 21 #include <drm/drm_of.h> 22 #include <drm/drm_panel.h> 23 #include <drm/drm_print.h> 24 25 #define PAGE0_AUXCH_CFG3 0x76 26 #define AUXCH_CFG3_RESET 0xff 27 #define PAGE0_SWAUX_ADDR_7_0 0x7d 28 #define PAGE0_SWAUX_ADDR_15_8 0x7e 29 #define PAGE0_SWAUX_ADDR_23_16 0x7f 30 #define SWAUX_ADDR_MASK GENMASK(19, 0) 31 #define PAGE0_SWAUX_LENGTH 0x80 32 #define SWAUX_LENGTH_MASK GENMASK(3, 0) 33 #define SWAUX_NO_PAYLOAD BIT(7) 34 #define PAGE0_SWAUX_WDATA 0x81 35 #define PAGE0_SWAUX_RDATA 0x82 36 #define PAGE0_SWAUX_CTRL 0x83 37 #define SWAUX_SEND BIT(0) 38 #define PAGE0_SWAUX_STATUS 0x84 39 #define SWAUX_M_MASK GENMASK(4, 0) 40 #define SWAUX_STATUS_MASK GENMASK(7, 5) 41 #define SWAUX_STATUS_NACK (0x1 << 5) 42 #define SWAUX_STATUS_DEFER (0x2 << 5) 43 #define SWAUX_STATUS_ACKM (0x3 << 5) 44 #define SWAUX_STATUS_INVALID (0x4 << 5) 45 #define SWAUX_STATUS_I2C_NACK (0x5 << 5) 46 #define SWAUX_STATUS_I2C_DEFER (0x6 << 5) 47 #define SWAUX_STATUS_TIMEOUT (0x7 << 5) 48 49 #define PAGE2_GPIO_H 0xa7 50 #define PS_GPIO9 BIT(1) 51 #define PAGE2_I2C_BYPASS 0xea 52 #define I2C_BYPASS_EN 0xd0 53 #define PAGE2_MCS_EN 0xf3 54 #define MCS_EN BIT(0) 55 56 #define PAGE3_SET_ADD 0xfe 57 #define VDO_CTL_ADD 0x13 58 #define VDO_DIS 0x18 59 #define VDO_EN 0x1c 60 61 #define NUM_MIPI_LANES 4 62 63 #define COMMON_PS8640_REGMAP_CONFIG \ 64 .reg_bits = 8, \ 65 .val_bits = 8, \ 66 .cache_type = REGCACHE_NONE 67 68 /* 69 * PS8640 uses multiple addresses: 70 * page[0]: for DP control 71 * page[1]: for VIDEO Bridge 72 * page[2]: for control top 73 * page[3]: for DSI Link Control1 74 * page[4]: for MIPI Phy 75 * page[5]: for VPLL 76 * page[6]: for DSI Link Control2 77 * page[7]: for SPI ROM mapping 78 */ 79 enum page_addr_offset { 80 PAGE0_DP_CNTL = 0, 81 PAGE1_VDO_BDG, 82 PAGE2_TOP_CNTL, 83 PAGE3_DSI_CNTL1, 84 PAGE4_MIPI_PHY, 85 PAGE5_VPLL, 86 PAGE6_DSI_CNTL2, 87 PAGE7_SPI_CNTL, 88 MAX_DEVS 89 }; 90 91 enum ps8640_vdo_control { 92 DISABLE = VDO_DIS, 93 ENABLE = VDO_EN, 94 }; 95 96 struct ps8640 { 97 struct drm_bridge bridge; 98 struct drm_bridge *panel_bridge; 99 struct drm_dp_aux aux; 100 struct mipi_dsi_device *dsi; 101 struct i2c_client *page[MAX_DEVS]; 102 struct regmap *regmap[MAX_DEVS]; 103 struct regulator_bulk_data supplies[2]; 104 struct gpio_desc *gpio_reset; 105 struct gpio_desc *gpio_powerdown; 106 struct device_link *link; 107 bool pre_enabled; 108 }; 109 110 static const struct regmap_config ps8640_regmap_config[] = { 111 [PAGE0_DP_CNTL] = { 112 COMMON_PS8640_REGMAP_CONFIG, 113 .max_register = 0xbf, 114 }, 115 [PAGE1_VDO_BDG] = { 116 COMMON_PS8640_REGMAP_CONFIG, 117 .max_register = 0xff, 118 }, 119 [PAGE2_TOP_CNTL] = { 120 COMMON_PS8640_REGMAP_CONFIG, 121 .max_register = 0xff, 122 }, 123 [PAGE3_DSI_CNTL1] = { 124 COMMON_PS8640_REGMAP_CONFIG, 125 .max_register = 0xff, 126 }, 127 [PAGE4_MIPI_PHY] = { 128 COMMON_PS8640_REGMAP_CONFIG, 129 .max_register = 0xff, 130 }, 131 [PAGE5_VPLL] = { 132 COMMON_PS8640_REGMAP_CONFIG, 133 .max_register = 0x7f, 134 }, 135 [PAGE6_DSI_CNTL2] = { 136 COMMON_PS8640_REGMAP_CONFIG, 137 .max_register = 0xff, 138 }, 139 [PAGE7_SPI_CNTL] = { 140 COMMON_PS8640_REGMAP_CONFIG, 141 .max_register = 0xff, 142 }, 143 }; 144 145 static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e) 146 { 147 return container_of(e, struct ps8640, bridge); 148 } 149 150 static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux) 151 { 152 return container_of(aux, struct ps8640, aux); 153 } 154 155 static bool ps8640_of_panel_on_aux_bus(struct device *dev) 156 { 157 struct device_node *bus, *panel; 158 159 bus = of_get_child_by_name(dev->of_node, "aux-bus"); 160 if (!bus) 161 return false; 162 163 panel = of_get_child_by_name(bus, "panel"); 164 of_node_put(bus); 165 if (!panel) 166 return false; 167 of_node_put(panel); 168 169 return true; 170 } 171 172 static int _ps8640_wait_hpd_asserted(struct ps8640 *ps_bridge, unsigned long wait_us) 173 { 174 struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; 175 int status; 176 177 /* 178 * Apparently something about the firmware in the chip signals that 179 * HPD goes high by reporting GPIO9 as high (even though HPD isn't 180 * actually connected to GPIO9). 181 */ 182 return regmap_read_poll_timeout(map, PAGE2_GPIO_H, status, 183 status & PS_GPIO9, wait_us / 10, wait_us); 184 } 185 186 static int ps8640_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us) 187 { 188 struct ps8640 *ps_bridge = aux_to_ps8640(aux); 189 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; 190 int ret; 191 192 /* 193 * Note that this function is called by code that has already powered 194 * the panel. We have to power ourselves up but we don't need to worry 195 * about powering the panel. 196 */ 197 pm_runtime_get_sync(dev); 198 ret = _ps8640_wait_hpd_asserted(ps_bridge, wait_us); 199 pm_runtime_mark_last_busy(dev); 200 pm_runtime_put_autosuspend(dev); 201 202 return ret; 203 } 204 205 static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux, 206 struct drm_dp_aux_msg *msg) 207 { 208 struct ps8640 *ps_bridge = aux_to_ps8640(aux); 209 struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL]; 210 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; 211 unsigned int len = msg->size; 212 unsigned int data; 213 unsigned int base; 214 int ret; 215 u8 request = msg->request & 216 ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE); 217 u8 *buf = msg->buffer; 218 u8 addr_len[PAGE0_SWAUX_LENGTH + 1 - PAGE0_SWAUX_ADDR_7_0]; 219 u8 i; 220 bool is_native_aux = false; 221 222 if (len > DP_AUX_MAX_PAYLOAD_BYTES) 223 return -EINVAL; 224 225 if (msg->address & ~SWAUX_ADDR_MASK) 226 return -EINVAL; 227 228 switch (request) { 229 case DP_AUX_NATIVE_WRITE: 230 case DP_AUX_NATIVE_READ: 231 is_native_aux = true; 232 fallthrough; 233 case DP_AUX_I2C_WRITE: 234 case DP_AUX_I2C_READ: 235 break; 236 default: 237 return -EINVAL; 238 } 239 240 ret = regmap_write(map, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET); 241 if (ret) { 242 DRM_DEV_ERROR(dev, "failed to write PAGE0_AUXCH_CFG3: %d\n", 243 ret); 244 return ret; 245 } 246 247 /* Assume it's good */ 248 msg->reply = 0; 249 250 base = PAGE0_SWAUX_ADDR_7_0; 251 addr_len[PAGE0_SWAUX_ADDR_7_0 - base] = msg->address; 252 addr_len[PAGE0_SWAUX_ADDR_15_8 - base] = msg->address >> 8; 253 addr_len[PAGE0_SWAUX_ADDR_23_16 - base] = (msg->address >> 16) | 254 (msg->request << 4); 255 addr_len[PAGE0_SWAUX_LENGTH - base] = (len == 0) ? SWAUX_NO_PAYLOAD : 256 ((len - 1) & SWAUX_LENGTH_MASK); 257 258 regmap_bulk_write(map, PAGE0_SWAUX_ADDR_7_0, addr_len, 259 ARRAY_SIZE(addr_len)); 260 261 if (len && (request == DP_AUX_NATIVE_WRITE || 262 request == DP_AUX_I2C_WRITE)) { 263 /* Write to the internal FIFO buffer */ 264 for (i = 0; i < len; i++) { 265 ret = regmap_write(map, PAGE0_SWAUX_WDATA, buf[i]); 266 if (ret) { 267 DRM_DEV_ERROR(dev, 268 "failed to write WDATA: %d\n", 269 ret); 270 return ret; 271 } 272 } 273 } 274 275 regmap_write(map, PAGE0_SWAUX_CTRL, SWAUX_SEND); 276 277 /* Zero delay loop because i2c transactions are slow already */ 278 regmap_read_poll_timeout(map, PAGE0_SWAUX_CTRL, data, 279 !(data & SWAUX_SEND), 0, 50 * 1000); 280 281 regmap_read(map, PAGE0_SWAUX_STATUS, &data); 282 if (ret) { 283 DRM_DEV_ERROR(dev, "failed to read PAGE0_SWAUX_STATUS: %d\n", 284 ret); 285 return ret; 286 } 287 288 switch (data & SWAUX_STATUS_MASK) { 289 /* Ignore the DEFER cases as they are already handled in hardware */ 290 case SWAUX_STATUS_NACK: 291 case SWAUX_STATUS_I2C_NACK: 292 /* 293 * The programming guide is not clear about whether a I2C NACK 294 * would trigger SWAUX_STATUS_NACK or SWAUX_STATUS_I2C_NACK. So 295 * we handle both cases together. 296 */ 297 if (is_native_aux) 298 msg->reply |= DP_AUX_NATIVE_REPLY_NACK; 299 else 300 msg->reply |= DP_AUX_I2C_REPLY_NACK; 301 302 fallthrough; 303 case SWAUX_STATUS_ACKM: 304 len = data & SWAUX_M_MASK; 305 break; 306 case SWAUX_STATUS_INVALID: 307 return -EOPNOTSUPP; 308 case SWAUX_STATUS_TIMEOUT: 309 return -ETIMEDOUT; 310 } 311 312 if (len && (request == DP_AUX_NATIVE_READ || 313 request == DP_AUX_I2C_READ)) { 314 /* Read from the internal FIFO buffer */ 315 for (i = 0; i < len; i++) { 316 ret = regmap_read(map, PAGE0_SWAUX_RDATA, &data); 317 if (ret) { 318 DRM_DEV_ERROR(dev, 319 "failed to read RDATA: %d\n", 320 ret); 321 return ret; 322 } 323 324 buf[i] = data; 325 } 326 } 327 328 return len; 329 } 330 331 static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, 332 struct drm_dp_aux_msg *msg) 333 { 334 struct ps8640 *ps_bridge = aux_to_ps8640(aux); 335 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; 336 int ret; 337 338 pm_runtime_get_sync(dev); 339 ret = ps8640_aux_transfer_msg(aux, msg); 340 pm_runtime_mark_last_busy(dev); 341 pm_runtime_put_autosuspend(dev); 342 343 return ret; 344 } 345 346 static void ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, 347 const enum ps8640_vdo_control ctrl) 348 { 349 struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1]; 350 struct device *dev = &ps_bridge->page[PAGE3_DSI_CNTL1]->dev; 351 u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl }; 352 int ret; 353 354 ret = regmap_bulk_write(map, PAGE3_SET_ADD, 355 vdo_ctrl_buf, sizeof(vdo_ctrl_buf)); 356 357 if (ret < 0) 358 dev_err(dev, "failed to %sable VDO: %d\n", 359 ctrl == ENABLE ? "en" : "dis", ret); 360 } 361 362 static int __maybe_unused ps8640_resume(struct device *dev) 363 { 364 struct ps8640 *ps_bridge = dev_get_drvdata(dev); 365 int ret; 366 367 ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies), 368 ps_bridge->supplies); 369 if (ret < 0) { 370 dev_err(dev, "cannot enable regulators %d\n", ret); 371 return ret; 372 } 373 374 gpiod_set_value(ps_bridge->gpio_powerdown, 0); 375 gpiod_set_value(ps_bridge->gpio_reset, 1); 376 usleep_range(2000, 2500); 377 gpiod_set_value(ps_bridge->gpio_reset, 0); 378 /* Double reset for T4 and T5 */ 379 msleep(50); 380 gpiod_set_value(ps_bridge->gpio_reset, 1); 381 msleep(50); 382 gpiod_set_value(ps_bridge->gpio_reset, 0); 383 384 /* 385 * Mystery 200 ms delay for the "MCU to be ready". It's unclear if 386 * this is truly necessary since the MCU will already signal that 387 * things are "good to go" by signaling HPD on "gpio 9". See 388 * _ps8640_wait_hpd_asserted(). For now we'll keep this mystery delay 389 * just in case. 390 */ 391 msleep(200); 392 393 return 0; 394 } 395 396 static int __maybe_unused ps8640_suspend(struct device *dev) 397 { 398 struct ps8640 *ps_bridge = dev_get_drvdata(dev); 399 int ret; 400 401 gpiod_set_value(ps_bridge->gpio_reset, 1); 402 gpiod_set_value(ps_bridge->gpio_powerdown, 1); 403 ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies), 404 ps_bridge->supplies); 405 if (ret < 0) 406 dev_err(dev, "cannot disable regulators %d\n", ret); 407 408 return ret; 409 } 410 411 static const struct dev_pm_ops ps8640_pm_ops = { 412 SET_RUNTIME_PM_OPS(ps8640_suspend, ps8640_resume, NULL) 413 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 414 pm_runtime_force_resume) 415 }; 416 417 static void ps8640_pre_enable(struct drm_bridge *bridge) 418 { 419 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); 420 struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; 421 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; 422 int ret; 423 424 pm_runtime_get_sync(dev); 425 ret = _ps8640_wait_hpd_asserted(ps_bridge, 200 * 1000); 426 if (ret < 0) 427 dev_warn(dev, "HPD didn't go high: %d\n", ret); 428 429 /* 430 * The Manufacturer Command Set (MCS) is a device dependent interface 431 * intended for factory programming of the display module default 432 * parameters. Once the display module is configured, the MCS shall be 433 * disabled by the manufacturer. Once disabled, all MCS commands are 434 * ignored by the display interface. 435 */ 436 437 ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0); 438 if (ret < 0) 439 dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret); 440 441 /* Switch access edp panel's edid through i2c */ 442 ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN); 443 if (ret < 0) 444 dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret); 445 446 ps8640_bridge_vdo_control(ps_bridge, ENABLE); 447 448 ps_bridge->pre_enabled = true; 449 } 450 451 static void ps8640_post_disable(struct drm_bridge *bridge) 452 { 453 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); 454 455 ps_bridge->pre_enabled = false; 456 457 ps8640_bridge_vdo_control(ps_bridge, DISABLE); 458 pm_runtime_put_sync_suspend(&ps_bridge->page[PAGE0_DP_CNTL]->dev); 459 } 460 461 static int ps8640_bridge_attach(struct drm_bridge *bridge, 462 enum drm_bridge_attach_flags flags) 463 { 464 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); 465 struct device *dev = &ps_bridge->page[0]->dev; 466 int ret; 467 468 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 469 return -EINVAL; 470 471 ps_bridge->aux.drm_dev = bridge->dev; 472 ret = drm_dp_aux_register(&ps_bridge->aux); 473 if (ret) { 474 dev_err(dev, "failed to register DP AUX channel: %d\n", ret); 475 return ret; 476 } 477 478 ps_bridge->link = device_link_add(bridge->dev->dev, dev, DL_FLAG_STATELESS); 479 if (!ps_bridge->link) { 480 dev_err(dev, "failed to create device link"); 481 ret = -EINVAL; 482 goto err_devlink; 483 } 484 485 /* Attach the panel-bridge to the dsi bridge */ 486 ret = drm_bridge_attach(bridge->encoder, ps_bridge->panel_bridge, 487 &ps_bridge->bridge, flags); 488 if (ret) 489 goto err_bridge_attach; 490 491 return 0; 492 493 err_bridge_attach: 494 device_link_del(ps_bridge->link); 495 err_devlink: 496 drm_dp_aux_unregister(&ps_bridge->aux); 497 498 return ret; 499 } 500 501 static void ps8640_bridge_detach(struct drm_bridge *bridge) 502 { 503 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); 504 505 drm_dp_aux_unregister(&ps_bridge->aux); 506 if (ps_bridge->link) 507 device_link_del(ps_bridge->link); 508 } 509 510 static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge, 511 struct drm_connector *connector) 512 { 513 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); 514 bool poweroff = !ps_bridge->pre_enabled; 515 struct edid *edid; 516 517 /* 518 * When we end calling get_edid() triggered by an ioctl, i.e 519 * 520 * drm_mode_getconnector (ioctl) 521 * -> drm_helper_probe_single_connector_modes 522 * -> drm_bridge_connector_get_modes 523 * -> ps8640_bridge_get_edid 524 * 525 * We need to make sure that what we need is enabled before reading 526 * EDID, for this chip, we need to do a full poweron, otherwise it will 527 * fail. 528 */ 529 drm_bridge_chain_pre_enable(bridge); 530 531 edid = drm_get_edid(connector, 532 ps_bridge->page[PAGE0_DP_CNTL]->adapter); 533 534 /* 535 * If we call the get_edid() function without having enabled the chip 536 * before, return the chip to its original power state. 537 */ 538 if (poweroff) 539 drm_bridge_chain_post_disable(bridge); 540 541 return edid; 542 } 543 544 static void ps8640_runtime_disable(void *data) 545 { 546 pm_runtime_dont_use_autosuspend(data); 547 pm_runtime_disable(data); 548 } 549 550 static const struct drm_bridge_funcs ps8640_bridge_funcs = { 551 .attach = ps8640_bridge_attach, 552 .detach = ps8640_bridge_detach, 553 .get_edid = ps8640_bridge_get_edid, 554 .post_disable = ps8640_post_disable, 555 .pre_enable = ps8640_pre_enable, 556 }; 557 558 static int ps8640_bridge_get_dsi_resources(struct device *dev, struct ps8640 *ps_bridge) 559 { 560 struct device_node *in_ep, *dsi_node; 561 struct mipi_dsi_device *dsi; 562 struct mipi_dsi_host *host; 563 const struct mipi_dsi_device_info info = { .type = "ps8640", 564 .channel = 0, 565 .node = NULL, 566 }; 567 568 /* port@0 is ps8640 dsi input port */ 569 in_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); 570 if (!in_ep) 571 return -ENODEV; 572 573 dsi_node = of_graph_get_remote_port_parent(in_ep); 574 of_node_put(in_ep); 575 if (!dsi_node) 576 return -ENODEV; 577 578 host = of_find_mipi_dsi_host_by_node(dsi_node); 579 of_node_put(dsi_node); 580 if (!host) 581 return -EPROBE_DEFER; 582 583 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 584 if (IS_ERR(dsi)) { 585 dev_err(dev, "failed to create dsi device\n"); 586 return PTR_ERR(dsi); 587 } 588 589 ps_bridge->dsi = dsi; 590 591 dsi->host = host; 592 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 593 MIPI_DSI_MODE_VIDEO_SYNC_PULSE; 594 dsi->format = MIPI_DSI_FMT_RGB888; 595 dsi->lanes = NUM_MIPI_LANES; 596 597 return 0; 598 } 599 600 static int ps8640_bridge_link_panel(struct drm_dp_aux *aux) 601 { 602 struct ps8640 *ps_bridge = aux_to_ps8640(aux); 603 struct device *dev = aux->dev; 604 struct device_node *np = dev->of_node; 605 int ret; 606 607 /* 608 * NOTE about returning -EPROBE_DEFER from this function: if we 609 * return an error (most relevant to -EPROBE_DEFER) it will only 610 * be passed out to ps8640_probe() if it called this directly (AKA the 611 * panel isn't under the "aux-bus" node). That should be fine because 612 * if the panel is under "aux-bus" it's guaranteed to have probed by 613 * the time this function has been called. 614 */ 615 616 /* port@1 is ps8640 output port */ 617 ps_bridge->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0); 618 if (IS_ERR(ps_bridge->panel_bridge)) 619 return PTR_ERR(ps_bridge->panel_bridge); 620 621 ret = devm_drm_bridge_add(dev, &ps_bridge->bridge); 622 if (ret) 623 return ret; 624 625 return devm_mipi_dsi_attach(dev, ps_bridge->dsi); 626 } 627 628 static int ps8640_probe(struct i2c_client *client) 629 { 630 struct device *dev = &client->dev; 631 struct ps8640 *ps_bridge; 632 int ret; 633 u32 i; 634 635 ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL); 636 if (!ps_bridge) 637 return -ENOMEM; 638 639 ps_bridge->supplies[0].supply = "vdd12"; 640 ps_bridge->supplies[1].supply = "vdd33"; 641 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies), 642 ps_bridge->supplies); 643 if (ret) 644 return ret; 645 646 ps_bridge->gpio_powerdown = devm_gpiod_get(&client->dev, "powerdown", 647 GPIOD_OUT_HIGH); 648 if (IS_ERR(ps_bridge->gpio_powerdown)) 649 return PTR_ERR(ps_bridge->gpio_powerdown); 650 651 /* 652 * Assert the reset to avoid the bridge being initialized prematurely 653 */ 654 ps_bridge->gpio_reset = devm_gpiod_get(&client->dev, "reset", 655 GPIOD_OUT_HIGH); 656 if (IS_ERR(ps_bridge->gpio_reset)) 657 return PTR_ERR(ps_bridge->gpio_reset); 658 659 ps_bridge->bridge.funcs = &ps8640_bridge_funcs; 660 ps_bridge->bridge.of_node = dev->of_node; 661 ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP; 662 663 /* 664 * In the device tree, if panel is listed under aux-bus of the bridge 665 * node, panel driver should be able to retrieve EDID by itself using 666 * aux-bus. So let's not set DRM_BRIDGE_OP_EDID here. 667 */ 668 if (!ps8640_of_panel_on_aux_bus(&client->dev)) 669 ps_bridge->bridge.ops = DRM_BRIDGE_OP_EDID; 670 671 /* 672 * Get MIPI DSI resources early. These can return -EPROBE_DEFER so 673 * we want to get them out of the way sooner. 674 */ 675 ret = ps8640_bridge_get_dsi_resources(&client->dev, ps_bridge); 676 if (ret) 677 return ret; 678 679 ps_bridge->page[PAGE0_DP_CNTL] = client; 680 681 ps_bridge->regmap[PAGE0_DP_CNTL] = devm_regmap_init_i2c(client, ps8640_regmap_config); 682 if (IS_ERR(ps_bridge->regmap[PAGE0_DP_CNTL])) 683 return PTR_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]); 684 685 for (i = 1; i < ARRAY_SIZE(ps_bridge->page); i++) { 686 ps_bridge->page[i] = devm_i2c_new_dummy_device(&client->dev, 687 client->adapter, 688 client->addr + i); 689 if (IS_ERR(ps_bridge->page[i])) 690 return PTR_ERR(ps_bridge->page[i]); 691 692 ps_bridge->regmap[i] = devm_regmap_init_i2c(ps_bridge->page[i], 693 ps8640_regmap_config + i); 694 if (IS_ERR(ps_bridge->regmap[i])) 695 return PTR_ERR(ps_bridge->regmap[i]); 696 } 697 698 i2c_set_clientdata(client, ps_bridge); 699 700 ps_bridge->aux.name = "parade-ps8640-aux"; 701 ps_bridge->aux.dev = dev; 702 ps_bridge->aux.transfer = ps8640_aux_transfer; 703 ps_bridge->aux.wait_hpd_asserted = ps8640_wait_hpd_asserted; 704 drm_dp_aux_init(&ps_bridge->aux); 705 706 pm_runtime_enable(dev); 707 /* 708 * Powering on ps8640 takes ~300ms. To avoid wasting time on power 709 * cycling ps8640 too often, set autosuspend_delay to 1000ms to ensure 710 * the bridge wouldn't suspend in between each _aux_transfer_msg() call 711 * during EDID read (~20ms in my experiment) and in between the last 712 * _aux_transfer_msg() call during EDID read and the _pre_enable() call 713 * (~100ms in my experiment). 714 */ 715 pm_runtime_set_autosuspend_delay(dev, 1000); 716 pm_runtime_use_autosuspend(dev); 717 pm_suspend_ignore_children(dev, true); 718 ret = devm_add_action_or_reset(dev, ps8640_runtime_disable, dev); 719 if (ret) 720 return ret; 721 722 ret = devm_of_dp_aux_populate_bus(&ps_bridge->aux, ps8640_bridge_link_panel); 723 724 /* 725 * If devm_of_dp_aux_populate_bus() returns -ENODEV then it's up to 726 * usa to call ps8640_bridge_link_panel() directly. NOTE: in this case 727 * the function is allowed to -EPROBE_DEFER. 728 */ 729 if (ret == -ENODEV) 730 return ps8640_bridge_link_panel(&ps_bridge->aux); 731 732 return ret; 733 } 734 735 static const struct of_device_id ps8640_match[] = { 736 { .compatible = "parade,ps8640" }, 737 { } 738 }; 739 MODULE_DEVICE_TABLE(of, ps8640_match); 740 741 static struct i2c_driver ps8640_driver = { 742 .probe_new = ps8640_probe, 743 .driver = { 744 .name = "ps8640", 745 .of_match_table = ps8640_match, 746 .pm = &ps8640_pm_ops, 747 }, 748 }; 749 module_i2c_driver(ps8640_driver); 750 751 MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>"); 752 MODULE_AUTHOR("CK Hu <ck.hu@mediatek.com>"); 753 MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>"); 754 MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver"); 755 MODULE_LICENSE("GPL v2"); 756